From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web12.7477.1622600168292899337 for ; Tue, 01 Jun 2021 19:16:10 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Wed, 02 Jun 2021 10:16:03 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: , , , Cc: "'Chang, Abner \(HPS SW/FW Technologist\)'" , "'Michael D Kinney'" , "'Zhiguang Liu'" , "'Leif Lindholm'" References: <20210515181234.15186-1-daniel.schaefer@hpe.com> <009501d74b81$bf063b40$3d12b1c0$@byosoft.com.cn> <003d01d74e00$321459c0$963d0d40$@byosoft.com.cn> <006501d74e0b$8c555b90$a50012b0$@byosoft.com.cn> <00cf01d75680$ea67e900$bf37bb00$@byosoft.com.cn> <5cf9ecf4-7d81-69a4-d410-9f7b8062edbb@redhat.com> In-Reply-To: <5cf9ecf4-7d81-69a4-d410-9f7b8062edbb@redhat.com> Subject: =?UTF-8?B?5Zue5aSNOiDlm57lpI06IOWbnuWkjTogW2VkazItZGV2ZWxdIFtQQVRDSCB2MSAxLzFdIEFkZCBNZW1vcnlGZW5jZSBpbXBsZW1lbnRhdGlvbiBmb3IgUmlzY1Y2NA==?= Date: Wed, 2 Jun 2021 10:16:02 +0800 Message-ID: <002801d75755$3d0b8200$b7228600$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQFJypucKS8cqqScHdSjLYIRs6xE8QGbDUQpAnI/8ZkBpd+X2wHlzPzZAeEaY6kDIBS6uAC0C3RKAmATlDernZ+3YA== Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Laszlo: Thanks for the detail information about QemuFwCfgLib. So, this library i= s arch generic. Now, it is only consumed by ARM and AARCH64.=20 Daniel: Can you show more on how RiscV64 uses this QemuFwCfgLib? Thanks Liming > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io = =E4=BB=A3=E8=A1=A8 Laszlo Ersek > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B46=E6=9C=881=E6=97=A5 = 15:58 > =E6=94=B6=E4=BB=B6=E4=BA=BA: gaoliming ; devel= @edk2.groups.io; > daniel.schaefer@hpe.com; ardb@kernel.org > =E6=8A=84=E9=80=81: 'Chang, Abner (HPS SW/FW Technologist)' ; > 'Michael D Kinney' ; 'Zhiguang Liu' > ; 'Leif Lindholm' > =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: =E5=9B=9E=E5=A4=8D: [edk2-de= vel] [PATCH v1 1/1] Add MemoryFence > implementation for RiscV64 >=20 > On 06/01/21 02:56, gaoliming wrote: > > Seemly, Edk2\ArmVirtPkg\Library\QemuFwCfgLib\QemuFwCfgLib.inf is not > arch > > specific library. It can also be used in RISCV64. > > > > > > > > Ard and Laszlo: > > > > If ArmVirtPkg\Library\QemuFwCfgLib is arch generic, can it be moved > from > > ArmVirtPkg into OvmfPkg? >=20 > ArmVirtPkg/Library/QemuFwCfgLib is a QemuFwCfgLib instance that is > currently only used by the ArmVirtQemu and ArmVirtQemuKernel platforms. >=20 > It depends on the FDT_CLIENT_PROTOCOL, from > "ArmVirtPkg/ArmVirtPkg.dec" > and "ArmVirtPkg/Include/Protocol/FdtClient.h", to locate the fw_cfg > device. The protocol is ArmVirtPkg specific. Due to the protocol depex, > the library is also DXE_DRIVER and UEFI_DRIVER only. >=20 > The library uses the MMIO data registers of the fw_cfg device by > default; if the DMA interface is supported, then it uses the DMA > interface. In both cases, some registers are accessed with 64-bit > accesses if MDE_CPU_AARCH64 is defined, and with 32-bit accesses > otherwise. >=20 > I don't see how RISCV could reuse this library verbatim. >=20 > The linked patch at > cbb308a> > is a no-go; the MDE_CPU_RISCV64 macro has no place in an ArmVirtPkg > library. >=20 > The library can be moved to the new directory >=20 > OvmfPkg/Library/DxeQemuFwCfgLibFdtMmio >=20 > (note the rename in the last pathname component), but it needs to be > done in multiple steps. The FDT protocol GUID and structure definition > has to be moved at first, separately from the library, and every move > operation (i.e., each one of the protocol move and the library muve) > must be implemented with *at least* three steps -- copy the original to > OvmfPkg (updating BASE_NAME at once), update DSC references under > ArmVirtPkg, remove the original under ArmVirtPkg. Only then can you add > customizations. >=20 > Regarding the processor type macros, I believe Mike recently introduced > ISA-independent macros, for expressing 64-bit vs. 32-bit. I'm not > exactly sure about the details, but I think we now have a macro under > MdePkg that says "64-bit processor" without having to state AARCH64 or > RISCV64. >=20 > Thanks > Laszlo >=20 >=20 > > > > > > > > Thanks > > > > Liming > > > > =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io =E4=BB=A3=E8=A1=A8 Daniel > Schaefer > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8821=E6=97= =A5 20:46 > > =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io; gaoliming@byosoft.c= om.cn > > =E6=8A=84=E9=80=81: Chang, Abner (HPS SW/FW Technologist) ; > 'Michael > > D Kinney' ; 'Zhiguang Liu' > > ; 'Leif Lindholm' > > =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v1 1/1= ] Add MemoryFence > implementation > > for RiscV64 > > > > > > > > It's not required to go into that tag. > > > > We need two more patches that we haven't submitted yet to boot on > Qemu. > > > > > > > > Would it be okay if we used a library from ArmVirtPkg for RISCV64? > > > > See: > > > https://github.com/riscv/riscv-edk2/commit/8c7960ef860c65f2646912c3dcc > bb308a > > 98e0cc3 > > > > Or does it have to be moved to some other place first? > > > > _____ > > > > From: devel@edk2.groups.io > > > on behalf of > gaoliming > > > > > Sent: Friday, May 21, 2021 14:35 > > To: devel@edk2.groups.io > > >; Schaefer, Danie= l > > > > > Cc: Chang, Abner (HPS SW/FW Technologist) > >; 'Michael D Kinney' > > >; > 'Zhiguang > > Liu' >; 'Leif > > Lindholm' > > > Subject: =E5=9B=9E=E5=A4=8D: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v= 1 1/1] Add MemoryFence > > implementation for RiscV64 > > > > > > > > Daniel: > > > > Thanks for your information. Acked-by: Liming Gao > > > > > > > > > > > And, do you request to merge this patch for edk2 stable tag 202105? > > > > > > > > Thanks > > > > Liming > > > > =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io > > > =E4=BB=A3=E8=A1= =A8 Daniel > Schaefer > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8821=E6=97= =A5 13:27 > > =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io ; > > gaoliming@byosoft.com.cn > > =E6=8A=84=E9=80=81: Chang, Abner (HPS SW/FW Technologist) > >; 'Michael D Kinney' > > >; > 'Zhiguang > > Liu' >; 'Leif > > Lindholm' > > > =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v1 1/1= ] Add MemoryFence > implementation > > for RiscV64 > > > > > > > > Great! > > > > > > > > It is verified I can boot Linux from a virtio ESP using this patch on = QEMU > > virt machine. > > > > See: > > > https://github.com/riscv/riscv-edk2-platforms/runs/2618819010?check_suit= e > _fo > > cus=3Dtrue > > > > > > > > Thanks, > > > > Daniel > > > > _____ > > > > From: devel@edk2.groups.io > > > on behalf of > gaoliming > > > > > Sent: Friday, May 21, 2021 13:14 > > To: devel@edk2.groups.io > > >; Schaefer, Danie= l > > > > > Cc: Chang, Abner (HPS SW/FW Technologist) > >; 'Michael D Kinney' > > >; > 'Zhiguang > > Liu' >; 'Leif > > Lindholm' > > > Subject: =E5=9B=9E=E5=A4=8D: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v= 1 1/1] Add MemoryFence > > implementation for RiscV64 > > > > > > > > Daniel: > > Now, it is clear to me. So, I suggest to merge this change when it i= s > > verified on generic RISC-V QEMU virt machine. Is it OK? > > > > Thanks > > Liming > >> -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > >> =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io > > > =E4=BB=A3=E8=A1= =A8 Daniel > >> Schaefer > >> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8818=E6=97= = =A5 10:35 > >> =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io ; > > gaoliming@byosoft.com.cn > >> =E6=8A=84=E9=80=81: 'Abner Chang' >; > > 'Michael D Kinney' > >> >; > > 'Zhiguang Liu' = >; > > 'Leif > >> Lindholm' > > >> =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v1 1/= 1] Add MemoryFence > >> implementation for RiscV64 > >> > >> On 5/18/21 9:04 AM, gaoliming wrote: > >>> Daniel: > >>> Seemly, this API is missing in BaseLib for RiscV64 arch. How do you > > detect > >>> this issue? > >> > >> What do you mean it's missing? > >> Yes MemoryFence() for RiscV64 is missing currently, that's why I'm ad= ding > > it > >> here. > >> > >> Maybe you mean that it's not currently used? That's also true. > >> I'm enabling the generic QEMU virt machine (like OVMF or ArmVirtPkg) = for > >> RISC-V. > >> At least QemuFwCfgLib and VirtioLib need it. > >> That's why I have the need to add this implementation now. > >> > >> Does that clear it up? > >> > >>> Thanks > >>> Liming > >>>> -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > >>>> =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io > > > =E4=BB=A3=E8=A1= =A8 Daniel > >>>> Schaefer > >>>> =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8816=E6= =97=A5 2:13 > >>>> =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io > >>>> =E6=8A=84=E9=80=81: Abner Chang >; > > Michael D Kinney > >>>> >; > > Liming Gao >; > >>>> Zhiguang Liu >; > > Leif Lindholm > > > > >>>> =E4=B8=BB=E9=A2=98: [edk2-devel] [PATCH v1 1/1] Add MemoryFence imp= lementation > for > >>>> RiscV64 > >>>> > >>>> Cc: Abner Chang > > >>>> Cc: Michael D Kinney > > > >>>> Cc: Liming Gao > cn> > > >>>> Cc: Zhiguang Liu > > > >>>> Cc: Leif Lindholm > > >>>> Signed-off-by: Daniel Schaefer > schaefer@hpe.com> > > >>>> --- > >>>> MdePkg/Library/BaseLib/BaseLib.inf | 1 + > >>>> MdePkg/Library/BaseLib/RiscV64/MemoryFence.S | 33 > >>>> ++++++++++++++++++++ > >>>> 2 files changed, 34 insertions(+) > >>>> > >>>> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf > >>>> b/MdePkg/Library/BaseLib/BaseLib.inf > >>>> index b76f3af380ea..b7ab5f632366 100644 > >>>> --- a/MdePkg/Library/BaseLib/BaseLib.inf > >>>> +++ b/MdePkg/Library/BaseLib/BaseLib.inf > >>>> @@ -399,6 +399,7 @@ > >>>> RiscV64/DisableInterrupts.c > >>>> > >>>> > >>>> RiscV64/EnableInterrupts.c > >>>> > >>>> > >>>> RiscV64/CpuPause.c > >>>> > >>>> > >>>> + RiscV64/MemoryFence.S | GCC > >>>> > >>>> > >>>> RiscV64/RiscVSetJumpLongJump.S | GCC > >>>> > >>>> > >>>> RiscV64/RiscVCpuBreakpoint.S | GCC > >>>> > >>>> > >>>> RiscV64/RiscVCpuPause.S | GCC > >>>> > >>>> > >>>> diff --git a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S > >>>> b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S > >>>> new file mode 100644 > >>>> index 000000000000..283df9356a9a > >>>> --- /dev/null > >>>> +++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S > >>>> @@ -0,0 +1,33 @@ > >>>> > >>> > > +##-------------------------------------------------------------------= ------ > >>> ----- > >>>> > >>>> > >>>> +# > >>>> > >>>> > >>>> +# MemoryFence() for RiscV64 > >>>> > >>>> > >>>> + > >>>> > >>>> > >>>> +# Copyright (c) 2021, Hewlett Packard Enterprise Development. All > > rights > >>>> reserved. > >>>> > >>>> > >>>> +# > >>>> > >>>> > >>>> +# SPDX-License-Identifier: BSD-2-Clause-Patent > >>>> > >>>> > >>>> +# > >>>> > >>>> > >>>> > >>> > > +##-------------------------------------------------------------------= ------ > >>> ----- > >>>> > >>>> > >>>> + > >>>> > >>>> > >>>> +.text > >>>> > >>>> > >>>> +.p2align 2 > >>>> > >>>> > >>>> + > >>>> > >>>> > >>>> +ASM_GLOBAL ASM_PFX(MemoryFence) > >>>> > >>>> > >>>> + > >>>> > >>>> > >>>> + > >>>> > >>>> > >>>> +#/** > >>>> > >>>> > >>>> +# Used to serialize load and store operations. > >>>> > >>>> > >>>> +# > >>>> > >>>> > >>>> +# All loads and stores that proceed calls to this function are > >>> guaranteed to > >>>> be > >>>> > >>>> > >>>> +# globally visible when this function returns. > >>>> > >>>> > >>>> +# > >>>> > >>>> > >>>> +#**/ > >>>> > >>>> > >>>> +#VOID > >>>> > >>>> > >>>> +#EFIAPI > >>>> > >>>> > >>>> +#MemoryFence ( > >>>> > >>>> > >>>> +# VOID > >>>> > >>>> > >>>> +# ); > >>>> > >>>> > >>>> +# > >>>> > >>>> > >>>> +ASM_PFX(MemoryFence): > >>>> > >>>> > >>>> + // Fence on all memory and I/O > >>>> > >>>> > >>>> + fence > >>>> > >>>> > >>>> + ret > >>>> > >>>> > >>>> -- > >>>> 2.30.1 > >>>> > >>>> > >>>> > >>>> > >>>> > >>> > >>> > >>> > >>> > >>> > >>> > >>> > >>> > >> > >> > >> > >> > > > > > > > > > > > > > > > > > > > > > > >=20 >=20 >=20 >=20 >=20