From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from walk.intel-email.com (walk.intel-email.com [101.227.64.242]) by mx.groups.io with SMTP id smtpd.web08.7051.1663223261244332395 for ; Wed, 14 Sep 2022 23:27:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@byosoft.com.cn header.s=cloud-union header.b=Kh8DT1Vz; spf=pass (domain: byosoft.com.cn, ip: 101.227.64.242, mailfrom: gaoliming@byosoft.com.cn) Received: from walk.intel-email.com (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id A7F22CD1F74B for ; Thu, 15 Sep 2022 14:27:37 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=byosoft.com.cn; s=cloud-union; t=1663223257; bh=FwJ53rjrcpZQOuSIqZT1w3gkphuM6hxG3JK5+kcH1FY=; h=From:To:Cc:References:In-Reply-To:Subject:Date; b=Kh8DT1VzdHyKmtqy8m7N5ucZIjU9lTlqFAKKt5bEZc/HGKqzw1WzuH81pRyrAlmFQ ch515wj331rQFORlPVHdeqacvzOQ6bRYgQY8F8+vs21fzvlp0V0D2JquwmP13uaxfO IPXEgGE9XGm/u6EH44ByeUO2r1Btl0Hsr3FAC8Z8= Received: from localhost (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id A06A8CD1F740 for ; Thu, 15 Sep 2022 14:27:37 +0800 (CST) X-Virus-Scanned: by SpamTitan at intel-email.com Received: from walk.intel-email.com (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id 40A37CD1F6EF for ; Thu, 15 Sep 2022 14:27:37 +0800 (CST) Authentication-Results: walk.intel-email.com; none Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by walk.intel-email.com (Postfix) with SMTP id B9EFBCD1F713 for ; Thu, 15 Sep 2022 14:27:33 +0800 (CST) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Thu, 15 Sep 2022 14:27:31 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: "'Chao Li'" , Cc: "'Bob Feng'" , "'Yuwei Chen'" , "'Dongyan Qian'" , "'Baoqi Zhang'" , "'Yang Zhou'" , "'Xiaotian Wu'" References: <20220914094019.3696219-1-lichao@loongson.cn> In-Reply-To: <20220914094019.3696219-1-lichao@loongson.cn> Subject: =?UTF-8?B?5Zue5aSNOiBbUEFUQ0ggdjIgMTUvMzRdIEJhc2VUb29sczogQmFzZVRvb2xzIGNoYW5nZXMgZm9yIExvb25nQXJjaCBwbGF0Zm9ybS4=?= Date: Thu, 15 Sep 2022 14:27:33 +0800 Message-ID: <003901d8c8cc$3d40cc50$b7c264f0$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIq47bcvh3rnVp2QNtwJlvVWUqPVq07x+tQ Sender: "gaoliming" Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Chao: This change is for BaseTools C tools . The commit message can be BaseTools: Update GenFw/GenFv to support LoongArch platform. The code change is good to me. Reviewed-by: Liming Gao = Thanks Liming > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: Chao Li > =B7=A2=CB=CD=CA=B1=BC=E4: 2022=C4=EA9=D4=C214=C8=D5 17:40 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io > =B3=AD=CB=CD: Bob Feng ; Liming Gao > ; Yuwei Chen ; > Dongyan Qian ; Baoqi Zhang > ; Yang Zhou ; Xiaotian > Wu > =D6=F7=CC=E2: [PATCH v2 15/34] BaseTools: BaseTools changes for = LoongArch > platform. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053 >=20 > C code changes for building EDK2 LoongArch platform. >=20 > For definitions of PE/COFF and LOONGARCH relocation types, see the > "Machine Types" and "Basic Relocation Types" sections of this URL for > LOONGARCH values: > https://docs.microsoft.com/en-us/windows/win32/debug/pe-format >=20 > Cc: Bob Feng > Cc: Liming Gao > Cc: Yuwei Chen >=20 > Signed-off-by: Chao Li > Co-authored-by: Dongyan Qian > Co-authored-by: Baoqi Zhang > Co-authored-by: Yang Zhou > Co-authored-by: Xiaotian Wu > --- > BaseTools/Source/C/Common/BasePeCoff.c | 15 +- > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 79 +++++ > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 125 +++++++- > BaseTools/Source/C/GenFw/Elf64Convert.c | 293 > +++++++++++++++++- > BaseTools/Source/C/GenFw/elf_common.h | 94 ++++++ > .../C/Include/IndustryStandard/PeImage.h | 57 ++-- > BaseTools/Source/C/Makefiles/header.makefile | 6 + > 7 files changed, 636 insertions(+), 33 deletions(-) >=20 > diff --git a/BaseTools/Source/C/Common/BasePeCoff.c > b/BaseTools/Source/C/Common/BasePeCoff.c > index 62fbb2985c..30400d1341 100644 > --- a/BaseTools/Source/C/Common/BasePeCoff.c > +++ b/BaseTools/Source/C/Common/BasePeCoff.c > @@ -5,6 +5,7 @@ > Copyright (c) 2004 - 2018, Intel Corporation. All rights = reserved.
>=20 > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
>=20 > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development = LP. All > rights reserved.
>=20 > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -68,6 +69,14 @@ PeCoffLoaderRelocateRiscVImage ( > IN UINT64 Adjust >=20 > ); >=20 >=20 >=20 > +RETURN_STATUS >=20 > +PeCoffLoaderRelocateLoongArch64Image ( >=20 > + IN UINT16 *Reloc, >=20 > + IN OUT CHAR8 *Fixup, >=20 > + IN OUT CHAR8 **FixupData, >=20 > + IN UINT64 Adjust >=20 > + ); >=20 > + >=20 > STATIC >=20 > RETURN_STATUS >=20 > PeCoffLoaderGetPeHeader ( >=20 > @@ -184,7 +193,8 @@ Returns: > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \ >=20 > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \ >=20 > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \ >=20 > - ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64) { >=20 > + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64 && \ >=20 > + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_LOONGARCH64) > { >=20 > if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) { >=20 > // >=20 > // There are two types of ARM images. Pure ARM and ARM/Thumb. >=20 > @@ -815,6 +825,9 @@ Returns: > case EFI_IMAGE_MACHINE_RISCV64: >=20 > Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, > &FixupData, Adjust); >=20 > break; >=20 > + case EFI_IMAGE_MACHINE_LOONGARCH64: >=20 > + Status =3D PeCoffLoaderRelocateLoongArch64Image (Reloc, = Fixup, > &FixupData, Adjust); >=20 > + break; >=20 > default: >=20 > Status =3D RETURN_UNSUPPORTED; >=20 > break; >=20 > diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c > b/BaseTools/Source/C/Common/PeCoffLoaderEx.c > index 799f282970..2cc428d733 100644 > --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c > +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c > @@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups > Copyright (c) 2004 - 2018, Intel Corporation. All rights = reserved.
>=20 > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
>=20 > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All = rights > reserved.
>=20 > +Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights > reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > --*/ >=20 > @@ -332,3 +333,81 @@ PeCoffLoaderRelocateArmImage ( >=20 >=20 > return RETURN_SUCCESS; >=20 > } >=20 > + >=20 > +/** >=20 > + Performs a LoongArch specific relocation fixup. >=20 > + >=20 > + @param[in] Reloc Pointer to the relocation record. >=20 > + @param[in, out] Fixup Pointer to the address to fix up. >=20 > + @param[in, out] FixupData Pointer to a buffer to log the fixups. >=20 > + @param[in] Adjust The offset to adjust the fixup. >=20 > + >=20 > + @return Status code. >=20 > +**/ >=20 > +RETURN_STATUS >=20 > +PeCoffLoaderRelocateLoongArch64Image ( >=20 > + IN UINT16 *Reloc, >=20 > + IN OUT CHAR8 *Fixup, >=20 > + IN OUT CHAR8 **FixupData, >=20 > + IN UINT64 Adjust >=20 > + ) >=20 > +{ >=20 > + UINT8 RelocType; >=20 > + UINT64 Value; >=20 > + UINT64 Tmp1; >=20 > + UINT64 Tmp2; >=20 > + >=20 > + RelocType =3D ((*Reloc) >> 12); >=20 > + Value =3D 0; >=20 > + Tmp1 =3D 0; >=20 > + Tmp2 =3D 0; >=20 > + >=20 > + switch (RelocType) { >=20 > + case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA: >=20 > + // The next four instructions are used to load a 64 bit = address, > relocate all of them >=20 > + Value =3D (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // = lu12i.w > 20bits from bit5 >=20 > + (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori > 12bits from bit10 >=20 > + Tmp1 =3D *((UINT32 *)Fixup + 2) & 0x1ffffe0; // = lu32i.d > 20bits from bit5 >=20 > + Tmp2 =3D *((UINT32 *)Fixup + 3) & 0x3ffc00; // = lu52i.d > 12bits from bit10 >=20 > + Value =3D Value | (Tmp1 << 27) | (Tmp2 << 42); >=20 > + Value +=3D Adjust; >=20 > + >=20 > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value = >> 12) > & 0xfffff) << 5); >=20 > + if (*FixupData !=3D NULL) { >=20 > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > (UINT32)); >=20 > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; >=20 > + *FixupData =3D *FixupData + sizeof (UINT32); >=20 > + } >=20 > + >=20 > + Fixup +=3D sizeof (UINT32); >=20 > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xfff) > << 10); >=20 > + if (*FixupData !=3D NULL) { >=20 > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > (UINT32)); >=20 > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; >=20 > + *FixupData =3D *FixupData + sizeof (UINT32); >=20 > + } >=20 > + >=20 > + Fixup +=3D sizeof (UINT32); >=20 > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value = >> 32) > & 0xfffff) << 5); >=20 > + if (*FixupData !=3D NULL) { >=20 > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > (UINT32)); >=20 > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; >=20 > + *FixupData =3D *FixupData + sizeof (UINT32); >=20 > + } >=20 > + >=20 > + Fixup +=3D sizeof (UINT32); >=20 > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value = >> 52) > & 0xfff) << 10); >=20 > + if (*FixupData !=3D NULL) { >=20 > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > (UINT32)); >=20 > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; >=20 > + *FixupData =3D *FixupData + sizeof (UINT32); >=20 > + } >=20 > + >=20 > + break; >=20 > + default: >=20 > + Error (NULL, 0, 3000, "", = "PeCoffLoaderRelocateLoongArch64Image: > Fixup[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32 = *)Fixup, > Adjust, *Reloc, RelocType); >=20 > + return RETURN_UNSUPPORTED; >=20 > + } >=20 > + >=20 > + return RETURN_SUCCESS; >=20 > +} >=20 > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > index d650a527a5..575b99b6ad 100644 > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > @@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All = rights > reserved.
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
>=20 > Portions Copyright (c) 2016 HP Development Company, L.P.
>=20 > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development = LP. All > rights reserved.
>=20 > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -57,6 +58,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 > BOOLEAN mArm =3D FALSE; >=20 > BOOLEAN mRiscV =3D FALSE; >=20 > +BOOLEAN mLoongArch =3D FALSE; >=20 > STATIC UINT32 MaxFfsAlignment =3D 0; >=20 > BOOLEAN VtfFileFlag =3D FALSE; >=20 >=20 >=20 > @@ -2416,6 +2418,98 @@ Returns: > return EFI_SUCCESS; >=20 > } >=20 >=20 >=20 > +EFI_STATUS >=20 > +UpdateLoongArchResetVectorIfNeeded ( >=20 > + IN MEMORY_FILE *FvImage, >=20 > + IN FV_INFO *FvInfo >=20 > + ) >=20 > +/*++ >=20 > + >=20 > +Routine Description: >=20 > + This parses the FV looking for SEC and patches that address into = the >=20 > + beginning of the FV header. >=20 > + >=20 > + For LoongArch ISA, the reset vector is at 0x1c000000. >=20 > + >=20 > + We relocate it to SecCoreEntry and copy the ResetVector code to the >=20 > + beginning of the FV. >=20 > + >=20 > +Arguments: >=20 > + FvImage Memory file for the FV memory image >=20 > + FvInfo Information read from INF file. >=20 > + >=20 > +Returns: >=20 > + >=20 > + EFI_SUCCESS Function Completed successfully. >=20 > + EFI_ABORTED Error encountered. >=20 > + EFI_INVALID_PARAMETER A required parameter was NULL. >=20 > + EFI_NOT_FOUND PEI Core file not found. >=20 > + >=20 > +--*/ >=20 > +{ >=20 > + EFI_STATUS Status; >=20 > + EFI_FILE_SECTION_POINTER SecPe32; >=20 > + BOOLEAN UpdateVectorSec =3D FALSE; >=20 > + UINT16 MachineType =3D 0; >=20 > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress =3D 0; >=20 > + >=20 > + // >=20 > + // Verify input parameters >=20 > + // >=20 > + if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) { >=20 > + return EFI_INVALID_PARAMETER; >=20 > + } >=20 > + >=20 > + // >=20 > + // Locate an SEC Core instance and if found extract the machine = type and > entry point address >=20 > + // >=20 > + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, > EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32); >=20 > + if (!EFI_ERROR(Status)) { >=20 > + >=20 > + Status =3D GetCoreMachineType(SecPe32, &MachineType); >=20 > + if (EFI_ERROR(Status)) { >=20 > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type > for SEC Core."); >=20 > + return EFI_ABORTED; >=20 > + } >=20 > + >=20 > + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, > SecPe32, &SecCoreEntryAddress); >=20 > + if (EFI_ERROR(Status)) { >=20 > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry = point > address for SEC Core."); >=20 > + return EFI_ABORTED; >=20 > + } >=20 > + >=20 > + UpdateVectorSec =3D TRUE; >=20 > + } >=20 > + >=20 > + if (!UpdateVectorSec) >=20 > + return EFI_SUCCESS; >=20 > + >=20 > + if (MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) { >=20 > + UINT32 ResetVector[1]; >=20 > + >=20 > + memset(ResetVector, 0, sizeof (ResetVector)); >=20 > + >=20 > + /* if we found an SEC core entry point then generate a branch > instruction */ >=20 > + if (UpdateVectorSec) { >=20 > + VerboseMsg("UpdateLoongArchResetVectorIfNeeded updating > LOONGARCH64 SEC vector"); >=20 > + >=20 > + ResetVector[0] =3D ((SecCoreEntryAddress - FvInfo->BaseAddress) = & > 0x3FFFFFF) >> 2; >=20 > + ResetVector[0] =3D ((ResetVector[0] & 0x0FFFF) << 10) | > ((ResetVector[0] >> 16) & 0x3FF); >=20 > + ResetVector[0] |=3D 0x54000000; /* bl offset */ >=20 > + } >=20 > + >=20 > + // >=20 > + // Copy to the beginning of the FV >=20 > + // >=20 > + memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector)); >=20 > + } else { >=20 > + Error(NULL, 0, 3000, "Invalid", "Unknown machine type"); >=20 > + return EFI_ABORTED; >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > + >=20 > EFI_STATUS >=20 > GetPe32Info ( >=20 > IN UINT8 *Pe32, >=20 > @@ -2509,7 +2603,7 @@ Returns: > // >=20 > if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && > (*MachineType !=3D EFI_IMAGE_MACHINE_X64) && (*MachineType !=3D > EFI_IMAGE_MACHINE_EBC) && >=20 > (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && > (*MachineType !=3D EFI_IMAGE_MACHINE_AARCH64) && >=20 > - (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64)) { >=20 > + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) && > (*MachineType !=3D EFI_IMAGE_MACHINE_LOONGARCH64)) { >=20 > Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in = the PE32 > file."); >=20 > return EFI_UNSUPPORTED; >=20 > } >=20 > @@ -2953,7 +3047,7 @@ Returns: > goto Finish; >=20 > } >=20 >=20 >=20 > - if (!mArm && !mRiscV) { >=20 > + if (!mArm && !mRiscV && !mLoongArch) { >=20 > // >=20 > // Update reset vector (SALE_ENTRY for IPF) >=20 > // Now for IA32 and IA64 platform, the fv which has bsf file = must > have the >=20 > @@ -3004,6 +3098,19 @@ Returns: > FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, > FvHeader->HeaderLength / sizeof (UINT16)); >=20 > } >=20 >=20 >=20 > + if (mLoongArch) { >=20 > + Status =3D UpdateLoongArchResetVectorIfNeeded = (&FvImageMemoryFile, > &mFvDataInfo); >=20 > + if (EFI_ERROR (Status)) { >=20 > + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector."); >=20 > + goto Finish; >=20 > + } >=20 > + // >=20 > + // Update Checksum for FvHeader >=20 > + // >=20 > + FvHeader->Checksum =3D 0; >=20 > + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, > FvHeader->HeaderLength / sizeof (UINT16)); >=20 > + } >=20 > + >=20 > // >=20 > // Update FV Alignment attribute to the largest alignment of all = the FFS > files in the FV >=20 > // >=20 > @@ -3450,6 +3557,12 @@ Returns: > VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV"); >=20 > mArm =3D TRUE; >=20 > } >=20 > + >=20 > + // Machine type is LOONGARCH64, set a flag so LoongArch64 reset > vector processed. >=20 > + if ((MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)) { >=20 > + VerboseMsg("Located LoongArch64 SEC core in child FV"); >=20 > + mLoongArch =3D TRUE; >=20 > + } >=20 > } >=20 >=20 >=20 > // >=20 > @@ -3608,6 +3721,10 @@ Returns: > mRiscV =3D TRUE; >=20 > } >=20 >=20 >=20 > + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) = ) > { >=20 > + mLoongArch =3D TRUE; >=20 > + } >=20 > + >=20 > // >=20 > // Keep Image Context for PE image in FV >=20 > // >=20 > @@ -3885,6 +4002,10 @@ Returns: > mArm =3D TRUE; >=20 > } >=20 >=20 >=20 > + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) = ) > { >=20 > + mLoongArch =3D TRUE; >=20 > + } >=20 > + >=20 > // >=20 > // Keep Image Context for TE image in FV >=20 > // >=20 > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c > b/BaseTools/Source/C/GenFw/Elf64Convert.c > index ca3c8f8bee..ede2f0ef90 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -4,6 +4,7 @@ Elf64 convert solution > Copyright (c) 2010 - 2021, Intel Corporation. All rights = reserved.
>=20 > Portions copyright (c) 2013-2022, ARM Ltd. All rights reserved.
>=20 > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development = LP. All > rights reserved.
>=20 > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > rights reserved.
>=20 >=20 >=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > @@ -177,7 +178,7 @@ InitializeElf64 ( > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or > ET_DYN"); >=20 > return FALSE; >=20 > } >=20 > - if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine = =3D=3D > EM_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) { >=20 > + if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine = =3D=3D > EM_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64) || > (mEhdr->e_machine =3D=3D EM_LOONGARCH))) { >=20 > Warning (NULL, 0, 3000, "Unsupported", "ELF e_machine is not = Elf64 > machine."); >=20 > } >=20 > if (mEhdr->e_version !=3D EV_CURRENT) { >=20 > @@ -799,6 +800,7 @@ ScanSections64 ( > case EM_X86_64: >=20 > case EM_AARCH64: >=20 > case EM_RISCV64: >=20 > + case EM_LOONGARCH: >=20 > mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64); >=20 > break; >=20 > default: >=20 > @@ -1088,6 +1090,10 @@ ScanSections64 ( > NtHdr->Pe32Plus.FileHeader.Machine =3D > EFI_IMAGE_MACHINE_RISCV64; >=20 > NtHdr->Pe32Plus.OptionalHeader.Magic =3D > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC; >=20 > break; >=20 > + case EM_LOONGARCH: >=20 > + NtHdr->Pe32Plus.FileHeader.Machine =3D > EFI_IMAGE_MACHINE_LOONGARCH64; >=20 > + NtHdr->Pe32Plus.OptionalHeader.Magic =3D > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC; >=20 > + break; >=20 >=20 >=20 > default: >=20 > VerboseMsg ("%s unknown e_machine type. Assume X64", > (UINTN)mEhdr->e_machine); >=20 > @@ -1333,10 +1339,10 @@ WriteSections64 ( > } >=20 >=20 >=20 > // >=20 > - // Skip error on EM_RISCV64 becasue no symble name is built >=20 > - // from RISC-V toolchain. >=20 > + // Skip error on EM_RISCV64 and EM_LOONGARCH because no > symbol name is built >=20 > + // from RISC-V and LoongArch toolchain. >=20 > // >=20 > - if (mEhdr->e_machine !=3D EM_RISCV64) { >=20 > + if ((mEhdr->e_machine !=3D EM_RISCV64) && > (mEhdr->e_machine !=3D EM_LOONGARCH)) { >=20 > Error (NULL, 0, 3000, "Invalid", >=20 > "%s: Bad definition for symbol '%s'@%#llx or > unsupported symbol type. " >=20 > "For example, absolute and undefined symbols are > not supported.", >=20 > @@ -1618,6 +1624,178 @@ WriteSections64 ( > // Write section for RISC-V 64 architecture. >=20 > // >=20 > WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym); >=20 > + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) { >=20 > + switch (ELF_R_TYPE(Rel->r_info)) { >=20 > + INT64 Offset; >=20 > + INT32 Lo, Hi; >=20 > + >=20 > + case R_LARCH_SOP_PUSH_ABSOLUTE: >=20 > + // >=20 > + // Absolute relocation. >=20 > + // >=20 > + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + > mCoffSectionsOffset[Sym->st_shndx]; >=20 > + break; >=20 > + >=20 > + case R_LARCH_MARK_LA: >=20 > + case R_LARCH_64: >=20 > + case R_LARCH_NONE: >=20 > + case R_LARCH_32: >=20 > + case R_LARCH_RELATIVE: >=20 > + case R_LARCH_COPY: >=20 > + case R_LARCH_JUMP_SLOT: >=20 > + case R_LARCH_TLS_DTPMOD32: >=20 > + case R_LARCH_TLS_DTPMOD64: >=20 > + case R_LARCH_TLS_DTPREL32: >=20 > + case R_LARCH_TLS_DTPREL64: >=20 > + case R_LARCH_TLS_TPREL32: >=20 > + case R_LARCH_TLS_TPREL64: >=20 > + case R_LARCH_IRELATIVE: >=20 > + case R_LARCH_MARK_PCREL: >=20 > + case R_LARCH_SOP_PUSH_PCREL: >=20 > + case R_LARCH_SOP_PUSH_DUP: >=20 > + case R_LARCH_SOP_PUSH_GPREL: >=20 > + case R_LARCH_SOP_PUSH_TLS_TPREL: >=20 > + case R_LARCH_SOP_PUSH_TLS_GOT: >=20 > + case R_LARCH_SOP_PUSH_TLS_GD: >=20 > + case R_LARCH_SOP_PUSH_PLT_PCREL: >=20 > + case R_LARCH_SOP_ASSERT: >=20 > + case R_LARCH_SOP_NOT: >=20 > + case R_LARCH_SOP_SUB: >=20 > + case R_LARCH_SOP_SL: >=20 > + case R_LARCH_SOP_SR: >=20 > + case R_LARCH_SOP_ADD: >=20 > + case R_LARCH_SOP_AND: >=20 > + case R_LARCH_SOP_IF_ELSE: >=20 > + case R_LARCH_SOP_POP_32_S_10_5: >=20 > + case R_LARCH_SOP_POP_32_U_10_12: >=20 > + case R_LARCH_SOP_POP_32_S_10_12: >=20 > + case R_LARCH_SOP_POP_32_S_10_16: >=20 > + case R_LARCH_SOP_POP_32_S_10_16_S2: >=20 > + case R_LARCH_SOP_POP_32_S_5_20: >=20 > + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: >=20 > + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: >=20 > + case R_LARCH_SOP_POP_32_U: >=20 > + case R_LARCH_ADD8: >=20 > + case R_LARCH_ADD16: >=20 > + case R_LARCH_ADD24: >=20 > + case R_LARCH_ADD32: >=20 > + case R_LARCH_ADD64: >=20 > + case R_LARCH_SUB8: >=20 > + case R_LARCH_SUB16: >=20 > + case R_LARCH_SUB24: >=20 > + case R_LARCH_SUB32: >=20 > + case R_LARCH_SUB64: >=20 > + case R_LARCH_GNU_VTINHERIT: >=20 > + case R_LARCH_GNU_VTENTRY: >=20 > + case R_LARCH_B16: >=20 > + case R_LARCH_B21: >=20 > + case R_LARCH_B26: >=20 > + case R_LARCH_ABS_HI20: >=20 > + case R_LARCH_ABS_LO12: >=20 > + case R_LARCH_ABS64_LO20: >=20 > + case R_LARCH_ABS64_HI12: >=20 > + case R_LARCH_PCALA_LO12: >=20 > + case R_LARCH_PCALA64_LO20: >=20 > + case R_LARCH_PCALA64_HI12: >=20 > + case R_LARCH_GOT_PC_LO12: >=20 > + case R_LARCH_GOT64_PC_LO20: >=20 > + case R_LARCH_GOT64_PC_HI12: >=20 > + case R_LARCH_GOT64_HI20: >=20 > + case R_LARCH_GOT64_LO12: >=20 > + case R_LARCH_GOT64_LO20: >=20 > + case R_LARCH_GOT64_HI12: >=20 > + case R_LARCH_TLS_LE_HI20: >=20 > + case R_LARCH_TLS_LE_LO12: >=20 > + case R_LARCH_TLS_LE64_LO20: >=20 > + case R_LARCH_TLS_LE64_HI12: >=20 > + case R_LARCH_TLS_IE_PC_HI20: >=20 > + case R_LARCH_TLS_IE_PC_LO12: >=20 > + case R_LARCH_TLS_IE64_PC_LO20: >=20 > + case R_LARCH_TLS_IE64_PC_HI12: >=20 > + case R_LARCH_TLS_IE64_HI20: >=20 > + case R_LARCH_TLS_IE64_LO12: >=20 > + case R_LARCH_TLS_IE64_LO20: >=20 > + case R_LARCH_TLS_IE64_HI12: >=20 > + case R_LARCH_TLS_LD_PC_HI20: >=20 > + case R_LARCH_TLS_LD64_HI20: >=20 > + case R_LARCH_TLS_GD_PC_HI20: >=20 > + case R_LARCH_TLS_GD64_HI20: >=20 > + case R_LARCH_RELAX: >=20 > + // >=20 > + // These types are not used or do not require fixup. >=20 > + // >=20 > + break; >=20 > + >=20 > + case R_LARCH_GOT_PC_HI20: >=20 > + Offset =3D Sym->st_value - (UINTN)(Targ - mCoffFile); >=20 > + if (Offset < 0) { >=20 > + Offset =3D (UINTN)(Targ - mCoffFile) - Sym->st_value; >=20 > + Hi =3D (Offset / 0x1000) << 12; >=20 > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; >=20 > + if ((Lo < 0) && (Lo > -2048)) { >=20 > + Hi +=3D 0x1000; >=20 > + Lo =3D ~(0x1000 - Lo) + 1; >=20 > + } >=20 > + Hi =3D ~Hi + 1; >=20 > + Lo =3D ~Lo + 1; >=20 > + } else { >=20 > + Hi =3D (Offset / 0x1000) << 12; >=20 > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; >=20 > + if (Lo < 0) { >=20 > + Hi +=3D 0x1000; >=20 > + Lo =3D ~(0x1000 - Lo) + 1; >=20 > + } >=20 > + } >=20 > + // Re-encode the offset as an PCADD.D + ADDI.D(Convert > LD.D) instruction >=20 > + *(UINT32 *)Targ &=3D 0x1f; >=20 > + *(UINT32 *)Targ |=3D 0x1c000000; >=20 > + *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5); >=20 > + *(UINT32 *)(Targ + 4) &=3D 0x3ff; >=20 > + *(UINT32 *)(Targ + 4) |=3D 0x2c00000 | ((Lo & 0xfff) << = 10); >=20 > + break; >=20 > + >=20 > + // >=20 > + // Attempt to convert instruction. >=20 > + // >=20 > + case R_LARCH_PCALA_HI20: >=20 > + // Decode the PCALAU12I + ADDI.D instruction >=20 > + Offset =3D ((INT32)((*(UINT32 *)Targ & 0x1ffffe0) << 7)); >=20 > + Offset +=3D ((INT32)((*(UINT32 *)(Targ + 4) & 0x3ffc00) = << 10) >> > 20); >=20 > + // >=20 > + // PCALA offset is relative to the previous page = boundary, >=20 > + // whereas PCADD offset is relative to the instruction itself. >=20 > + // So fix up the offset so it points to the page = containing >=20 > + // the symbol. >=20 > + // >=20 > + Offset -=3D (UINTN)(Targ - mCoffFile) & 0xfff; >=20 > + if (Offset < 0) { >=20 > + Offset =3D -Offset; >=20 > + Hi =3D (Offset / 0x1000) << 12; >=20 > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; >=20 > + if ((Lo < 0) && (Lo > -2048)) { >=20 > + Hi +=3D 0x1000; >=20 > + Lo =3D ~(0x1000 - Lo) + 1; >=20 > + } >=20 > + Hi =3D ~Hi + 1; >=20 > + Lo =3D ~Lo + 1; >=20 > + } else { >=20 > + Hi =3D (Offset / 0x1000) << 12; >=20 > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; >=20 > + if (Lo < 0) { >=20 > + Hi +=3D 0x1000; >=20 > + Lo =3D ~(0x1000 - Lo) + 1; >=20 > + } >=20 > + } >=20 > + // Re-encode the offset as an PCADD.D + ADDI.D = instruction >=20 > + *(UINT32 *)Targ &=3D 0x1f; >=20 > + *(UINT32 *)Targ |=3D 0x1c000000; >=20 > + *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5); >=20 > + *(UINT32 *)(Targ + 4) &=3D 0xffc003ff; >=20 > + *(UINT32 *)(Targ + 4) |=3D (Lo & 0xfff) << 10; >=20 > + break; >=20 > + default: >=20 > + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s > unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, > (unsigned) ELF64_R_TYPE(Rel->r_info)); >=20 > + } >=20 > } else { >=20 > Error (NULL, 0, 3000, "Invalid", "Not a supported machine > type"); >=20 > } >=20 > @@ -1850,6 +2028,113 @@ WriteRelocations64 ( > default: >=20 > Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): = %s > unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) > ELF_R_TYPE(Rel->r_info)); >=20 > } >=20 > + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) { >=20 > + switch (ELF_R_TYPE(Rel->r_info)) { >=20 > + case R_LARCH_MARK_LA: >=20 > + CoffAddFixup( >=20 > + (UINT32) ((UINT64) > mCoffSectionsOffset[RelShdr->sh_info] >=20 > + + (Rel->r_offset - SecShdr->sh_addr)), >=20 > + EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA); >=20 > + break; >=20 > + case R_LARCH_64: >=20 > + CoffAddFixup( >=20 > + (UINT32) ((UINT64) > mCoffSectionsOffset[RelShdr->sh_info] >=20 > + + (Rel->r_offset - SecShdr->sh_addr)), >=20 > + EFI_IMAGE_REL_BASED_DIR64); >=20 > + break; >=20 > + case R_LARCH_NONE: >=20 > + case R_LARCH_32: >=20 > + case R_LARCH_RELATIVE: >=20 > + case R_LARCH_COPY: >=20 > + case R_LARCH_JUMP_SLOT: >=20 > + case R_LARCH_TLS_DTPMOD32: >=20 > + case R_LARCH_TLS_DTPMOD64: >=20 > + case R_LARCH_TLS_DTPREL32: >=20 > + case R_LARCH_TLS_DTPREL64: >=20 > + case R_LARCH_TLS_TPREL32: >=20 > + case R_LARCH_TLS_TPREL64: >=20 > + case R_LARCH_IRELATIVE: >=20 > + case R_LARCH_MARK_PCREL: >=20 > + case R_LARCH_SOP_PUSH_PCREL: >=20 > + case R_LARCH_SOP_PUSH_ABSOLUTE: >=20 > + case R_LARCH_SOP_PUSH_DUP: >=20 > + case R_LARCH_SOP_PUSH_GPREL: >=20 > + case R_LARCH_SOP_PUSH_TLS_TPREL: >=20 > + case R_LARCH_SOP_PUSH_TLS_GOT: >=20 > + case R_LARCH_SOP_PUSH_TLS_GD: >=20 > + case R_LARCH_SOP_PUSH_PLT_PCREL: >=20 > + case R_LARCH_SOP_ASSERT: >=20 > + case R_LARCH_SOP_NOT: >=20 > + case R_LARCH_SOP_SUB: >=20 > + case R_LARCH_SOP_SL: >=20 > + case R_LARCH_SOP_SR: >=20 > + case R_LARCH_SOP_ADD: >=20 > + case R_LARCH_SOP_AND: >=20 > + case R_LARCH_SOP_IF_ELSE: >=20 > + case R_LARCH_SOP_POP_32_S_10_5: >=20 > + case R_LARCH_SOP_POP_32_U_10_12: >=20 > + case R_LARCH_SOP_POP_32_S_10_12: >=20 > + case R_LARCH_SOP_POP_32_S_10_16: >=20 > + case R_LARCH_SOP_POP_32_S_10_16_S2: >=20 > + case R_LARCH_SOP_POP_32_S_5_20: >=20 > + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: >=20 > + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: >=20 > + case R_LARCH_SOP_POP_32_U: >=20 > + case R_LARCH_ADD8: >=20 > + case R_LARCH_ADD16: >=20 > + case R_LARCH_ADD24: >=20 > + case R_LARCH_ADD32: >=20 > + case R_LARCH_ADD64: >=20 > + case R_LARCH_SUB8: >=20 > + case R_LARCH_SUB16: >=20 > + case R_LARCH_SUB24: >=20 > + case R_LARCH_SUB32: >=20 > + case R_LARCH_SUB64: >=20 > + case R_LARCH_GNU_VTINHERIT: >=20 > + case R_LARCH_GNU_VTENTRY: >=20 > + case R_LARCH_B16: >=20 > + case R_LARCH_B21: >=20 > + case R_LARCH_B26: >=20 > + case R_LARCH_ABS_HI20: >=20 > + case R_LARCH_ABS_LO12: >=20 > + case R_LARCH_ABS64_LO20: >=20 > + case R_LARCH_ABS64_HI12: >=20 > + case R_LARCH_PCALA_HI20: >=20 > + case R_LARCH_PCALA_LO12: >=20 > + case R_LARCH_PCALA64_LO20: >=20 > + case R_LARCH_PCALA64_HI12: >=20 > + case R_LARCH_GOT_PC_HI20: >=20 > + case R_LARCH_GOT_PC_LO12: >=20 > + case R_LARCH_GOT64_PC_LO20: >=20 > + case R_LARCH_GOT64_PC_HI12: >=20 > + case R_LARCH_GOT64_HI20: >=20 > + case R_LARCH_GOT64_LO12: >=20 > + case R_LARCH_GOT64_LO20: >=20 > + case R_LARCH_GOT64_HI12: >=20 > + case R_LARCH_TLS_LE_HI20: >=20 > + case R_LARCH_TLS_LE_LO12: >=20 > + case R_LARCH_TLS_LE64_LO20: >=20 > + case R_LARCH_TLS_LE64_HI12: >=20 > + case R_LARCH_TLS_IE_PC_HI20: >=20 > + case R_LARCH_TLS_IE_PC_LO12: >=20 > + case R_LARCH_TLS_IE64_PC_LO20: >=20 > + case R_LARCH_TLS_IE64_PC_HI12: >=20 > + case R_LARCH_TLS_IE64_HI20: >=20 > + case R_LARCH_TLS_IE64_LO12: >=20 > + case R_LARCH_TLS_IE64_LO20: >=20 > + case R_LARCH_TLS_IE64_HI12: >=20 > + case R_LARCH_TLS_LD_PC_HI20: >=20 > + case R_LARCH_TLS_LD64_HI20: >=20 > + case R_LARCH_TLS_GD_PC_HI20: >=20 > + case R_LARCH_TLS_GD64_HI20: >=20 > + case R_LARCH_RELAX: >=20 > + // >=20 > + // These types are not used or do not require fixup = in PE > format files. >=20 > + // >=20 > + break; >=20 > + default: >=20 > + Error (NULL, 0, 3000, "Invalid", > "WriteRelocations64(): %s unsupported ELF EM_LOONGARCH relocation > 0x%x.", mInImageName, (unsigned) ELF64_R_TYPE(Rel->r_info)); >=20 > + } >=20 > } else { >=20 > Error (NULL, 0, 3000, "Not Supported", "This tool does = not > support relocations for ELF with e_machine %u (processor type).", (unsigned) > mEhdr->e_machine); >=20 > } >=20 > diff --git a/BaseTools/Source/C/GenFw/elf_common.h > b/BaseTools/Source/C/GenFw/elf_common.h > index b67f59e7a0..7b7fdeb329 100644 > --- a/BaseTools/Source/C/GenFw/elf_common.h > +++ b/BaseTools/Source/C/GenFw/elf_common.h > @@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD > Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
>=20 > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
>=20 > Portion Copyright (c) 2020, Hewlett Packard Enterprise Development = LP. All > rights reserved.
>=20 > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 >=20 >=20 > @@ -181,6 +182,7 @@ typedef struct { > #define EM_AARCH64 183 /* ARM 64bit Architecture */ >=20 > #define EM_RISCV64 243 /* 64bit RISC-V Architecture */ >=20 > #define EM_RISCV 244 /* 32bit RISC-V Architecture */ >=20 > +#define EM_LOONGARCH 258 /* LoongArch Architecture */ >=20 >=20 >=20 > /* Non-standard or deprecated. */ >=20 > #define EM_486 6 /* Intel i486. */ >=20 > @@ -1042,4 +1044,96 @@ typedef struct { > #define R_RISCV_SET8 54 >=20 > #define R_RISCV_SET16 55 >=20 > #define R_RISCV_SET32 56 >=20 > + >=20 > +/* >=20 > + * LoongArch relocation types >=20 > + */ >=20 > +#define R_LARCH_NONE 0 >=20 > +#define R_LARCH_32 1 >=20 > +#define R_LARCH_64 2 >=20 > +#define R_LARCH_RELATIVE 3 >=20 > +#define R_LARCH_COPY 4 >=20 > +#define R_LARCH_JUMP_SLOT 5 >=20 > +#define R_LARCH_TLS_DTPMOD32 6 >=20 > +#define R_LARCH_TLS_DTPMOD64 7 >=20 > +#define R_LARCH_TLS_DTPREL32 8 >=20 > +#define R_LARCH_TLS_DTPREL64 9 >=20 > +#define R_LARCH_TLS_TPREL32 10 >=20 > +#define R_LARCH_TLS_TPREL64 11 >=20 > +#define R_LARCH_IRELATIVE 12 >=20 > +#define R_LARCH_MARK_LA 20 >=20 > +#define R_LARCH_MARK_PCREL 21 >=20 > +#define R_LARCH_SOP_PUSH_PCREL 22 >=20 > +#define R_LARCH_SOP_PUSH_ABSOLUTE 23 >=20 > +#define R_LARCH_SOP_PUSH_DUP 24 >=20 > +#define R_LARCH_SOP_PUSH_GPREL 25 >=20 > +#define R_LARCH_SOP_PUSH_TLS_TPREL 26 >=20 > +#define R_LARCH_SOP_PUSH_TLS_GOT 27 >=20 > +#define R_LARCH_SOP_PUSH_TLS_GD 28 >=20 > +#define R_LARCH_SOP_PUSH_PLT_PCREL 29 >=20 > +#define R_LARCH_SOP_ASSERT 30 >=20 > +#define R_LARCH_SOP_NOT 31 >=20 > +#define R_LARCH_SOP_SUB 32 >=20 > +#define R_LARCH_SOP_SL 33 >=20 > +#define R_LARCH_SOP_SR 34 >=20 > +#define R_LARCH_SOP_ADD 35 >=20 > +#define R_LARCH_SOP_AND 36 >=20 > +#define R_LARCH_SOP_IF_ELSE 37 >=20 > +#define R_LARCH_SOP_POP_32_S_10_5 38 >=20 > +#define R_LARCH_SOP_POP_32_U_10_12 39 >=20 > +#define R_LARCH_SOP_POP_32_S_10_12 40 >=20 > +#define R_LARCH_SOP_POP_32_S_10_16 41 >=20 > +#define R_LARCH_SOP_POP_32_S_10_16_S2 42 >=20 > +#define R_LARCH_SOP_POP_32_S_5_20 43 >=20 > +#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44 >=20 > +#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45 >=20 > +#define R_LARCH_SOP_POP_32_U 46 >=20 > +#define R_LARCH_ADD8 47 >=20 > +#define R_LARCH_ADD16 48 >=20 > +#define R_LARCH_ADD24 49 >=20 > +#define R_LARCH_ADD32 50 >=20 > +#define R_LARCH_ADD64 51 >=20 > +#define R_LARCH_SUB8 52 >=20 > +#define R_LARCH_SUB16 53 >=20 > +#define R_LARCH_SUB24 54 >=20 > +#define R_LARCH_SUB32 55 >=20 > +#define R_LARCH_SUB64 56 >=20 > +#define R_LARCH_GNU_VTINHERIT 57 >=20 > +#define R_LARCH_GNU_VTENTRY 58 >=20 > +#define R_LARCH_B16 64 >=20 > +#define R_LARCH_B21 65 >=20 > +#define R_LARCH_B26 66 >=20 > +#define R_LARCH_ABS_HI20 67 >=20 > +#define R_LARCH_ABS_LO12 68 >=20 > +#define R_LARCH_ABS64_LO20 69 >=20 > +#define R_LARCH_ABS64_HI12 70 >=20 > +#define R_LARCH_PCALA_HI20 71 >=20 > +#define R_LARCH_PCALA_LO12 72 >=20 > +#define R_LARCH_PCALA64_LO20 73 >=20 > +#define R_LARCH_PCALA64_HI12 74 >=20 > +#define R_LARCH_GOT_PC_HI20 75 >=20 > +#define R_LARCH_GOT_PC_LO12 76 >=20 > +#define R_LARCH_GOT64_PC_LO20 77 >=20 > +#define R_LARCH_GOT64_PC_HI12 78 >=20 > +#define R_LARCH_GOT64_HI20 79 >=20 > +#define R_LARCH_GOT64_LO12 80 >=20 > +#define R_LARCH_GOT64_LO20 81 >=20 > +#define R_LARCH_GOT64_HI12 82 >=20 > +#define R_LARCH_TLS_LE_HI20 83 >=20 > +#define R_LARCH_TLS_LE_LO12 84 >=20 > +#define R_LARCH_TLS_LE64_LO20 85 >=20 > +#define R_LARCH_TLS_LE64_HI12 86 >=20 > +#define R_LARCH_TLS_IE_PC_HI20 87 >=20 > +#define R_LARCH_TLS_IE_PC_LO12 88 >=20 > +#define R_LARCH_TLS_IE64_PC_LO20 89 >=20 > +#define R_LARCH_TLS_IE64_PC_HI12 90 >=20 > +#define R_LARCH_TLS_IE64_HI20 91 >=20 > +#define R_LARCH_TLS_IE64_LO12 92 >=20 > +#define R_LARCH_TLS_IE64_LO20 93 >=20 > +#define R_LARCH_TLS_IE64_HI12 94 >=20 > +#define R_LARCH_TLS_LD_PC_HI20 95 >=20 > +#define R_LARCH_TLS_LD64_HI20 96 >=20 > +#define R_LARCH_TLS_GD_PC_HI20 97 >=20 > +#define R_LARCH_TLS_GD64_HI20 98 >=20 > +#define R_LARCH_RELAX 99 >=20 > #endif /* !_SYS_ELF_COMMON_H_ */ >=20 > diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > index 21c968e650..77ded3f611 100644 > --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > @@ -7,6 +7,7 @@ > Copyright (c) 2006 - 2018, Intel Corporation. All rights = reserved.
>=20 > Portions copyright (c) 2011 - 2013, ARM Ltd. All rights = reserved.
>=20 > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights > reserved.
>=20 > + Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights > reserved.
>=20 >=20 >=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > @@ -36,23 +37,25 @@ > // >=20 > // PE32+ Machine type for EFI images >=20 > // >=20 > -#define IMAGE_FILE_MACHINE_I386 0x014c >=20 > -#define IMAGE_FILE_MACHINE_EBC 0x0EBC >=20 > -#define IMAGE_FILE_MACHINE_X64 0x8664 >=20 > -#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only >=20 > -#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM > and Thumb/Thumb 2 Little Endian >=20 > -#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM > Architecture, Little Endian >=20 > -#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA >=20 > +#define IMAGE_FILE_MACHINE_I386 0x014c >=20 > +#define IMAGE_FILE_MACHINE_EBC 0x0EBC >=20 > +#define IMAGE_FILE_MACHINE_X64 0x8664 >=20 > +#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only >=20 > +#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed > ARM and Thumb/Thumb 2 Little Endian >=20 > +#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM > Architecture, Little Endian >=20 > +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA >=20 > +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit > LoongArch Architecture >=20 >=20 >=20 > // >=20 > // Support old names for backward compatible >=20 > // >=20 > -#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386 >=20 > -#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC >=20 > -#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 >=20 > -#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT >=20 > -#define EFI_IMAGE_MACHINE_AARCH64 > IMAGE_FILE_MACHINE_ARM64 >=20 > -#define EFI_IMAGE_MACHINE_RISCV64 > IMAGE_FILE_MACHINE_RISCV64 >=20 > +#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386 >=20 > +#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC >=20 > +#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 >=20 > +#define EFI_IMAGE_MACHINE_ARMT > IMAGE_FILE_MACHINE_ARMT >=20 > +#define EFI_IMAGE_MACHINE_AARCH64 > IMAGE_FILE_MACHINE_ARM64 >=20 > +#define EFI_IMAGE_MACHINE_RISCV64 > IMAGE_FILE_MACHINE_RISCV64 >=20 > +#define EFI_IMAGE_MACHINE_LOONGARCH64 > IMAGE_FILE_MACHINE_LOONGARCH64 >=20 >=20 >=20 > #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ >=20 > #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE >=20 > @@ -500,19 +503,21 @@ typedef struct { > // >=20 > // Based relocation types. >=20 > // >=20 > -#define EFI_IMAGE_REL_BASED_ABSOLUTE 0 >=20 > -#define EFI_IMAGE_REL_BASED_HIGH 1 >=20 > -#define EFI_IMAGE_REL_BASED_LOW 2 >=20 > -#define EFI_IMAGE_REL_BASED_HIGHLOW 3 >=20 > -#define EFI_IMAGE_REL_BASED_HIGHADJ 4 >=20 > -#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 >=20 > -#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 >=20 > -#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 >=20 > -#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 >=20 > -#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 >=20 > -#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 >=20 > -#define EFI_IMAGE_REL_BASED_IA64_IMM64 9 >=20 > -#define EFI_IMAGE_REL_BASED_DIR64 10 >=20 > +#define EFI_IMAGE_REL_BASED_ABSOLUTE 0 >=20 > +#define EFI_IMAGE_REL_BASED_HIGH 1 >=20 > +#define EFI_IMAGE_REL_BASED_LOW 2 >=20 > +#define EFI_IMAGE_REL_BASED_HIGHLOW 3 >=20 > +#define EFI_IMAGE_REL_BASED_HIGHADJ 4 >=20 > +#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 >=20 > +#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 >=20 > +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 >=20 > +#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 >=20 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 >=20 > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 >=20 > +#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8 >=20 > +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8 >=20 > +#define EFI_IMAGE_REL_BASED_IA64_IMM64 9 >=20 > +#define EFI_IMAGE_REL_BASED_DIR64 10 >=20 >=20 >=20 >=20 >=20 > /// >=20 > diff --git a/BaseTools/Source/C/Makefiles/header.makefile > b/BaseTools/Source/C/Makefiles/header.makefile > index 0df728f327..4e88a4fbd8 100644 > --- a/BaseTools/Source/C/Makefiles/header.makefile > +++ b/BaseTools/Source/C/Makefiles/header.makefile > @@ -31,6 +31,9 @@ ifndef HOST_ARCH > ifneq (,$(findstring riscv64,$(uname_m))) >=20 > HOST_ARCH=3DRISCV64 >=20 > endif >=20 > + ifneq (,$(findstring loongarch64,$(uname_m))) >=20 > + HOST_ARCH=3DLOONGARCH64 >=20 > + endif >=20 > ifndef HOST_ARCH >=20 > $(info Could not detected HOST_ARCH from uname results) >=20 > $(error HOST_ARCH is not defined!) >=20 > @@ -70,6 +73,9 @@ ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/AArch64/ > else ifeq ($(HOST_ARCH), RISCV64) >=20 > ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/RiscV64/ >=20 >=20 >=20 > +else ifeq ($(HOST_ARCH), LOONGARCH64) >=20 > +ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/LoongArch64/ >=20 > + >=20 > else >=20 > $(error Bad HOST_ARCH) >=20 > endif >=20 > -- > 2.27.0 >=20