From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web08.2042.1623894203984643424 for ; Wed, 16 Jun 2021 18:43:25 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Thu, 17 Jun 2021 09:43:21 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: "'Sunil V L'" , Cc: "'Abner Chang'" , "'Daniel Schaefer'" , "'Bob Feng'" , "'Yuwei Chen'" , "'Heinrich Schuchardt'" References: <20210611140503.28409-1-sunilvl@ventanamicro.com> In-Reply-To: <20210611140503.28409-1-sunilvl@ventanamicro.com> Subject: =?UTF-8?B?5Zue5aSNOiBbUkVTRU5EIFBBVENIIHYyXSBCYXNlVG9vbHM6IEFkZCBzdXBwb3J0IGZvciBSSVNDViBHT1QvUExUIHJlbG9jYXRpb25z?= Date: Thu, 17 Jun 2021 09:43:21 +0800 Message-ID: <004901d7631a$28140860$783c1920$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQJygX2BZFUrE1T5+6MekZfNV2zxRKnhMOpw Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Sunil: I add my comments below.=20 Thanks Liming > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: Sunil V L > =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA6=D4=C211=C8=D5 22:05 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io > =B3=AD=CB=CD: Sunil V L ; Abner Chang > ; Daniel Schaefer ; Bob > Feng ; Liming Gao ; > Yuwei Chen ; Heinrich Schuchardt > > =D6=F7=CC=E2: [RESEND PATCH v2] BaseTools: Add support for RISCV = GOT/PLT > relocations >=20 > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096 >=20 > This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 > relocations generated by PIE enabled compiler. This also needed > changes to R_RISCV_32 and R_RISCV_64 relocations as explained in > = https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-8466= > 82710 >=20 > Changes in v2: > - Addressed Daniel's comment on formatting >=20 > Testing: > 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. > 2) Debian 10.2.0 and booted QEMU virt model. > 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. >=20 > Signed-off-by: Sunil V L >=20 > Acked-by: Abner Chang > Reviewed-by: Daniel Schaefer > Tested-by: Tested-By format is invalid. Its format is same Reviewed-by.=20 >=20 > Cc: Bob Feng > Cc: Liming Gao > Cc: Yuwei Chen > Cc: Heinrich Schuchardt > --- > BaseTools/Source/C/GenFw/Elf64Convert.c | 44 > +++++++++++++++++++++---- > 1 file changed, 38 insertions(+), 6 deletions(-) >=20 > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c > b/BaseTools/Source/C/GenFw/Elf64Convert.c > index d097db8632..d684318269 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > STATIC UINT8 *mRiscVPass1Targ =3D NULL; >=20 > STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL; >=20 > STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0; >=20 > +STATIC INT32 mRiscVPass1Offset; >=20 > +STATIC INT32 mRiscVPass1GotFixup; >=20 >=20 >=20 > // >=20 > // Initialization Function >=20 > @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( > break; >=20 >=20 >=20 > case R_RISCV_32: >=20 > - *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - > SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); >=20 > + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend; >=20 > break; >=20 >=20 >=20 > case R_RISCV_64: >=20 > - *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + > mCoffSectionsOffset[Sym->st_shndx]; >=20 > + *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend; >=20 > break; >=20 >=20 >=20 > case R_RISCV_HI20: >=20 > @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( > mRiscVPass1SymSecIndex =3D 0; >=20 > break; >=20 >=20 >=20 > + case R_RISCV_GOT_HI20: >=20 > + Value =3D (Sym->st_value - Rel->r_offset); >=20 > + mRiscVPass1Offset =3D RV_X(Value, 0, 12); >=20 > + Value =3D RV_X(Value, 12, 20); >=20 > + *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, = 12)); >=20 > + >=20 > + mRiscVPass1Targ =3D Targ; >=20 > + mRiscVPass1Sym =3D SymShdr; >=20 > + mRiscVPass1SymSecIndex =3D Sym->st_shndx; >=20 > + mRiscVPass1GotFixup =3D 1; >=20 > + break; >=20 > + >=20 > case R_RISCV_PCREL_HI20: >=20 > mRiscVPass1Targ =3D Targ; >=20 > mRiscVPass1Sym =3D SymShdr; >=20 > @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( > if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && > mRiscVPass1SymSecIndex !=3D 0) { >=20 > int i; >=20 > Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); >=20 > - Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); >=20 > - if(Value & (RISCV_IMM_REACH/2)) { >=20 > - Value |=3D ~(RISCV_IMM_REACH-1); >=20 > + >=20 > + if(mRiscVPass1GotFixup) { >=20 > + Value =3D (UINT32)(mRiscVPass1Offset); >=20 > + } else { >=20 > + Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); >=20 > + if(Value & (RISCV_IMM_REACH/2)) { >=20 > + Value |=3D ~(RISCV_IMM_REACH-1); >=20 > + } >=20 > } >=20 > Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + > mCoffSectionsOffset[mRiscVPass1SymSecIndex]; >=20 > + >=20 > if(-2048 > (INT32)Value) { >=20 > i =3D (((INT32)Value * -1) / 4096); >=20 > Value2 -=3D i; >=20 > @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( > } >=20 > } >=20 >=20 >=20 > - *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, > 0, 20)); >=20 > + if(mRiscVPass1GotFixup) { >=20 > + *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20) >=20 > + | (RV_X(*(UINT32*)Targ, 0, 20)); >=20 > + /* Convert LD instruction to ADDI */ >=20 > + *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13); >=20 Can you add the comments for the hard value 0x707f and 0x13?=20 Thanks Liming > + } else { >=20 > + *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | > (RV_X(*(UINT32*)Targ, 0, 20)); >=20 > + } >=20 > *(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | > (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); >=20 > } >=20 > mRiscVPass1Sym =3D NULL; >=20 > mRiscVPass1Targ =3D NULL; >=20 > mRiscVPass1SymSecIndex =3D 0; >=20 > + mRiscVPass1Offset =3D 0; >=20 > + mRiscVPass1GotFixup =3D 0; >=20 > break; >=20 >=20 >=20 > case R_RISCV_ADD64: >=20 > @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( > case R_RISCV_GPREL_I: >=20 > case R_RISCV_GPREL_S: >=20 > case R_RISCV_CALL: >=20 > + case R_RISCV_CALL_PLT: >=20 > case R_RISCV_RVC_BRANCH: >=20 > case R_RISCV_RVC_JUMP: >=20 > case R_RISCV_RELAX: >=20 > @@ -1528,6 +1558,7 @@ WriteRelocations64 ( > case R_RISCV_GPREL_I: >=20 > case R_RISCV_GPREL_S: >=20 > case R_RISCV_CALL: >=20 > + case R_RISCV_CALL_PLT: >=20 > case R_RISCV_RVC_BRANCH: >=20 > case R_RISCV_RVC_JUMP: >=20 > case R_RISCV_RELAX: >=20 > @@ -1537,6 +1568,7 @@ WriteRelocations64 ( > case R_RISCV_SET16: >=20 > case R_RISCV_SET32: >=20 > case R_RISCV_PCREL_HI20: >=20 > + case R_RISCV_GOT_HI20: >=20 > case R_RISCV_PCREL_LO12_I: >=20 > break; >=20 >=20 >=20 > -- > 2.25.1