From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web12.2898.1600824115399443952 for ; Tue, 22 Sep 2020 18:21:56 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Wed, 23 Sep 2020 09:21:50 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: , , Cc: "'Bob Feng'" References: <20200922022853.13251-1-aaron.li@intel.com> <16370675CEBE211F.12779@groups.io> In-Reply-To: <16370675CEBE211F.12779@groups.io> Subject: =?UTF-8?B?5Zue5aSNOiBbZWRrMi1kZXZlbF0gW1BBVENIIHYyIDEvMV0gVG9vbHMvRml0R2VuOiBGaXggbWljcm9jb2RlIGFsaWdubWVudCBzdXBwb3J0?= Date: Wed, 23 Sep 2020 09:21:52 +0800 Message-ID: <005801d69147$eb138980$c13a9c80$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQEGqF86QvZl4ZgSq90y3awTFYQnBAE/or2yqwtByTA= Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Aaron: Merge this patch @4efd9ab2cfabdcbd6ca410f870bc889e76f18d85 on edk2-platforms. Please change BZ status to fixed with the commit hash.=20 Thanks Liming > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: bounce+27952+65428+4905953+8761045@groups.io > =B4=FA=B1=ED gaoliming > =B7=A2=CB=CD=CA=B1=BC=E4: 2020=C4=EA9=D4=C222=C8=D5 14:15 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io; aaron.li@intel.com > =B3=AD=CB=CD: 'Bob Feng' > =D6=F7=CC=E2: =BB=D8=B8=B4: [edk2-devel] [PATCH v2 1/1] Tools/FitGen: Fi= x microcode > alignment support >=20 > Aaron: > Thanks for your update. This version is good to me. Reviewed-by: Limin= g > Gao >=20 > If no more comment, I will merge this patch tomorrow. >=20 > Thanks > Liming > > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > > =B7=A2=BC=FE=C8=CB: bounce+27952+65422+4905953+8761045@groups.io > > =B4=FA=B1=ED Aaron Li > > =B7=A2=CB=CD=CA=B1=BC=E4: 2020=C4=EA9=D4=C222=C8=D5 10:29 > > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io > > =B3=AD=CB=CD: Bob Feng ; Liming Gao > > > > =D6=F7=CC=E2: [edk2-devel] [PATCH v2 1/1] Tools/FitGen: Fix microcode = alignment > > support > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2971 > > > > v2: Add check for basic 16-byte alignment. > > > > This patch is to fix a issue that "-A" option would only support > > 2^n Byte alignment of microcode. > > > > Signed-off-by: Aaron Li > > Cc: Bob Feng > > Cc: Liming Gao > > --- > > Silicon/Intel/Tools/FitGen/FitGen.c | 8 ++++++-- > > Silicon/Intel/Tools/FitGen/FitGen.h | 4 +++- > > 2 files changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c > > b/Silicon/Intel/Tools/FitGen/FitGen.c > > index c4006e69c822..851d42cb4aca 100644 > > --- a/Silicon/Intel/Tools/FitGen/FitGen.c > > +++ b/Silicon/Intel/Tools/FitGen/FitGen.c > > @@ -363,7 +363,7 @@ Returns: > > printf ("\tMicrocodeSlotSize - Occupied region size of each > > Microcode binary.\n"); > > > > printf ("\tMicrocodeFfsGuid - Guid of FFS which is used to sa= ve > > Microcode binary"); > > > > printf ("\t-NA - No 0x800 aligned Microcode > > requirement. No -NA means Microcode is aligned with option > > MicrocodeAlignment value.\n"); > > > > - printf ("\tMicrocodeAlignment - HEX value of Microcode alignmen= t. > > Ignored if \"-NA\" is specified. Default value is 0x800.\n"); > > > > + printf ("\tMicrocodeAlignment - HEX value of Microcode > alignment. > > Ignored if \"-NA\" is specified. Default value is 0x800. The Microcode > update > > data must start at a 16-byte aligned linear address.\n"); > > > > printf ("\tRecordType - FIT entry record type. User > should > > ensure it is ordered.\n"); > > > > printf ("\tRecordDataAddress - FIT entry record data > address.\n"); > > > > printf ("\tRecordDataSize - FIT entry record data size.\n")= ; > > > > @@ -1176,7 +1176,11 @@ Returns: > > // MCU might be put at 2KB alignment, if so, we need > to > > adjust the size as 2KB alignment. > > > > // > > > > if (gFitTableContext.MicrocodeIsAligned) { > > > > - MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32= ) > + > > (gFitTableContext.MicrocodeAlignValue - 1)) & > > ~(gFitTableContext.MicrocodeAlignValue - 1); > > > > + if (gFitTableContext.MicrocodeAlignValue & 0xF) { > > > > + printf ("-A Parameter incorrect, Microcode data > > must start at a 16-byte aligned linear address!\n"); > > > > + return 0; > > > > + } > > > > + MicrocodeSize =3D ROUNDUP (*(UINT32 > > *)(MicrocodeBuffer + 32), gFitTableContext.MicrocodeAlignValue); > > > > } else { > > > > MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + > 32)); > > > > } > > > > diff --git a/Silicon/Intel/Tools/FitGen/FitGen.h > > b/Silicon/Intel/Tools/FitGen/FitGen.h > > index abad2d8799c8..435fc26209da 100644 > > --- a/Silicon/Intel/Tools/FitGen/FitGen.h > > +++ b/Silicon/Intel/Tools/FitGen/FitGen.h > > @@ -31,7 +31,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > // Utility version information > > > > // > > > > #define UTILITY_MAJOR_VERSION 0 > > > > -#define UTILITY_MINOR_VERSION 62 > > > > +#define UTILITY_MINOR_VERSION 63 > > > > #define UTILITY_DATE __DATE__ > > > > > > > > // > > > > @@ -45,4 +45,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > (ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) = & > > ((Alignment) - 1)) > > > > ; > > > > > > > > +#define ROUNDUP(Size, Alignment) (((Size) + (Alignment) - 1) / > (Alignment) * > > (Alignment)) > > > > + > > > > #endif > > > > -- > > 2.23.0.windows.1 > > > > > > > > -=3D-=3D-=3D-=3D-=3D-=3D > > Groups.io Links: You receive all messages sent to this group. > > View/Reply Online (#65422): > https://edk2.groups.io/g/devel/message/65422 > > Mute This Topic: https://groups.io/mt/77005848/4905953 > > Group Owner: devel+owner@edk2.groups.io > > Unsubscribe: https://edk2.groups.io/g/devel/unsub > > [gaoliming@byosoft.com.cn] > > -=3D-=3D-=3D-=3D-=3D-=3D > > >=20 >=20 >=20 >=20 >=20 >=20 >=20