From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web08.15943.1621236248216103453 for ; Mon, 17 May 2021 00:24:09 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Mon, 17 May 2021 15:24:00 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: "'Etienne Carriere'" , Cc: "'Achin Gupta'" , "'Ard Biesheuvel'" , "'Jiewen Yao'" , "'Leif Lindholm'" , "'Sami Mujawar'" , "'Sughosh Ganu'" , "'Bob Feng'" References: <20210517054911.30665-1-etienne.carriere@linaro.org> <20210517054911.30665-3-etienne.carriere@linaro.org> In-Reply-To: <20210517054911.30665-3-etienne.carriere@linaro.org> Subject: =?UTF-8?B?5Zue5aSNOiBbUEFUQ0ggdjIgMy81XSBHZW5GdjogQXJtOiBzdXBwb3J0IGltYWdlcyBlbnRlcmVkIGluIFRodW1iIG1vZGU=?= Date: Mon, 17 May 2021 15:24:02 +0800 Message-ID: <006301d74aed$9c7a14f0$d56e3ed0$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIDTOX6m+biTjmm13w54NAQzekYfwG2U648qoGOv/A= Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Acked-by: Liming Gao > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: Etienne Carriere > =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA5=D4=C217=C8=D5 13:49 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io > =B3=AD=CB=CD: Achin Gupta ; Ard Biesheuvel > ; Jiewen Yao ; Leif > Lindholm ; Sami Mujawar ; > Sughosh Ganu ; Etienne Carriere > ; Bob Feng ; Liming > Gao > =D6=F7=CC=E2: [PATCH v2 3/5] GenFv: Arm: support images entered in = Thumb mode >=20 > Change GenFv for Arm architecture to generate a specific jump > instruction as image entry instruction, when the target entry label > is assembled with Thumb instruction set. This is possible since > SecCoreEntryAddress value fetched from the PE32 has its LSBit set when > the entry instruction executes in Thumb mode. >=20 > Cc: Bob Feng > Cc: Liming Gao > Cc: Achin Gupta > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Sughosh Ganu > Signed-off-by: Etienne Carriere > --- > Changes since v1: > - Fix typos in commit log and inline comments > - Change if() test operand to be an explicit boolean > --- > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 +++++++++++++++----- > 1 file changed, 29 insertions(+), 9 deletions(-) >=20 > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > index 6e296b8ad6..5f3fd4f808 100644 > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include "FvLib.h" > #include "PeCoffLib.h" >=20 > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION > 0xEB000000 > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION > 0x14000000 >=20 > +/* > + * Arm instruction to jump to Fv entry instruction in Arm or Thumb = mode. > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX > (immediate) > + * BLX (encoding A2) branches to offset in Thumb instruction set = mode. > + * BL (encoding A1) branches to offset in Arm instruction set mode. > + */ > +#define ARM_JUMP_OFFSET_MAX 0xffffff > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> 2)) > + > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \ > + (((Imm32) & (1 << 1)) << (24 - = 1)) > | \ > + (((Imm32) >> 2) & 0x7fffff)) > +#define ARM_JUMP_TO_THUMB(Offset) > _ARM_JUMP_TO_THUMB((Offset) - 8) > + > +/* > + * Arm instruction to retrun from exception (MOVS PC, LR) > + */ > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E > + > BOOLEAN mArm =3D FALSE; > BOOLEAN mRiscV =3D FALSE; > STATIC UINT32 MaxFfsAlignment =3D 0; > @@ -2203,23 +2221,25 @@ Returns: > // if we found an SEC core entry point then generate a branch > instruction > // to it and populate a debugger SWI entry as well > if (UpdateVectorSec) { > + UINT32 EntryOffset; >=20 > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM SEC > vector"); >=20 > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset > - // on ARM, the PC is always 8 ahead, so we're not really = jumping from > the base address, but from base address + 8 > - ResetVector[0] =3D (INT32)(SecCoreEntryAddress - > FvInfo->BaseAddress - 8) >> 2; > + EntryOffset =3D (INT32)(SecCoreEntryAddress - = FvInfo->BaseAddress); >=20 > - if (ResetVector[0] > 0x00FFFFFF) { > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be = within > 32MB of the start of the FV"); > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) { > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset = above > 1MB of the start of the FV"); > return EFI_ABORTED; > } >=20 > - // Add opcode for an unconditional branch with no link. i.e.: " = B > SecEntryPoint" > - ResetVector[0] |=3D ARMT_UNCONDITIONAL_JUMP_INSTRUCTION; > + if (SecCoreEntryAddress & 1 !=3D 0) { > + ResetVector[0] =3D ARM_JUMP_TO_THUMB(EntryOffset); > + } else { > + ResetVector[0] =3D ARM_JUMP_TO_ARM(EntryOffset); > + } >=20 > // SWI handler movs pc,lr. Just in case a debugger uses SWI > - ResetVector[2] =3D 0xE1B0F07E; > + ResetVector[2] =3D ARM_RETURN_FROM_EXCEPTION; >=20 > // Place holder to support a common interrupt handler from ROM. > // Currently not supported. For this to be used the reset = vector would > not be in this FV > -- > 2.17.1