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From: "gaoliming" <gaoliming@byosoft.com.cn>
To: <devel@edk2.groups.io>, <jiaxin.wu@intel.com>
Cc: "'Michael D Kinney'" <michael.d.kinney@intel.com>,
	"'Zhiguang Liu'" <zhiguang.liu@intel.com>,
	"'Zhang Hongbin1'" <hongbin1.zhang@intel.com>
Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control Register(XCR) Read and Write.
Date: Wed, 31 Mar 2021 09:50:57 +0800	[thread overview]
Message-ID: <006901d725d0$4b525070$e1f6f150$@byosoft.com.cn> (raw)
In-Reply-To: <20210331012007.12824-1-Jiaxin.wu@intel.com>

Where is X64 implementation for this new API?

> -----邮件原件-----
> 发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Wu, Jiaxin
> 发送时间: 2021年3月31日 9:20
> 收件人: devel@edk2.groups.io
> 抄送: Michael D Kinney <michael.d.kinney@intel.com>; Liming Gao
> <gaoliming@byosoft.com.cn>; Zhiguang Liu <zhiguang.liu@intel.com>; Zhang
> Hongbin1 <hongbin1.zhang@intel.com>
> 主题: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
> Register(XCR) Read and Write.
> 
> https://bugzilla.tianocore.org/show_bug.cgi?id=3284
> 
> This patch is to support Extended Control Register(XCR) Read
> and Write.
> 
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com>
> Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
> ---
>  MdePkg/Include/Library/BaseLib.h          | 46
> ++++++++++++++++++++++++++++++-
>  MdePkg/Library/BaseLib/BaseLib.inf        |  4 ++-
>  MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm  | 31
> +++++++++++++++++++++
>  MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm | 34
> +++++++++++++++++++++++
>  4 files changed, 113 insertions(+), 2 deletions(-)
>  create mode 100644 MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
>  create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index 1171a0ffb5..c51633ad73 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -1,10 +1,10 @@
>  /** @file
>    Provides string functions, linked list functions, math functions,
> synchronization
>    functions, file path functions, and CPU architecture-specific
functions.
> 
> -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
>  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>  Copyright (c) Microsoft Corporation.<BR>
>  Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.
All
> rights reserved.<BR>
> 
>  SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -7493,7 +7493,51 @@ PatchInstructionX86 (
>    OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
>    IN  UINT64                   PatchValue,
>    IN  UINTN                    ValueSize
>    );
> 
> +/**
> +  Returns a 64-bit Extended Control Register(XCR).
> +
> +  Reads and returns the 64-bit XCR specified by Index. No parameter
> checking is
> +  performed on Index, and some Index values may cause CPU exceptions.
> The
> +  caller must either guarantee that Index is valid, or the caller must
set up
> +  exception handlers to catch the exceptions. This function is only
available
> +  on IA-32 and x64.
> +
> +  @param  Index The 32-bit XCR index to read.
> +
> +  @return The value of the XCR identified by Index.
> +
> +**/
> +UINT64
> +EFIAPI
> +AsmReadXcr (
> +  IN UINT32  Index
> +  );
> +
> +/**
> +  Writes a 64-bit value to a Extended Control Register(XCR), and returns
the
> +  value.
> +
> +  Writes the 64-bit value specified by Value to the XCR specified by
Index.
> The
> +  64-bit value written to the XCR is returned. No parameter checking is
> +  performed on Index or Value, and some of these may cause CPU
> exceptions. The
> +  caller must either guarantee that Index and Value are valid, or the
caller
> +  must establish proper exception handlers. This function is only
available
> on
> +  IA-32 and x64.
> +
> +  @param  Index The 32-bit XCR index to write.
> +  @param  Value The 64-bit value to write to the XCR.
> +
> +  @return Value
> +
> +**/
> +UINT64
> +EFIAPI
> +AsmWriteXcr (
> +  IN UINT32  Index,
> +  IN UINT64  Value
> +  );
> +
>  #endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
>  #endif // !defined (__BASE_LIB__)
> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> b/MdePkg/Library/BaseLib/BaseLib.inf
> index 3b85c56c3c..e62031ea11 100644
> --- a/MdePkg/Library/BaseLib/BaseLib.inf
> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> @@ -1,9 +1,9 @@
>  ## @file
>  #  Base Library implementation.
>  #
> -#  Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
> +#  Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
>  #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights
reserved.<BR>
>  #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
>  #  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
> rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -63,10 +63,12 @@
>    BaseLibInternals.h
> 
>  [Sources.Ia32]
>    Ia32/WriteTr.nasm
>    Ia32/Lfence.nasm
> +  Ia32/ReadXcr.nasm
> +  Ia32/WriteXcr.nasm
> 
>    Ia32/Wbinvd.c | MSFT
>    Ia32/WriteMm7.c | MSFT
>    Ia32/WriteMm6.c | MSFT
>    Ia32/WriteMm5.c | MSFT
> diff --git a/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
> b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
> new file mode 100644
> index 0000000000..5d50d8ba01
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
> @@ -0,0 +1,31 @@
>
+;--------------------------------------------------------------------------
----
> +;
> +; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Module Name:
> +;
> +;   ReadXcr.Asm
> +;
> +; Abstract:
> +;
> +;   AsmReadXcr function
> +;
> +; Notes:
> +;
>
+;--------------------------------------------------------------------------
----
> +
> +    SECTION .text
> +
>
+;--------------------------------------------------------------------------
----
> +; UINT64
> +; EFIAPI
> +; AsmReadXcr (
> +;   IN UINT32  Index
> +;   );
>
+;--------------------------------------------------------------------------
----
> +global ASM_PFX(AsmReadXcr)
> +ASM_PFX(AsmReadXcr):
> +    mov     ecx, [esp + 4]
> +    xgetbv
> +    ret
> \ No newline at end of file
> diff --git a/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> new file mode 100644
> index 0000000000..009d41864b
> --- /dev/null
> +++ b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
> @@ -0,0 +1,34 @@
>
+;--------------------------------------------------------------------------
----
> +;
> +; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Module Name:
> +;
> +;   WriteXcr.nasm
> +;
> +; Abstract:
> +;
> +;   AsmWriteXcr function
> +;
> +; Notes:
> +;
>
+;--------------------------------------------------------------------------
----
> +
> +    SECTION .text
> +
>
+;--------------------------------------------------------------------------
----
> +; UINT64
> +; EFIAPI
> +; AsmWriteXcr (
> +;   IN UINT32  Index,
> +;   IN UINT64  Value
> +;   );
>
+;--------------------------------------------------------------------------
----
> +global ASM_PFX(AsmWriteXcr)
> +ASM_PFX(AsmWriteXcr):
> +    mov     edx, [esp + 12]
> +    mov     eax, [esp + 8]
> +    mov     ecx, [esp + 4]
> +    xsetbv
> +    ret
> \ No newline at end of file
> --
> 2.16.2.windows.1
> 
> 
> 
> 
> 




  reply	other threads:[~2021-03-31  1:50 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-31  1:20 [PATCH v1] MdePkg: Support Extended Control Register(XCR) Read and Write Wu, Jiaxin
2021-03-31  1:50 ` gaoliming [this message]
2021-03-31  1:55   ` [edk2-devel] " Wu, Jiaxin
2021-03-31  2:05     ` 回复: " gaoliming
2021-03-31  2:19       ` Yao, Jiewen
2021-03-31  4:21         ` Wu, Jiaxin
2021-03-31  7:58         ` Wu, Jiaxin

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