From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web08.16106.1621237680495823913 for ; Mon, 17 May 2021 00:48:01 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Mon, 17 May 2021 15:47:53 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: , Cc: "'Achin Gupta'" , "'Ard Biesheuvel'" , "'Jiewen Yao'" , "'Leif Lindholm'" , "'Sami Mujawar'" , "'Sughosh Ganu'" , "'Bob Feng'" References: <20210517054911.30665-1-etienne.carriere@linaro.org> <20210517054911.30665-3-etienne.carriere@linaro.org> <006301d74aed$9c7a14f0$d56e3ed0$@byosoft.com.cn> In-Reply-To: Subject: =?UTF-8?B?5Zue5aSNOiBbZWRrMi1kZXZlbF0gW1BBVENIIHYyIDMvNV0gR2VuRnY6IEFybTogc3VwcG9ydCBpbWFnZXMgZW50ZXJlZCBpbiBUaHVtYiBtb2Rl?= Date: Mon, 17 May 2021 15:47:55 +0800 Message-ID: <006901d74af0$f2fa5ee0$d8ef1ca0$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQIDTOX6m+biTjmm13w54NAQzekYfwG2U648AvesDJwAc3REZapmO41Q Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Etienne: Thanks for your reminder. I try VS compiler and meet with the compiler e= rror on this line.=20 Here, does if ((SecCoreEntryAddress & 1) !=3D 0) mean the lowest bit of = this address is 1? Thanks Liming > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io = =E4=BB=A3=E8=A1=A8 Etienne > Carriere > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8817=E6=97=A5= 15:35 > =E6=94=B6=E4=BB=B6=E4=BA=BA: gaoliming > =E6=8A=84=E9=80=81: devel@edk2.groups.io; Achin Gupta ; Ard > Biesheuvel ; Jiewen Yao > ; Leif Lindholm ; Sami Mujawar > ; Sughosh Ganu ; Bob > Feng > =E4=B8=BB=E9=A2=98: Re: [edk2-devel] [PATCH v2 3/5] GenFv: Arm: support = images entered in > Thumb mode >=20 > On Mon, 17 May 2021 at 09:24, gaoliming > wrote: > > > > Acked-by: Liming Gao > > > > > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > > > =E5=8F=91=E4=BB=B6=E4=BA=BA: Etienne Carriere > > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B45=E6=9C=8817=E6= =97=A5 13:49 > > > =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io > > > =E6=8A=84=E9=80=81: Achin Gupta ; Ard Biesheuve= l > > > ; Jiewen Yao ; Leif > > > Lindholm ; Sami Mujawar > ; > > > Sughosh Ganu ; Etienne Carriere > > > ; Bob Feng ; Limi= ng > > > Gao > > > =E4=B8=BB=E9=A2=98: [PATCH v2 3/5] GenFv: Arm: support images entere= d in Thumb > mode > > > > > > Change GenFv for Arm architecture to generate a specific jump > > > instruction as image entry instruction, when the target entry label > > > is assembled with Thumb instruction set. This is possible since > > > SecCoreEntryAddress value fetched from the PE32 has its LSBit set wh= en > > > the entry instruction executes in Thumb mode. > > > > > > Cc: Bob Feng > > > Cc: Liming Gao > > > Cc: Achin Gupta > > > Cc: Ard Biesheuvel > > > Cc: Leif Lindholm > > > Cc: Sughosh Ganu > > > Signed-off-by: Etienne Carriere > > > --- > > > Changes since v1: > > > - Fix typos in commit log and inline comments > > > - Change if() test operand to be an explicit boolean > > > --- > > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 38 > +++++++++++++++----- > > > 1 file changed, 29 insertions(+), 9 deletions(-) > > > > > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > > index 6e296b8ad6..5f3fd4f808 100644 > > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > > @@ -34,9 +34,27 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > #include "FvLib.h" > > > #include "PeCoffLib.h" > > > > > > -#define ARMT_UNCONDITIONAL_JUMP_INSTRUCTION > > > 0xEB000000 > > > #define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION > > > 0x14000000 > > > > > > +/* > > > + * Arm instruction to jump to Fv entry instruction in Arm or Thumb = mode. > > > + * From ARM Arch Ref Manual versions b/c/d, section A8.8.25 BL, BLX > > > (immediate) > > > + * BLX (encoding A2) branches to offset in Thumb instruction set mo= de. > > > + * BL (encoding A1) branches to offset in Arm instruction set mode. > > > + */ > > > +#define ARM_JUMP_OFFSET_MAX 0xffffff > > > +#define ARM_JUMP_TO_ARM(Offset) (0xeb000000 | ((Offset - 8) >> > 2)) > > > + > > > +#define _ARM_JUMP_TO_THUMB(Imm32) (0xfa000000 | \ > > > + (((Imm32) & (1 << 1)) << (24 > - 1)) > > > | \ > > > + (((Imm32) >> 2) & 0x7fffff)) > > > +#define ARM_JUMP_TO_THUMB(Offset) > > > _ARM_JUMP_TO_THUMB((Offset) - 8) > > > + > > > +/* > > > + * Arm instruction to retrun from exception (MOVS PC, LR) > > > + */ > > > +#define ARM_RETURN_FROM_EXCEPTION 0xE1B0F07E > > > + > > > BOOLEAN mArm =3D FALSE; > > > BOOLEAN mRiscV =3D FALSE; > > > STATIC UINT32 MaxFfsAlignment =3D 0; > > > @@ -2203,23 +2221,25 @@ Returns: > > > // if we found an SEC core entry point then generate a branch > > > instruction > > > // to it and populate a debugger SWI entry as well > > > if (UpdateVectorSec) { > > > + UINT32 EntryOffset; > > > > > > VerboseMsg("UpdateArmResetVectorIfNeeded updating ARM > SEC > > > vector"); > > > > > > - // B SecEntryPoint - signed_immed_24 part +/-32MB offset > > > - // on ARM, the PC is always 8 ahead, so we're not really jump= ing > > from > > > the base address, but from base address + 8 > > > - ResetVector[0] =3D (INT32)(SecCoreEntryAddress - > > > FvInfo->BaseAddress - 8) >> 2; > > > + EntryOffset =3D (INT32)(SecCoreEntryAddress - > FvInfo->BaseAddress); > > > > > > - if (ResetVector[0] > 0x00FFFFFF) { > > > - Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be wi= thin > > > 32MB of the start of the FV"); > > > + if (EntryOffset > ARM_JUMP_OFFSET_MAX) { > > > + Error(NULL, 0, 3000, "Invalid", "SEC Entry point offset a= bove > > > 1MB of the start of the FV"); > > > return EFI_ABORTED; > > > } > > > > > > - // Add opcode for an unconditional branch with no link. i.e.:= " B > > > SecEntryPoint" > > > - ResetVector[0] |=3D > ARMT_UNCONDITIONAL_JUMP_INSTRUCTION; > > > + if (SecCoreEntryAddress & 1 !=3D 0) { >=20 > Sorry, I missed this one. > This needs extra parantheses. >=20 > I'll sent a v3. My apologies... >=20 > etienne >=20 > > > + ResetVector[0] =3D ARM_JUMP_TO_THUMB(EntryOffset); > > > + } else { > > > + ResetVector[0] =3D ARM_JUMP_TO_ARM(EntryOffset); > > > + } > > > > > > // SWI handler movs pc,lr. Just in case a debugger uses SWI > > > - ResetVector[2] =3D 0xE1B0F07E; > > > + ResetVector[2] =3D ARM_RETURN_FROM_EXCEPTION; > > > > > > // Place holder to support a common interrupt handler from > ROM. > > > // Currently not supported. For this to be used the reset vec= tor > > would > > > not be in this FV > > > -- > > > 2.17.1 > > > > > > >=20 >=20 >=20 >=20