From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from walk.intel-email.com (walk.intel-email.com [101.227.64.242]) by mx.groups.io with SMTP id smtpd.web11.30656.1688953376751523850 for ; Sun, 09 Jul 2023 18:43:04 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@byosoft.com.cn header.s=cloud-union header.b=nDwsgl0S; spf=pass (domain: byosoft.com.cn, ip: 101.227.64.242, mailfrom: gaoliming@byosoft.com.cn) Received: from walk.intel-email.com (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id 8F93DCD1F74A for ; Mon, 10 Jul 2023 09:42:52 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=byosoft.com.cn; s=cloud-union; t=1688953372; bh=eqecyM/X3MIpmB5fBMJN2istD8HKoTJ9UsxxBNULhbo=; h=From:To:Cc:References:In-Reply-To:Subject:Date; b=nDwsgl0SMEnj2amOWnUcVBhDqz4IwzPDLoyQM+IfH22fhgXzzLu1EOjX+65Vr9soI 7lBnYbn8L0AUQgCwa5t8nFxo70FKGCJitjPOvg6qOp/a17wDS0sySI3WEeP2OPIMOF q2jKiNCd5hnN3o6HFiHpDok4GvKt8CgK/kfJ4J2o= Received: from localhost (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id 8B423CD1F740 for ; Mon, 10 Jul 2023 09:42:52 +0800 (CST) Received: from walk.intel-email.com (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id 579C8CD1F6E6 for ; Mon, 10 Jul 2023 09:42:52 +0800 (CST) Authentication-Results: walk.intel-email.com; none Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by walk.intel-email.com (Postfix) with SMTP id D599CCD1F68B for ; Mon, 10 Jul 2023 09:42:48 +0800 (CST) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Mon, 10 Jul 2023 09:42:38 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: , , "'Ni, Ray'" , "'Yao, Jiewen'" , "'Nong, Foster'" Cc: , "'Open Source Submission'" References: In-Reply-To: Subject: =?UTF-8?B?5Zue5aSNOiBbICoqIFNQQU1NQUlMICoqIF1bZWRrMi1kZXZlbF0gW1BBVENIIHYyIDEvMV0gTWRlUGtnOiBBZGQgQ3hsMjAuaCBpbnRvIEluZHVzdHJ5U3RhbmRhcmQ=?= Date: Mon, 10 Jul 2023 09:42:46 +0800 Message-ID: <008901d9b2cf$d39f57f0$7ade07d0$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQGSuHq7MNQaaBcmNl0W2ZB4F3D2sgHu9oNjAedrXpwCjbwanAF8eR2CsAEp46A= Sender: "gaoliming" Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Acked-by: Liming Gao > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io =B4=FA=B1= =ED Chris Li OS > via groups.io > =B7=A2=CB=CD=CA=B1=BC=E4: 2023=C4=EA7=D4=C23=C8=D5 17:39 > =CA=D5=BC=FE=C8=CB: Ni, Ray ; devel@edk2.groups.io; Yao= , Jiewen > ; Nong, Foster > =B3=AD=CB=CD: gaoliming@byosoft.com.cn; michael.d.kinney@intel.com; Open = Source > Submission > =D6=F7=CC=E2: [ ** SPAMMAIL ** ][edk2-devel] [PATCH v2 1/1] MdePkg: Add C= xl20.h > into IndustryStandard >=20 > +To/Cc >=20 > Updated places from v1: > +#define CXL_2_0_DVSEC_REVISON_ID 0x1 >=20 > -#define CXL20_DVSEC_REVISON_REGISTOR_LOCATOR 0x0 > +#define CXL_2_0_DVSEC_REVISON_REGISTOR_LOCATOR 0x0 >=20 > -} HDM_DECODER_N_INFO; > +} CXL_HDM_DECODER_N_INFO; >=20 > ----- >=20 > 1) Add CXL 2.0 header file to comply with CXL 2.0 specification > 2) CXL 2.0 header will embed Cxl11.h > 3) Updated Cxl.h to point to 2.0 header file >=20 > Signed-off-by: Chris Li > --- > MdePkg/Include/IndustryStandard/Cxl.h | 2 +- > MdePkg/Include/IndustryStandard/Cxl20.h | 479 > ++++++++++++++++++++++++ > 2 files changed, 480 insertions(+), 1 deletion(-) > create mode 100644 MdePkg/Include/IndustryStandard/Cxl20.h >=20 > diff --git a/MdePkg/Include/IndustryStandard/Cxl.h > b/MdePkg/Include/IndustryStandard/Cxl.h > index 06c1230e3e..9ad3242e25 100644 > --- a/MdePkg/Include/IndustryStandard/Cxl.h > +++ b/MdePkg/Include/IndustryStandard/Cxl.h > @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #ifndef _CXL_MAIN_H_ > #define _CXL_MAIN_H_ >=20 > -#include > +#include > // > // CXL assigned new Vendor ID > // > diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h > b/MdePkg/Include/IndustryStandard/Cxl20.h > new file mode 100644 > index 0000000000..16ac6d5aff > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/Cxl20.h > @@ -0,0 +1,479 @@ > +/** @file > + CXL 2.0 Register definitions > + > + This file contains the register definitions based on the Compute Express > Link > + (CXL) Specification Revision 2.0. > + > + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef CXL20_H_ > +#define CXL20_H_ > + > +#include > + > +// > +// Ensure proper structure formats > +// > +#pragma pack(1) > + > + > +// > +// CXL DVSEC IDs and Revisions > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.1 > +// > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE 0x0 > +#define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP > 0x2 > +#define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS 0x3 > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS 0x4 > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES 0x5 > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT 0x7 > +#define CXL_DVSEC_ID_REGISTER_LOCATOR 0x8 > +#define CXL_DVSEC_ID_MLD 0x9 > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY 0xA > + > +#define CXL_2_0_DVSEC_REVISON_ID 0x1 > + > +#define CXL_2_0_DVSEC_REVISON_REGISTOR_LOCATOR 0x0 > + > +// > +// Register Block ID > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1 > +// > +#define CXL_REGISTER_BLOCK_ID_EMPTY 0x0 > +#define CXL_REGISTER_BLOCK_ID_COMPONENT > 0x01 > +#define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL 0x02 > +#define CXL_REGISTER_BLOCK_ID_DEVICE 0x03 > + > +// > +// Component Register Block Register Ranges Offset > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.4 > +// > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_IO > 0x0 > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_CACHE_MEM > 0x1000 > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_ARB_MUX > 0xE000 > + > +// > +// CXL Cache Memory Capability IDs > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5 > +// > +#define CXL_CACHE_MEM_CAPABILITY_ID_CXL 0x1 > +#define CXL_CACHE_MEM_CAPABILITY_ID_RAS 0x2 > +#define CXL_CACHE_MEM_CAPABILITY_ID_SECURITY 0x3 > +#define CXL_CACHE_MEM_CAPABILITY_ID_LINK 0x4 > +#define CXL_CACHE_MEM_CAPABILITY_ID_HDM_DECODER > 0x5 > +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_SECURITY 0x6 > +#define CXL_CACHE_MEM_CAPABILITY_ID_IDE 0x7 > +#define CXL_CACHE_MEM_CAPABILITY_ID_SNOOP_FILTER 0x8 > +#define CXL_CACHE_MEM_CAPABILITY_ID_MASK > 0xFFFF > + > +// > +// Generic CXL Device Capability IDs 0x0000 ~ 0x3FFF > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 > +// > +#define CXL_DEVICE_CAPABILITY_ID_CAPABILITIES_ARRAY_REGISTER > 0x0000 > +#define CXL_DEVICE_CAPABILITY_ID_DEVICE_STATUS > 0x0001 > +#define CXL_DEVICE_CAPABILITY_ID_PRIMARY_MAILBOX > 0x0002 > +#define CXL_DEVICE_CAPABILITY_ID_SECONDARY_MAILBOX > 0x0003 > + > +// > +// Specific CXL Device Capability IDs 0x4000 ~ 0x7FFF > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2.1 > +// > +// (ref: CXL 2.0 spec $8.2.8.5) > +#define CXL_DEVICE_CAPABILITY_ID_MEMORY_DEVICE_STATUS > 0x4000 > +#define CXL_DEVICE_CAPABILITY_ID_MASK > 0xFFFF > + > +// > +// Memory Device Status > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5.1.1 > +// > +#define CXL_MEM_DEVICE_MEDIA_STATUS_NOT_READY > 0b00 > +#define CXL_MEM_DEVICE_MEDIA_STATUS_READY > 0b01 > +#define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR > 0b10 > +#define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED > 0b11 > + > +// > +// PCIe DVSEC for CXL Device > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.3 > +// > +typedef union { > + struct { > + UINT16 CacheCapable : 1; // > bit 0 > + UINT16 IoCapable : 1; // > bit 1 > + UINT16 MemCapable : 1; // > bit 2 > + UINT16 MemHwInitMode : 1; > // bit 3 > + UINT16 HdmCount : 2; // > bit 4..5 > + UINT16 CacheWriteBackAndInvalidateCapable : 1; // bit 6 > + UINT16 CxlResetCapable : 1; // bit > 7 > + UINT16 CxlResetTimeout : 3; // > bit 8..10 > + UINT16 CxlResetMemClrCapable : 1; // > bit 11 > + UINT16 Reserved : 1; // > bit 12 > + UINT16 MultipleLogicalDevice : 1; // bit > 13 > + UINT16 ViralCapable : 1; // bit > 14 > + UINT16 PmInitCompletionReportingCapable : 1; // bit > 15 > + } Bits; > + UINT16 Uint16; > +} CXL_DVSEC_CXL_DEVICE_CAPABILITY; > + > +typedef union { > + struct { > + UINT16 CacheEnable : 1; // bit 0 > + UINT16 IoEnable : 1; // bit 1 > + UINT16 MemEnable : 1; // bit 2 > + UINT16 CacheSfCoverage : 5; // bit 3..7 > + UINT16 CacheSfGranularity : 3; // bit 8..10 > + UINT16 CacheCleanEviction : 1; // bit 11 > + UINT16 Reserved1 : 2; // bit 12..13 > + UINT16 ViralEnable : 1; // bit 14 > + UINT16 Reserved2 : 1; // bit 15 > + } Bits; > + UINT16 Uint16; > +} CXL_DVSEC_CXL_DEVICE_CONTROL; > + > +typedef union { > + struct { > + UINT16 Reserved1 : 14; // bit 0..13 > + UINT16 ViralStatus : 1; // bit 14 > + UINT16 Reserved2 : 1; // bit 15 > + } Bits; > + UINT16 Uint16; > +} CXL_DVSEC_CXL_DEVICE_STATUS; > + > +typedef union { > + struct { > + UINT16 DisableCaching : 1; // bit > 0 > + UINT16 InitiateCacheWriteBackAndInvalidate : 1; // bit 1 > + UINT16 InitiateCxlReset : 1; // bit 2 > + UINT16 CxlResetMemClrEnable : 1; // > bit 3 > + UINT16 Reserved : 12; // > bit 4..15 > + } Bits; > + UINT16 Uint16; > +} CXL_2_0_DVSEC_CXL_DEVICE_CONTROL2; > + > +typedef union { > + struct { > + UINT16 CacheInvalid : 1; > // bit 0 > + UINT16 CxlResetComplete : 1; > // bit 1 > + UINT16 Reserved : 13; > // bit 2..14 > + UINT16 PowerManagementInitialzationComplete : 1; // > bit 15 > + } Bits; > + UINT16 Uint16; > +} CXL_2_0_DVSEC_CXL_DEVICE_STATUS2; > + > +typedef union { > + struct { > + UINT16 ConfigLock : 1; // bit 0 > + UINT16 Reserved : 15; // bit 1..15 > + } Bits; > + UINT16 Uint16; > +} CXL_DVSEC_CXL_DEVICE_LOCK; > + > +typedef union { > + struct { > + UINT16 CacheSizeUnit : 4; // bit 0..3 > + UINT16 Reserved : 4; // bit 4..7 > + UINT16 CacheSize : 8; // bit 8..15 > + } Bits; > + UINT16 Uint16; > +} CXL_2_0_DVSEC_CXL_DEVICE_CAPABILITY2; > + > +typedef union { > + struct { > + UINT32 MemorySizeHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_HIGH; > + > +typedef union { > + struct { > + UINT32 MemoryInfoValid : 1; // bit 0 > + UINT32 MemoryActive : 1; // bit 1 > + UINT32 MediaType : 3; // bit 2..4 > + UINT32 MemoryClass : 3; // bit 5..7 > + UINT32 DesiredInterleave : 5; // bit 8..12 > + UINT32 MemoryActiveTimeout : 3; // bit 13..15 > + UINT32 Reserved : 12; // bit 16..27 > + UINT32 MemorySizeLow : 4; // bit 28..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_LOW; > + > +typedef union { > + struct { > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_HIGH; > + > +typedef union { > + struct { > + UINT32 Reserved : 28; // bit 0..27 > + UINT32 MemoryBaseLow : 4; // bit 28..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_LOW; > + > +typedef union { > + struct { > + UINT32 MemorySizeHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_HIGH; > + > +typedef union { > + struct { > + UINT32 MemoryInfoValid : 1; // bit 0 > + UINT32 MemoryActive : 1; // bit 1 > + UINT32 MediaType : 3; // bit 2..4 > + UINT32 MemoryClass : 3; // bit 5..7 > + UINT32 DesiredInterleave : 5; // bit 8..12 > + UINT32 MemoryActiveTimeout : 3; // bit 13..15 > + UINT32 Reserved : 12; // bit 16..27 > + UINT32 MemorySizeLow : 4; // bit 28..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_LOW; > + > +typedef union { > + struct { > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_HIGH; > + > +typedef union { > + struct { > + UINT32 Reserved : 28; // bit 0..27 > + UINT32 MemoryBaseLow : 4; // bit 28..31 > + } Bits; > + UINT32 Uint32; > +} CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_LOW; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > // offset 0x00 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 > DesignatedVendorSpecificHeader1; // offset 0x04 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 > DesignatedVendorSpecificHeader2; // offset 0x08 > + CXL_DVSEC_CXL_DEVICE_CAPABILITY > DeviceCapability; // offset 0x0A > + CXL_DVSEC_CXL_DEVICE_CONTROL > DeviceControl; // offset 0x0C > + CXL_DVSEC_CXL_DEVICE_STATUS > DeviceStatus; // offset 0x0E > + CXL_2_0_DVSEC_CXL_DEVICE_CONTROL2 > DeviceControl2; // offset 0x10 > + CXL_2_0_DVSEC_CXL_DEVICE_STATUS2 > DeviceStatus2; // offset 0x12 > + CXL_DVSEC_CXL_DEVICE_LOCK > DeviceLock; // offset 0x14 > + CXL_2_0_DVSEC_CXL_DEVICE_CAPABILITY2 > DeviceCapability2; // offset 0x16 > + CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_HIGH > DeviceRange1SizeHigh; // offset 0x18 > + CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_LOW > DeviceRange1SizeLow; // offset 0x1C > + CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_HIGH > DeviceRange1BaseHigh; // offset 0x20 > + CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_LOW > DeviceRange1BaseLow; // offset 0x24 > + CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_HIGH > DeviceRange2SizeHigh; // offset 0x28 > + CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_LOW > DeviceRange2SizeLow; // offset 0x2C > + CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_HIGH > DeviceRange2BaseHigh; // offset 0x30 > + CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_LOW > DeviceRange2BaseLow; // offset 0x34 > +} CXL_2_0_DVSEC_CXL_DEVICE; > + > +// > +// Register Locator DVSEC > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9 > +// > +typedef union { > + struct { > + UINT32 RegisterBir : 3; // bit 0..2 > + UINT32 Reserved : 5; // bit 3..7 > + UINT32 RegisterBlockIdentifier : 8; // bit 8..15 > + UINT32 RegisterBlockOffsetLow : 16; // bit 16..31 > + } Bits; > + UINT32 Uint32; > +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_LOW; > + > +typedef union { > + struct { > + UINT32 RegisterBlockOffsetHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_HIGH; > + > +typedef struct { > + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_LOW > OffsetLow; > + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_HIGH > OffsetHigh; > +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_BLOCK; > + > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > // offset 0x00 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 > DesignatedVendorSpecificHeader1; // offset 0x04 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 > DesignatedVendorSpecificHeader2; // offset 0x08 > + UINT16 Reserved; > // offset 0x0A > + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_BLOCK > RegisterBlock[1]; // offset 0x0C > +} CXL_REGISTER_LOCATOR_DVSEC; > + > +// > +// CXL HDM Decoder Capability Header Register > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.5 > +// > +typedef union { > + struct { > + UINT32 CxlCapabilityId : 16; // bit 0..15 > + UINT32 CxlCapabilityVersion : 4; // bit 16..19 > + UINT32 CxlHdmDecoderCapabilityPointer : 12; // bit 20..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_CAPABILITY_HEADER_REGISTER; > + > +// > +// CXL HDM Decoder Capability Register > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.12 > +// > +typedef union { > + struct { > + UINT32 DecoderCount : 4; // bit > 0..3 > + UINT32 TargetCount : 4; // bit 4..7 > + UINT32 A11to8InterleaveCapable : 1; // bit 8 > + UINT32 A14to12InterleaveCapable : 1; // bit 9 > + UINT32 PoisonOnDecodeErrorCapability : 1; // bit 10 > + UINT32 Reserved : 21; // bit > 11..31 > + } Bits; > + UINT32 Uint32; > +} CXL_2_0_HDM_DECODER_CAPABILITY_REGISTER; > + > +typedef union { > + struct { > + UINT32 PoisonOnDecodeErrorEnable : 1; // bit 0 > + UINT32 HdmDecoderEnable : 1; // bit 1 > + UINT32 Reserved : 30; // bit 2..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_GLOBAL_CONTROL_REGISTER; > + > +typedef union { > + struct { > + UINT32 Reserved : 28; // bit 0..27 > + UINT32 MemoryBaseLow : 4; // bit 28..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_BASE_LOW_REGISTER; > + > +typedef union { > + struct { > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_BASE_HIGH_REGISTER; > + > +typedef union { > + struct { > + UINT32 Reserved : 28; // bit 0..27 > + UINT32 MemorySizeLow : 4; // bit 28..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_SIZE_LOW_REGISTER; > + > +typedef union { > + struct { > + UINT32 MemorySizeHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_SIZE_HIGH_REGISTER; > + > +typedef union { > + struct { > + UINT32 InterleaveGranularity : 4; // bit 0..3 > + UINT32 InterleaveWays : 4; // bit 4..7 > + UINT32 LockOnCommit : 1; // bit 8 > + UINT32 Commit : 1; // bit 9 > + UINT32 Committed : 1; // bit 10 > + UINT32 ErrorNotCommitted : 1; // bit 11 > + UINT32 TargetDeviceType : 1; // bit 12 > + UINT32 Reserved : 19; // bit 13..31 > + } Bits; > + UINT32 Uint32; > +} CXL_2_0_HDM_DECODER_N_CONTROL_REGISTER; > + > +typedef union { > + struct { > + UINT32 TargetPortIdentiferWay0 : 8; // bit 0..7 > + UINT32 TargetPortIdentiferWay1 : 8; // bit 8..15 > + UINT32 TargetPortIdentiferWay2 : 8; // bit 16..23 > + UINT32 TargetPortIdentiferWay3 : 8; // bit 24..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_TARGET_LIST_LOW_REGISTER; > + > +typedef union { > + struct { > + UINT32 Reserved : 28; // bit 0..27 > + UINT32 DpaSkipLow : 4; // bit 28..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_DPA_SKIP_LOW_REGISTER; > + > +typedef union { > + struct { > + UINT32 TargetPortIdentiferWay4 : 8; // bit 0..7 > + UINT32 TargetPortIdentiferWay5 : 8; // bit 8..15 > + UINT32 TargetPortIdentiferWay6 : 8; // bit 16..23 > + UINT32 TargetPortIdentiferWay7 : 8; // bit 24..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_TARGET_LIST_HIGH_REGISTER; > + > +typedef union { > + struct { > + UINT32 DpaSkipHigh : 32; // bit 0..31 > + } Bits; > + UINT32 Uint32; > +} CXL_HDM_DECODER_N_DPA_SKIP_HIGH_REGISTER; > + > +typedef union { > + CXL_HDM_DECODER_N_TARGET_LIST_LOW_REGISTER > TargetListLow; > + CXL_HDM_DECODER_N_DPA_SKIP_LOW_REGISTER DpaSkipLow; > +} CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_LOW; > + > +typedef union { > + CXL_HDM_DECODER_N_TARGET_LIST_HIGH_REGISTER > TargetListHigh; > + CXL_HDM_DECODER_N_DPA_SKIP_HIGH_REGISTER DpaSkipHigh; > +} CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_HIGH; > + > +typedef struct { > + CXL_HDM_DECODER_N_BASE_LOW_REGISTER > DecoderBaseLow; // 0x10 > + CXL_HDM_DECODER_N_BASE_HIGH_REGISTER > DecoderBaseHigh; // 0x14 > + CXL_HDM_DECODER_N_SIZE_LOW_REGISTER > DecoderSizeLow; // 0x18 > + CXL_HDM_DECODER_N_SIZE_HIGH_REGISTER > DecoderSizeHigh; // 0x1c > + CXL_2_0_HDM_DECODER_N_CONTROL_REGISTER > DecoderControl; // 0x20 > + CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_LOW > DecoderTargetListDpaSkipLow; // 0x24 > + CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_HIGH > DecoderTargetListDpaSkipHigh; // 0x28 > + UINT32 Reserved; > // 0x2C > +} CXL_HDM_DECODER_N_INFO; > + > +typedef union { > + struct { > + UINT64 CxlDeviceCapabilityId : 16; // bit 0..15 > + UINT64 CxlDeviceCapabilityVersion : 8; // bit 16..23 > + UINT64 Reserved1 : 8; // bit 24..31 > + UINT64 CxlDeviceCapabilitiesCount : 16; // bit 32..47 > + UINT64 Reserved2 : 16; // bit 48..63 > + } Bits; > + UINT64 Uint64; > +} CXL_DEVICE_CAPABILITIES_ARRAY_REGISTER; > + > +// > +// CXL Memory Status Register > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5 > +// > +typedef union { > + struct { > + UINT64 DeviceFatal : 1; // bit 0 > + UINT64 FwHalt : 1; // bit 1 > + UINT64 MediaStatus : 2; // bit 2..3 > + UINT64 MailboxInterfacesReady : 1; // bit 4 > + UINT64 ResetNeeded : 3; // bit 5..7 > + UINT64 Reserved : 56; // bit 8..63 > + } Bits; > + UINT64 Uint64; > +} CXL_MEMORY_DEVICE_STATUS_REGISTER; > + > +#pragma pack() > + > +#endif > -- > 2.34.1 >=20 >=20 >=20 > ________________________________________ > From: Ni, Ray > Sent: Friday, June 30, 2023 2:08 PM > To: devel@edk2.groups.io; Chris Li OS; Yao, Jiewen; Nong, Foster > Subject: RE: [edk2-devel] [PATCH 1/1] MdePkg: Add Cxl20.h into > IndustryStandard >=20 > +@Nong, Foster >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of Chris Li > OS > > via groups.io > > Sent: Friday, June 30, 2023 2:07 PM > > To: Yao, Jiewen ; devel@edk2.groups.io > > Subject: Re: [edk2-devel] [PATCH 1/1] MdePkg: Add Cxl20.h into > > IndustryStandard > > > > Thanks Jiewen, will soon send an v2 for it. > > > > ________________________________________ > > From: Yao, Jiewen > > Sent: Thursday, June 29, 2023 4:43 PM > > To: Chris Li OS; devel@edk2.groups.io > > Cc: Yao, Jiewen > > Subject: RE: [PATCH 1/1] MdePkg: Add Cxl20.h into IndustryStandard > > > > Thanks for the update. > > > > +} HDM_DECODER_N_INFO; > > > > I think this need add CXL_ prefix. > > > > Other looks good to me. > > > > Thank you > > Yao, Jiewen > > > > > > > > > -----Original Message----- > > > From: Chris Li OS > > > Sent: Wednesday, June 28, 2023 1:28 PM > > > To: devel@edk2.groups.io; Yao, Jiewen > > > Subject: [PATCH 1/1] MdePkg: Add Cxl20.h into IndustryStandard > > > > > > 1) Add CXL 2.0 header file to comply with CXL 2.0 specification > > > 2) CXL 2.0 header will embed Cxl11.h > > > 3) Updated Cxl.h to point to 2.0 header file > > > > > > Signed-off-by: Chris Li > > > --- > > > MdePkg/Include/IndustryStandard/Cxl.h | 2 +- > > > MdePkg/Include/IndustryStandard/Cxl20.h | 477 > > ++++++++++++++++++++++++ > > > 2 files changed, 478 insertions(+), 1 deletion(-) > > > create mode 100644 MdePkg/Include/IndustryStandard/Cxl20.h > > > > > > diff --git a/MdePkg/Include/IndustryStandard/Cxl.h > > > b/MdePkg/Include/IndustryStandard/Cxl.h > > > index 06c1230e3e..9ad3242e25 100644 > > > --- a/MdePkg/Include/IndustryStandard/Cxl.h > > > +++ b/MdePkg/Include/IndustryStandard/Cxl.h > > > @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > #ifndef _CXL_MAIN_H_ > > > #define _CXL_MAIN_H_ > > > > > > -#include > > > +#include > > > // > > > // CXL assigned new Vendor ID > > > // > > > diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h > > > b/MdePkg/Include/IndustryStandard/Cxl20.h > > > new file mode 100644 > > > index 0000000000..a08251f4e9 > > > --- /dev/null > > > +++ b/MdePkg/Include/IndustryStandard/Cxl20.h > > > @@ -0,0 +1,477 @@ > > > +/** @file > > > + CXL 2.0 Register definitions > > > + > > > + This file contains the register definitions based on the Compute > Express Link > > > + (CXL) Specification Revision 2.0. > > > + > > > + Copyright (c) 2023, Ampere Computing LLC. All rights reserved.
> > > + > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > + > > > +**/ > > > + > > > +#ifndef CXL20_H_ > > > +#define CXL20_H_ > > > + > > > +#include > > > + > > > +// > > > +// Ensure proper structure formats > > > +// > > > +#pragma pack(1) > > > + > > > + > > > +// > > > +// CXL DVSEC IDs and Revisions > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.1 > > > +// > > > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_CXL_DEVICE > 0x0 > > > +#define CXL_DVSEC_ID_NON_CXL_FUNCTION_MAP > 0x2 > > > +#define CXL_DVSEC_ID_CXL20_EXTENSIONS_DVSEC_FOR_PORTS > 0x3 > > > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_PORTS > 0x4 > > > +#define CXL_DVSEC_ID_GPF_DVSEC_FOR_CXL_DEVICES > 0x5 > > > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_FLEX_BUS_PORT > 0x7 > > > +#define CXL_DVSEC_ID_REGISTER_LOCATOR > 0x8 > > > +#define CXL_DVSEC_ID_MLD > 0x9 > > > +#define CXL_DVSEC_ID_PCIE_DVSEC_FOR_TEST_CAPABILITY > 0xA > > > + > > > +#define CXL20_DVSEC_REVISON_REGISTOR_LOCATOR > 0x0 > > > + > > > +// > > > +// Register Block ID > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9.1 > > > +// > > > +#define CXL_REGISTER_BLOCK_ID_EMPTY > 0x0 > > > +#define CXL_REGISTER_BLOCK_ID_COMPONENT > 0x01 > > > +#define CXL_REGISTER_BLOCK_ID_BAR_VIRTUALIZATION_ACL > 0x02 > > > +#define CXL_REGISTER_BLOCK_ID_DEVICE > 0x03 > > > + > > > +// > > > +// Component Register Block Register Ranges Offset > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.4 > > > +// > > > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_IO > 0x0 > > > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_CACHE_MEM > > > 0x1000 > > > +#define CXL_COMPONENT_REGISTERS_RANGE_OFFSET_ARB_MUX > > 0xE000 > > > + > > > +// > > > +// CXL Cache Memory Capability IDs > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5 > > > +// > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_CXL > 0x1 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_RAS > 0x2 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_SECURITY > 0x3 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_LINK > 0x4 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_HDM_DECODER > 0x5 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_SECURITY > 0x6 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_IDE > 0x7 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_SNOOP_FILTER > 0x8 > > > +#define CXL_CACHE_MEM_CAPABILITY_ID_MASK > 0xFFFF > > > + > > > +// > > > +// Generic CXL Device Capability IDs 0x0000 ~ 0x3FFF > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2= . 1 > > > +// > > > +#define > CXL_DEVICE_CAPABILITY_ID_CAPABILITIES_ARRAY_REGISTER > > > 0x0000 > > > +#define CXL_DEVICE_CAPABILITY_ID_DEVICE_STATUS > 0x0001 > > > +#define CXL_DEVICE_CAPABILITY_ID_PRIMARY_MAILBOX > 0x0002 > > > +#define CXL_DEVICE_CAPABILITY_ID_SECONDARY_MAILBOX > 0x0003 > > > + > > > +// > > > +// Specific CXL Device Capability IDs 0x4000 ~ 0x7FFF > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.2= . 1 > > > +// > > > +// (ref: CXL 2.0 spec $8.2.8.5) > > > +#define CXL_DEVICE_CAPABILITY_ID_MEMORY_DEVICE_STATUS > > > 0x4000 > > > +#define CXL_DEVICE_CAPABILITY_ID_MASK > 0xFFFF > > > + > > > +// > > > +// Memory Device Status > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5= . 1.1 > > > +// > > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_NOT_READY > 0b00 > > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_READY > 0b01 > > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_ERROR > 0b10 > > > +#define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED > 0b11 > > > + > > > +// > > > +// PCIe DVSEC for CXL Device > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.3 > > > +// > > > +typedef union { > > > + struct { > > > + UINT16 CacheCapable : 1; > // bit 0 > > > + UINT16 IoCapable : 1; > // bit 1 > > > + UINT16 MemCapable : 1; > // bit 2 > > > + UINT16 MemHwInitMode : 1; > // bit 3 > > > + UINT16 HdmCount : 2; > // bit 4..5 > > > + UINT16 CacheWriteBackAndInvalidateCapable : 1; // > bit 6 > > > + UINT16 CxlResetCapable : 1; > // bit 7 > > > + UINT16 CxlResetTimeout : 3; > // bit 8..10 > > > + UINT16 CxlResetMemClrCapable : 1; > // bit 11 > > > + UINT16 Reserved : 1; > // bit 12 > > > + UINT16 MultipleLogicalDevice : 1; // > bit 13 > > > + UINT16 ViralCapable : 1; > // bit 14 > > > + UINT16 PmInitCompletionReportingCapable : 1; // > bit 15 > > > + } Bits; > > > + UINT16 Uint16; > > > +} CXL_DVSEC_CXL_DEVICE_CAPABILITY; > > > + > > > +typedef union { > > > + struct { > > > + UINT16 CacheEnable : 1; // bit 0 > > > + UINT16 IoEnable : 1; // bit 1 > > > + UINT16 MemEnable : 1; // bit 2 > > > + UINT16 CacheSfCoverage : 5; // bit 3..7 > > > + UINT16 CacheSfGranularity : 3; // bit 8..10 > > > + UINT16 CacheCleanEviction : 1; // bit 11 > > > + UINT16 Reserved1 : 2; // bit 12..13 > > > + UINT16 ViralEnable : 1; // bit 14 > > > + UINT16 Reserved2 : 1; // bit 15 > > > + } Bits; > > > + UINT16 Uint16; > > > +} CXL_DVSEC_CXL_DEVICE_CONTROL; > > > + > > > +typedef union { > > > + struct { > > > + UINT16 Reserved1 : 14; // bit 0..13 > > > + UINT16 ViralStatus : 1; // bit 14 > > > + UINT16 Reserved2 : 1; // bit 15 > > > + } Bits; > > > + UINT16 Uint16; > > > +} CXL_DVSEC_CXL_DEVICE_STATUS; > > > + > > > +typedef union { > > > + struct { > > > + UINT16 DisableCaching : 1; > // bit 0 > > > + UINT16 InitiateCacheWriteBackAndInvalidate : 1; // bit > 1 > > > + UINT16 InitiateCxlReset : 1; // > bit 2 > > > + UINT16 CxlResetMemClrEnable : 1; > // bit 3 > > > + UINT16 Reserved : 12; > // bit 4..15 > > > + } Bits; > > > + UINT16 Uint16; > > > +} CXL_2_0_DVSEC_CXL_DEVICE_CONTROL2; > > > + > > > +typedef union { > > > + struct { > > > + UINT16 CacheInvalid : 1; > // bit 0 > > > + UINT16 CxlResetComplete : 1; > // bit 1 > > > + UINT16 Reserved : 13; > // bit 2..14 > > > + UINT16 PowerManagementInitialzationComplete : 1; > // bit 15 > > > + } Bits; > > > + UINT16 Uint16; > > > +} CXL_2_0_DVSEC_CXL_DEVICE_STATUS2; > > > + > > > +typedef union { > > > + struct { > > > + UINT16 ConfigLock : 1; // bit 0 > > > + UINT16 Reserved : 15; // bit 1..15 > > > + } Bits; > > > + UINT16 Uint16; > > > +} CXL_DVSEC_CXL_DEVICE_LOCK; > > > + > > > +typedef union { > > > + struct { > > > + UINT16 CacheSizeUnit : 4; // bit 0..3 > > > + UINT16 Reserved : 4; // bit 4..7 > > > + UINT16 CacheSize : 8; // bit 8..15 > > > + } Bits; > > > + UINT16 Uint16; > > > +} CXL_2_0_DVSEC_CXL_DEVICE_CAPABILITY2; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemorySizeHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_HIGH; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemoryInfoValid : 1; // bit 0 > > > + UINT32 MemoryActive : 1; // bit 1 > > > + UINT32 MediaType : 3; // bit 2..4 > > > + UINT32 MemoryClass : 3; // bit 5..7 > > > + UINT32 DesiredInterleave : 5; // bit 8..12 > > > + UINT32 MemoryActiveTimeout : 3; // bit 13..15 > > > + UINT32 Reserved : 12; // bit 16..27 > > > + UINT32 MemorySizeLow : 4; // bit 28..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_LOW; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_HIGH; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 Reserved : 28; // bit 0..27 > > > + UINT32 MemoryBaseLow : 4; // bit 28..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_LOW; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemorySizeHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_HIGH; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemoryInfoValid : 1; // bit 0 > > > + UINT32 MemoryActive : 1; // bit 1 > > > + UINT32 MediaType : 3; // bit 2..4 > > > + UINT32 MemoryClass : 3; // bit 5..7 > > > + UINT32 DesiredInterleave : 5; // bit 8..12 > > > + UINT32 MemoryActiveTimeout : 3; // bit 13..15 > > > + UINT32 Reserved : 12; // bit 16..27 > > > + UINT32 MemorySizeLow : 4; // bit 28..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_LOW; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_HIGH; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 Reserved : 28; // bit 0..27 > > > + UINT32 MemoryBaseLow : 4; // bit 28..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_LOW; > > > + > > > +typedef struct { > > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER > Header; > > > // offset 0x00 > > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 > > > DesignatedVendorSpecificHeader1; // offset 0x04 > > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 > > > DesignatedVendorSpecificHeader2; // offset 0x08 > > > + CXL_DVSEC_CXL_DEVICE_CAPABILITY > DeviceCapability; > > > // offset 0x0A > > > + CXL_DVSEC_CXL_DEVICE_CONTROL > DeviceControl; > > > // offset 0x0C > > > + CXL_DVSEC_CXL_DEVICE_STATUS > DeviceStatus; // > > > offset 0x0E > > > + CXL_2_0_DVSEC_CXL_DEVICE_CONTROL2 > DeviceControl2; > > > // offset 0x10 > > > + CXL_2_0_DVSEC_CXL_DEVICE_STATUS2 > DeviceStatus2; > > > // offset 0x12 > > > + CXL_DVSEC_CXL_DEVICE_LOCK > DeviceLock; // > > > offset 0x14 > > > + CXL_2_0_DVSEC_CXL_DEVICE_CAPABILITY2 > DeviceCapability2; > > > // offset 0x16 > > > + CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_HIGH > > DeviceRange1SizeHigh; > > > // offset 0x18 > > > + CXL_DVSEC_CXL_DEVICE_RANGE1_SIZE_LOW > > DeviceRange1SizeLow; > > > // offset 0x1C > > > + CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_HIGH > > > DeviceRange1BaseHigh; // offset 0x20 > > > + CXL_DVSEC_CXL_DEVICE_RANGE1_BASE_LOW > > > DeviceRange1BaseLow; // offset 0x24 > > > + CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_HIGH > > DeviceRange2SizeHigh; > > > // offset 0x28 > > > + CXL_DVSEC_CXL_DEVICE_RANGE2_SIZE_LOW > > DeviceRange2SizeLow; > > > // offset 0x2C > > > + CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_HIGH > > > DeviceRange2BaseHigh; // offset 0x30 > > > + CXL_DVSEC_CXL_DEVICE_RANGE2_BASE_LOW > > > DeviceRange2BaseLow; // offset 0x34 > > > +} CXL_2_0_DVSEC_CXL_DEVICE; > > > + > > > +// > > > +// Register Locator DVSEC > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.1.9 > > > +// > > > +typedef union { > > > + struct { > > > + UINT32 RegisterBir : 3; // bit 0..2 > > > + UINT32 Reserved : 5; // bit 3..7 > > > + UINT32 RegisterBlockIdentifier : 8; // bit 8..15 > > > + UINT32 RegisterBlockOffsetLow : 16; // bit 16..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_LOW; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 RegisterBlockOffsetHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_HIGH; > > > + > > > +typedef struct { > > > + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_LOW > OffsetLow; > > > + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_OFFSET_HIGH > OffsetHigh; > > > +} CXL_REGISTER_LOCATOR_DVSEC_REGISTER_BLOCK; > > > + > > > + > > > +typedef struct { > > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER > Header; > > > // offset 0x00 > > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 > > > DesignatedVendorSpecificHeader1; // offset 0x04 > > > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 > > > DesignatedVendorSpecificHeader2; // offset 0x08 > > > + UINT16 > Reserved; // offset 0x0A > > > + CXL_REGISTER_LOCATOR_DVSEC_REGISTER_BLOCK > RegisterBlock[1]; > > > // offset 0x0C > > > +} CXL_REGISTER_LOCATOR_DVSEC; > > > + > > > +// > > > +// CXL HDM Decoder Capability Header Register > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.5 > > > +// > > > +typedef union { > > > + struct { > > > + UINT32 CxlCapabilityId : 16; // bit > 0..15 > > > + UINT32 CxlCapabilityVersion : 4; // bit > 16..19 > > > + UINT32 CxlHdmDecoderCapabilityPointer : 12; // bit > 20..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_CAPABILITY_HEADER_REGISTER; > > > + > > > +// > > > +// CXL HDM Decoder Capability Register > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.5.1= 2 > > > +// > > > +typedef union { > > > + struct { > > > + UINT32 DecoderCount : 4; // bit > 0..3 > > > + UINT32 TargetCount : 4; // bit > 4..7 > > > + UINT32 A11to8InterleaveCapable : 1; // bit 8 > > > + UINT32 A14to12InterleaveCapable : 1; // bit 9 > > > + UINT32 PoisonOnDecodeErrorCapability : 1; // bit 10 > > > + UINT32 Reserved : 21; // bit > 11..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_2_0_HDM_DECODER_CAPABILITY_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 PoisonOnDecodeErrorEnable : 1; // bit 0 > > > + UINT32 HdmDecoderEnable : 1; // bit 1 > > > + UINT32 Reserved : 30; // bit > 2..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_GLOBAL_CONTROL_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 Reserved : 28; // bit 0..27 > > > + UINT32 MemoryBaseLow : 4; // bit 28..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_BASE_LOW_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemoryBaseHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_BASE_HIGH_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 Reserved : 28; // bit 0..27 > > > + UINT32 MemorySizeLow : 4; // bit 28..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_SIZE_LOW_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 MemorySizeHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_SIZE_HIGH_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 InterleaveGranularity : 4; // bit 0..3 > > > + UINT32 InterleaveWays : 4; // bit 4..7 > > > + UINT32 LockOnCommit : 1; // bit 8 > > > + UINT32 Commit : 1; // bit 9 > > > + UINT32 Committed : 1; // bit 10 > > > + UINT32 ErrorNotCommitted : 1; // bit 11 > > > + UINT32 TargetDeviceType : 1; // bit 12 > > > + UINT32 Reserved : 19; // bit 13..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_2_0_HDM_DECODER_N_CONTROL_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 TargetPortIdentiferWay0 : 8; // bit 0..7 > > > + UINT32 TargetPortIdentiferWay1 : 8; // bit 8..15 > > > + UINT32 TargetPortIdentiferWay2 : 8; // bit 16..23 > > > + UINT32 TargetPortIdentiferWay3 : 8; // bit 24..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_TARGET_LIST_LOW_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 Reserved : 28; // bit 0..27 > > > + UINT32 DpaSkipLow : 4; // bit 28..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_DPA_SKIP_LOW_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 TargetPortIdentiferWay4 : 8; // bit 0..7 > > > + UINT32 TargetPortIdentiferWay5 : 8; // bit 8..15 > > > + UINT32 TargetPortIdentiferWay6 : 8; // bit 16..23 > > > + UINT32 TargetPortIdentiferWay7 : 8; // bit 24..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_TARGET_LIST_HIGH_REGISTER; > > > + > > > +typedef union { > > > + struct { > > > + UINT32 DpaSkipHigh : 32; // bit 0..31 > > > + } Bits; > > > + UINT32 Uint32; > > > +} CXL_HDM_DECODER_N_DPA_SKIP_HIGH_REGISTER; > > > + > > > +typedef union { > > > + CXL_HDM_DECODER_N_TARGET_LIST_LOW_REGISTER > TargetListLow; > > > + CXL_HDM_DECODER_N_DPA_SKIP_LOW_REGISTER > DpaSkipLow; > > > +} CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_LOW; > > > + > > > +typedef union { > > > + CXL_HDM_DECODER_N_TARGET_LIST_HIGH_REGISTER > TargetListHigh; > > > + CXL_HDM_DECODER_N_DPA_SKIP_HIGH_REGISTER > DpaSkipHigh; > > > +} CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_HIGH; > > > + > > > +typedef struct { > > > + CXL_HDM_DECODER_N_BASE_LOW_REGISTER > DecoderBaseLow; > > > // 0x10 > > > + CXL_HDM_DECODER_N_BASE_HIGH_REGISTER > DecoderBaseHigh; > > > // 0x14 > > > + CXL_HDM_DECODER_N_SIZE_LOW_REGISTER > DecoderSizeLow; > > > // 0x18 > > > + CXL_HDM_DECODER_N_SIZE_HIGH_REGISTER > DecoderSizeHigh; > > > // 0x1c > > > + CXL_2_0_HDM_DECODER_N_CONTROL_REGISTER > DecoderControl; > > > // 0x20 > > > + CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_LOW > > > DecoderTargetListDpaSkipLow; // 0x24 > > > + CXL_HDM_DECODER_N_TARGET_LIST_OR_DPA_SKIP_HIGH > > > DecoderTargetListDpaSkipHigh; // 0x28 > > > + UINT32 Reserved; > // 0x2C > > > +} HDM_DECODER_N_INFO; > > > + > > > +typedef union { > > > + struct { > > > + UINT64 CxlDeviceCapabilityId : 16; // bit 0..15 > > > + UINT64 CxlDeviceCapabilityVersion : 8; // bit 16..23 > > > + UINT64 Reserved1 : 8; // bit > 24..31 > > > + UINT64 CxlDeviceCapabilitiesCount : 16; // bit 32..47 > > > + UINT64 Reserved2 : 16; // bit > 48..63 > > > + } Bits; > > > + UINT64 Uint64; > > > +} CXL_DEVICE_CAPABILITIES_ARRAY_REGISTER; > > > + > > > +// > > > +// CXL Memory Status Register > > > +// Compute Express Link Specification Revision 2.0 - Chapter 8.2.8.5 > > > +// > > > +typedef union { > > > + struct { > > > + UINT64 DeviceFatal : 1; // bit 0 > > > + UINT64 FwHalt : 1; // bit 1 > > > + UINT64 MediaStatus : 2; // bit 2..3 > > > + UINT64 MailboxInterfacesReady : 1; // bit 4 > > > + UINT64 ResetNeeded : 3; // bit 5..7 > > > + UINT64 Reserved : 56; // bit 8..63 > > > + } Bits; > > > + UINT64 Uint64; > > > +} CXL_MEMORY_DEVICE_STATUS_REGISTER; > > > + > > > +#pragma pack() > > > + > > > +#endif > > > -- > > > 2.34.1 > > > > > > > > >=20 >=20 >=20 >=20 >=20