From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web12.3712.1603330015938228980 for ; Wed, 21 Oct 2020 18:26:56 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Thu, 22 Oct 2020 09:26:46 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: "'Sami Mujawar'" , Cc: , , , , , , , References: <20201021155552.28772-1-sami.mujawar@arm.com> <20201021155552.28772-2-sami.mujawar@arm.com> In-Reply-To: <20201021155552.28772-2-sami.mujawar@arm.com> Subject: =?UTF-8?B?5Zue5aSNOiBbUEFUQ0ggdjIgMS8yXSBNZGVQa2cvSW5kdXN0cnlTdGFuZGFyZDogQUVTVCBUYWJsZSBkZWZpbml0aW9u?= Date: Thu, 22 Oct 2020 09:26:48 +0800 Message-ID: <008c01d6a812$699cf4e0$3cd6dea0$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQFzJnj7qpIuqvFlkZ1GryYOpqnPKAJQmfCPqldTCbA= Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Reviewed-by: Liming Gao > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: Sami Mujawar > =B7=A2=CB=CD=CA=B1=BC=E4: 2020=C4=EA10=D4=C221=C8=D5 23:56 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io > =B3=AD=CB=CD: Sami Mujawar ; > michael.d.kinney@intel.com; gaoliming@byosoft.com.cn; > zhiguang.liu@intel.com; ray.ni@intel.com; zhichao.gao@intel.com; > ard.biesheuvel@arm.com; Matteo.Carlini@arm.com; > Ben.Adderson@arm.com; nd@arm.com > =D6=F7=CC=E2: [PATCH v2 1/2] MdePkg/IndustryStandard: AEST Table = definition >=20 > From: Marc Moisson-Franckhauser >=20 > Add definition for the Arm Error Source Table (AEST) described in > the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, > dated 28 September 2020. > (https://developer.arm.com/documentation/den0085/0101/) >=20 > Signed-off-by: Marc Moisson-Franckhauser > > Signed-off-by: Sami Mujawar > --- >=20 > Notes: > v2: > - AEST is not defined in ACPI 6.3 spec and should not be [Liming] > added to Acpi63.h and for structure definition and its > field, its comment starts with /// or //. > - Moved AEST table signature to ArmErrorSourceTable.h and > [SAMI] > updated structure and field documenting style to match > coding convention. > Ref: https://edk2.groups.io/g/devel/message/66151 >=20 > MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h | 357 > ++++++++++++++++++++ > 1 file changed, 357 insertions(+) >=20 > diff --git a/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h > b/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h > new file mode 100644 > index > 0000000000000000000000000000000000000000..369b03a50b65a7f6d0012 > eec9898a14dcd61976d > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h > @@ -0,0 +1,357 @@ > +/** @file > + Arm Error Source Table as described in the > + 'ACPI for the Armv8 RAS Extensions 1.1' Specification. > + > + Copyright (c) 2020 Arm Limited. > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > + @par Reference(s): > + - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, > + dated 28 September 2020. > + (https://developer.arm.com/documentation/den0085/0101/) > + > + @par Glossary > + - Ref : Reference > + - Id : Identifier > +**/ > + > +#ifndef ARM_ERROR_SOURCE_TABLE_H_ > +#define ARM_ERROR_SOURCE_TABLE_H_ > + > +/// > +/// "AEST" Arm Error Source Table > +/// > +#define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE > SIGNATURE_32('A', 'E', 'S', 'T') > + > +#define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION 1 > + > +#pragma pack(1) > + > +/// > +/// Arm Error Source Table definition. > +/// > +typedef struct { > + EFI_ACPI_DESCRIPTION_HEADER Header; > +} EFI_ACPI_ARM_ERROR_SOURCE_TABLE; > + > +/// > +/// AEST Node structure. > +/// > +typedef struct { > + /// Node type: > + /// 0x00 - Processor error node > + /// 0x01 - Memory error node > + /// 0x02 - SMMU error node > + /// 0x03 - Vendor-defined error node > + /// 0x04 - GIC error node > + UINT8 Type; > + > + /// Length of structure in bytes. > + UINT16 Length; > + > + /// Reserved - Must be zero. > + UINT8 Reserved; > + > + /// Offset from the start of the node to node-specific data. > + UINT32 DataOffset; > + > + /// Offset from the start of the node to the node interface = structure. > + UINT32 InterfaceOffset; > + > + /// Offset from the start of the node to node interrupt array. > + UINT32 InterruptArrayOffset; > + > + /// Number of entries in the interrupt array. > + UINT32 InterruptArrayCount; > + > + // Generic node data > + > + /// The timestamp frequency of the counter in Hz. > + UINT64 TimestampRate; > + > + /// Reserved - Must be zero. > + UINT64 Reserved1; > + > + /// The rate in Hz at which the Error Generation Counter = decrements. > + UINT64 ErrorInjectionCountdownRate; > +} EFI_ACPI_AEST_NODE_STRUCT; > + > +// AEST Node type definitions > +#define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR 0x0 > +#define EFI_ACPI_AEST_NODE_TYPE_MEMORY 0x1 > +#define EFI_ACPI_AEST_NODE_TYPE_SMMU 0x2 > +#define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED 0x3 > +#define EFI_ACPI_AEST_NODE_TYPE_GIC 0x4 > + > +/// > +/// AEST Node Interface structure. > +/// > +typedef struct { > + /// Interface type: > + /// 0x0 - System register (SR) > + /// 0x1 - Memory mapped (MMIO) > + UINT8 Type; > + > + /// Reserved - Must be zero. > + UINT8 Reserved[3]; > + > + /// AEST node interface flags. > + UINT32 Flags; > + > + /// Base address of error group that contains the error node. > + UINT64 BaseAddress; > + > + /// Zero-based index of the first standard error record that > + /// belongs to this node. > + UINT32 StartErrorRecordIndex; > + > + /// Number of error records in this node including both > + /// implemented and unimplemented records. > + UINT32 NumberErrorRecords; > + > + /// A bitmap indicating the error records within this > + /// node that are implemented in the current system. > + UINT64 ErrorRecordImplemented; > + > + /// A bitmap indicating the error records within this node that > + /// support error status reporting through the ERRGSR register. > + UINT64 ErrorRecordStatusReportingSupported; > + > + /// A bitmap indicating the addressing mode used by each error > + /// record within this node to populate the ERR_ADDR register. > + UINT64 AddressingMode; > +} EFI_ACPI_AEST_INTERFACE_STRUCT; > + > +// AEST Interface node type definitions. > +#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0 > +#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1 > + > +// AEST node interface flag definitions. > +#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0 > +#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0 > +#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1 > + > +/// > +/// AEST Node Interrupt structure. > +/// > +typedef struct { > + /// Interrupt type: > + /// 0x0 - Fault Handling Interrupt > + /// 0x1 - Error Recovery Interrupt > + UINT8 InterruptType; > + > + /// Reserved - Must be zero. > + UINT8 Reserved[2]; > + > + /// Interrupt flags > + /// Bits [31:1]: Must be zero. > + /// Bit 0: > + /// 0b - Interrupt is edge-triggered > + /// 1b - Interrupt is level-triggered > + UINT8 InterruptFlags; > + > + /// GSIV of interrupt, if interrupt is an SPI or a PPI. > + UINT32 InterruptGsiv; > + > + /// If MSI is supported, then this field must be set to the > + /// Identifier field of the IORT ITS Group node. > + UINT8 ItsGroupRefId; > + > + /// Reserved - must be zero. > + UINT8 Reserved1[3]; > +} EFI_ACPI_AEST_INTERRUPT_STRUCT; > + > +// AEST Interrupt node - interrupt type defintions. > +#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0 > +#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1 > + > +// AEST Interrupt node - interrupt flag defintions. > +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0 > +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0 > + > +/// > +/// Cache Processor Resource structure. > +/// > +typedef struct { > + /// Reference to the cache structure in the PPTT table. > + UINT32 CacheRefId; > + > + /// Reserved > + UINT32 Reserved; > +} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT; > + > +/// > +/// TLB Processor Resource structure. > +/// > +typedef struct { > + /// TLB level from perspective of current processor. > + UINT32 TlbRefId; > + > + /// Reserved > + UINT32 Reserved; > +} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT; > + > +/// > +/// Processor Generic Resource structure. > +/// > +typedef struct { > + /// Vendor-defined supplementary data. > + UINT32 Data; > +} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT; > + > +/// > +/// AEST Processor Resource union. > +/// > +typedef union { > + /// Processor Cache resource. > + EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache; > + > + /// Processor TLB resource. > + EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb; > + > + /// Processor Generic resource. > + EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic; > +} EFI_ACPI_AEST_PROCESSOR_RESOURCE; > + > +/// > +/// AEST Processor structure. > +/// > +typedef struct { > + /// AEST Node header > + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; > + > + /// Processor ID of node. > + UINT32 AcpiProcessorId; > + > + /// Resource type of the processor node. > + /// 0x0 - Cache > + /// 0x1 - TLB > + /// 0x2 - Generic > + UINT8 ResourceType; > + > + /// Reserved - must be zero. > + UINT8 Reserved; > + > + /// Processor structure flags. > + UINT8 Flags; > + > + /// Processor structure revision. > + UINT8 Revision; > + > + /// Processor affinity descriptor for the resource that this > + /// error node pertains to. > + UINT64 ProcessorAffinityLevelIndicator; > + > + /// Processor resource > + EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource; > + > + // Node Interface > + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; > + > + // Node Interrupt Array > + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; > +} EFI_ACPI_AEST_PROCESSOR_STRUCT; > + > +// AEST Processor resource type definitions. > +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0 > +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1 > +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2 > + > +// AEST Processor flag definitions. > +#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0 > +#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1 > + > +/// > +/// Memory Controller structure. > +/// > +typedef struct { > + /// AEST Node header > + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; > + > + /// SRAT proximity domain. > + UINT32 ProximityDomain; > + > + // Node Interface > + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; > + > + // Node Interrupt Array > + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; > +} EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT; > + > +/// > +/// SMMU structure. > +/// > +typedef struct { > + /// AEST Node header > + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; > + > + /// Reference to the IORT table node that describes this SMMU. > + UINT32 SmmuRefId; > + > + /// Reference to the IORT table node that is associated with the > + /// sub-component within this SMMU. > + UINT32 SubComponentRefId; > + > + // Node Interface > + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; > + > + // Node Interrupt Array > + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; > +} EFI_ACPI_AEST_SMMU_STRUCT; > + > +/// > +/// Vendor-Defined structure. > +/// > +typedef struct { > + /// AEST Node header > + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; > + > + /// ACPI HID of the component. > + UINT32 HardwareId; > + > + /// The ACPI Unique identifier of the component. > + UINT32 UniqueId; > + > + /// Vendor-specific data, for example to identify this error = source. > + UINT8 VendorData[16]; > + > + // Node Interface > + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; > + > + // Node Interrupt Array > + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; > +} EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT; > + > +/// > +/// GIC structure. > +/// > +typedef struct { > + /// AEST Node header > + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; > + > + /// Type of GIC interface that is associated with this error node. > + /// 0x0 - GIC CPU (GICC) > + /// 0x1 - GIC Distributor (GICD) > + /// 0x2 - GIC Resistributor (GICR) > + /// 0x3 - GIC ITS (GITS) > + UINT32 InterfaceType; > + > + /// Identifier for the interface instance. > + UINT32 GicInterfaceRefId; > + > + // Node Interface > + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; > + > + // Node Interrupt Array > + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; > +} EFI_ACPI_AEST_GIC_STRUCT; > + > +// AEST GIC interface type definitions. > +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0 > +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1 > +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2 > +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3 > + > +#pragma pack() > + > +#endif // ARM_ERROR_SOURCE_TABLE_H_ > -- > 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'