From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3ACEA2218E927 for ; Tue, 5 Dec 2017 12:00:45 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9745A8B125; Tue, 5 Dec 2017 20:05:16 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-123-60.rdu2.redhat.com [10.10.123.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id F1B9E69559; Tue, 5 Dec 2017 20:05:15 +0000 (UTC) To: Jian J Wang , edk2-devel@lists.01.org References: <20171205081604.11644-1-jian.j.wang@intel.com> From: Laszlo Ersek Message-ID: <00ac8be3-af36-c3e4-3cb8-c67a8479e2ee@redhat.com> Date: Tue, 5 Dec 2017 21:05:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <20171205081604.11644-1-jian.j.wang@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 05 Dec 2017 20:05:16 +0000 (UTC) Subject: Re: [PATCH v3 0/2] Enable page table write protection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Dec 2017 20:00:46 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 12/05/17 09:16, Jian J Wang wrote: >> v3 changes: >> a. According to code review comments, remove the public definitions of >> page table pool. Now the DxeIpl and CpuDxe will have their own page >> table pool but in the same mechanism. Related PCDs, GUDI and headers >> are also removed. >> b. Apply protection to all page tables, including new ones added in >> CpuDxe driver. >> c. Code/comments cleanup. > >> v2 changes: >> a. Enable protection on any newly added page table after DxeIpl. >> b. Introduce page table pool concept to make page table allocation >> and protection easier and error free. > > Write Protect feature (CR0.WP) is always enabled in driver UefiCpuPkg/CpuDxe. > But the memory pages used for page table are not set as read-only in the driver > DxeIplPeim, after the paging is setup. This might jeopardize the page table > integrity if there's buffer overflow occured in other part of system. > > This patch series will change this situation by clearing R/W bit in page attribute > of the pages used as page table. > > Validation works include booting Windows (10/server 2016) and Linux (Fedora/Ubuntu) > on OVMF and Intel real platform. > > Jian J Wang (2): > MdeModulePkg/DxeIpl: Mark page table as read-only > UefiCpuPkg/CpuDxe: Enable protection for newly added page table > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.h | 34 +++ > MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 8 +- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 301 ++++++++++++++++++++++- > MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 26 ++ > UefiCpuPkg/CpuDxe/CpuDxe.c | 17 +- > UefiCpuPkg/CpuDxe/CpuDxe.h | 2 + > UefiCpuPkg/CpuDxe/CpuPageTable.c | 226 ++++++++++++++++- > UefiCpuPkg/CpuDxe/CpuPageTable.h | 34 +++ > 8 files changed, 635 insertions(+), 13 deletions(-) > series Regression-tested-by: Laszlo Ersek Thanks Laszlo