From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 487077803D2 for ; Sat, 25 May 2024 12:00:55 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=zc309VlRmOI1G456NIEsG8TqnHzOyrLDvXeotkd7Y2E=; c=relaxed/simple; d=groups.io; h=From:To:References:In-Reply-To:Subject:Date:Message-ID:MIME-Version:Thread-Index:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Language; s=20240206; t=1716638453; v=1; b=fC4t21iiLMBklt1c+0YpLkVx7imaNOMJ+KrXdNYv9kpt2CSuAlEX2KldWeThFNLBpV4MIGIR tykRp1te/CMxYLhb1wOdZwL4INT+u8wf3Cu7UfuIQcBofs3LPFZrVKk8ZN26NeztUlVRmqxHhY2 0OxxIPMLGdwSqo7hYGPT0oMqKkpmwLaDyl/aVfHLIcCvNH+/8aObzngHrSWGwPTomMIWORlubp0 lVAejG9+R5Lss0ZznPM7v6f56r5OR5kAqYSaIWMAH/YrjsiRXqGjwpkkH1cKDUvSfpABGphHide yEYUzD/o09i9oBmRkxS6AzYZ5hgmUSs2OhPdYdi7FbzXA== X-Received: by 127.0.0.2 with SMTP id 6qxsYY7687511xuXX3MwA1Uq; Sat, 25 May 2024 05:00:53 -0700 X-Received: from zrleap.intel-email.com (zrleap.intel-email.com [114.80.218.36]) by mx.groups.io with SMTP id smtpd.web11.9875.1716638452870236650 for ; Sat, 25 May 2024 05:00:53 -0700 X-Received: from zrleap.intel-email.com (localhost [127.0.0.1]) by zrleap.intel-email.com (Postfix) with ESMTP id 31C34A32E085 for ; Sat, 25 May 2024 20:00:50 +0800 (CST) X-Received: from localhost (localhost [127.0.0.1]) by zrleap.intel-email.com (Postfix) with ESMTP id 192E5A32E076 for ; Sat, 25 May 2024 20:00:50 +0800 (CST) X-Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by zrleap.intel-email.com (Postfix) with SMTP id 67BFFA32E07D for ; Sat, 25 May 2024 20:00:47 +0800 (CST) X-Received: from DESKTOPS6D0PVI ([114.92.182.254]) (envelope-sender ) by 192.168.6.13 with ESMTP(SSL) for ; Sat, 25 May 2024 20:00:47 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 114.92.182.254 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming via groups.io" To: , , "'Feng, Ning'" References: <20240525074209.1672006-1-ning.feng@intel.com> <17D29748B3A2AE5A.12956@groups.io> In-Reply-To: Subject: =?UTF-8?B?5Zue5aSNOiBbZWRrMi1kZXZlbF0gW1BBVENIXSBVZWZpQ3B1UGtnL01wTGliOkRvIG5vdCBhc3N1bWUgQlNQIGlzICMwLg==?= Date: Sat, 25 May 2024 20:00:46 +0800 Message-ID: <00c901daae9b$2d686070$88392150$@byosoft.com.cn> MIME-Version: 1.0 Thread-Index: AQGczXZPU6Lkq4qpATSKzrThcThBZgGvktN/Ae2tWlayBrFKAA== Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Sat, 25 May 2024 05:00:53 -0700 Resent-From: gaoliming@byosoft.com.cn Reply-To: devel@edk2.groups.io,gaoliming@byosoft.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: vjmPVIEtisL6C6DBvm7AIaxMx7686176AA= Content-Type: multipart/alternative; boundary="----=_NextPart_000_00CA_01DAAEDE.3B8C8AD0" Content-Language: zh-cn X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=fC4t21ii; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io ------=_NextPart_000_00CA_01DAAEDE.3B8C8AD0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Ray: This PR doesn=A1=AFt pass CI. Please check. =20 Thanks Liming =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io =B4=FA=B1= =ED Ni, Ray =B7=A2=CB=CD=CA=B1=BC=E4: 2024=C4=EA5=D4=C225=C8=D5 9:35 =CA=D5=BC=FE=C8=CB: Feng, Ning ; devel@edk2.groups.io;= Ni, Ray ; Gao, Liming =D6=F7=CC=E2: Re: [edk2-devel] [PATCH] UefiCpuPkg/MpLib:Do not assume BSP i= s #0. =20 I created PR for merge: UefiCpuPkg/MpLib:Do not assume BSP is #0. by niruiy= u =A1=A4 Pull Request #5683 =A1=A4 tianocore/edk2 (github.com) =20 But, I cannot set "push" label. =20 @Gao, Liming? =20 Thanks, Ray _____ =20 From: devel@edk2.groups.io > on behalf of Ni, Ray > Sent: Saturday, May 25, 2024 9:32 To: Feng, Ning >; devel@edk2.groups.io > Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/MpLib:Do not assume BSP is #0.= =20 =20 Reviewed-by: Ray Ni > =20 Thanks, Ray _____ =20 From: Feng, Ning > Sent: Saturday, May 25, 2024 15:42 To: devel@edk2.groups.io > Cc: Feng, Ning >; Ni, Ray > Subject: [PATCH] UefiCpuPkg/MpLib:Do not assume BSP is #0.=20 =20 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4778 MPInitlib have wrong expectation that BSP index should always be 0 in MpInitLibInitialize(), SwitchBsp(),ApWakeupFunction(). That will cause the data mismatch, if the initial BSP is not 0. Cc: Ray Ni > Signed-off-by: Ning Feng = > --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 47 ++++++++++++++++++---------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index d724456502..ba497cbfd9 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -114,6 +114,10 @@ FutureBSPProc ( SaveVolatileRegisters (&DataInHob->APInfo.VolatileRegisters); AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo); RestoreVolatileRegisters (&DataInHob->APInfo.VolatileRegisters, FALSE); + // + // Restore VolatileReg saved in CpuMpData->CpuData + // + CopyMem (&DataInHob->CpuData[DataInHob->BspNumber].VolatileRegisters, &DataInHob->APInfo.VolatileRegisters, sizeof (CPU_VOLATILE_REGISTERS)); } =20 /** @@ -761,11 +765,11 @@ ApWakeupFunction ( BistData =3D (UINT32)ApStackData->Bist; =20 // - // CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment, + // CpuMpData->CpuData[BspNumber].VolatileRegisters is initialized based on BSP environment, // to initialize AP in InitConfig path. - // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters points to a different IDT shared by all APs. + // NOTE: IDTR.BASE stored in CpuMpData->CpuData[BspNumber].VolatileRegisters points to a different IDT shared by all APs. // - RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE); + RestoreVolatileRegisters (&CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegisters, FALSE); InitializeApData (CpuMpData, ProcessorNumber, BistData, ApTopOfStack); ApStartupSignalBuffer =3D CpuMpData->CpuData[ProcessorNumber].StartupApSignal; } else { @@ -798,10 +802,10 @@ ApWakeupFunction ( // 1. AP is re-enabled after it's disabled, in either PEI or DXE phase. // 2. AP is initialized in DXE phase. // In either case, use the volatile registers value derived from BSP. - // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].VolatileRegisters points to a + // NOTE: IDTR.BASE stored in CpuMpData->CpuData[BspNumber].VolatileRegisters points to a // different IDT shared by all APs. // - RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters= , FALSE); + RestoreVolatileRegisters (&CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegisters, FALSE); } else { if (CpuMpData->ApLoopMode =3D=3D ApInHltLoop) { // @@ -927,7 +931,7 @@ DxeApEntryPoint ( AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64); } =20 - RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE); + RestoreVolatileRegisters (&CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegisters, FALSE); InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount); PlaceAPInMwaitLoopOrRunLoop ( CpuMpData->ApLoopMode, @@ -2151,11 +2155,16 @@ MpInitLibInitialize ( CpuMpData->BackupBufferSize =3D ApResetVectorSizeBelow1Mb; CpuMpData->WakeupBuffer =3D (UINTN)-1; CpuMpData->CpuCount =3D 1; - CpuMpData->BspNumber =3D 0; - CpuMpData->WaitEvent =3D NULL; - CpuMpData->SwitchBspFlag =3D FALSE; - CpuMpData->CpuData =3D (CPU_AP_DATA *)(CpuMpData + 1); - CpuMpData->CpuInfoInHob =3D (UINT64)(UINTN)(CpuMpData->CpuData + MaxLogicalProcessorNumber); + if (FirstMpHandOff =3D=3D NULL) { + CpuMpData->BspNumber =3D 0; + } else { + CpuMpData->BspNumber =3D GetBspNumber (FirstMpHandOff); + } + + CpuMpData->WaitEvent =3D NULL; + CpuMpData->SwitchBspFlag =3D FALSE; + CpuMpData->CpuData =3D (CPU_AP_DATA *)(CpuMpData + 1); + CpuMpData->CpuInfoInHob =3D (UINT64)(UINTN)(CpuMpData->CpuData + MaxLogicalProcessorNumber); InitializeSpinLock (&CpuMpData->MpLock); CpuMpData->SevEsIsEnabled =3D ConfidentialComputingGuestHas (CCAttrAmdSevEs); CpuMpData->SevSnpIsEnabled =3D ConfidentialComputingGuestHas (CCAttrAmdSevSnp); @@ -2186,11 +2195,11 @@ MpInitLibInitialize ( // Don't pass BSP's TR to APs to avoid AP init failure. // VolatileRegisters.Tr =3D 0; - CopyMem (&CpuMpData->CpuData[0].VolatileRegisters, &VolatileRegisters, sizeof (VolatileRegisters)); + CopyMem (&CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegisters, &VolatileRegisters, sizeof (VolatileRegisters)); // // Set BSP basic information // - InitializeApData (CpuMpData, 0, 0, CpuMpData->Buffer + ApStackSize); + InitializeApData (CpuMpData, CpuMpData->BspNumber, 0, CpuMpData->Buffer = + ApStackSize * (CpuMpData->BspNumber + 1)); // // Save assembly code information // @@ -2245,9 +2254,8 @@ MpInitLibInitialize ( AmdSevUpdateCpuMpData (CpuMpData); } =20 - CpuMpData->CpuCount =3D MaxLogicalProcessorNumber; - CpuMpData->BspNumber =3D GetBspNumber (FirstMpHandOff); - CpuInfoInHob =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; + CpuMpData->CpuCount =3D MaxLogicalProcessorNumber; + CpuInfoInHob =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; for (MpHandOff =3D FirstMpHandOff; MpHandOff !=3D NULL; MpHandOff =3D GetNextMpHandOffHob (MpHandOff)) @@ -2615,7 +2623,12 @@ SwitchBSPWorker ( SaveVolatileRegisters (&CpuMpData->BSPInfo.VolatileRegisters); AsmExchangeRole (&CpuMpData->BSPInfo, &CpuMpData->APInfo); RestoreVolatileRegisters (&CpuMpData->BSPInfo.VolatileRegisters, FALSE); - + // + // Restore VolatileRegs saved in CpuMpData->CpuData + // Don't pass BSP's TR to APs to avoid AP init failure. + // + CopyMem (&CpuMpData->CpuData[CpuMpData->NewBspNumber].VolatileRegisters, &CpuMpData->BSPInfo.VolatileRegisters, sizeof (CPU_VOLATILE_REGISTERS)); + CpuMpData->CpuData[CpuMpData->NewBspNumber].VolatileRegisters.Tr =3D 0; // // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP // --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#119267): https://edk2.groups.io/g/devel/message/119267 Mute This Topic: https://groups.io/mt/106297368/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- ------=_NextPart_000_00CA_01DAAEDE.3B8C8AD0 Content-Type: text/html; charset="gb2312" Content-Transfer-Encoding: quoted-printable

Ray:

  This PR doesn=A1=AFt p= ass CI. Please check.

 <= /span>

Thanks

Liming=

=B7=A2=BC=FE=C8=CB: devel@edk2.groups.io <d= evel@edk2.groups.io> =B4= =FA=B1=ED Ni, = Ray
=B7=A2=CB=CD=CA=B1=BC= =E4: 2024=C4=EA5=D4=C225=C8=D5 9:35
=CA=D5=BC=FE=C8=CB: Feng, Ning <ning.feng@intel.com>; devel@edk2.gr= oups.io; Ni, Ray <ray.ni@intel.com>; Gao, Liming <gaoliming@byosof= t.com.cn>
=D6=F7=CC=E2: Re: [edk2-devel] [PATCH] UefiCpuPkg/MpLib:Do not assume BSP i= s #0.

 

But, I cannot set "push" label.

<= /div>

 

 <= /o:p>

Thanks,

Ray

=

From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of = Ni, Ray <ray.ni@intel.com>Sent: Saturday, May 25, 2024 9:32
To: Feng, Ning <ning.feng@intel.com>; devel@edk2.groups.io <devel@edk2.groups.io>
Subject: Re: = [edk2-devel] [PATCH] UefiCpuPkg/MpLib:Do not assume BSP is #0.

 

R= eviewed-by: Ray Ni <ray.ni@intel.com= >

 

Thanks,

Ray

=

From:= Feng, Ning <ning.feng@intel.com<= /a>>
Sent: Saturday, May 25, 2024 15:42
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Feng,= Ning <ning.feng@intel.com>= ;; Ni, Ray <ray.ni@intel.com>=
Subject: [PATCH] UefiCpuPkg/MpLib:Do not assume BSP is #0.

 

REF:https://bugz= illa.tianocore.org/show_bug.cgi?id=3D4778
MPInitlib have wrong expectati= on that BSP index should always be 0 in
MpInitLibInitialize(), SwitchBsp= (),ApWakeupFunction().
That will cause the data mismatch, if the initial= BSP is not 0.
Cc: Ray Ni <ray.ni= @intel.com>
Signed-off-by: Ning Feng <ning.feng@intel.com>
---
 UefiCpuPkg/Libra= ry/MpInitLib/MpLib.c | 47 ++++++++++++++++++----------
 1 file chan= ged, 30 insertions(+), 17 deletions(-)

diff --git a/UefiCpuPkg/Libra= ry/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index d72445= 6502..ba497cbfd9 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
++= + b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -114,6 +114,10 @@ FutureBSPP= roc (
   SaveVolatileRegisters (&DataInHob->APInfo.Vola= tileRegisters);

   AsmExchangeRole (&DataInHob->API= nfo, &DataInHob->BSPInfo);

   RestoreVolatileRegist= ers (&DataInHob->APInfo.VolatileRegisters, FALSE);

+  //=

+  // Restore VolatileReg saved in CpuMpData->CpuData
+  //

+  CopyMem (&DataInHob->CpuData[DataInHob-&= gt;BspNumber].VolatileRegisters, &DataInHob->APInfo.VolatileRegister= s, sizeof (CPU_VOLATILE_REGISTERS));

 }

 

&n= bsp;/**

@@ -761,11 +765,11 @@ ApWakeupFunction (
  &nbs= p;    BistData     =3D (UINT32)ApStackDa= ta->Bist;

 

       //
-      // CpuMpData->CpuData[0].VolatileR= egisters is initialized based on BSP environment,

+   = ;   // CpuMpData->CpuData[BspNumber].VolatileRegisters is init= ialized based on BSP environment,

     &nbs= p; //   to initialize AP in InitConfig path.

-  =     // NOTE: IDTR.BASE stored in CpuMpData->CpuData[0].Vo= latileRegisters points to a different IDT shared by all APs.

+ =      // NOTE: IDTR.BASE stored in CpuMpData->CpuData= [BspNumber].VolatileRegisters points to a different IDT shared by all APs.<= br>
       //

-   &n= bsp;  RestoreVolatileRegisters (&CpuMpData->CpuData[0].Volatile= Registers, FALSE);

+      RestoreVolatileRe= gisters (&CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegist= ers, FALSE);

       InitializeApData (= CpuMpData, ProcessorNumber, BistData, ApTopOfStack);

  &nb= sp;    ApStartupSignalBuffer =3D CpuMpData->CpuData[Proce= ssorNumber].StartupApSignal;

     } else {
@@ -798,10 +802,10 @@ ApWakeupFunction (
     = ;    // 1. AP is re-enabled after it's disabled, in either P= EI or DXE phase.

         //= 2. AP is initialized in DXE phase.

     &n= bsp;   // In either case, use the volatile registers value derive= d from BSP.

-        // NOTE: IDT= R.BASE stored in CpuMpData->CpuData[0].VolatileRegisters points to a
=
+        // NOTE: IDTR.BASE stored i= n CpuMpData->CpuData[BspNumber].VolatileRegisters points to a

&nb= sp;        //   different IDT = shared by all APs.

         = //

-        RestoreVolatileRegist= ers (&CpuMpData->CpuData[0].VolatileRegisters, FALSE);

+ = ;       RestoreVolatileRegisters (&CpuMpD= ata->CpuData[CpuMpData->BspNumber].VolatileRegisters, FALSE);

=        } else {

   &nbs= p;     if (CpuMpData->ApLoopMode =3D=3D ApInHltLoop)= {

           //
@@ -927,7 +931,7 @@ DxeApEntryPoint (
     Asm= WriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64);

   }

&n= bsp;

-  RestoreVolatileRegisters (&CpuMpData->CpuData[0]= .VolatileRegisters, FALSE);

+  RestoreVolatileRegisters (&C= puMpData->CpuData[CpuMpData->BspNumber].VolatileRegisters, FALSE);
   InterlockedIncrement ((UINT32 *)&CpuMpData->Finish= edCount);

   PlaceAPInMwaitLoopOrRunLoop (

 &n= bsp;   CpuMpData->ApLoopMode,

@@ -2151,11 +2155,16 @@ M= pInitLibInitialize (
   CpuMpData->BackupBufferSize =3D ApR= esetVectorSizeBelow1Mb;

   CpuMpData->WakeupBuffer = ;    =3D (UINTN)-1;

   CpuMpData->CpuCou= nt         =3D 1;

-  Cp= uMpData->BspNumber        =3D 0;
<= br>-  CpuMpData->WaitEvent       = ; =3D NULL;

-  CpuMpData->SwitchBspFlag    = =3D FALSE;

-  CpuMpData->CpuData    &nbs= p;     =3D (CPU_AP_DATA *)(CpuMpData + 1);

-&nbs= p; CpuMpData->CpuInfoInHob     =3D (UINT64)(UINTN)(C= puMpData->CpuData + MaxLogicalProcessorNumber);

+  if (First= MpHandOff =3D=3D NULL) {

+    CpuMpData->BspNumber= =3D 0;

+  } else {

+    CpuMpData->Bs= pNumber =3D GetBspNumber (FirstMpHandOff);

+  }

+
+  CpuMpData->WaitEvent     =3D NULL;

+=   CpuMpData->SwitchBspFlag =3D FALSE;

+  CpuMpData->= CpuData       =3D (CPU_AP_DATA *)(CpuMpData += 1);

+  CpuMpData->CpuInfoInHob  =3D (UINT64)(UINTN)(Cp= uMpData->CpuData + MaxLogicalProcessorNumber);

   Initi= alizeSpinLock (&CpuMpData->MpLock);

   CpuMpData-&g= t;SevEsIsEnabled   =3D ConfidentialComputingGuestHas (CCAttrAmdSe= vEs);

   CpuMpData->SevSnpIsEnabled  =3D Confident= ialComputingGuestHas (CCAttrAmdSevSnp);

@@ -2186,11 +2195,11 @@ MpIn= itLibInitialize (
   // Don't pass BSP's TR to APs to avoid AP= init failure.

   //

   VolatileRegisters= .Tr =3D 0;

-  CopyMem (&CpuMpData->CpuData[0].VolatileRe= gisters, &VolatileRegisters, sizeof (VolatileRegisters));

+ = ; CopyMem (&CpuMpData->CpuData[CpuMpData->BspNumber].VolatileRegi= sters, &VolatileRegisters, sizeof (VolatileRegisters));

 &n= bsp; //

   // Set BSP basic information

  = ; //

-  InitializeApData (CpuMpData, 0, 0, CpuMpData->Buffer= + ApStackSize);

+  InitializeApData (CpuMpData, CpuMpData->= BspNumber, 0, CpuMpData->Buffer + ApStackSize * (CpuMpData->BspNumber= + 1));

   //

   // Save assembly code in= formation

   //

@@ -2245,9 +2254,8 @@ MpInitLibInit= ialize (
       AmdSevUpdateCpuMpData (Cpu= MpData);

     }

 

- &nbs= p;  CpuMpData->CpuCount  =3D MaxLogicalProcessorNumber;
-    CpuMpData->BspNumber =3D GetBspNumber (FirstMpHandO= ff);

-    CpuInfoInHob     &= nbsp;   =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;=

+    CpuMpData->CpuCount =3D MaxLogicalProcessorN= umber;

+    CpuInfoInHob     = ;   =3D (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
=
     for (MpHandOff =3D FirstMpHandOff;

&nbs= p;         MpHandOff !=3D NULL;
=
          MpHandOff =3D Ge= tNextMpHandOffHob (MpHandOff))

@@ -2615,7 +2623,12 @@ SwitchBSPWorke= r (
   SaveVolatileRegisters (&CpuMpData->BSPInfo.Volat= ileRegisters);

   AsmExchangeRole (&CpuMpData->BSPI= nfo, &CpuMpData->APInfo);

   RestoreVolatileRegiste= rs (&CpuMpData->BSPInfo.VolatileRegisters, FALSE);

-

+=   //

+  // Restore VolatileRegs saved in CpuMpData->Cpu= Data

+  // Don't pass BSP's TR to APs to avoid AP init failure.=

+  //

+  CopyMem (&CpuMpData->CpuData[CpuMp= Data->NewBspNumber].VolatileRegisters, &CpuMpData->BSPInfo.Volati= leRegisters, sizeof (CPU_VOLATILE_REGISTERS));

+  CpuMpData->= ;CpuData[CpuMpData->NewBspNumber].VolatileRegisters.Tr =3D 0;

&nb= sp;  //

   // Set the BSP bit of MSR_IA32_APIC_BASE o= n new BSP

   //

--
2.25.1

=

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