From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web12.51664.1622508974642532044 for ; Mon, 31 May 2021 17:56:16 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Tue, 01 Jun 2021 08:56:12 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: , , "'Laszlo Ersek'" , Cc: "'Chang, Abner \(HPS SW/FW Technologist\)'" , "'Michael D Kinney'" , "'Zhiguang Liu'" , "'Leif Lindholm'" References: <20210515181234.15186-1-daniel.schaefer@hpe.com> <009501d74b81$bf063b40$3d12b1c0$@byosoft.com.cn> ,<003d01d74e00$321459c0$963d0d40$@byosoft.com.cn> ,<006501d74e0b$8c555b90$a50012b0$@byosoft.com.cn> In-Reply-To: Subject: =?UTF-8?B?5Zue5aSNOiDlm57lpI06IFtlZGsyLWRldmVsXSBbUEFUQ0ggdjEgMS8xXSBBZGQgTWVtb3J5RmVuY2UgaW1wbGVtZW50YXRpb24gZm9yIFJpc2NWNjQ=?= Date: Tue, 1 Jun 2021 08:56:11 +0800 Message-ID: <00cf01d75680$ea67e900$bf37bb00$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQFJypucKS8cqqScHdSjLYIRs6xE8QGbDUQpAnI/8ZkBpd+X2wHlzPzZAeEaY6kDIBS6uKu0mZ5w Content-Type: multipart/alternative; boundary="----=_NextPart_000_00D0_01D756C3.F88D4BE0" Content-Language: zh-cn ------=_NextPart_000_00D0_01D756C3.F88D4BE0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Seemly, Edk2\ArmVirtPkg\Library\QemuFwCfgLib\QemuFwCfgLib.inf is not arch specific library. It can also be used in RISCV64.=20 =20 Ard and Laszlo: If ArmVirtPkg\Library\QemuFwCfgLib is arch generic, can it be moved from ArmVirtPkg into OvmfPkg? =20 Thanks Liming =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io =B4=FA=B1= =ED Daniel Schaefer =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA5=D4=C221=C8=D5 20:46 =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io; gaoliming@byosoft.com.cn =B3=AD=CB=CD: Chang, Abner (HPS SW/FW Technologist) ;= 'Michael D Kinney' ; 'Zhiguang Liu' ; 'Leif Lindholm' =D6=F7=CC=E2: Re: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFenc= e implementation for RiscV64 =20 It's not required to go into that tag. We need two more patches that we haven't submitted yet to boot on Qemu. =20 Would it be okay if we used a library from ArmVirtPkg for RISCV64? See: https://github.com/riscv/riscv-edk2/commit/8c7960ef860c65f2646912c3dccbb30= 8a 98e0cc3 Or does it have to be moved to some other place first? _____ From: devel@edk2.groups.io > on behalf of gaolimi= ng > Sent: Friday, May 21, 2021 14:35 To: devel@edk2.groups.io >; Schaefer, Daniel > Cc: Chang, Abner (HPS SW/FW Technologist) >; 'Michael D Kinney' >; 'Zhigua= ng Liu' >; 'Leif Lindholm' > Subject: =BB=D8=B8=B4: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add Memor= yFence implementation for RiscV64=20 =20 Daniel: Thanks for your information. Acked-by: Liming Gao > =20 And, do you request to merge this patch for edk2 stable tag 202105?=20 Thanks Liming =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io > =B4=FA=B1=ED Daniel = Schaefer =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA5=D4=C221=C8=D5 13:27 =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io ; gaoliming@byosoft.com.cn =20 =B3=AD=CB=CD: Chang, Abner (HPS SW/FW Technologist) >; 'Michael D Kinney' >; 'Zhigua= ng Liu' >; 'Leif Lindholm' > =D6=F7=CC=E2: Re: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFenc= e implementation for RiscV64 =20 Great! =20 It is verified I can boot Linux from a virtio ESP using this patch on QEMU virt machine. See: https://github.com/riscv/riscv-edk2-platforms/runs/2618819010?check_suite_= fo cus=3Dtrue =20 Thanks, Daniel _____ From: devel@edk2.groups.io > on behalf of gaolimi= ng > Sent: Friday, May 21, 2021 13:14 To: devel@edk2.groups.io >; Schaefer, Daniel > Cc: Chang, Abner (HPS SW/FW Technologist) >; 'Michael D Kinney' >; 'Zhigua= ng Liu' >; 'Leif Lindholm' > Subject: =BB=D8=B8=B4: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add Memor= yFence implementation for RiscV64=20 =20 Daniel: Now, it is clear to me. So, I suggest to merge this change when it is verified on generic RISC-V QEMU virt machine. Is it OK? Thanks Liming > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io > =B4=FA=B1=ED Daniel > Schaefer > =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA5=D4=C218=C8=D5 10:35 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io ; gaoliming@byosoft.com.cn =20 > =B3=AD=CB=CD: 'Abner Chang' >; 'Michael D Kinney' > >; 'Zhiguang Liu' >; 'Leif > Lindholm' > > =D6=F7=CC=E2: Re: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFe= nce > implementation for RiscV64 >=20 > On 5/18/21 9:04 AM, gaoliming wrote: > > Daniel: > > Seemly, this API is missing in BaseLib for RiscV64 arch. How do you detect > > this issue? >=20 > What do you mean it's missing? > Yes MemoryFence() for RiscV64 is missing currently, that's why I'm addin= g it > here. >=20 > Maybe you mean that it's not currently used? That's also true. > I'm enabling the generic QEMU virt machine (like OVMF or ArmVirtPkg) for > RISC-V. > At least QemuFwCfgLib and VirtioLib need it. > That's why I have the need to add this implementation now. >=20 > Does that clear it up? >=20 > > Thanks > > Liming > >> -----=D3=CA=BC=FE=D4=AD=BC=FE----- > >> =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io > =B4=FA=B1=ED Daniel > >> Schaefer > >> =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA5=D4=C216=C8=D5 2:13 > >> =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io =20 > >> =B3=AD=CB=CD: Abner Chang >; Michael D Kinney > >> >; Liming Gao >; > >> Zhiguang Liu = >; Leif Lindholm > > >> =D6=F7=CC=E2: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementat= ion for > >> RiscV64 > >> > >> Cc: Abner Chang > > >> Cc: Michael D Kinney > > >> Cc: Liming Gao > > >> Cc: Zhiguang Liu > > >> Cc: Leif Lindholm > > >> Signed-off-by: Daniel Schaefer > > >> --- > >> MdePkg/Library/BaseLib/BaseLib.inf | 1 + > >> MdePkg/Library/BaseLib/RiscV64/MemoryFence.S | 33 > >> ++++++++++++++++++++ > >> 2 files changed, 34 insertions(+) > >> > >> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf > >> b/MdePkg/Library/BaseLib/BaseLib.inf > >> index b76f3af380ea..b7ab5f632366 100644 > >> --- a/MdePkg/Library/BaseLib/BaseLib.inf > >> +++ b/MdePkg/Library/BaseLib/BaseLib.inf > >> @@ -399,6 +399,7 @@ > >> RiscV64/DisableInterrupts.c > >> > >> > >> RiscV64/EnableInterrupts.c > >> > >> > >> RiscV64/CpuPause.c > >> > >> > >> + RiscV64/MemoryFence.S | GCC > >> > >> > >> RiscV64/RiscVSetJumpLongJump.S | GCC > >> > >> > >> RiscV64/RiscVCpuBreakpoint.S | GCC > >> > >> > >> RiscV64/RiscVCpuPause.S | GCC > >> > >> > >> diff --git a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S > >> b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S > >> new file mode 100644 > >> index 000000000000..283df9356a9a > >> --- /dev/null > >> +++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S > >> @@ -0,0 +1,33 @@ > >> > > +##-----------------------------------------------------------------------= -- > > ----- > >> > >> > >> +# > >> > >> > >> +# MemoryFence() for RiscV64 > >> > >> > >> + > >> > >> > >> +# Copyright (c) 2021, Hewlett Packard Enterprise Development. All rights > >> reserved. > >> > >> > >> +# > >> > >> > >> +# SPDX-License-Identifier: BSD-2-Clause-Patent > >> > >> > >> +# > >> > >> > >> > > +##-----------------------------------------------------------------------= -- > > ----- > >> > >> > >> + > >> > >> > >> +.text > >> > >> > >> +.p2align 2 > >> > >> > >> + > >> > >> > >> +ASM_GLOBAL ASM_PFX(MemoryFence) > >> > >> > >> + > >> > >> > >> + > >> > >> > >> +#/** > >> > >> > >> +# Used to serialize load and store operations. > >> > >> > >> +# > >> > >> > >> +# All loads and stores that proceed calls to this function are > > guaranteed to > >> be > >> > >> > >> +# globally visible when this function returns. > >> > >> > >> +# > >> > >> > >> +#**/ > >> > >> > >> +#VOID > >> > >> > >> +#EFIAPI > >> > >> > >> +#MemoryFence ( > >> > >> > >> +# VOID > >> > >> > >> +# ); > >> > >> > >> +# > >> > >> > >> +ASM_PFX(MemoryFence): > >> > >> > >> + // Fence on all memory and I/O > >> > >> > >> + fence > >> > >> > >> + ret > >> > >> > >> -- > >> 2.30.1 > >> > >> > >> > >> > >> > > > > > > > > > > > > > > > > >=20 >=20 >=20 >=20 ------=_NextPart_000_00D0_01D756C3.F88D4BE0 Content-Type: text/html; charset="gb2312" Content-Transfer-Encoding: quoted-printable

Seemly, Edk2\ArmVirtPkg\Library\QemuFwCfgLib\QemuFwCfgLib.in= f is not arch specific library. It can also be used in RISCV64. =

 

Ar= d and Laszlo:

 If ArmVirtPkg\Li= brary\QemuFwCfgLib is arch generic, can it be moved from ArmVirtPkg into Ov= mfPkg?

 

Thanks

Liming<= /o:p>

=B7=A2=BC=FE=C8=CB:= devel@edk2.groups.io <devel@edk2.groups.io> =B4=FA=B1=ED Daniel Schaefer
=B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4= =EA5=D4=C221=C8=D5 20:46
=CA=D5=BC=FE=C8=CB: devel@edk2.groups.io; gaoliming@byosoft.com.cn=
=B3=AD=CB=CD: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; 'Micha= el D Kinney' <michael.d.kinney@intel.com>; 'Zhiguang Liu' <zhiguan= g.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
=D6=F7=CC=E2: Re: = = =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFen= ce implementation for RiscV64

 

It's not required to go into that tag.

We need two more patches that we haven't submi= tted yet to boot on Qemu.

 

Would it b= e okay if we used a library from ArmVirtPkg for RISCV64?<= /p>

Or does it have to be mo= ved to some other place first?

From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of gaol= iming <gaoliming@byosoft.com= .cn>
Sent: Friday, May 21, 2021 14:35
To: devel@edk2.groups.io <devel@edk2.groups.io>; Schaefer, Daniel = <daniel.schaefer@hpe.com&= gt;
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; 'Michael D Kinney' <= ;michael.d.kinney@intel.com>; 'Zhiguang Liu' <zhigua= ng.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
Subject: =BB=D8=B8=B4: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementation for Ris= cV64

 

Daniel:

 Thank= s for your information. Acked-by: Liming Gao <gaoliming@byosoft.com.cn>

 

  And, do you request to me= rge this patch for edk2 stable tag 202105? <= /o:p>

  

Thanks<= /o:p>

Liming

=B7=A2=BC=FE=C8=CB: devel@edk2.groups.i= o <devel@edk2.groups.io&= gt; =B4= = =FA=B1=ED Daniel Schaefer
=B7=A2=CB=CD=CA=B1=BC=E4:<= /span> 2021=C4=EA5=D4=C221=C8=D5 13:27
=CA=D5=BC=FE=C8=CB: devel@edk2.groups.io; gaoliming@byosoft.com.cn
=B3=AD=CB=CD: Chang, Abner (HPS SW/FW Technologist) <= abner.chang@hpe.com>; 'Michae= l D Kinney' <michael.d.kin= ney@intel.com>; 'Zhiguang Liu' <zhiguang.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
=D6=F7=CC=E2<= span lang=3DEN-US>: Re: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementati= on for RiscV64

=

 

=

Great!

 <= /o:p>

It is verified I can boo= t Linux from a virtio ESP using this patch on QEMU virt machine.

See: <= a href=3D"https://github.com/riscv/riscv-edk2-platforms/runs/2618819010?che= ck_suite_focus=3Dtrue">https://github.com/riscv/riscv-edk2-platforms/runs/2= 618819010?check_suite_focus=3Dtrue=

 =

Thanks,

Daniel

From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of gaoli= ming <gaoliming@byosoft.com.= cn>
Sent: Friday, May 21, 2021 13:14
To: devel@edk2.groups.io <devel@edk2.groups.io>; Schaefer, Daniel = <daniel.schaefer@hpe.com&= gt;
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; 'Michael D Kinney' <= ;michael.d.kinney@intel.com>; 'Zhiguang Liu' <zhigua= ng.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
Subject: =BB=D8=B8=B4: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementation for Ris= cV64

 

<= p class=3Dxmsonormal style=3D'margin-bottom:12.0pt'>Daniel:
  Now, it is clear to me. So, I sugg= est to merge this change when it is
verified on generic RISC-V QEMU virt= machine. Is it OK?

Thanks
Liming
> -----=D3=CA=BC=FE=D4=AD=BC=FE-----
= > =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io <devel@edk2.groups.io> =B4=FA=B1=ED Daniel
> Schaefer
> =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA5=D4=C218=C8=D5 10:35
> =CA=D5=BC=FE= =C8=CB: devel@e= dk2.groups.io; gaoliming@by= osoft.com.cn
> =B3=AD=CB=CD: 'Abner Cha= ng' <abner.chang@hpe.com>;= 'Michael D Kinney'
> <michael.d.kinney@intel.com>; 'Zhiguang Liu' <zhiguang.liu@intel.com>;
'Leif
> L= indholm' <leif@nuviainc.com>=
> =D6=F7=CC=E2: Re: =BB=D8=B8=B4: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
> imple= mentation for RiscV64
>
> On 5/18/21 9:04 AM, gaoliming wrote:=
> > Daniel:
> >  Seemly, this API is missing in Bas= eLib for RiscV64 arch. How do you
detect
> > this issue?
>= ;
> What do you mean it's missing?
> Yes MemoryFence() for Ris= cV64 is missing currently, that's why I'm adding
it
> here.
>= ;
> Maybe you mean that it's not currently used? That's also true.> I'm enabling the generic QEMU virt machine (like OVMF or ArmVirtPkg)= for
> RISC-V.
> At least QemuFwCfgLib and VirtioLib need it.> That's why I have the need to add this implementation now.
> <= br>> Does that clear it up?
>
> > Thanks
> > Li= ming
> >> -----=D3=CA=BC=FE=D4=AD=BC=FE-----
> >> =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io <devel@edk2.groups.io> =B4=FA=B1= = =ED Daniel
> >> Schaefer
> >> <= /span>=B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA5=D4=C216=C8=D5 2:13
> >> =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io
> >= > =B3=AD=CB=CD: Abner Chang <abner.chang@hpe.com>; Michael D Kinney
&= gt; >> <michael.d.ki= nney@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>;
> >> Zhiguang Liu <= ;zhiguang.liu@intel.com>; = Leif Lindholm
<leif@nuviainc.com= >
> >> =D6=F7=CC=E2: [edk2-dev= el] [PATCH v1 1/1] Add MemoryFence implementation for
> >> Risc= V64
> >>
> >> Cc: Abner Chang <abner.chang@hpe.com>
> >> Cc: Mich= ael D Kinney <michael.d.ki= nney@intel.com>
> >> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> >&g= t; Cc: Zhiguang Liu <zhiguang.= liu@intel.com>
> >> Cc: Leif Lindholm <leif@nuviainc.com>
> >> Signed-of= f-by: Daniel Schaefer <daniel= .schaefer@hpe.com>
> >> ---
> >>  MdePk= g/Library/BaseLib/BaseLib.inf       &nbs= p;   |  1 +
> >>  MdePkg/Library/BaseLib/Ri= scV64/MemoryFence.S | 33
> >> ++++++++++++++++++++
> >= >  2 files changed, 34 insertions(+)
> >>
> >&= gt; diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
> >> b/MdeP= kg/Library/BaseLib/BaseLib.inf
> >> index b76f3af380ea..b7ab5f6= 32366 100644
> >> --- a/MdePkg/Library/BaseLib/BaseLib.inf
&= gt; >> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
> >> @@ -= 399,6 +399,7 @@
> >>    RiscV64/DisableInterrupt= s.c
> >>
> >>
> >>    Ri= scV64/EnableInterrupts.c
> >>
> >>
> >>=     RiscV64/CpuPause.c
> >>
> >>
= > >> +  RiscV64/MemoryFence.S     &n= bsp;       | GCC
> >>
> >= ;>
> >>    RiscV64/RiscVSetJumpLongJump.S&nbs= p;   | GCC
> >>
> >>
> >>&nbs= p;   RiscV64/RiscVCpuBreakpoint.S      |= GCC
> >>
> >>
> >>    R= iscV64/RiscVCpuPause.S         = ;  | GCC
> >>
> >>
> >> diff --git= a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
> >> b/MdePkg/L= ibrary/BaseLib/RiscV64/MemoryFence.S
> >> new file mode 100644<= br>> >> index 000000000000..283df9356a9a
> >> --- /dev= /null
> >> +++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S> >> @@ -0,0 +1,33 @@
> >>
> >
+##------= -------------------------------------------------------------------
>= > -----
> >>
> >>
> >> +#
> &= gt;>
> >>
> >> +# MemoryFence() for RiscV64
&= gt; >>
> >>
> >> +
> >>
> &= gt;>
> >> +# Copyright (c) 2021, Hewlett Packard Enterprise = Development. All
rights
> >> reserved.
> >>
&= gt; >>
> >> +#
> >>
> >>
> = >> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> >>> >>
> >> +#
> >>
> >>
&g= t; >>
> >
+##--------------------------------------------= -----------------------------
> > -----
> >>
> &= gt;>
> >> +
> >>
> >>
> >&g= t; +.text
> >>
> >>
> >> +.p2align 2> >>
> >>
> >> +
> >>
>= >>
> >> +ASM_GLOBAL ASM_PFX(MemoryFence)
> >>= ;
> >>
> >> +
> >>
> >>
= > >> +
> >>
> >>
> >> +#/**> >>
> >>
> >> +#  Used to serialize= load and store operations.
> >>
> >>
> >&= gt; +#
> >>
> >>
> >> +#  All load= s and stores that proceed calls to this function are
> > guarantee= d to
> >> be
> >>
> >>
> >>= +#  globally visible when this function returns.
> >>
= > >>
> >> +#
> >>
> >>
>= >> +#**/
> >>
> >>
> >> +#VOID> >>
> >>
> >> +#EFIAPI
> >>=
> >>
> >> +#MemoryFence (
> >>
>= >>
> >> +#  VOID
> >>
> >><= br>> >> +#  );
> >>
> >>
> >= > +#
> >>
> >>
> >> +ASM_PFX(MemoryF= ence):
> >>
> >>
> >> +  &nbs= p; // Fence on all memory and I/O
> >>
> >>
>= >> +    fence
> >>
> >>
&g= t; >> +    ret
> >>
> >>
&g= t; >> --
> >> 2.30.1
> >>
> >>> >>
> >>
> >>
> >
> ><= br>> >
> >
> >
> >
> >
> &g= t;
>
>
>
>






=

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