From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from walk.intel-email.com (walk.intel-email.com [101.227.64.242]) by mx.groups.io with SMTP id smtpd.web10.759.1668130630598556136 for ; Thu, 10 Nov 2022 17:37:11 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@byosoft.com.cn header.s=cloud-union header.b=O25cbmw5; spf=pass (domain: byosoft.com.cn, ip: 101.227.64.242, mailfrom: gaoliming@byosoft.com.cn) Received: from walk.intel-email.com (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id 9E97BCD1F664 for ; Fri, 11 Nov 2022 09:37:07 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=byosoft.com.cn; s=cloud-union; t=1668130627; bh=p87RDpI/L4Z8Cbebwwi7m1Vu9t8wvgi6n66gBnrPLqg=; h=From:To:Cc:References:In-Reply-To:Subject:Date; b=O25cbmw5VrEIzQjfvN8EXi6dY0rfInlR7oW8eMSyz18TABTQmUss+GPgchIxBe5fs IdEwCy2w5WJJagv1OpC/s/A+2CHgiJYkhPhrGwvu2khQF8YI/H19DzXAQzgjLC7H4C Qle2rnAg6J8Gi21VU21k8ut7hZvPTBIoc7Qd9YaY= Received: from localhost (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id 9A073CD1F673 for ; Fri, 11 Nov 2022 09:37:07 +0800 (CST) Received: from walk.intel-email.com (localhost [127.0.0.1]) by walk.intel-email.com (Postfix) with ESMTP id 6D71DCD1F69C for ; Fri, 11 Nov 2022 09:37:07 +0800 (CST) Authentication-Results: walk.intel-email.com; none Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by walk.intel-email.com (Postfix) with SMTP id 06F56CD1F6D0 for ; Fri, 11 Nov 2022 09:37:04 +0800 (CST) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Fri, 11 Nov 2022 09:37:02 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: , , "'Kinney, Michael D'" Cc: "'Desimone, Nathaniel L'" , "'Zeng, Star'" , "'S, Ashraf Ali'" , "'Duggapu, Chinni B'" , "'Kuo, Ted'" References: <982993884529155a9bba1fa0a09a33301a0ded35.1667982515.git.ted.kuo@intel.com> <00e801d8f568$173ce3e0$45b6aba0$@byosoft.com.cn> In-Reply-To: Subject: =?UTF-8?B?5Zue5aSNOiBbZWRrMi1kZXZlbF1bUEFUQ0ggdjFdIEludGVsRnNwMlBrZzogSW1wcm92ZW1lbnQgb2Ygc3VwcG9ydGluZyBudWxsIFVQRCBwb2ludGVyIGluIEZTUC1U?= Date: Fri, 11 Nov 2022 09:37:04 +0800 Message-ID: <010001d8f56e$1a910930$4fb31b90$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQKTs1X8BrygnG5z8eBLmNWwoq5A6gFbryafAOwiYdoBY4A9nKymGcLw Sender: "gaoliming" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Chasel: Seemly, this is a bug fix for the previous change. In soft feature freeze= , the bug is still allowed. Since this patch has passed review, I can help = merge it.=20 Thanks Liming > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io = =E4=BB=A3=E8=A1=A8 Chiu, Chasel > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2022=E5=B9=B411=E6=9C=8811=E6=97=A5= 9:08 > =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io; Gao, Liming ; > Kinney, Michael D > =E6=8A=84=E9=80=81: Desimone, Nathaniel L ; Zeng, Star > ; S, Ashraf Ali ; Duggapu, > Chinni B ; Kuo, Ted > =E4=B8=BB=E9=A2=98: Re: [edk2-devel][PATCH v1] IntelFsp2Pkg: Improvement = of supporting > null UPD pointer in FSP-T >=20 >=20 > Sorry for missing this message. > Since this patch is important for unblocking platform FSP implementation, > @Gao, Liming, @Kinney, Michael D, could you please help to merge it to ca= tch > this stable tag? >=20 > Thanks, > Chasel >=20 >=20 >=20 > > -----Original Message----- > > From: devel@edk2.groups.io On Behalf Of > > gaoliming via groups.io > > Sent: Thursday, November 10, 2022 4:54 PM > > To: Chiu, Chasel ; Kinney, Michael D > > > > Cc: Desimone, Nathaniel L ; Zeng, Star > > ; S, Ashraf Ali ; Duggapu, > > Chinni B ; devel@edk2.groups.io; Kuo, Ted > > > > Subject: =E5=9B=9E=E5=A4=8D: [edk2-devel][PATCH v1] IntelFsp2Pkg: Impro= vement of > > supporting null UPD pointer in FSP-T > > > > Chasel: > > Please see the announce mail > > https://edk2.groups.io/g/devel/message/96175 > > > > Now, we are in soft feature freeze. If the patch wants to catch this = stable > > tag, please highlight it and get approval from Stewards. > > > > Thanks > > Liming > > > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > > > =E5=8F=91=E4=BB=B6=E4=BA=BA: Chiu, Chasel > > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2022=E5=B9=B411=E6=9C=8811=E6= =97=A5 8:47 > > > =E6=94=B6=E4=BB=B6=E4=BA=BA: Gao, Liming ; = Kinney, Michael D > > > > > > =E6=8A=84=E9=80=81: Desimone, Nathaniel L ; Zeng, > > Star > > > ; S, Ashraf Ali ; > > > Duggapu, Chinni B ; devel@edk2.groups.io; > > > Kuo, Ted > > > =E4=B8=BB=E9=A2=98: RE: [edk2-devel][PATCH v1] IntelFsp2Pkg: Improvem= ent of > > supporting > > > null UPD pointer in FSP-T > > > > > > > > > Hi Liming, Michael, > > > > > > May I know why we cannot merge this PR > > > https://github.com/tianocore/edk2/pull/3624 ? > > > Was it due to Hard Feature Freeze? But I thought we still have time r= ight? > > > > > > Thanks, > > > Chasel > > > > > > > > > > -----Original Message----- > > > > From: devel@edk2.groups.io On Behalf Of Kuo, > > > > Ted > > > > Sent: Wednesday, November 9, 2022 3:31 AM > > > > To: devel@edk2.groups.io > > > > Cc: Chiu, Chasel ; Desimone, Nathaniel L > > > > ; Zeng, Star ; > > > > S, Ashraf Ali ; Duggapu, Chinni B > > > > > > > > Subject: [edk2-devel][PATCH v1] IntelFsp2Pkg: Improvement of > > > > supporting null UPD pointer in FSP-T > > > > > > > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4114 > > > > > > > > 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD > > pointer > > > > respectively in TempRamInitApi in IA32 FspSecCoreT. > > > > 2.Correct inappropriate description in the return value of > > > > AsmGetFspInfoHeader. > > > > 3.Replace hardcoded offset value 0x1C with > > FSP_HEADER_IMGBASE_OFFSET > > > > in > > > > FspHeler.nasm. > > > > > > > > Cc: Chasel Chiu > > > > Cc: Nate DeSimone > > > > Cc: Star Zeng > > > > Cc: Ashraf Ali S > > > > Cc: Chinni B Duggapu > > > > Signed-off-by: Ted Kuo > > > > --- > > > > .../FspSecCore/Ia32/FspApiEntryT.nasm | 17 +++-- > > > > IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm | 4 +- > > > > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 74 > > > ++++++++++--------- > > > > IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- > > > > IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 4 +- > > > > 5 files changed, 55 insertions(+), 46 deletions(-) > > > > > > > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > > > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > > > index 73821ad22a..2cff8b3643 100644 > > > > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > > > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm > > > > @@ -594,37 +594,38 @@ ASM_PFX(TempRamInitApi): > > > > SAVE_EAX SAVE_EDX + CALL_EBP > > > ASM_PFX(LoadUpdPointerToECX) ; > > > > ECX for UPD param+ > SAVE_ECX ; > > > save UPD param to slot > > > > 3 in xmm6+ ; ; Sec Platform Init ;- CALL_EBP > > > > ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param CALL_MMX > > > > ASM_PFX(SecPlatformInit) cmp eax, 0 jnz > > > TempRamInitExit ; > > > > Load microcode LOAD_ESP- CALL_EBP > > > ASM_PFX(LoadUpdPointerToECX) ; > > > > ECX for UPD param+ LOAD_ECX CALL_MMX > > > > ASM_PFX(LoadMicrocodeDefault)- SXMMN xmm6, 3, > > > eax ;Save > > > > microcode return status in ECX-SLOT 3 in xmm6.+ > > > > SAVE_UCODE_STATUS ; Save microcode return > status in > > > slot 1 in > > > > xmm5. ;@note If return value eax is not 0, microcode did not load= , > but > > > > continue and attempt to boot. ; Call Sec CAR Init LOAD_ESP- > > > CALL_EBP > > > > ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param+ LOAD_ECX > > > > CALL_MMX ASM_PFX(SecCarInit) cmp eax, 0 jnz > > > TempRamInitExit > > > > LOAD_ESP- CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for > UPD > > > > param- mov edi, ecx ; Save UPD > param > > > to EDI for later code > > > > use+ LOAD_ECX+ mov edi, ecx ; Save > UPD > > > param to EDI for > > > > later code use CALL_MMX ASM_PFX(EstablishStackFsp) cmp > > > eax, 0 > > > > jnz TempRamInitExit - LXMMN xmm6, eax, 3 ;Restore > > > microcode > > > > status if no CAR init error from ECX-SLOT 3 in xmm6.- SXMMN > xmm6, > > > 3, > > > > edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6.+ > > > > LOAD_UCODE_STATUS ; Restore microcode status if > no > > > CAR init > > > > error from slot 1 in xmm5. TempRamInitExit: mov bl, > > > al ; > > > > save al data in bldiff --git > > a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm > > > > b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm > > > > index e3e1945473..3c63f6eea5 100644 > > > > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm > > > > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm > > > > @@ -7,6 +7,8 @@ > > > > SECTION .text +FSP_HEADER_IMGBASE_OFFSET EQU > 1Ch+ > > > global > > > > ASM_PFX(FspInfoHeaderRelativeOff) > > ASM_PFX(FspInfoHeaderRelativeOff): > > > > DD 0x12345678 ; This value must be patched by > the > > > build > > > > script@@ -14,7 +16,7 @@ ASM_PFX(FspInfoHeaderRelativeOff): > > > > global ASM_PFX(AsmGetFspBaseAddress) > > > > ASM_PFX(AsmGetFspBaseAddress): call > > > > ASM_PFX(AsmGetFspInfoHeader)- add eax, 0x1C+ add eax, > > > > FSP_HEADER_IMGBASE_OFFSET mov eax, dword [eax] ret > diff > > > --git > > > > a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > > > > b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > > > > index 4c321cbece..a222f2e376 100644 > > > > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > > > > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > > > > @@ -1,6 +1,6 @@ > > > > > > ;----------------------------------------------------------------------= ----- > > --- ;-; > > > Copyright (c) > > > > 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyrigh= t > > > > (c) > > > > 2015 - 2022, Intel Corporation. All rights reserved.
; > > > > SPDX-License- > > > > Identifier: BSD-2-Clause-Patent ; ; Abstract:@@ -16,21 +16,21 @@ ; > > > > ; Define SSE macros using SSE 4.1 instructions ; args 1:XMM, 2:IDX, > > > > 3:REG-%macro SXMMN 3+%macro SXMMN 3 > > > pinsrd %1, %3, > > > > (%2 & 3) %endmacro ; ;args 1:XMM, 2:REG, > > > 3:IDX ;-%macro > > > > LXMMN 3+%macro LXMMN 3 > > > pextrd %2, %1, (%3 & 3) > > > > %endmacro %else ; ; Define SSE macros using SSE 2 instructions ; ar= gs > > > > 1:XMM, 2:IDX, 3:REG-%macro SXMMN 3+%macro SXMMN > 3 > > > > pinsrw %1, %3, (%2 & 3) * 2 ror %3, 16 > > > pinsrw %1, %3, > > > > (%2 & 3) * 2 + 1@@ -38,19 +38,19 @@ > > > > %endmacro ;-;args 1:XMM, 2:REG, 3:IDX+;args > > > 1:XMM, 2:REG, > > > > 3:IDX ; %macro LXMMN 3- pshufd %1, %1, > > > ((0E4E4E4h >> (%3 * 2)) > > > > & 0FFh)+ pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & > > > 0FFh) > > > > movd %2, %1- pshufd %1, %1, ((0E4E4E4h >> > (%3 * > > > 2 + (%3 & 1) * > > > > 4)) & 0FFh)+ pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + > (%3 > > > & 1) * 4)) > > > > & 0FFh) %endmacro %endif ;-; XMM7 to save/restore > > > EBP, EBX, ESI, > > > > EDI+; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2= , > > > > EDI+EDI > > - slot > > > > 3 ;-%macro SAVE_REGS 0+%macro SAVE_REGS 0 SXMMN > > > xmm7, 0, > > > > ebp SXMMN xmm7, 1, ebx SXMMN xmm7, 2, > esi@@ > > > -67,63 +67,67 > > > > @@ > > > > %endmacro ;-; XMM6 to save/restore EAX, EDX, > ECX, > > > ESP+; XMM6 > > > > to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slo= t > > > > 3 > > ;-%macro > > > > LOAD_EAX 0+%macro LOAD_ESP 0+ movd esp, > > > xmm6+ > > > > %endmacro++%macro SAVE_ESP 0+ SXMMN xmm6, 0, > esp+ > > > > %endmacro++%macro LOAD_EAX 0 LXMMN xmm6, eax, > 1 > > > > %endmacro -%macro SAVE_EAX 0+%macro SAVE_EAX 0 > > > SXMMN > > > > xmm6, 1, eax %endmacro -%macro LOAD_EDX > > > 0+%macro > > > > LOAD_EDX 0 LXMMN xmm6, edx, > > > 2 %endmacro -%macro > > > > SAVE_EDX 0+%macro SAVE_EDX 0 SXMMN xmm6, > 2, > > > edx > > > > %endmacro -%macro SAVE_ECX 0- SXMMN xmm6, 3, > ecx- > > > > %endmacro--%macro LOAD_ECX 0+%macro LOAD_ECX 0 > > > LXMMN > > > > xmm6, ecx, 3 %endmacro -%macro SAVE_ESP 0- > > > SXMMN > > > > xmm6, 0, esp+%macro SAVE_ECX 0+ SXMMN xmm6, 3, ecx > > > > %endmacro -%macro LOAD_ESP 0- movd esp, xmm6- > > > > %endmacro ;-; XMM5 for calling stack+; XMM5 slot 0 for calling stac= k > > > > ; > > arg > > > > 1:Entry %macro CALL_XMM 1 mov > > > esi, %%ReturnAddress- > > > > pslldq xmm5, 4-%ifdef USE_SSE41_FLAG- pinsrd > xmm5, > > > esi, 0- > > > > %else- pinsrw xmm5, esi, 0- ror > esi, > > > 16- pinsrw > > > > xmm5, esi, 1-%endif+ SXMMN xmm5, 0, esi > > > mov esi, %1 > > > > jmp esi %%ReturnAddress: %endmacro %macro > > > RET_XMM 0- > > > > movd esi, xmm5- psrldq xmm5, 4+ > > > LXMMN xmm5, esi, 0 > > > > jmp esi %endmacro +;+; XMM5 slot 1 for uCode > > > status+;+%macro > > > > LOAD_UCODE_STATUS 0+ LXMMN xmm5, eax, 1+ > > > > %endmacro++%macro SAVE_UCODE_STATUS 0+ SXMMN > > > xmm5, 1, > > > > eax+ %endmacro+ %macro ENABLE_SSE > > > 0 ; ; Initialize > > > > floating point unitsdiff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h > > > > b/IntelFsp2Pkg/FspSecCore/SecFsp.h > > > > index d7a5976c12..693af29f20 100644 > > > > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.h > > > > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h > > > > @@ -79,7 +79,7 @@ AsmGetFspBaseAddress ( > > > > /** This interface gets FspInfoHeader pointer - @return FSP > > > binary base > > > > address.+ @return FSP info header. **/ UINTNdiff --git > > > > a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > > > > b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > > > > index 122fa1d174..71624a3aad 100644 > > > > --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > > > > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm > > > > @@ -7,10 +7,12 @@ > > > > DEFAULT REL SECTION .text > > > +FSP_HEADER_IMGBASE_OFFSET EQU > > > > 1Ch+ global ASM_PFX(AsmGetFspBaseAddress) > > > > ASM_PFX(AsmGetFspBaseAddress): call > > > > ASM_PFX(AsmGetFspInfoHeader)- add rax, 0x1C+ add rax, > > > > FSP_HEADER_IMGBASE_OFFSET mov eax, [rax] ret -- > > > > 2.35.3.windows.1 > > > > > > > > > > > > > > > > -=3D-=3D-=3D-=3D-=3D-=3D > > > > Groups.io Links: You receive all messages sent to this group. > > > > View/Reply Online (#96131): > > > > https://edk2.groups.io/g/devel/message/96131 > > > > Mute This Topic: https://groups.io/mt/94910671/1777047 > > > > Group Owner: devel+owner@edk2.groups.io > > > > Unsubscribe: https://edk2.groups.io/g/devel/unsub > > > [chasel.chiu@intel.com] > > > > -=3D-=3D-=3D-=3D-=3D-=3D > > > > > > > > > > > > > > > > > > >=20 >=20 >=20 >=20 >=20