From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from a7-11.smtp-out.eu-west-1.amazonses.com (a7-11.smtp-out.eu-west-1.amazonses.com [54.240.7.11]) by mx.groups.io with SMTP id smtpd.web11.3019.1676625411036002048 for ; Fri, 17 Feb 2023 01:16:51 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ipxe.org header.s=cphpx6z2rfcgehlykjjh3gknqe3hsoe2 header.b=mayN6XPr; spf=pass (domain: eu-west-1.amazonses.com, ip: 54.240.7.11, mailfrom: 010201865ea973b9-f0358277-9198-4adc-a8c9-9c106220b25a-000000@eu-west-1.amazonses.com) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=cphpx6z2rfcgehlykjjh3gknqe3hsoe2; d=ipxe.org; t=1676625409; h=Message-ID:Date:MIME-Version:To:Cc:References:From:Subject:In-Reply-To:Content-Type:Content-Transfer-Encoding; bh=SrXQAxRPqUl51l4Thx7W+GfizBoBvnGxSWP6S+qjazI=; b=mayN6XPrinYZTqUwLgaJ6REEDo2nnzdvTRasUKKj7ImHUejvKFeQnQY8fzRwMv+C pGbjbSM7o5+/T5AoFOIKun86zPl+lIAkKmn6ueBlkHWeNIUjIIukgesYeheNgtUIBKG sW+e0//VEmRXmOWRr+EFLjsUt4S5C7U5Y2+VzIMZxBC4KpW5sN5JXOR9cXcb/RhU9lV 4+d4uUNU4YiolzL28ripd+M6MVTRpFH2/SvJ4MaeJ/sXnCAU5A3xhHwNr/LVABFBWE2 ohPgVhXzBamyZYjKM5iVKMq2GPP4tjVsalAoFQJlMgSTJSM9aoKD3Qxr51+iG61rh74 01/Yy+YJfA== DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/simple; s=ihchhvubuqgjsxyuhssfvqohv7z3u4hn; d=amazonses.com; t=1676625409; h=Message-ID:Date:MIME-Version:To:Cc:References:From:Subject:In-Reply-To:Content-Type:Content-Transfer-Encoding:Feedback-ID; bh=SrXQAxRPqUl51l4Thx7W+GfizBoBvnGxSWP6S+qjazI=; b=qTqOSFfSkHDUl6KtPcwKWLtKpg7d41ca/8C0TAEN51c6grCjp+2k9LmfWS4UQ2qu Xt7KcCFBWo1QuvPPYjVF5CvvT2ZF/YPS1u5xWTCQLqvwybH2fBjeCEAyaqD3hJLXfh3 tsBg/uxADDjy/YUb/vIFVrLcbT6Rr0eFWDSgbiRE= Message-ID: <010201865ea973b9-f0358277-9198-4adc-a8c9-9c106220b25a-000000@eu-west-1.amazonses.com> Date: Fri, 17 Feb 2023 09:16:48 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 To: devel@edk2.groups.io, sunilvl@ventanamicro.com, dann frazier Cc: Abner Chang , Daniel Schaefer , Michael D Kinney , Liming Gao , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sami Mujawar , Leif Lindholm , Eric Dong , Ray Ni , Rahul Kumar , Zhiguang Liu , Anup Patel , Heinrich Schuchardt , Andrei Warkentin References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> From: "Michael Brown" Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 00/19] Add support for RISC-V virt machine In-Reply-To: X-Spam-Status: No, score=-2.9 required=5.0 tests=ALL_TRUSTED,BAYES_00, URIBL_DBL_BLOCKED_OPENDNS,URIBL_ZEN_BLOCKED_OPENDNS autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on blyat.fensystems.co.uk Feedback-ID: 1.eu-west-1.fspj4M/5bzJ9NLRzJP0PaxRwxrpZqiDQJ1IF94CF2TA=:AmazonSES X-SES-Outgoing: 2023.02.17-54.240.7.11 Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/02/2023 04:27, Sunil V L wrote: > On Thu, Feb 16, 2023 at 03:45:49PM -0700, dann frazier wrote: >> Thanks for your work getting this merged! In the above wiki, it >> notes that GCC 12+ is not supported. Is that still accurate? If so, >> can you clarify what is blocking that? > > Please see https://bugzilla.tianocore.org/show_bug.cgi?id=4061. > > My attempt to fix this issue > (https://edk2.groups.io/g/devel/message/93831) was not accepted due to > the concerns that it can cause weird issues in CI. > > So, we are left with either support gcc <12 or gcc >=12. We can mandate > gcc 12 itself for RISC-V, but that change need to be done hand in hand > with CI tests moving to use gcc 12. Otherwise, it will break CI. Is there an alternative (and presumably less ideal) way to force an instruction cache invalidation? For example, does a global TSO "fence" instruction as used in RiscVInvalidateDataCacheAsm() also invalidate the instruction cache? If so, then a viable solution would be: --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S @@ -15,3 +15,7 @@ ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) ASM_PFX(RiscVInvalidateInstCacheAsm): - fence.i +#ifdef __riscv_zifencei + fence.i +#else + fence +#endif ret This would also permit EDK2 to be used on implementations that genuinely do not provide the fence.i instruction. Michael