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From: "Michael Brown" <mcb30@ipxe.org>
To: devel@edk2.groups.io, jianfeng.zhou@intel.com
Cc: Ray Ni <ray.ni@intel.com>, Laszlo Ersek <lersek@redhat.com>,
	 Rahul Kumar <rahul1.kumar@intel.com>,
	 Gerd Hoffmann <kraxel@redhat.com>,
	 Pedro Falcato <pedro.falcato@gmail.com>,
	 Zhang Di <di.zhang@intel.com>, Tan Dun <dun.tan@intel.com>
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib: qualify page table accesses as volatile
Date: Fri, 1 Mar 2024 11:50:48 +0000	[thread overview]
Message-ID: <0102018df9da479a-6e0a86c0-651c-46f4-bba9-66a6c921001a-000000@eu-west-1.amazonses.com> (raw)
In-Reply-To: <20240301025447.41170-1-jianfeng.zhou@intel.com>

Reviewed-by: Michael Brown <mcb30@ipxe.org>

Thanks,

Michael

On 01/03/2024 02:54, Zhou Jianfeng wrote:
> Add volatile qualifier to page table related variable to prevent
> compiler from optimizing away the variables which may lead to
> unexpected result.
> 
> Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Pedro Falcato <pedro.falcato@gmail.com>
> Cc: Zhang Di <di.zhang@intel.com>
> Cc: Tan Dun <dun.tan@intel.com>
> Cc: Michael Brown <mcb30@ipxe.org>
> ---
>   .../Library/CpuPageTableLib/CpuPageTableMap.c | 36 +++++++++----------
>   1 file changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> index c4e46a6d74..0a380a04cb 100644
> --- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> +++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
> @@ -20,17 +20,17 @@
>   **/
>   VOID
>   PageTableLibSetPte4K (
> -  IN OUT IA32_PTE_4K         *Pte4K,
> -  IN UINT64                  Offset,
> -  IN IA32_MAP_ATTRIBUTE      *Attribute,
> -  IN IA32_MAP_ATTRIBUTE      *Mask
> +  IN OUT volatile IA32_PTE_4K  *Pte4K,
> +  IN UINT64                    Offset,
> +  IN IA32_MAP_ATTRIBUTE        *Attribute,
> +  IN IA32_MAP_ATTRIBUTE        *Mask
>     )
>   {
>     IA32_PTE_4K  LocalPte4K;
> 
>     LocalPte4K.Uint64 = Pte4K->Uint64;
>     if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddressHigh) {
> -    LocalPte4K.Uint64 = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) | (Pte4K->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40);
> +    LocalPte4K.Uint64 = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) | (LocalPte4K.Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40);
>     }
> 
>     if (Mask->Bits.Present) {
> @@ -94,17 +94,17 @@ PageTableLibSetPte4K (
>   **/
>   VOID
>   PageTableLibSetPleB (
> -  IN OUT IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE  *PleB,
> -  IN UINT64                                 Offset,
> -  IN IA32_MAP_ATTRIBUTE                     *Attribute,
> -  IN IA32_MAP_ATTRIBUTE                     *Mask
> +  IN OUT volatile IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE  *PleB,
> +  IN UINT64                                          Offset,
> +  IN IA32_MAP_ATTRIBUTE                              *Attribute,
> +  IN IA32_MAP_ATTRIBUTE                              *Mask
>     )
>   {
>     IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE  LocalPleB;
> 
>     LocalPleB.Uint64 = PleB->Uint64;
>     if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddressHigh) {
> -    LocalPleB.Uint64 = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) | (PleB->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39);
> +    LocalPleB.Uint64 = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) | (LocalPleB.Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39);
>     }
> 
>     LocalPleB.Bits.MustBeOne = 1;
> @@ -171,11 +171,11 @@ PageTableLibSetPleB (
>   **/
>   VOID
>   PageTableLibSetPle (
> -  IN UINTN                   Level,
> -  IN OUT IA32_PAGING_ENTRY   *Ple,
> -  IN UINT64                  Offset,
> -  IN IA32_MAP_ATTRIBUTE      *Attribute,
> -  IN IA32_MAP_ATTRIBUTE      *Mask
> +  IN UINTN                            Level,
> +  IN OUT volatile IA32_PAGING_ENTRY   *Ple,
> +  IN UINT64                           Offset,
> +  IN IA32_MAP_ATTRIBUTE               *Attribute,
> +  IN IA32_MAP_ATTRIBUTE               *Mask
>     )
>   {
>     if (Level == 1) {
> @@ -195,9 +195,9 @@ PageTableLibSetPle (
>   **/
>   VOID
>   PageTableLibSetPnle (
> -  IN OUT IA32_PAGE_NON_LEAF_ENTRY  *Pnle,
> -  IN IA32_MAP_ATTRIBUTE            *Attribute,
> -  IN IA32_MAP_ATTRIBUTE            *Mask
> +  IN OUT volatile IA32_PAGE_NON_LEAF_ENTRY  *Pnle,
> +  IN IA32_MAP_ATTRIBUTE                     *Attribute,
> +  IN IA32_MAP_ATTRIBUTE                     *Mask
>     )
>   {
>     IA32_PAGE_NON_LEAF_ENTRY  LocalPnle;
> --
> 2.31.1.windows.1
> 
> 
> 
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> 



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  reply	other threads:[~2024-03-01 11:50 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-01  2:54 [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib: qualify page table accesses as volatile Zhou Jianfeng
2024-03-01 11:50 ` Michael Brown [this message]
2024-03-01 12:21 ` Laszlo Ersek
2024-03-01 18:56 ` Laszlo Ersek
  -- strict thread matches above, loose matches on Subject: below --
2024-02-22  8:41 Zhou Jianfeng
2024-02-23 11:59 ` Michael Brown
2024-02-23 15:12   ` Zhou, Jianfeng
2024-02-23 15:51     ` Michael Brown
2024-02-25 13:47       ` Laszlo Ersek

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