From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by mx.groups.io with SMTP id smtpd.web11.1968.1641266996172028013 for ; Mon, 03 Jan 2022 19:29:57 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=none, err=permanent DNS error (domain: byosoft.com.cn, ip: 58.240.74.242, mailfrom: gaoliming@byosoft.com.cn) Received: from DESKTOPS6D0PVI ([58.246.60.130]) (envelope-sender ) by 192.168.6.13 with ESMTP for ; Tue, 04 Jan 2022 11:29:52 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 58.246.60.130 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming" To: "'Maggie Chu'" , Cc: "'Michael D Kinney'" , "'Zhiguang Liu'" References: <20211226155440.1726-1-maggie.chu@intel.com> In-Reply-To: <20211226155440.1726-1-maggie.chu@intel.com> Subject: =?UTF-8?B?5Zue5aSNOiBbUEFUQ0ggdjJdIE1kZVBrZzogQWRkIHJlZ2lzdGVycyBvZiBib290IHBhcnRpdGlvbiBmZWF0dXJl?= Date: Tue, 4 Jan 2022 11:29:53 +0800 Message-ID: <012b01d8011b$569d6510$03d82f30$@byosoft.com.cn> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQHbwhLtFZz4gTLeYyLUJ6i5ur9aqaxKsoHw Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn Reviewed-by: Liming Gao > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: Maggie Chu > =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA12=D4=C226=C8=D5 23:55 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io > =B3=AD=CB=CD: Liming Gao ; Michael D Kinney > ; Zhiguang Liu > =D6=F7=CC=E2: [PATCH v2] MdePkg: Add registers of boot partition = feature >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3757 >=20 > Add registers of boot partition feature which defined in NVM Express = 1.4 Spec >=20 > Cc: Liming Gao > Cc: Michael D Kinney > Cc: Zhiguang Liu > Signed-off-by: Maggie Chu > --- > MdePkg/Include/IndustryStandard/Nvme.h | 108 > ++++++++++++++++++++----- > 1 file changed, 89 insertions(+), 19 deletions(-) >=20 > diff --git a/MdePkg/Include/IndustryStandard/Nvme.h > b/MdePkg/Include/IndustryStandard/Nvme.h > index 7d4aee9dc8..8a2c747a85 100644 > --- a/MdePkg/Include/IndustryStandard/Nvme.h > +++ b/MdePkg/Include/IndustryStandard/Nvme.h > @@ -2,11 +2,12 @@ > Definitions based on NVMe spec. version 1.1. >=20 >=20 >=20 > (C) Copyright 2016 Hewlett Packard Enterprise Development LP
>=20 > - Copyright (c) 2017, Intel Corporation. All rights reserved.
>=20 > + Copyright (c) 2017 - 2021, Intel Corporation. All rights = reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > @par Specification Reference: >=20 > NVMe Specification 1.1 >=20 > + NVMe Specification 1.4 >=20 >=20 >=20 > **/ >=20 >=20 >=20 > @@ -18,18 +19,21 @@ > // >=20 > // controller register offsets >=20 > // >=20 > -#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities >=20 > -#define NVME_VER_OFFSET 0x0008 // Version >=20 > -#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set >=20 > -#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear >=20 > -#define NVME_CC_OFFSET 0x0014 // Controller > Configuration >=20 > -#define NVME_CSTS_OFFSET 0x001c // Controller Status >=20 > -#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset >=20 > -#define NVME_AQA_OFFSET 0x0024 // Admin Queue > Attributes >=20 > -#define NVME_ASQ_OFFSET 0x0028 // Admin Submission > Queue Base Address >=20 > -#define NVME_ACQ_OFFSET 0x0030 // Admin Completion > Queue Base Address >=20 > -#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 > (admin) Tail Doorbell >=20 > -#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 > (admin) Head Doorbell >=20 > +#define NVME_CAP_OFFSET 0x0000 // Controller > Capabilities >=20 > +#define NVME_VER_OFFSET 0x0008 // Version >=20 > +#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set >=20 > +#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear >=20 > +#define NVME_CC_OFFSET 0x0014 // Controller > Configuration >=20 > +#define NVME_CSTS_OFFSET 0x001c // Controller Status >=20 > +#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem > Reset >=20 > +#define NVME_AQA_OFFSET 0x0024 // Admin Queue > Attributes >=20 > +#define NVME_ASQ_OFFSET 0x0028 // Admin Submission > Queue Base Address >=20 > +#define NVME_ACQ_OFFSET 0x0030 // Admin Completion > Queue Base Address >=20 > +#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition > Information >=20 > +#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read > Select >=20 > +#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition > Memory Buffer Location >=20 > +#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 > (admin) Tail Doorbell >=20 > +#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 > (admin) Head Doorbell >=20 >=20 >=20 > // >=20 > // These register offsets are defined as 0x1000 + (N * (4 << = CAP.DSTRD)) >=20 > @@ -51,11 +55,14 @@ typedef struct { > UINT8 To; // Timeout >=20 > UINT16 Dstrd : 4; >=20 > UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS >=20 > - UINT16 Css : 4; // Command Sets Supported - Bit 37 >=20 > - UINT16 Rsvd3 : 7; >=20 > + UINT16 Css : 8; // Command Sets Supported - Bit 37 >=20 > + UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4 >=20 > + UINT16 Rsvd3 : 2; >=20 > UINT8 Mpsmin : 4; >=20 > UINT8 Mpsmax : 4; >=20 > - UINT8 Rsvd4; >=20 > + UINT8 Pmrs : 1; >=20 > + UINT8 Cmbs : 1; >=20 > + UINT8 Rsvd4 : 6; >=20 > } NVME_CAP; >=20 >=20 >=20 > // >=20 > @@ -115,7 +122,36 @@ typedef struct { > #define NVME_ACQ UINT64 >=20 >=20 >=20 > // >=20 > -// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission > Queue y Tail Doorbell >=20 > +// 3.1.13 Offset 40h: BPINFO - Boot Partition Information >=20 > +// >=20 > +typedef struct { >=20 > + UINT32 Bpsz : 15; // Boot Partition Size >=20 > + UINT32 Rsvd1 : 9; >=20 > + UINT32 Brs : 2; // Boot Read Status >=20 > + UINT32 Rsvd2 : 5; >=20 > + UINT32 Abpid : 1; // Active Boot Partition ID >=20 > +} NVME_BPINFO; >=20 > + >=20 > +// >=20 > +// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select >=20 > +// >=20 > +typedef struct { >=20 > + UINT32 Bprsz : 10; // Boot Partition Read Size >=20 > + UINT32 Bprof : 20; // Boot Partition Read Offset >=20 > + UINT32 Rsvd1 : 1; >=20 > + UINT32 Bpid : 1; // Boot Partition Identifier >=20 > +} NVME_BPRSEL; >=20 > + >=20 > +// >=20 > +// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location > (Optional) >=20 > +// >=20 > +typedef struct { >=20 > + UINT64 Rsvd1 : 12; >=20 > + UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address >=20 > +} NVME_BPMBL; >=20 > + >=20 > +// >=20 > +// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission > Queue y Tail Doorbell >=20 > // >=20 > typedef struct { >=20 > UINT16 Sqt; >=20 > @@ -353,7 +389,7 @@ typedef struct { > UINT8 Avscc; /* Admin Vendor Specific Command > Configuration */ >=20 > UINT8 Apsta; /* Autonomous Power State Transition > Attributes */ >=20 > // >=20 > - // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec >=20 > + // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec >=20 > // >=20 > UINT16 Wctemp; /* Warning Composite > Temperature Threshold */ >=20 > UINT16 Cctemp; /* Critical Composite > Temperature Threshold */ >=20 > @@ -361,7 +397,12 @@ typedef struct { > UINT32 Hmpre; /* Host Memory Buffer > Preferred Size */ >=20 > UINT32 Hmmin; /* Host Memory Buffer > Minimum Size */ >=20 > UINT8 Tnvmcap[16]; /* Total NVM Capacity */ >=20 > - UINT8 Rsvd2[216]; /* Reserved as of NVM Express > */ >=20 > + UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */ >=20 > + UINT32 Rpmbs; /* Replay Protected Memory > Block Support */ >=20 > + UINT16 Edstt; /* Extended Device Self-test > Time */ >=20 > + UINT8 Dsto; /* Device Self-test Options */ >=20 > + UINT8 Fwug; /* Firmware Update > Granularity */ >=20 > + UINT8 Rsvd2[192]; /* Reserved as of Nvm Express > 1.4 Spec */ >=20 > // >=20 > // NVM Command Set Attributes >=20 > // >=20 > @@ -433,6 +474,34 @@ typedef struct { > UINT8 VendorData[3712]; /* Vendor specific data */ >=20 > } NVME_ADMIN_NAMESPACE_DATA; >=20 >=20 >=20 > +// >=20 > +// RPMB Device Configuration Block Data Structure as of Nvm Express = 1.4 > Spec >=20 > +// >=20 > +typedef struct { >=20 > + UINT8 Bppe; /* Boot Partition Protection Enable */ >=20 > + UINT8 Bpl; /* Boot Partition Lock */ >=20 > + UINT8 Nwpac; /* Namespace Write Protection Authentication > Control */ >=20 > + UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */ >=20 > +} NVME_RPMB_CONFIGURATION_DATA; >=20 > + >=20 > +#define RPMB_FRAME_STUFF_BYTES 223 >=20 > + >=20 > +// >=20 > +// RPMB Data Frame as of Nvm Express 1.4 Spec >=20 > +// >=20 > +typedef struct { >=20 > + UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff > Bytes */ >=20 > + /* [222:222-(N-1)] > Authentication Key or Message Authentication Code (MAC) */ >=20 > + UINT8 Rpmbt; /* RPMB Target */ >=20 > + UINT64 Nonce[2]; >=20 > + UINT32 Wcounter; /* Write Counter */ >=20 > + UINT32 Address; /* Starting address of > data to be programmed to or read from the RPMB. */ >=20 > + UINT32 Scount; /* Sector Count */ >=20 > + UINT16 Result; >=20 > + UINT16 Rpmessage; /* > Request/Response Message */ >=20 > +// UINT8 *Data; /* Data to be written > or read by signed access where M =3D 512 * Sector Count. */ >=20 > +} NVME_RPMB_DATA_FRAME; >=20 > + >=20 > // >=20 > // NvmExpress Admin Identify Cmd >=20 > // >=20 > @@ -564,6 +633,7 @@ typedef struct { > #define LID_ERROR_INFO 0x1 >=20 > #define LID_SMART_INFO 0x2 >=20 > #define LID_FW_SLOT_INFO 0x3 >=20 > + #define LID_BP_INFO 0x15 >=20 > UINT32 Rsvd1 : 8; >=20 > UINT32 Numd : 12; /* Number of Dwords */ >=20 > UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec > */ >=20 > -- > 2.26.2.windows.1