From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=eric.auger@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA63E21195BD1 for ; Tue, 27 Nov 2018 06:51:30 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 42D6283F3E; Tue, 27 Nov 2018 14:51:30 +0000 (UTC) Received: from [10.36.116.102] (ovpn-116-102.ams2.redhat.com [10.36.116.102]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1196C1A909; Tue, 27 Nov 2018 14:51:25 +0000 (UTC) To: Ard Biesheuvel , edk2-devel@lists.01.org Cc: Laszlo Ersek , Leif Lindholm , Andrew Jones , Philippe Mathieu-Daude , Julien Grall References: <20181126223801.17121-1-ard.biesheuvel@linaro.org> <20181126223801.17121-2-ard.biesheuvel@linaro.org> From: Auger Eric Message-ID: <01a3ac7b-14c7-4c7c-6a5b-68a012f81feb@redhat.com> Date: Tue, 27 Nov 2018 15:51:24 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.0 MIME-Version: 1.0 In-Reply-To: <20181126223801.17121-2-ard.biesheuvel@linaro.org> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 27 Nov 2018 14:51:30 +0000 (UTC) Subject: Re: [PATCH v2 01/13] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Nov 2018 14:51:31 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Hi, On 11/26/18 11:37 PM, Ard Biesheuvel wrote: > Add a helper function that returns the maximum physical address space > size as supported by the current CPU. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Include/Library/ArmLib.h | 17 +++++++++++++++++ > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 16 ++++++++++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > 3 files changed, 41 insertions(+) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index ffda50e9d767..b22879fe6e94 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -29,6 +29,17 @@ > #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ > EFI_MEMORY_WT | EFI_MEMORY_WB | \ > EFI_MEMORY_UCE) > +// > +// ARM_MMU_IDMAP_RANGE defines the maximum size of the identity mapping > +// that covers the entire address space when running in UEFI. This is > +// limited to what can architecturally be mapped using a 4 KB granule, > +// even if the hardware is capable of mapping more using larger pages. > +// > +#ifdef MDE_CPU_ARM > +#define ARM_MMU_IDMAP_RANGE (1ULL << 32) > +#else > +#define ARM_MMU_IDMAP_RANGE (1ULL << 48) > +#endif > > /** > * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes. > @@ -733,4 +744,10 @@ ArmWriteCntvOff ( > UINT64 Val > ); > > +UINTN > +EFIAPI > +ArmGetPhysicalAddressBits ( > + VOID > + ); > + > #endif // __ARM_LIB__ > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > index 1ef2f61f5979..7332601241aa 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > @@ -196,4 +196,20 @@ ASM_FUNC(ArmWriteSctlr) > 3:msr sctlr_el3, x0 > 4:ret > > +ASM_FUNC(ArmGetPhysicalAddressBits) > + mrs x0, id_aa64mmfr0_el1 > + adr x1, .LPARanges > + and x0, x0, #7 > + ldrb w0, [x1, x0] > + ret > + > +// > +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the > +// physical address space support on this CPU: > +// 0 == 32 bits, 1 == 36 bits, etc etc > +// 6 and 7 are reserved > +// > +.LPARanges: > + .byte 32, 36, 40, 42, 44, 48, 52, -1 > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > index f2a517671f0a..f2f3c9a25991 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > isb > bx lr > > +ASM_FUNC (ArmGetPhysicalAddressBits) > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > + and r0, r0, #0xf // VMSA [3:0] > + cmp r0, #5 // >5 implies LPAE support nit: >= 5 in the comment Thanks Eric > + movlt r0, #32 // 32 bits if no LPAE > + movge r0, #40 // 40 bits if LPAE > + bx lr > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED >