From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 160B074003A for ; Tue, 23 Apr 2024 13:15:33 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=MHFB9GmUN0zQdi4UXTjA5iz+uLnFWpwfxFm25Y3CrWM=; c=relaxed/simple; d=groups.io; h=From:To:Cc:References:In-Reply-To:Subject:Date:Message-ID:MIME-Version:Thread-Index:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding:Content-Language; s=20240206; t=1713878132; v=1; b=KbCTCzVG8O28f9WPGd6Lpn8TMN1nM5XbZpLRU56vwDkRF2Ayd4tNVOdwfItYlOhL8I2RyVCN DEbq00nUT+uV2gobKo6lx7v6qN7r1/9/JUkP216Je5g8fj1NZDfGfg8OYzcXpvFcy4YGk37sGJc c7gISakAg1ljvndxRBBi/ZHOP40GGp6HN25c7abI+9kd0IKS5KRYwpnLAFIoSOBwkfUKhhpJ6nj +PRHbVYNehFb768fTI5Q3B0/z8pztgUCTLwXXBtY4HNcdK4aQUQ1zlFakJGGnSFOVJ8EntGh2/1 97vyPU7VF+FLtFq4E7RiKHRGpejC2JYA3jpWG8rRxop8g== X-Received: by 127.0.0.2 with SMTP id 0XdbYY7687511xMeToRdN0Go; Tue, 23 Apr 2024 06:15:32 -0700 X-Received: from cxsh.intel-email.com (cxsh.intel-email.com [121.46.250.151]) by mx.groups.io with SMTP id smtpd.web11.18217.1713878130942196296 for ; Tue, 23 Apr 2024 06:15:31 -0700 X-Received: from cxsh.intel-email.com (localhost [127.0.0.1]) by cxsh.intel-email.com (Postfix) with ESMTP id C0F29DDA7A0 for ; Tue, 23 Apr 2024 21:15:26 +0800 (CST) X-Received: from localhost (localhost [127.0.0.1]) by cxsh.intel-email.com (Postfix) with ESMTP id B717FDDA798 for ; Tue, 23 Apr 2024 21:15:26 +0800 (CST) X-Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by cxsh.intel-email.com (Postfix) with SMTP id DB961DDA795 for ; Tue, 23 Apr 2024 21:15:23 +0800 (CST) X-Received: from DESKTOPS6D0PVI ([114.92.234.250]) (envelope-sender ) by 192.168.6.13 with ESMTP(SSL) for ; Tue, 23 Apr 2024 21:15:20 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 114.92.234.250 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming via groups.io" To: "'Nong, Foster'" , , "'Kinney, Michael D'" , "'Chris Li'" Cc: "'Ni, Ray'" References: <20231129065729.8259-1-foster.nong@intel.com> <00f101da327b$ea268490$be738db0$@byosoft.com.cn> In-Reply-To: Subject: =?UTF-8?B?5Zue5aSNOiBbZWRrMi1kZXZlbF0gW1BBVENIIHYxXSBNZGVQa2c6IEFkZCBDeGwzMC5oIGludG8gSW5kdXN0cnlTdGFuZGFyZA==?= Date: Tue, 23 Apr 2024 21:15:21 +0800 Message-ID: <01bf01da9580$4bfe7210$e3fb5630$@byosoft.com.cn> MIME-Version: 1.0 Thread-Index: AQGQLw+Fwmn+BQtTNUAEf7U9KYfPWgEZxS7xAuKhD5QB+hcLBwKjH7QnscXVd6A= Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 23 Apr 2024 06:15:32 -0700 Resent-From: gaoliming@byosoft.com.cn Reply-To: devel@edk2.groups.io,gaoliming@byosoft.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 7SZ8zY5N2RDO10ofyuV9MOlsx7686176AA= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=KbCTCzVG; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io Seemly, there is no other comments. I create PR https://github.com/tianocor= e/edk2/pull/5585 to merge it.=20 Thanks Liming > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > =E5=8F=91=E4=BB=B6=E4=BA=BA: Nong, Foster > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2024=E5=B9=B44=E6=9C=8823=E6=97=A5 = 18:07 > =E6=94=B6=E4=BB=B6=E4=BA=BA: gaoliming ; devel@= edk2.groups.io; > Kinney, Michael D ; 'Chris Li' > > =E6=8A=84=E9=80=81: Ni, Ray > =E4=B8=BB=E9=A2=98: RE: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h into > IndustryStandard >=20 > Hi Liming, >=20 > What is the patch review status? Can this patch be merged? >=20 > -----Original Message----- > From: Nong, Foster > Sent: Wednesday, December 27, 2023 2:05 PM > To: gaoliming ; devel@edk2.groups.io; Kinney, > Michael D ; 'Chris Li' > > Cc: Ni, Ray > Subject: RE: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h into > IndustryStandard >=20 > Thanks Liming! > @'Chris Li' and @Kinney, Michael D, please help comment the patch. Thanks= ! >=20 > -----Original Message----- > From: gaoliming > Sent: Tuesday, December 19, 2023 9:05 PM > To: devel@edk2.groups.io; Nong, Foster ; Kinney, > Michael D ; 'Chris Li' > > Cc: Ni, Ray > Subject: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h = into > IndustryStandard >=20 > Foster: > I have no comments for this patch. Acked-by: Liming Gao > >=20 > Thanks > Liming > > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > > =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io =E4=BB=A3=E8=A1=A8 Nong, > Foster > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2023=E5=B9=B412=E6=9C=8819=E6=97= =A5 18:17 > > =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io; Kinney, Michael D > > ; Gao, Liming ; > > Chris Li > > =E6=8A=84=E9=80=81: Ni, Ray > > =E4=B8=BB=E9=A2=98: Re: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h int= o > > IndustryStandard > > > > @Gao, Liming @Chris Li @Kinney, Michael D, > > > > Don't forget reviewing the patch. Thanks! > > > > -----Original Message----- > > From: Nong, Foster > > Sent: Wednesday, November 29, 2023 2:57 PM > > To: devel@edk2.groups.io > > Cc: Nong, Foster ; Kinney, Michael D > > ; Gao, Liming ; > > Ni, Ray ; Chris Li > > Subject: [PATCH v1] MdePkg: Add Cxl30.h into IndustryStandard > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4516 > > > > 1) Add CXL 3.0 header file to comply with CXL 3.0 specification > > 2) CXL 3.0 header will embed Cxl20.h > > 3) Updated Cxl.h to point to 3.0 header file > > > > Signed-off-by: Foster Nong > > Cc: Michael D Kinney > > Cc: Liming Gao > > Cc: Ray Ni > > Cc: Chris Li > > --- > > MdePkg/Include/IndustryStandard/Cxl.h | 2 +- > > MdePkg/Include/IndustryStandard/Cxl30.h | 315 > ++++++++++++++++++++ > > 2 files changed, 316 insertions(+), 1 deletion(-) > > > > diff --git a/MdePkg/Include/IndustryStandard/Cxl.h > > b/MdePkg/Include/IndustryStandard/Cxl.h > > index 9ad3242e25..cb623a355d 100755 > > --- a/MdePkg/Include/IndustryStandard/Cxl.h > > +++ b/MdePkg/Include/IndustryStandard/Cxl.h > > @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef > > _CXL_MAIN_H_ #define _CXL_MAIN_H_ -#include > > +#include // // > > CXL assigned new Vendor ID //diff --git > > a/MdePkg/Include/IndustryStandard/Cxl30.h > > b/MdePkg/Include/IndustryStandard/Cxl30.h > > new file mode 100644 > > index 0000000000..feb6b9c52f > > --- /dev/null > > +++ b/MdePkg/Include/IndustryStandard/Cxl30.h > > @@ -0,0 +1,315 @@ > > +/** @file+ CXL 3.0 Register definitions++ This file contains the > register > > definitions based on the Compute Express Link+ (CXL) Specification > Revision > > 3.0.++ Copyright (c) 2023, Intel Corporation. All rights > > reserved.
++ > > SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef > > CXL30_H_+#define CXL30_H_++#include > ++//+// > > CXL Cache Memory Capability IDs+// Compute Express Link Specification > > Revision 3.0 - Chapter 8.2.4 Table 8-22+//+#define > > CXL_CACHE_MEM_CAPABILITY_ID_TIMEOUT_AND_ISOLATION > > 0x0009+#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED > > 0x000A+#define CXL_CACHE_MEM_CAPABILITY_ID_BI_ROUTE_TABLE > > 0x000B+#define CXL_CACHE_MEM_CAPABILITY_ID_BI_DECODER > > 0x000C+#define > > CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_ROUTE_TABLE > > 0x000D+#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_DECODER > > 0x000E+#define > > CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_HDM_DECODER > > 0x000F++//+// CXL_Capability_Version+// Compute Express ink > > 0x000F++Specification > > Revision 3.0 - Chapter 8.2.4.5+//+#define > CXL_HDM_DECODER_VERSION_30 > > 0x3++//+// CXL CXL HDM Decoder n Control+// Compute Express Link > > Specification Revision 3.0 - 8.2.4.19.7+//+//+// Bit4..7: Interleave > > Ways (IW)+//+#define CXL_HDM_16_WAY_INTERLEAVING > > 0x4+#define CXL_HDM_3_WAY_INTERLEAVING > > 0x8+#define CXL_HDM_6_WAY_INTERLEAVING > > 0x9+#define CXL_HDM_12_WAY_INTERLEAVING > > 0xA++//+// Ensure proper structure formats+//+#pragma pack(1)++//+// > > CXL.cachemem Extended Register Capability+// Compute Express Link > > Specification Revision 3.0 - Chapter 8.2.4.24+//+typedef union {+ > > struct > {+ > > UINT32 ExtendedRangesBitmap : 16; // Bit 0..15+ UINT32 > > Reserved : 16; // Bit 16..31+ } Bits;+ UINT32 > > Uint32;+} CXL_CM_EXTENTED_REGISTER_CAPABILITY;++#define > > CXL_CM_EXTENTED_RANGES_BITMAP (BIT2 | BIT3 | BIT4 | BIT5 | > BIT6 > > | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT15)++//+// > > | CXL > BI > > Route Table Capability+// Compute Express Link Specification Revision > > 3.0 > - > > Chapter 8.2.4.25+//+typedef union {+ struct {+ UINT32 > > ExplicitBiRtCommitRequired :1; // bit 0+ > > UINT32 Reserved :31; // > bit > > 1..31+ } Bits;+ UINT32 Uint32;+} CXL_BI_RT_CAPABILITY;++typedef > > union {+ struct {+ UINT32 > > BiRtCommit :1; // bit 0+ > > UINT32 Reserved :31; // > > bit 1..31+ } Bits;+ UINT32 Uint32;+} > CXL_BI_RT_CONTROL;++typedef > > union {+ struct {+ UINT32 > > BiRtCommitted :1; // bit 0+ > > UINT32 BiRtErrorNotCommitted :1; // bit > > 1+ UINT32 > Reserved1 :6; > > // bit 2..7+ UINT32 > > BiRtCommitTimeoutScale :4; // bit 8..11+ > > UINT32 BiRtCommitTimeoutBase :4; // > bit > > 12..15+ UINT32 > > Reserved2 :16; // bit > 16..31+ } > > Bits;+ UINT32 Uint32;+} CXL_BI_RT_STATUS;++typedef struct {+ > > CXL_BI_RT_CAPABILITY > BiRtCap; > > // offset 0x00+ CXL_BI_RT_CONTROL > > BiRtControl; // offset 0x04+ CXL_BI_RT_STATUS > > BiRtStatus; // offset 0x08+} > CXL_BI_ROUTE_TABLE_CAPABILITY;++//+// > > CXL BI Decoder Capability+// Compute Express Link Specification > > Revision > 3.0 > > - Chapter 8.2.4.26+//+typedef union {+ struct {+ UINT32 > > HdmDCapable :1; // bit 0+ > > UINT32 ExplicitBiDecoderCommitRequired :1; // bit > 1+ > > UINT32 Reserved :30; // > bit > > 2..31+ } Bits;+ UINT32 Uint32;+} CXL_BI_DECODER_CAP;++typedef > > union {+ struct {+ UINT32 > > BiForward :1; // bit 0+ > > UINT32 BiEnable :1; // > bit > > 1+ UINT32 > BiDecoderCommit :1; > > // bit 2+ UINT32 > > Reserved :29; // bit > 3..31+ } > > Bits;+ UINT32 Uint32;+} CXL_BI_DECODER_CONTROL;++typedef > union > > {+ struct {+ UINT32 > > BiDecoderCommitted :1; // bit 0+ > > UINT32 BiDecoderErrorNotCommitted :1; // bit > > 1+ UINT32 > Reserved1 :6; > > // bit 2..7+ UINT32 > > BiDecoderCommitTimeoutScale :4; // bit 8..11+ > > UINT32 BiDecoderCommitTimeoutBase :4; // > bit > > 12..15+ UINT32 > > Reserved2 :16; // bit > 16..31+ } > > Bits;+ UINT32 Uint32;+} CXL_BI_DECODER_STATUS;++typedef struct > {+ > > CXL_BI_DECODER_CAP BiDecoderCap; > > // offset 0x00+ CXL_BI_DECODER_CONTROL > > BiDecoderControl; // offset 0x04+ CXL_BI_DECODER_STATUS > > BiDecoderStatus; // offset 0x08+} > > CXL_BI_DECODER_CAPABILITY;++//+// CXL Cache ID Route Table > > Capability+// Compute Express Link Specification Revision 3.0 - > > Capability+Chapter > > 8.2.4.27+//+typedef union {+ struct {+ UINT32 > > CacheIdTargetCount : 5; // Bit 0..4+ UINT32 > > Reserved1 : 3; // Bit 5..7+ UINT32 > > HdmDType2DeviceMaxCount : 4; // Bit 8..11+ > > UINT32 Reserved2 : 4; // Bit > > 12..15+ UINT32 ExplicitCacheIdRtCommitRequired : 1; > > // Bit 16+ UINT32 > Reserved3 : > > 15; // Bit 17:31+ } Bits;+ UINT32 Uint32;+} > > CXL_CACHE_ID_RT_CAPABILITY;++typedef union {+ struct {+ UINT32 > > CacheIdRtCommit : 1; // Bit 0+ UINT32 > > Reserved : 31; // Bit 1..31+ } Bits;+ UINT32 > > Uint32;+} CXL_CACHE_ID_RT_CONTROL;++typedef union {+ struct {+ > > UINT32 CacheIdRtCommitted : 1; // Bit 0+ > > UINT32 CacheIdRtErrNotCommitted : 1; // Bit 1+ > > UINT32 Reserved1 : 6; // Bit 2..7+ > > UINT32 CacheIdRtCommitTimeoutScale : 4; // Bit 8..11+ > > UINT32 CacheIdRtCommitTimeoutBase : 4; // Bit 12..15+ > > UINT32 Reserved2 : 16; // Bit 16..31+ } > > Bits;+ UINT32 Uint32;+} > CXL_CACHE_ID_RT_STATUS;++typedef > > union {+ struct {+ UINT16 > Valid : > > 1; // Bit 0+ UINT16 Reserved : 7; > // > > Bit 1..7+ UINT16 PortNumber : 8; // > Bit > > 8..15+ } Bits;+ UINT16 Uint16;+} > > CXL_CACHE_ID_RT_TARGET;++typedef struct {+ > > CXL_CACHE_ID_RT_CAPABILITY CacheIdRtCap; // > > offset 0x00+ CXL_CACHE_ID_RT_CONTROL > > CacheIdRtControl; // offset 0x04+ CXL_CACHE_ID_RT_STATUS > > CacheIdRtStatus; // offset 0x08+ UINT32 > > Reserved; // offset 0x0C+ CXL_CACHE_ID_RT_TARGET > > CacheIdRtTarget[]; // offset 0x10+} > > CXL_CACHE_ID_ROUTE_TABLE_CAPABILITY;++//+// CXL Cache ID Decoder > > Capability+// Compute Express Link Specification Revision 3.0 - > > Capability+Chapter > > 8.2.4.28+//+typedef union {+ struct {+ UINT32 > > ExplicitCacheIdDecoderCommitRequired : 1; // Bit 0+ UINT32 > > Reserved : 31; // Bit 1..31+ } > > Bits;+ UINT32 Uint32;+} > > CXL_CACHE_ID_DECODER_CAP;++typedef union {+ struct {+ UINT32 > > ForwardCacheId : 1; // Bit 0+ UINT32 > > AssignCacheId : 1; // Bit 1+ UINT32 > > HdmDType2DevicePresent : 1; // Bit 2+ UINT32 > > CacheIdDecoderCommit : 1; // Bit 3+ UINT32 > > Reserved1 : 4; // Bit 4..7+ UINT32 > > HdmDType2DeviceCacheId : 4; // Bit 8..11+ UINT32 > > Reserved2 : 4; // Bit 12..15+ UINT32 > > LocalCacheId : 4; // Bit 16..19+ UINT32 > > Reserved3 : 4; // Bit 20..23+ UINT32 > > TrustLevel : 2; // Bit 24..25+ UINT32 > > Reserved4 : 6; // Bit 26..31+ } Bits;+ UINT32 > > Uint32;+} CXL_CACHE_ID_DECODER_CONTROL;++typedef union {+ struct > > {+ UINT32 CacheIdDecoderCommitted : 1; > > // Bit 0+ UINT32 CacheIdDecoderErrorNotCommitted : > 1; > > // Bit 1+ UINT32 > Reserved1 : > > 6; // Bit 2..7+ UINT32 > > CacheIdDecoderCommitTimeoutScale : 4; // Bit 8..11+ UINT32 > > CacheIdDecoderCommitTimeoutBase : 4; // Bit 12..15+ > > UINT32 Reserved2 : 16; // Bit > > 16..31+ } Bits;+ UINT32 Uint32;+} > > CXL_CACHE_ID_DECODER_STATUS;++typedef struct {+ > > CXL_CACHE_ID_DECODER_CAP CacheIdDecoderCap; > > // offset 0x00+ CXL_CACHE_ID_DECODER_CONTROL > > CacheIdDecoderControl; // offset 0x04+ > > CXL_CACHE_ID_DECODER_STATUS CacheIdDecoderStatus; > // > > offset 0x08+} CXL_CACHE_ID_DECODER_CAPABILITY;++//+// CXL Timeout > and > > Isolation Capability Structure+// Compute Express Link Specification > > Revision 3.0 - Chapter 8.2.4.23+//+typedef union {+ struct {+ > UINT32 > > CxlmemTransactionTimeoutRangesSupported : 4; // Bits 3:0+ > > UINT32 CxlmemTransactionTimeoutSupported : 1; // Bits 4+ > > UINT32 Reserved1 : 3; // Bits > 7:5+ > > UINT32 CxlcacheTransactionTimeoutRangesSupported : 4; // Bits 11:8+ > > UINT32 CxlcacheTransactionTimeoutSupported : 1; // Bits 12+ > > UINT32 Reserved2 : 3; // Bits > > 15:13+ UINT32 CxlmemIsolationSupported : 1; > // > > Bits 16+ UINT32 CxlmemIsolationLinkdownSupported : 1; > > // Bits 17+ UINT32 CxlcacheIsolationSupported : 1; > > // Bits 18+ UINT32 CxlcacheIsolationLinkdownSupported : 1; > > // Bits 19+ UINT32 > Reserved3 : > > 5; // Bits 24:20+ UINT32 > IsolationErrCorSignalingSupported : > > 1; // Bits 25+ UINT32 IsolationInterruptSupported : > 1; > > // Bits 26+ UINT32 IsolationInterruptMessageNumber : 5; > > // Bits 31:27+ } Bits;+ UINT32 > > Data32;+} > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY;++typedef > > union {+ struct {+ UINT32 CxlmemTransactionTimeoutValue : 4; > > // Bits 3:0+ UINT32 CxlmemTransactionTimeoutEnable : 1; // Bits > > 4+ UINT32 Reserved1 : 3; // Bits 7:5+ > > UINT32 CxlcacheTransactionTimeoutValue : 4; // Bits 11:8+ > UINT32 > > CxlcacheTransactionTimeoutEnable : 1; // Bits 12+ UINT32 > > Reserved2 : 3; // Bits 15:13+ UINT32 > > CxlmemIsolationEnable : 1; // Bits 16+ UINT32 > > CxlmemIsolationLinkdownEnable : 1; // Bits 17+ UINT32 > > CxlcacheIsolationEnable : 1; // Bits 18+ UINT32 > > CxlcacheIsolationLinkdownEnable : 1; // Bits 19+ UINT32 > > Reserved3 : 5; // Bits 24:20+ UINT32 > > IsolationErrCorSignalingEnable : 1; // Bits 25+ UINT32 > > IsolationInterruptEnable : 1; // Bits 26+ UINT32 > > Reserved4 : 5; // Bits 31:27+ } Bits;+ > > UINT32 Data32;+} > > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL;++typedef union {+ > > struct {+ UINT32 CxlmemTransactionTimeout : 1; // Bits > 0+ > > UINT32 Reserved1 : 3; // Bits 3:1+ > > UINT32 CxlcacheTransactionTimeout : 1; // Bits 4+ UINT32 > > Reserved2 : 3; // Bits 7:5+ UINT32 > > CxlmemIsolationStatus : 1; // Bits 8+ UINT32 > > CxlmemIsolationLinkdownStatus : 1; // Bits 9+ UINT32 > > Reserved3 : 2; // Bits 11:10+ UINT32 > > CxlcacheIsolationStatus : 1; // Bits 12+ UINT32 > > CxlcacheIsolationLinkdownStatus : 1; // Bits 13+ UINT32 > > CxlRpBusy : 1; // Bits 14+ UINT32 > > Reserved4 : 17; // Bits 31:15+ } Bits;+ > > UINT32 Data32;+} > > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS;++typedef struct {+ > > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY > > TimeoutAndIsolationCap;+ UINT32 > > Reserved;+ CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL > > TimeoutAndIsolationControl;+ > > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS > > TimeoutAndIsolationStatus;+} > > > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE;++#pra > > gma pack()++#endif-- > > 2.37.1.windows.1 > > > > > > > >=20 > > >=20 >=20 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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