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From: "Ashish Singhal" <ashishsingha@nvidia.com>
To: <leif@nuviainc.com>, <ardb+tianocore@kernel.org>, <devel@edk2.groups.io>
Cc: Ashish Singhal <ashishsingha@nvidia.com>
Subject: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority
Date: Thu, 25 Feb 2021 10:19:46 -0700	[thread overview]
Message-ID: <0284001c888f058e59853e725d4f02a00840506a.1614273201.git.ashishsingha@nvidia.com> (raw)

Incorrect register is being set for configuring interrupt
priority. Correct register is located in SGI space and not
in RD space.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
 ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 8ef32b3..3c0bee6 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -236,7 +236,7 @@ ArmGicSetInterruptPriority (
     }
 
     MmioAndThenOr32 (
-      GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
+      GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + (4 * RegOffset),
       ~(0xff << RegShift),
       Priority << RegShift
       );
-- 
2.7.4


             reply	other threads:[~2021-02-25 17:19 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-25 17:19 Ashish Singhal [this message]
2021-02-25 20:07 ` [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority Leif Lindholm
2021-03-01 14:48   ` Ashish Singhal

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