[PATCH v3] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

[PATCH v3] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

[Chasel, Chiu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating
FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.
Also Keeps new structure size 8 bytes alignment as other
structures.

Test: Verified on internal platform to boot with this PPI
installed successfully.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 IntelFsp2Pkg/IntelFsp2Pkg.dec                |  3 +++
 2 files changed, 57 insertions(+)

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..5bedb95aa7
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,54 @@
+/** @file
+  Header file for FSP-M Arch Config PPI for Dispatch mode
+
+ @copyright
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License which accompanies this distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+  { \
+    0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
+  }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+  ///
+  /// Revision of the structure
+  ///
+  UINT8         Revision;
+  UINT8         Reserved[3];
+  ///
+  /// Pointer to the non-volatile storage (NVS) data buffer.
+  /// If it is NULL it indicates the NVS data is not available.
+  ///
+  VOID          *NvsBufferPtr;
+  ///
+  /// Size of memory to be reserved by FSP below "top
+  /// of low usable memory" for bootloader usage.
+  ///
+  UINT32        BootLoaderTolumSize;
+  UINT8         Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec
index 50496241da..de1bece562 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -70,6 +70,9 @@
   gFspPerformanceDataGuid               = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
   gFspEventEndOfFirmwareGuid            = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
 
+[Ppis]
+  gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
+
 [PcdsFixedAtBuild]
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32|0x10001001
-- 
2.13.3.windows.1

Re: [PATCH v3] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

[Zeng, Star]

Reviewed-by: Star Zeng <star.zeng@intel.com>

-----Original Message-----
From: Chiu, Chasel 
Sent: Tuesday, January 15, 2019 2:03 PM
To: edk2-devel@lists.01.org
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>
Subject: [PATCH v3] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.
Also Keeps new structure size 8 bytes alignment as other structures.

Test: Verified on internal platform to boot with this PPI installed successfully.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 IntelFsp2Pkg/IntelFsp2Pkg.dec                |  3 +++
 2 files changed, 57 insertions(+)

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..5bedb95aa7
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,54 @@
+/** @file
+  Header file for FSP-M Arch Config PPI for Dispatch mode
+
+ @copyright
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made 
+ available under  the terms and conditions of the BSD License which accompanies this distribution.
+  The full text of the license may be found at  
+ http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,  
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+  { \
+    0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 
+0x4a, 0xbb } \
+  }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+  ///
+  /// Revision of the structure
+  ///
+  UINT8         Revision;
+  UINT8         Reserved[3];
+  ///
+  /// Pointer to the non-volatile storage (NVS) data buffer.
+  /// If it is NULL it indicates the NVS data is not available.
+  ///
+  VOID          *NvsBufferPtr;
+  ///
+  /// Size of memory to be reserved by FSP below "top
+  /// of low usable memory" for bootloader usage.
+  ///
+  UINT32        BootLoaderTolumSize;
+  UINT8         Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index 50496241da..de1bece562 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -70,6 +70,9 @@
   gFspPerformanceDataGuid               = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
   gFspEventEndOfFirmwareGuid            = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
 
+[Ppis]
+  gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
+
 [PcdsFixedAtBuild]
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32|0x10001001
--
2.13.3.windows.1

Re: [PATCH v3] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

[Desimone, Nathaniel L]

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

-----Original Message-----
From: Chasel, Chiu <chasel.chiu@intel.com> 
Sent: Monday, January 14, 2019 10:03 PM
To: edk2-devel@lists.01.org
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>; Star Zeng <star.zeng@intel.com>; Chasel Chiu <chasel.chiu@intel.com>
Subject: [PATCH v3] IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.
Also Keeps new structure size 8 bytes alignment as other structures.

Test: Verified on internal platform to boot with this PPI installed successfully.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h | 54 ++++++++++++++++++++++++++=+++++++++++++++++++++++++++
 IntelFsp2Pkg/IntelFsp2Pkg.dec                |  3 +++
 2 files changed, 57 insertions(+)

diff --git a/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/IntelFsp2Pkg/Incl=de/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..5bedb95aa7
--- /dev/null
+++ b/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,54 @@
+/** @file
+  Header file for FSP-M Arch Config PPI for Dispatch mode
+
+ @copyright
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+
+  This program and the accompanying materials are licensed and made 
+ availabl= under  the terms and conditions of the BSD License which accompanies this distrib=tion.
+  The full text of the license may be found at  
+ http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,  
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI=D.
+
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+  { \
+    0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 
+0x4a, =xbb } \
+  }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+  ///
+  /// Revision of the structure
+  ///
+  UINT8         Revision;
+  UINT8         Reserved[3];
+  ///
+  /// Pointer to the non-volatile storage (NVS) data buffer.
+  /// If it is NULL it indicates the NVS data is not available.
+  ///
+  VOID          *NvsBufferPtr;
+  ///
+  /// Size of memory to be reserved by FSP below "top
+  /// of low usable memory" for bootloader usage.
+  ///
+  UINT32        BootLoaderTolumSize;
+  UINT8         Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index 50496241da..de1bece562 100644
--- a/IntelFsp2Pkg/IntelFsp2Pkg.dec
+++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec
@@ -70,6 +70,9 @@
   gFspPerformanceDataGuid               = { 0x56ed21b6, 0xba23, 0x429e, { =x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
   gFspEventEndOfFirmwareGuid            = { 0xbd44f629, 0xeae7, 0x4198, { =x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
 
+[Ppis]
+  gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, { =x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
+
 [PcdsFixedAtBuild]
   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32=0x00000001
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32=0x10001001
--
2.13.3.windows.1