From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=nathaniel.l.desimone@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 97626211E2C01 for ; Sun, 31 Mar 2019 22:42:28 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Mar 2019 22:42:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,295,1549958400"; d="scan'208";a="146903896" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by orsmga002.jf.intel.com with ESMTP; 31 Mar 2019 22:42:27 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.54]) by ORSMSX104.amr.corp.intel.com ([169.254.4.204]) with mapi id 14.03.0415.000; Sun, 31 Mar 2019 22:42:26 -0700 From: "Desimone, Nathaniel L" To: "Kubacki, Michael A" , "edk2-devel@lists.01.org" CC: "Sinha, Ankit" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" Thread-Topic: [edk2-platforms][PATCH v1 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update Thread-Index: AQHU6Bl0BJVwy+foBkC99BkJyvU9PaYmywBA Date: Mon, 1 Apr 2019 05:42:25 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAE9B2D87@ORSMSX114.amr.corp.intel.com> References: <20190331232740.16872-1-michael.a.kubacki@intel.com> <20190331232740.16872-3-michael.a.kubacki@intel.com> In-Reply-To: <20190331232740.16872-3-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTViYzQyNDAtODkxYi00MGIxLWI0NTctNTc5ZDNlOThlMGFmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRExcL0ZqWCtqMmlKQUphRGsycnNoWFRjcnh6T0hoakhDMWN5NWdsdTdcL2xjMkFQaG9LKzNrRDFnbzdsSmllQWs1In0= x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Subject: Re: [edk2-platforms][PATCH v1 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map update X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Apr 2019 05:42:28 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Your math looks correct. Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Sunday, March 31, 2019 4:28 PM To: edk2-devel@lists.01.org Cc: Sinha, Ankit ; Desimone, Nathaniel L ; Chiu, Chasel ; Gao, Liming ; Kinney, Michael D Subject: [edk2-platforms][PATCH v1 2/3] ClevoOpenBoardPkg/N1xxWU: Flash map= update Updates the total BIOS flash image size to 0x5E0000. This size matches the = BIOS region size already configured in the SPI flash descriptor. To write an image produced from the N1xxWU board build, write the N1XXWU.fd= file (~6 MB) to the beginning of the BIOS region in the SPI flash (current= ly 0x220000). Always back up the original SPI flash image. These offsets and sizes are su= bject to change over time. Cc: Ankit Sinha Cc: Nate DeSimone Cc: Chasel Chiu Cc: Liming Gao Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kubacki --- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 2 +- .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 44 +++++++++++-------= ---- .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 4 +- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 81487ed58d..2116c48fc0 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -55,7 +55,7 @@ # # Default value for OpenBoardPkg.fdf use # - DEFINE BIOS_SIZE_OPTION =3D SIZE_70 + DEFINE BIOS_SIZE_OPTION =3D SIZE_60 =20 ##########################################################################= ###### # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapIn= clude.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInc= lude.fdf index a727eb3b83..423c6b18f5 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.f= df +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclud +++ e.fdf @@ -14,39 +14,41 @@ ## =20 #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# -# 8 M BIOS - for FSP wrapper +# 6 M BIOS - for FSP wrapper #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# -DEFINE FLASH_BASE =3D 0x= FF800000 # -DEFINE FLASH_SIZE =3D 0x= 00800000 # +DEFINE FLASH_BASE =3D 0x= FFA20000 # +DEFINE FLASH_SIZE =3D 0x= 005E0000 # DEFINE FLASH_BLOCK_SIZE =3D 0x= 00010000 # -DEFINE FLASH_NUM_BLOCKS =3D 0x= 00000080 # +DEFINE FLASH_NUM_BLOCKS =3D 0x= 0000005E # #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# =20 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFFA20000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D 0x= 00040000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFFA20000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x= 0001E000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D 0x= 0001E000 # Flash addr (0xFF81E000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D=20 +0x0001E000 # Flash addr (0xFFA3E000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x= 00002000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFF820000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFFA40000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x= 00020000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00040000 # Flash addr (0xFF840000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset =3D 0x= 00040000 # Flash addr (0xFFA60000) +SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize =3D 0x= 00010000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00050000 # Flash addr (0xFFA70000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 000A0000 # Flash addr (0xFF8A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 000B0000 # Flash addr (0xFFAD0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00070000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00110000 # Flash addr (0xFF910000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00120000 # Flash addr (0xFFB40000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 00090000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 001A0000 # Flash addr (0xFF9A0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 001E0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 00380000 # Flash addr (0xFFB80000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00180000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 00500000 # Flash addr (0xFFD00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 001B0000 # Flash addr (0xFFBD0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 002F0000 # Flash addr (0xFFD10000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 000B0000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 003A0000 # Flash addr (0xFFDC0000) SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 005A0000 # Flash addr (0xFFDA0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00440000 # Flash addr (0xFFE60000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 00600000 # Flash addr (0xFFE00000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 004A0000 # Flash addr (0xFFEC0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000BC000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 006BC000 # Flash addr (0xFFEBC000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 0055C000 # Flash addr (0xFFF7C000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00004000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006C0000 # Flash addr (0xFFEC0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 00560000 # Flash addr (0xFFF80000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00080000 # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat b/Platfor= m/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat index c09d2d5b16..c3360403f1 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat @@ -202,8 +202,8 @@ cl =20 @set BIOS_SIZE_OPTION=3D =20 -@REM default size option is 7M -@set BIOS_SIZE_OPTION=3D-DBIOS_SIZE_OPTION=3DSIZE_70 +@REM default size option is 6M +@set BIOS_SIZE_OPTION=3D-DBIOS_SIZE_OPTION=3DSIZE_60 =20 :BiosSizeDone @echo BIOS_SIZE_OPTION=3D%BIOS_SIZE_OPTION% -- 2.16.2.windows.1