From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by groups.io with SMTP; Fri, 12 Apr 2019 18:05:27 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2019 18:05:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,343,1549958400"; d="scan'208";a="223105491" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by orsmga001.jf.intel.com with ESMTP; 12 Apr 2019 18:05:25 -0700 Received: from orsmsx156.amr.corp.intel.com (10.22.240.22) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 12 Apr 2019 18:05:25 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.50]) by ORSMSX156.amr.corp.intel.com ([169.254.8.17]) with mapi id 14.03.0415.000; Fri, 12 Apr 2019 18:05:25 -0700 From: "Nate DeSimone" To: "Chiu, Chasel" , "devel@edk2.groups.io" CC: "Zeng, Star" Subject: Re: [PATCH] IntelFsp2WrapperPkg: Perform post FSP-S process. Thread-Topic: [PATCH] IntelFsp2WrapperPkg: Perform post FSP-S process. Thread-Index: AQHU8UDGGj7t7kdK906hs5wSoLdREqY5Q7RQ Date: Sat, 13 Apr 2019 01:05:24 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEA34472@ORSMSX114.amr.corp.intel.com> References: <20190412150203.14836-1-chasel.chiu@intel.com> In-Reply-To: <20190412150203.14836-1-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMDkyYmY4ODUtZmFmZi00ZWU1LTg3NjktM2Y1NDZiNDRkMmUzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibnYxUGlwQWg5QUl5RmJGSG4zUEk4dkRkMWJWR3NDN05Ea2VYeDFjemRcL0dFYlRPMW1qSTdXR2xhcmNnNXJYd0EifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Chasel, Looks good! This is mildly unrelated to your change, but could you put a co= mment on the following line that informs the reader that 1 =3D=3D API Mode? if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) { Once that is done... Reviewed-by: Nate DeSimone -----Original Message----- From: Chiu, Chasel=20 Sent: Friday, April 12, 2019 8:02 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Zeng, Star Subject: [PATCH] IntelFsp2WrapperPkg: Perform post FSP-S process. From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1716 In API mode FSP wrapper will perform some post FSP-S process but such proce= ss was skipped in Dispatch mode which may impact some of boot loaders. To align behavior between API and Dispatch, an End-of-Pei callback is intro= duced to perform same process in Dispatch mode. Test: Verified on internal platform and both FSP API and Dispatch modes booted successfully. Cc: Nate DeSimone Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu --- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 50 +++++++++++++++= ++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelF= sp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index bb126797ae..c1823656ed 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -3,7 +3,7 @@ register TemporaryRamDonePpi to call TempRamExit API, and register Memor= yDiscoveredPpi notify to call FspSiliconInit API. =20 - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights=20 + reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -179,6 +179,46 @@ FspSiliconInitDoneGetFspHobList ( } =20 /** + This function is for FSP dispatch mode to perform post FSP-S process. + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Status returned by PeiServicesInstallPpi () +**/ +EFI_STATUS +EFIAPI +FspsWrapperEndOfPeiNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + + // + // In Dispatch mode no FspHobList so passing NULL // =20 + PostFspsHobProcess (NULL); + + // + // Install FspSiliconInitDonePpi so that any other driver can consume th= is info. + // + Status =3D PeiServicesInstallPpi (&mPeiFspSiliconInitDonePpi); =20 + ASSERT_EFI_ERROR(Status); + + return Status; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mFspsWrapperEndOfPeiNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |=20 +EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiEndOfPeiSignalPpiGuid, + FspsWrapperEndOfPeiNotify +}; + +/** This function is called after PEI core discover memory and finish migrat= ion. =20 @param[in] PeiServices Pointer to PEI Services Table. @@ -341,6 +381,8 @@ FspsWrapperPeimEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices ) { + EFI_STATUS Status; + DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n")); =20 if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) { @@ -353,6 +395,12 @@ FspsW= rapperPeimEntryPoint ( NULL, NULL ); + + // + // Register EndOfPei Nofity to run post FSP-S process. + // + Status =3D PeiServicesNotifyPpi (&mFspsWrapperEndOfPeiNotifyDesc); + ASSERT_EFI_ERROR (Status); } =20 return EFI_SUCCESS; -- 2.13.3.windows.1