From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Mon, 15 Apr 2019 09:50:21 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Apr 2019 09:50:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,354,1549958400"; d="scan'208";a="161755268" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by fmsmga002.fm.intel.com with ESMTP; 15 Apr 2019 09:50:20 -0700 Received: from orsmsx153.amr.corp.intel.com (10.22.226.247) by ORSMSX103.amr.corp.intel.com (10.22.225.130) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 15 Apr 2019 09:50:20 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.50]) by ORSMSX153.amr.corp.intel.com ([169.254.12.186]) with mapi id 14.03.0415.000; Mon, 15 Apr 2019 09:50:19 -0700 From: "Nate DeSimone" To: "Chiu, Chasel" , "devel@edk2.groups.io" CC: "Zeng, Star" Subject: Re: [PATCH v2] IntelFsp2WrapperPkg: Perform post FSP-S process. Thread-Topic: [PATCH v2] IntelFsp2WrapperPkg: Perform post FSP-S process. Thread-Index: AQHU810yqFQfxolDakGnBJVRE8252KY9b88g Date: Mon, 15 Apr 2019 16:50:19 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEA3BAD9@ORSMSX114.amr.corp.intel.com> References: <20190415060914.5644-1-chasel.chiu@intel.com> In-Reply-To: <20190415060914.5644-1-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWNkYWJiNWYtM2Y3MS00NWVmLThlMTItM2JkMGIzNzJhZmQ0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiQ1A4SHREakVnZHFTUGt5bWdqSldMZ3FLN2dxRnVyUUxzTFNwU0lsTDNHeXErK0JvMndQTkd6M3lYWFwvUjJweW4ifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Chiu, Chasel=20 Sent: Sunday, April 14, 2019 11:09 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Zeng, Star Subject: [PATCH v2] IntelFsp2WrapperPkg: Perform post FSP-S process. From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1716 In API mode FSP wrapper will perform some post FSP-S process but such proce= ss was skipped in Dispatch mode which may impact some of the boot loaders. To align behavior between API and Dispatch, an End-of-Pei callback is intro= duced to perform same process in Dispatch mode. Note: If boot loader implemented its own PostFspsHobProcess (), it has to check PcdFspModeSelection and support each mode properly. Test: Verified on internal platform and both FSP API and Dispatch modes booted successfully. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c = | 63 ++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++--- IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/FspWrapperHob= ProcessLibSample.c | 18 +++++++++++++++--- IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/PeiFspWrapper= HobProcessLibSample.inf | 3 ++- 3 files changed, 77 insertions(+), 7 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelF= sp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index bb126797ae..441233dfda 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -3,7 +3,7 @@ register TemporaryRamDonePpi to call TempRamExit API, and register Memor= yDiscoveredPpi notify to call FspSiliconInit API. =20 - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights=20 + reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -130,7 +130,7 @@ S3EndOfPeiNotify( @param[in] This The pointer to this instance of this PPI. @param[out] FspHobList The pointer to Hob list produced by FSP. =20 - @return EFI_SUCCESS FReturn Hob list produced by FSP successfully. + @return EFI_SUCCESS Return Hob list produced by FSP successfully. **/ EFI_STATUS EFIAPI @@ -157,7 +157,7 @@ EFI_PEI_PPI_DESCRIPTOR mPeiFspSiliconInitDon= ePpi =3D { @param[in] This The pointer to this instance of this PPI. @param[out] FspHobList The pointer to Hob list produced by FSP. =20 - @return EFI_SUCCESS FReturn Hob list produced by FSP successfully. + @return EFI_SUCCESS Return Hob list produced by FSP successfully. **/ EFI_STATUS EFIAPI @@ -179,6 +179,49 @@ FspSiliconInitDoneGetFspHobList ( } =20 /** + This function is for FSP dispatch mode to perform post FSP-S process. + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Status returned by PeiServicesInstallPpi () +**/ +EFI_STATUS +EFIAPI +FspsWrapperEndOfPeiNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + + // + // This step may include platform specific process in some boot=20 + loaders so // aligning the same behavior between API and Dispatch modes. + // Note: In Dispatch mode no FspHobList so passing NULL to function and + // expecting function will handle it. + // + PostFspsHobProcess (NULL); + + // + // Install FspSiliconInitDonePpi so that any other driver can consume th= is info. + // + Status =3D PeiServicesInstallPpi (&mPeiFspSiliconInitDonePpi); =20 + ASSERT_EFI_ERROR(Status); + + return Status; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mFspsWrapperEndOfPeiNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |=20 +EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiEndOfPeiSignalPpiGuid, + FspsWrapperEndOfPeiNotify +}; + +/** This function is called after PEI core discover memory and finish migrat= ion. =20 @param[in] PeiServices Pointer to PEI Services Table. @@ -341,11 +384,19 @@ FspsWrapperPeimEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices ) { + EFI_STATUS Status; + DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n")); =20 if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) { + // + // FSP-S Wrapper running in API mode and calls to FSP API entry point. + // FspsWrapperInit (); } else { + // + // FSP-S Wrapper running in Dispatch mode and reports FSP-S FV to PEI = dispatcher. + // PeiServicesInstallFvInfoPpi ( NULL, (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress), @@ -353,6 +404,12 @@ = FspsWrapperPeimEntryPoint ( NULL, NULL ); + + // + // Register EndOfPei Nofity to run post FSP-S process. + // + Status =3D PeiServicesNotifyPpi (&mFspsWrapperEndOfPeiNotifyDesc); + ASSERT_EFI_ERROR (Status); } =20 return EFI_SUCCESS; diff --git a/IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/F= spWrapperHobProcessLibSample.c b/IntelFsp2WrapperPkg/Library/PeiFspWrapperH= obProcessLibSample/FspWrapperHobProcessLibSample.c index 1c7f661c47..54cebe127c 100644 --- a/IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/FspWrapp= erHobProcessLibSample.c +++ b/IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/FspWr +++ apperHobProcessLibSample.c @@ -1,7 +1,7 @@ /** @file Sample to provide FSP wrapper hob process related function. =20 - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights=20 + reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -378,7 +378,19 @@ PostFspsHobProcess ( IN VOID *FspHobList ) { - ProcessFspHobList (FspHobList); - + // + // PostFspsHobProcess () will be called in both FSP API and Dispatch=20 + modes to // align the same behavior and support a variety of boot loader= implementations. + // Boot loader provided library function is recommended to support=20 + both API and // Dispatch modes by checking PcdFspModeSelection. + // + if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) { + // + // Only in FSP API mode the wrapper has to build hobs basing on FSP ou= tput data. + // In this case FspHobList cannot be NULL. + // + ASSERT (FspHobList !=3D NULL); + ProcessFspHobList (FspHobList); + } return EFI_SUCCESS; } diff --git a/IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/P= eiFspWrapperHobProcessLibSample.inf b/IntelFsp2WrapperPkg/Library/PeiFspWra= pperHobProcessLibSample/PeiFspWrapperHobProcessLibSample.inf index 938ffae494..6d9e306313 100644 --- a/IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/PeiFspWr= apperHobProcessLibSample.inf +++ b/IntelFsp2WrapperPkg/Library/PeiFspWrapperHobProcessLibSample/PeiFs +++ pWrapperHobProcessLibSample.inf @@ -1,7 +1,7 @@ ## @file # Sample to provide FSP wrapper hob process related function. # -# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -61,6 +61,7 @@ [Pcd= ] gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES =20 [Guids] gFspReservedMemoryResourceHobGuid ## CONSUMES ## H= OB -- 2.13.3.windows.1