From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Tue, 28 May 2019 18:12:32 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 May 2019 18:12:30 -0700 X-ExtLoop1: 1 Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by fmsmga006.fm.intel.com with ESMTP; 28 May 2019 18:12:32 -0700 Received: from orsmsx123.amr.corp.intel.com (10.22.240.116) by ORSMSX103.amr.corp.intel.com (10.22.225.130) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 28 May 2019 18:12:32 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.116]) by ORSMSX123.amr.corp.intel.com ([169.254.1.141]) with mapi id 14.03.0415.000; Tue, 28 May 2019 18:12:31 -0700 From: "Nate DeSimone" To: "Chiu, Chasel" , "devel@edk2.groups.io" CC: "Kubacki, Michael A" Subject: Re: [PATCH 2/2] KabylakeOpenBoardPkg: Add FSP Dispatch switch. Thread-Topic: [PATCH 2/2] KabylakeOpenBoardPkg: Add FSP Dispatch switch. Thread-Index: AQHVEHlXS2YlJ22Ys0qsFqgrGFPLS6aBViqA Date: Wed, 29 May 2019 01:12:31 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEB5FEA9@ORSMSX114.amr.corp.intel.com> References: <20190522083510.17476-1-chasel.chiu@intel.com> <20190522083510.17476-3-chasel.chiu@intel.com> In-Reply-To: <20190522083510.17476-3-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTk3YzZhMmYtNjViNi00YmMyLWE3OTAtZGEyNmE2MjI4OTg4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoianVEMGU0eTl5eFdOT1hnVG1CZWsrdXQwRUNyVzBnMTljUElNSmtPVVUyUWZxS2VqMFJLUTBtV1poblJtMGQ1TyJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Chiu, Chasel=20 Sent: Wednesday, May 22, 2019 1:35 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Kubacki, Michael A Subject: [PATCH 2/2] KabylakeOpenBoardPkg: Add FSP Dispatch switch. From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1832 Basing on PcdFspModeSelection setting either KabylakeFspBinPkg or AmberLake= FspBinPkg will be used and temporary memory arrangement will be different a= s AmberLakeFspBinPkg will share the same stack with boot loader. Also enlar= ged FSP-T size to support future larger FSP binary. Test: Booted Kabylake RVP3 to Windows successfully. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf | 8 = ++++---- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 33 = +++++++++++++++++++++++++++++---- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 29 = +++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 8 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclud= e.fdf b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf index 3a28bd4109..6cb49c941c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fd +++ f @@ -1,7 +1,7 @@ ## @file # FDF file of Platform. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +41,6 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = =3D 0x00060000 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 00600000 # Flash addr (0xFFE00000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000BC000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 006BC000 # Flash addr (0xFFEBC000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00004000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006C0000 # Flash addr (0xFFEC0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00014000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006D0000 # Flash addr (0xFFED0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00130000 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 7f19ad1eed..1dfe49a7ad 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,7 @@ DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE =3D KabylakeFspBinPkg + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg DEFINE BOARD =3D KabylakeRvp3 DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD) @@ -24,6 +24,21 @@ # Platform On/Off features are defined here # !include OpenBoardPkgConfig.dsc + !include OpenBoardPkgPcd.dsc + +[Defines] +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # For backward compatibility API mode will use KabylakeFspBinPkg. + # KabylakeFspBinPkg only supports API mode. + # + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D KabylakeFspBinPkg +!else + # + # AmberLakeFspBinPkg supports both API and Dispatch modes + # + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg +!endif =20 ##########################################################################= ###### # @@ -92,8 +107,20 @@ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf =20 FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # Below library are used by FSP API mode + # SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf + =20 +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLibFsp/PeiSiliconPolicyInitLibFsp.inf +!else + # + # Below library are used by FSP Dispatch mode and non-FSP build (EDK2=20 +build) + # + =20 +SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiSili +conPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf + =20 +SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyIni +tLibFsp/PeiSiliconPolicyInitLibFspAml.inf +!endif =20 ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInit= Lib.inf @@ -173,8 +200,6 @@ [LibraryClasses.X64.DXE_RUNTIME_DRIVER] ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf =20 -!include OpenBoardPkgPcd.dsc - [Components.IA32] =20 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index 9774acb5eb..63d0c4c2e6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d +++ sc @@ -28,6 +28,11 @@ =20 [PcdsFixedAtBuild.common] gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + # + # 0: FSP Wrapper is running in Dispatch mode. + # 1: FSP Wrapper is running in API mode. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 =20 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 @@ -49,9 +54,33 @@ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 =20 +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # FSP API mode is backward compatible with earlier FSP which + # does not share stack with boot loader, so FSP needs more + # temporary memory for FSP heap + stack size. + # gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 =20 + # + # In FSP API mode, FSP and boot loader runnig on different stack #=20 + so no need to enlarge boot loader stack size. + # gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 +!else + # + # FSP Dispatch mode will share the same stack with boot loader, + # here temporary ram size is used by FSP heap and can be smaller + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00010000 + + # + # In FSP Dispatch mode boot loader stack size must be big enough for=20 +executing + # both boot loader and FSP. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 -- 2.13.3.windows.1