From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Wed, 05 Jun 2019 12:45:42 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jun 2019 12:45:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,556,1549958400"; d="scan'208";a="182057083" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by fmsmga002.fm.intel.com with ESMTP; 05 Jun 2019 12:45:41 -0700 Received: from orsmsx156.amr.corp.intel.com (10.22.240.22) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 5 Jun 2019 12:45:41 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.116]) by ORSMSX156.amr.corp.intel.com ([169.254.8.144]) with mapi id 14.03.0415.000; Wed, 5 Jun 2019 12:45:40 -0700 From: "Nate DeSimone" To: "Chiu, Chasel" , "devel@edk2.groups.io" CC: "Kubacki, Michael A" , "Chaganty, Rangasai V" Subject: Re: [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP. Thread-Topic: [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP. Thread-Index: AQHVF6XlX5I+SMQoRka4+aEd0fu+26aNfnJA Date: Wed, 5 Jun 2019 19:45:40 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEBD24F0@ORSMSX114.amr.corp.intel.com> References: <20190531114207.21112-1-chasel.chiu@intel.com> <20190531114207.21112-2-chasel.chiu@intel.com> In-Reply-To: <20190531114207.21112-2-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNThhZmZjNDYtNzE1Yi00YmRiLWEzN2YtMTczOWY5Y2Y1YzIxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoic25JTnoyWlwvcXU1RFppRWkxTDY5RTBWc2hlZnJQRUNTZHpjVUJka04xcTdsMGdjWWZoQW5TY2RFYXdkTmxZbFMifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Chiu, Chasel=20 Sent: Friday, May 31, 2019 4:42 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Kubacki, Michael A ; Chaganty, Rangasai V ; Desi= mone, Nathaniel L Subject: [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP. From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1864 FSP Dispatch mode can consume DynamicEx PCD from boot loader so it must inc= lude those PCD in PCD database for FSP to consume. PeiPostMemSiliconPolicyInitLib.inf (this is for FSP Dispatch mode) has all = PCDs included to ensure they can be built into PCD database. Also cleaned up unused PciExpress related PCD from INFs. Cc: Michael A Kubacki Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Chasel Chiu --- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciL= ib.c | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDx= eSmmCpuPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc = | 6 +++++- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciL= ib.inf | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf= | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec = | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLi= b/PeiDxeSmmSaPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaP= olicyLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf = | 3 +-- 9 files changed, 25 insertions(+), 25 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/Pei= DxeSmmMmPciLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciL= ib/PeiDxeSmmMmPciLib.c index 51a06528e0..d99ee8e644 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmM= mPciLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeS +++ mmMmPciLib.c @@ -1,7 +1,7 @@ /** @file This file contains routines that get PCI Express Address =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -27,5 +27,9 @@ MmPciBase ( { ASSERT ((Bus <=3D 0xFF) && (Device <=3D 0x1F) && (Function <=3D 0x7)); =20 - return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20= ) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#ifdef FSP_FLAG + return ((UINTN) PcdGet64 (PcdSiPciExpressBaseAddress) + (UINTN) (Bus=20 +<< 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); #else + return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << = 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#endif } diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatf= ormLib/PeiDxeSmmCpuPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/L= ibrary/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf index 21d441a577..d2e813fea3 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/= PeiDxeSmmCpuPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformL +++ ib/PeiDxeSmmCpuPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for CPU Platform Lib # -# Copyright (c) 2017= , Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -34,11 +34,6 @@ MdePk= g/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec =20 - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] CpuPlatformLibrary.h CpuPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Sili= con/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc index 5b114ae99e..aa481d0307 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc @@ -47,7 +47,11 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FA= LSE =20 [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000 +# +# This DSC mainly for GreenH Silicon code build so=20 +PciExpressBaseAddress can be FixedAtBuild #=20 +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGui +d.PcdPciExpressBaseAddress =20 [Defines] PLATFORM_NAME =3D KabylakeSiliconPkg diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/Pei= DxeSmmMmPciLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPc= iLib/PeiDxeSmmMmPciLib.inf index 8ae40a0c9e..02495953a7 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmM= mPciLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeS +++ mmMmPciLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiDxeSmmMmPciLib # -# Copyright (c)= 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -31,11 +31,12 @@ Debu= gLib =20 [Packages] MdePkg/MdePkg.dec +KabylakeSiliconPkg/SiPkg.dec =20 =20 [Pcd] +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress =20 - [Sources] PeiDxeSmmMmPciLib.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/Silico= nInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/Sili= conInitLib.inf index 9007f299bb..132080e876 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLi= b.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconIni +++ tLib.inf @@ -1,6 +1,6 @@ ### @file # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ SiliconInitPreMem.c =20 [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES =20 diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/Kab= ylakeSiliconPkg/SiPkg.dec index a613079dd4..baee73038b 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec @@ -573,8 +573,12 @@ gSiPkgTokenSpaceGuid.PcdSerialIoUartInputClock |18432= 00|UINT32|0x00100003 ## PCI Express MMIO region length ## Valid settings:= 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB ## -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0010004 - +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000|UINT32|0x00 +10004 +## +## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciE= xpressBaseAddress. +## This PCD is added for supporting different PCD type in different phases= . +## +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress=20 +|0xE0000000|UINT64|0x0010008 =20 [PcdsFeatureFlag] ## diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmm= SaPlatformLib/PeiDxeSmmSaPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg= /SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf index 9fe71e5bac..5b034c2e9d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf= ormLib/PeiDxeSmmSaPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPl +++ atformLib/PeiDxeSmmSaPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for SA Platform Lib # -# Copyright (c) 2017,= Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,11 +28,6 @@ IoLib= MdePkg/MdePkg.dec KabylakeSiliconPkg/SiPkg.dec =20 - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] SaPlatformLibrary.h SaPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPoli= cyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Lib= rary/PeiSaPolicyLib/PeiSaPolicyLib.inf index 8fae4cee61..2adfc28d6c 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/P= eiSaPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLi +++ b/PeiSaPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSaPolicy library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -35,7 +35,6 @@ UefiCp= uPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit= Dxe.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe= .inf index cc05f336b3..3c4c79affb 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe. +++ inf @@ -1,7 +1,7 @@ ## @file # Component description file for SystemAgent Initialization driver # -# C= opyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -53,7 +53,6 @@ Kabyla= keSiliconPkg/KabylakeSiliconPrivate.dec =20 =20 [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId gSiPkgTokenSpaceGuid.PcdMchBaseAddress =20 -- 2.19.1.windows.1