From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Fri, 16 Aug 2019 17:51:17 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:51:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="177349695" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by fmsmga008.fm.intel.com with ESMTP; 16 Aug 2019 17:51:15 -0700 Received: from orsmsx163.amr.corp.intel.com (10.22.240.88) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 16 Aug 2019 17:51:15 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.96]) by ORSMSX163.amr.corp.intel.com ([169.254.9.208]) with mapi id 14.03.0439.000; Fri, 16 Aug 2019 17:51:15 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Thread-Topic: [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Thread-Index: AQHVVJEQ9XneLc986UGoSFHzcgjG6ab+go6g Date: Sat, 17 Aug 2019 00:51:13 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE1284F@ORSMSX114.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-5-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-5-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMzExODM2M2UtYTJhYi00M2JkLTliNWUtZWRlMGUwYWNhNDBiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieUV4R0FBSURidTFHVXNlWDl6TldlbitXa0ZYbU1GYWZQRDZnVm8yZDJlUEdKXC9hUHRlN0hZXC83Vk9GUDNtNUNDIn0= x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:16 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Gao, Liming ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add inc= lude headers REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds Pch/Include headers. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h = | 135 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h = | 326 +++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h = | 381 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h = | 340 +++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h = | 241 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h = | 200 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h = | 54 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h = | 38 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h = | 80 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h = | 53 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h = | 47 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h = | 47 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h = | 59 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResources.h = | 53 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h = | 23 ++ 15 files changed, 2077 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h new file mode 100644 index 0000000000..91222fd54d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h @@ -0,0 +1,135 @@ +/** @file + Header file for DxePchHdaNhltLib - NHLT structure definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_HDA_NHLT_H_ +#define _DXE_HDA_NHLT_H_ + +#include + +// +// ACPI support protocol instance signature definition. +// +#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T') + +// MSFT defined structures +#define SPEAKER_FRONT_LEFT 0x1 +#define SPEAKER_FRONT_RIGHT 0x2 +#define SPEAKER_FRONT_CENTER 0x4 +#define SPEAKER_BACK_LEFT 0x10 +#define SPEAKER_BACK_RIGHT 0x20 + +#define KSAUDIO_SPEAKER_MONO (SPEAKER_FRONT_CENTER) +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT) +#define KSAUDIO_SPEAKER_QUAD (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT |= SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT) + +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE +#define KSDATAFORMAT_SUBTYPE_PCM \ + {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, = 0x9b, 0x71}} + +#pragma pack (push, 1) + +typedef struct { + UINT16 wFormatTag; + UINT16 nChannels; + UINT32 nSamplesPerSec; + UINT32 nAvgBytesPerSec; + UINT16 nBlockAlign; + UINT16 wBitsPerSample; + UINT16 cbSize; +} WAVEFORMATEX; + +typedef struct { + WAVEFORMATEX Format; + union { + UINT16 wValidBitsPerSample; + UINT16 wSamplesPerBlock; + UINT16 wReserved; + } Samples; + UINT32 dwChannelMask; + GUID SubFormat; +} WAVEFORMATEXTENSIBLE; + +// +// List of supported link type. +// +enum NHLT_LINK_TYPE +{ + HdaNhltLinkHd =3D 0, + HdaNhltLinkDsp =3D 1, + HdaNhltLinkDmic =3D 2, + HdaNhltLinkSsp =3D 3, + HdaNhltLinkInvalid +}; + +// +// List of supported device type. +// +enum NHLT_DEVICE_TYPE +{ + HdaNhltDeviceBt =3D 0, + HdaNhltDeviceDmic =3D 1, + HdaNhltDeviceI2s =3D 4, + HdaNhltDeviceInvalid +}; + +typedef struct { + UINT32 CapabilitiesSize; + UINT8 Capabilities[1]; +} SPECIFIC_CONFIG; + +typedef struct { + WAVEFORMATEXTENSIBLE Format; + SPECIFIC_CONFIG FormatConfiguration; +} FORMAT_CONFIG; + +typedef struct { + UINT8 FormatsCount; + FORMAT_CONFIG FormatsConfiguration[1]; +} FORMATS_CONFIG; + +typedef struct { + UINT8 DeviceId[16]; + UINT8 DeviceInstanceId; + UINT8 DevicePortId; +} DEVICE_INFO; + +typedef struct { + UINT8 DeviceInfoCount; + DEVICE_INFO DeviceInformation[1]; +} DEVICES_INFO; + +typedef struct { + UINT32 EndpointDescriptorLength; + UINT8 LinkType; + UINT8 InstanceId; + UINT16 HwVendorId; + UINT16 HwDeviceId; + UINT16 HwRevisionId; + UINT32 HwSubsystemId; + UINT8 DeviceType; + UINT8 Direction; + UINT8 VirtualBusId; + SPECIFIC_CONFIG EndpointConfig; + FORMATS_CONFIG FormatsConfig; + DEVICES_INFO DevicesInformation; +} ENDPOINT_DESCRIPTOR; + +// +// High Level Table structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'} + UINT8 EndpointCount; // Actual number of endpoin= ts + ENDPOINT_DESCRIPTOR EndpointDescriptors[1]; + SPECIFIC_CONFIG OedConfiguration; +} NHLT_ACPI_TABLE; + +#pragma pack (pop) + +#endif // _DXE_HDA_NHLT_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h new file mode 100644 index 0000000000..babbf1ce3a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h @@ -0,0 +1,326 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unn= ecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 5; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion, Out, both In and Out, both In = with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 6; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). + This setting is applicable only if GPIO is in GpioMode with input enable= d. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 9; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 8; + /** + GPIO Electrical Configuration + This setting controls pads termination. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 9; + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 4; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 9; + UINT32 RsvdBits : 10; ///< Reserved bits for future extensio= n +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault =3D 0x0 ///< Leave setting unmodified +} GPIO_HARDWARE_DEFAULT; + +/** + GPIO Pad Mode + Refer to GPIO documentation on native functions available for certain pa= d. + If GPIO is set to one of NativeX modes then following settings are not a= pplicable + and can be skipped: + - Interrupt related settings + - Host Software Ownership + - Output/Input enabling/disabling + - Output lock +**/ +typedef enum { + GpioPadModeGpio =3D 0x1, + GpioPadModeNative1 =3D 0x3, + GpioPadModeNative2 =3D 0x5, + GpioPadModeNative3 =3D 0x7, + GpioPadModeNative4 =3D 0x9, + GpioPadModeNative5 =3D 0xB +} GPIO_PAD_MODE; + +/** + Host Software Pad Ownership modes + This setting affects GPIO interrupt status registers. Depending on chose= n ownership + some GPIO Interrupt status register get updated and other masked. + Please refer to EDS for HOSTSW_OWN register description. +**/ +typedef enum { + GpioHostOwnDefault =3D 0x0, ///< Leave ownership value unmodified + /** + Set HOST ownership to ACPI. + Use this setting if pad is not going to be used by GPIO OS driver. + If GPIO is configured to generate SCI/SMI/NMI then this setting must be + used for interrupts to work + **/ + GpioHostOwnAcpi =3D 0x1, + /** + Set HOST ownership to GPIO Driver mode. + Use this setting only if GPIO pad should be controlled by GPIO OS Driver= . + GPIO OS Driver will be able to control the pad if appropriate entry in + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descript= ors) + **/ + GpioHostOwnGpio =3D 0x3 +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault =3D 0x0, ///< Leave pad direction = setting unmodified + GpioDirInOut =3D (0x1 | (0x1 << 3)), ///< Set pad for both out= put and input + GpioDirInInvOut =3D (0x1 | (0x3 << 3)), ///< Set pad for both out= put and input with inversion + GpioDirIn =3D (0x3 | (0x1 << 3)), ///< Set pad for input on= ly + GpioDirInInv =3D (0x3 | (0x3 << 3)), ///< Set pad for input wi= th inversion + GpioDirOut =3D 0x5, ///< Set pad for output o= nly + GpioDirNone =3D 0x7 ///< Disable both output = and input +} GPIO_DIRECTION; + +/** + GPIO Output State + This field is relevant only if output is enabled +**/ +typedef enum { + GpioOutDefault =3D 0x0, ///< Leave output value unmodified + GpioOutLow =3D 0x1, ///< Set output to low + GpioOutHigh =3D 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/** + GPIO interrupt configuration + This setting is applicable only if pad is in GPIO mode and has input ena= bled. + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/S= CI/SMI/NMI) + and how it is triggered (edge or level). Refer to PADCFG_DW0 register de= scription in + EDS for details on this settings. + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to G= pioIntBothEdge + to describe an interrupt e.g. GpioIntApic | GpioIntLevel + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this = pad. + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this = pad. + Not all GPIO are capable of generating an SMI or NMI interrupt. + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as t= his + interrupt cannot be shared and its IRQn number is not configurable. + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt des= criptor + exist then use only trigger type setting (from GpioIntLevel to GpioIntBo= thEdge). + This type of GPIO Driver interrupt doesn't have any additional routing s= etting + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. +**/ + +typedef enum { + GpioIntDefault =3D 0x0, ///< Leave value of interrupt routing= unmodified + GpioIntDis =3D 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI inte= rrupt generation + GpioIntNmi =3D 0x3, ///< Enable NMI interrupt only + GpioIntSmi =3D 0x5, ///< Enable SMI interrupt only + GpioIntSci =3D 0x9, ///< Enable SCI interrupt only + GpioIntApic =3D 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel =3D (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge =3D (0x3 << 5), ///< Set interrupt as edge triggered = (type of edge depends on input inversion) + GpioIntLvlEdgDis =3D (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge =3D (0x7 << 5) ///< Set interrupt as both edge trigg= ered +} GPIO_INT_CONFIG; + +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CON= FIG for interrupt source +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CON= FIG for interrupt type + +/** + GPIO Power Configuration + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) w= hich will + be used to reset certain GPIO settings. + Refer to EDS for settings that are controllable by PadRstCfg. +**/ +typedef enum { + GpioResetDefault =3D 0x00, ///< Leave value of pad reset unmodi= fied + /** + Resume Reset (RSMRST) + GPP: PadRstCfg =3D 00b =3D "Powergood" + GPD: PadRstCfg =3D 11b =3D "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioResumeReset =3D 0x01, + /** + Host Deep Reset + PadRstCfg =3D 01b =3D "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioHostDeepReset =3D 0x03, + /** + Platform Reset (PLTRST) + PadRstCfg =3D 10b =3D "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioPlatformReset =3D 0x05, + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg =3D 00b =3D "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioDswReset =3D 0x07 +} GPIO_RESET_CONFIG; + +/** + GPIO Electrical Configuration + Configuration options for GPIO termination setting +**/ +typedef enum { + GpioTermDefault =3D 0x0, ///< Leave termination setting unmodi= fied + GpioTermNone =3D 0x1, ///< none + GpioTermWpd5K =3D 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K =3D 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K =3D 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K =3D 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K =3D 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K =3D 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K =3D 0x1B, ///< 1kOhm & 2kOhm weak pull-up + /** + Native function controls pads termination + This setting is applicable only to some native modes. + Please check EDS to determine which native functionality + can control pads termination + **/ + GpioTermNative =3D 0x1F +} GPIO_ELECTRICAL_CONFIG; + +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for = GPIO_ELECTRICAL_CONFIG for termination value + +/** + GPIO LockConfiguration + Set GPIO configuration lock and output state lock. + GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. + By default GPIO pads will be locked unless GPIO lib is explicitly + informed that certain pad is to be left unlocked. + Lock settings reset is in Powergood domain. Care must be taken when usin= g this setting + as fields it locks may be reset by a different signal and can be control= led + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library pro= vides + functions which allow to unlock a GPIO pad. If possible each GPIO lib fu= nction will try to unlock + an already locked pad upon request for reconfiguration +**/ +typedef enum { + /** + Perform default action + - if pad is an GPO, lock configuration but leave output unlocked + - if pad is an GPI, lock everything + - if pad is in native, lock everything +**/ + GpioLockDefault =3D 0x0, + GpioPadConfigUnlock =3D 0x3, ///< Leave Pad configuration unlocked + GpioPadConfigLock =3D 0x1, ///< Lock Pad configuration + GpioOutputStateUnlock =3D 0xC, ///< Leave Pad output control unlocked + GpioPadUnlock =3D 0xF, ///< Leave both Pad configuration and ou= tput control unlocked + GpioPadLock =3D 0x5 ///< Lock both Pad configuration and out= put control +} GPIO_LOCK_CONFIG; + +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOC= K_CONFIG for Pad Configuration Lock +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOC= K_CONFIG for Pad Output Lock + +/** + Other GPIO Configuration + GPIO_OTHER_CONFIG is used for less often settings and for future extensi= ons + Supported settings: + - RX raw override to '1' - allows to override input value to '1' + This setting is applicable only if in input mode (both in GPIO and n= ative usage). + The override takes place at the internal pad state directly from buf= fer and before the RXINV. +**/ +typedef enum { + GpioRxRaw1Default =3D 0x0, ///< Use default input override va= lue + GpioRxRaw1Dis =3D 0x1, ///< Don't override input + GpioRxRaw1En =3D 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_= OTHER_CONFIG for RxRaw1 setting + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h new file mode 100644 index 0000000000..524328d3e3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h @@ -0,0 +1,381 @@ +/** @file + GPIO pins, + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_CNL_H_H_ +#define _GPIO_PINS_CNL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// Unique ID used in GpioPad defines +/// +#define GPIO_CNL_H_CHIPSET_ID 0x3 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_CNL_H_GROUP_GPP_A 0x0300 +#define GPIO_CNL_H_GROUP_GPP_B 0x0301 +#define GPIO_CNL_H_GROUP_GPP_C 0x0302 +#define GPIO_CNL_H_GROUP_GPP_D 0x0303 +#define GPIO_CNL_H_GROUP_GPP_E 0x0304 +#define GPIO_CNL_H_GROUP_GPP_F 0x0305 +#define GPIO_CNL_H_GROUP_GPP_G 0x0306 +#define GPIO_CNL_H_GROUP_GPP_H 0x0307 +#define GPIO_CNL_H_GROUP_GPP_I 0x0308 +#define GPIO_CNL_H_GROUP_GPP_J 0x0309 +#define GPIO_CNL_H_GROUP_GPP_K 0x030A +#define GPIO_CNL_H_GROUP_GPD 0x030B +#define GPIO_CNL_H_GROUP_VGPIO 0x030C +#define GPIO_CNL_H_GROUP_SPI 0x030D +#define GPIO_CNL_H_GROUP_AZA 0x030E +#define GPIO_CNL_H_GROUP_CPU 0x030F +#define GPIO_CNL_H_GROUP_JTAG 0x0310 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_CNL_H_GPP_A0 0x03000000 +#define GPIO_CNL_H_GPP_A1 0x03000001 +#define GPIO_CNL_H_GPP_A2 0x03000002 +#define GPIO_CNL_H_GPP_A3 0x03000003 +#define GPIO_CNL_H_GPP_A4 0x03000004 +#define GPIO_CNL_H_GPP_A5 0x03000005 +#define GPIO_CNL_H_GPP_A6 0x03000006 +#define GPIO_CNL_H_GPP_A7 0x03000007 +#define GPIO_CNL_H_GPP_A8 0x03000008 +#define GPIO_CNL_H_GPP_A9 0x03000009 +#define GPIO_CNL_H_GPP_A10 0x0300000A +#define GPIO_CNL_H_GPP_A11 0x0300000B +#define GPIO_CNL_H_GPP_A12 0x0300000C +#define GPIO_CNL_H_GPP_A13 0x0300000D +#define GPIO_CNL_H_GPP_A14 0x0300000E +#define GPIO_CNL_H_GPP_A15 0x0300000F +#define GPIO_CNL_H_GPP_A16 0x03000010 +#define GPIO_CNL_H_GPP_A17 0x03000011 +#define GPIO_CNL_H_GPP_A18 0x03000012 +#define GPIO_CNL_H_GPP_A19 0x03000013 +#define GPIO_CNL_H_GPP_A20 0x03000014 +#define GPIO_CNL_H_GPP_A21 0x03000015 +#define GPIO_CNL_H_GPP_A22 0x03000016 +#define GPIO_CNL_H_GPP_A23 0x03000017 +#define GPIO_CNL_H_ESPI_CLK_LOOPBK 0x03000018 + +#define GPIO_CNL_H_GPP_B0 0x03010000 +#define GPIO_CNL_H_GPP_B1 0x03010001 +#define GPIO_CNL_H_GPP_B2 0x03010002 +#define GPIO_CNL_H_GPP_B3 0x03010003 +#define GPIO_CNL_H_GPP_B4 0x03010004 +#define GPIO_CNL_H_GPP_B5 0x03010005 +#define GPIO_CNL_H_GPP_B6 0x03010006 +#define GPIO_CNL_H_GPP_B7 0x03010007 +#define GPIO_CNL_H_GPP_B8 0x03010008 +#define GPIO_CNL_H_GPP_B9 0x03010009 +#define GPIO_CNL_H_GPP_B10 0x0301000A +#define GPIO_CNL_H_GPP_B11 0x0301000B +#define GPIO_CNL_H_GPP_B12 0x0301000C +#define GPIO_CNL_H_GPP_B13 0x0301000D +#define GPIO_CNL_H_GPP_B14 0x0301000E +#define GPIO_CNL_H_GPP_B15 0x0301000F +#define GPIO_CNL_H_GPP_B16 0x03010010 +#define GPIO_CNL_H_GPP_B17 0x03010011 +#define GPIO_CNL_H_GPP_B18 0x03010012 +#define GPIO_CNL_H_GPP_B19 0x03010013 +#define GPIO_CNL_H_GPP_B20 0x03010014 +#define GPIO_CNL_H_GPP_B21 0x03010015 +#define GPIO_CNL_H_GPP_B22 0x03010016 +#define GPIO_CNL_H_GPP_B23 0x03010017 +#define GPIO_CNL_H_GSPI0_CLK_LOOPBK 0x03010018 +#define GPIO_CNL_H_GSPI1_CLK_LOOPBK 0x03010019 + +#define GPIO_CNL_H_GPP_C0 0x03020000 +#define GPIO_CNL_H_GPP_C1 0x03020001 +#define GPIO_CNL_H_GPP_C2 0x03020002 +#define GPIO_CNL_H_GPP_C3 0x03020003 +#define GPIO_CNL_H_GPP_C4 0x03020004 +#define GPIO_CNL_H_GPP_C5 0x03020005 +#define GPIO_CNL_H_GPP_C6 0x03020006 +#define GPIO_CNL_H_GPP_C7 0x03020007 +#define GPIO_CNL_H_GPP_C8 0x03020008 +#define GPIO_CNL_H_GPP_C9 0x03020009 +#define GPIO_CNL_H_GPP_C10 0x0302000A +#define GPIO_CNL_H_GPP_C11 0x0302000B +#define GPIO_CNL_H_GPP_C12 0x0302000C +#define GPIO_CNL_H_GPP_C13 0x0302000D +#define GPIO_CNL_H_GPP_C14 0x0302000E +#define GPIO_CNL_H_GPP_C15 0x0302000F +#define GPIO_CNL_H_GPP_C16 0x03020010 +#define GPIO_CNL_H_GPP_C17 0x03020011 +#define GPIO_CNL_H_GPP_C18 0x03020012 +#define GPIO_CNL_H_GPP_C19 0x03020013 +#define GPIO_CNL_H_GPP_C20 0x03020014 +#define GPIO_CNL_H_GPP_C21 0x03020015 +#define GPIO_CNL_H_GPP_C22 0x03020016 +#define GPIO_CNL_H_GPP_C23 0x03020017 + +#define GPIO_CNL_H_GPP_D0 0x03030000 +#define GPIO_CNL_H_GPP_D1 0x03030001 +#define GPIO_CNL_H_GPP_D2 0x03030002 +#define GPIO_CNL_H_GPP_D3 0x03030003 +#define GPIO_CNL_H_GPP_D4 0x03030004 +#define GPIO_CNL_H_GPP_D5 0x03030005 +#define GPIO_CNL_H_GPP_D6 0x03030006 +#define GPIO_CNL_H_GPP_D7 0x03030007 +#define GPIO_CNL_H_GPP_D8 0x03030008 +#define GPIO_CNL_H_GPP_D9 0x03030009 +#define GPIO_CNL_H_GPP_D10 0x0303000A +#define GPIO_CNL_H_GPP_D11 0x0303000B +#define GPIO_CNL_H_GPP_D12 0x0303000C +#define GPIO_CNL_H_GPP_D13 0x0303000D +#define GPIO_CNL_H_GPP_D14 0x0303000E +#define GPIO_CNL_H_GPP_D15 0x0303000F +#define GPIO_CNL_H_GPP_D16 0x03030010 +#define GPIO_CNL_H_GPP_D17 0x03030011 +#define GPIO_CNL_H_GPP_D18 0x03030012 +#define GPIO_CNL_H_GPP_D19 0x03030013 +#define GPIO_CNL_H_GPP_D20 0x03030014 +#define GPIO_CNL_H_GPP_D21 0x03030015 +#define GPIO_CNL_H_GPP_D22 0x03030016 +#define GPIO_CNL_H_GPP_D23 0x03030017 + +#define GPIO_CNL_H_GPP_E0 0x03040000 +#define GPIO_CNL_H_GPP_E1 0x03040001 +#define GPIO_CNL_H_GPP_E2 0x03040002 +#define GPIO_CNL_H_GPP_E3 0x03040003 +#define GPIO_CNL_H_GPP_E4 0x03040004 +#define GPIO_CNL_H_GPP_E5 0x03040005 +#define GPIO_CNL_H_GPP_E6 0x03040006 +#define GPIO_CNL_H_GPP_E7 0x03040007 +#define GPIO_CNL_H_GPP_E8 0x03040008 +#define GPIO_CNL_H_GPP_E9 0x03040009 +#define GPIO_CNL_H_GPP_E10 0x0304000A +#define GPIO_CNL_H_GPP_E11 0x0304000B +#define GPIO_CNL_H_GPP_E12 0x0304000C + +#define GPIO_CNL_H_GPP_F0 0x03050000 +#define GPIO_CNL_H_GPP_F1 0x03050001 +#define GPIO_CNL_H_GPP_F2 0x03050002 +#define GPIO_CNL_H_GPP_F3 0x03050003 +#define GPIO_CNL_H_GPP_F4 0x03050004 +#define GPIO_CNL_H_GPP_F5 0x03050005 +#define GPIO_CNL_H_GPP_F6 0x03050006 +#define GPIO_CNL_H_GPP_F7 0x03050007 +#define GPIO_CNL_H_GPP_F8 0x03050008 +#define GPIO_CNL_H_GPP_F9 0x03050009 +#define GPIO_CNL_H_GPP_F10 0x0305000A +#define GPIO_CNL_H_GPP_F11 0x0305000B +#define GPIO_CNL_H_GPP_F12 0x0305000C +#define GPIO_CNL_H_GPP_F13 0x0305000D +#define GPIO_CNL_H_GPP_F14 0x0305000E +#define GPIO_CNL_H_GPP_F15 0x0305000F +#define GPIO_CNL_H_GPP_F16 0x03050010 +#define GPIO_CNL_H_GPP_F17 0x03050011 +#define GPIO_CNL_H_GPP_F18 0x03050012 +#define GPIO_CNL_H_GPP_F19 0x03050013 +#define GPIO_CNL_H_GPP_F20 0x03050014 +#define GPIO_CNL_H_GPP_F21 0x03050015 +#define GPIO_CNL_H_GPP_F22 0x03050016 +#define GPIO_CNL_H_GPP_F23 0x03050017 + +#define GPIO_CNL_H_GPP_G0 0x03060000 +#define GPIO_CNL_H_GPP_G1 0x03060001 +#define GPIO_CNL_H_GPP_G2 0x03060002 +#define GPIO_CNL_H_GPP_G3 0x03060003 +#define GPIO_CNL_H_GPP_G4 0x03060004 +#define GPIO_CNL_H_GPP_G5 0x03060005 +#define GPIO_CNL_H_GPP_G6 0x03060006 +#define GPIO_CNL_H_GPP_G7 0x03060007 + +#define GPIO_CNL_H_GPP_H0 0x03070000 +#define GPIO_CNL_H_GPP_H1 0x03070001 +#define GPIO_CNL_H_GPP_H2 0x03070002 +#define GPIO_CNL_H_GPP_H3 0x03070003 +#define GPIO_CNL_H_GPP_H4 0x03070004 +#define GPIO_CNL_H_GPP_H5 0x03070005 +#define GPIO_CNL_H_GPP_H6 0x03070006 +#define GPIO_CNL_H_GPP_H7 0x03070007 +#define GPIO_CNL_H_GPP_H8 0x03070008 +#define GPIO_CNL_H_GPP_H9 0x03070009 +#define GPIO_CNL_H_GPP_H10 0x0307000A +#define GPIO_CNL_H_GPP_H11 0x0307000B +#define GPIO_CNL_H_GPP_H12 0x0307000C +#define GPIO_CNL_H_GPP_H13 0x0307000D +#define GPIO_CNL_H_GPP_H14 0x0307000E +#define GPIO_CNL_H_GPP_H15 0x0307000F +#define GPIO_CNL_H_GPP_H16 0x03070010 +#define GPIO_CNL_H_GPP_H17 0x03070011 +#define GPIO_CNL_H_GPP_H18 0x03070012 +#define GPIO_CNL_H_GPP_H19 0x03070013 +#define GPIO_CNL_H_GPP_H20 0x03070014 +#define GPIO_CNL_H_GPP_H21 0x03070015 +#define GPIO_CNL_H_GPP_H22 0x03070016 +#define GPIO_CNL_H_GPP_H23 0x03070017 + +#define GPIO_CNL_H_GPP_I0 0x03080000 +#define GPIO_CNL_H_GPP_I1 0x03080001 +#define GPIO_CNL_H_GPP_I2 0x03080002 +#define GPIO_CNL_H_GPP_I3 0x03080003 +#define GPIO_CNL_H_GPP_I4 0x03080004 +#define GPIO_CNL_H_GPP_I5 0x03080005 +#define GPIO_CNL_H_GPP_I6 0x03080006 +#define GPIO_CNL_H_GPP_I7 0x03080007 +#define GPIO_CNL_H_GPP_I8 0x03080008 +#define GPIO_CNL_H_GPP_I9 0x03080009 +#define GPIO_CNL_H_GPP_I10 0x0308000A +#define GPIO_CNL_H_GPP_I11 0x0308000B +#define GPIO_CNL_H_GPP_I12 0x0308000C +#define GPIO_CNL_H_GPP_I13 0x0308000D +#define GPIO_CNL_H_GPP_I14 0x0308000E +#define GPIO_CNL_H_SYS_PWROK 0x0308000F +#define GPIO_CNL_H_SYS_RESETB 0x03080010 +#define GPIO_CNL_H_MLK_RSTB 0x03080011 + +#define GPIO_CNL_H_GPP_J0 0x03090000 +#define GPIO_CNL_H_GPP_J1 0x03090001 +#define GPIO_CNL_H_GPP_J2 0x03090002 +#define GPIO_CNL_H_GPP_J3 0x03090003 +#define GPIO_CNL_H_GPP_J4 0x03090004 +#define GPIO_CNL_H_GPP_J5 0x03090005 +#define GPIO_CNL_H_GPP_J6 0x03090006 +#define GPIO_CNL_H_GPP_J7 0x03090007 +#define GPIO_CNL_H_GPP_J8 0x03090008 +#define GPIO_CNL_H_GPP_J9 0x03090009 +#define GPIO_CNL_H_GPP_J10 0x0309000A +#define GPIO_CNL_H_GPP_J11 0x0309000B + +#define GPIO_CNL_H_GPP_K0 0x030A0000 +#define GPIO_CNL_H_GPP_K1 0x030A0001 +#define GPIO_CNL_H_GPP_K2 0x030A0002 +#define GPIO_CNL_H_GPP_K3 0x030A0003 +#define GPIO_CNL_H_GPP_K4 0x030A0004 +#define GPIO_CNL_H_GPP_K5 0x030A0005 +#define GPIO_CNL_H_GPP_K6 0x030A0006 +#define GPIO_CNL_H_GPP_K7 0x030A0007 +#define GPIO_CNL_H_GPP_K8 0x030A0008 +#define GPIO_CNL_H_GPP_K9 0x030A0009 +#define GPIO_CNL_H_GPP_K10 0x030A000A +#define GPIO_CNL_H_GPP_K11 0x030A000B +#define GPIO_CNL_H_GPP_K12 0x030A000C +#define GPIO_CNL_H_GPP_K13 0x030A000D +#define GPIO_CNL_H_GPP_K14 0x030A000E +#define GPIO_CNL_H_GPP_K15 0x030A000F +#define GPIO_CNL_H_GPP_K16 0x030A0010 +#define GPIO_CNL_H_GPP_K17 0x030A0011 +#define GPIO_CNL_H_GPP_K18 0x030A0012 +#define GPIO_CNL_H_GPP_K19 0x030A0013 +#define GPIO_CNL_H_GPP_K20 0x030A0014 +#define GPIO_CNL_H_GPP_K21 0x030A0015 +#define GPIO_CNL_H_GPP_K22 0x030A0016 +#define GPIO_CNL_H_GPP_K23 0x030A0017 + +#define GPIO_CNL_H_GPD0 0x030B0000 +#define GPIO_CNL_H_GPD1 0x030B0001 +#define GPIO_CNL_H_GPD2 0x030B0002 +#define GPIO_CNL_H_GPD3 0x030B0003 +#define GPIO_CNL_H_GPD4 0x030B0004 +#define GPIO_CNL_H_GPD5 0x030B0005 +#define GPIO_CNL_H_GPD6 0x030B0006 +#define GPIO_CNL_H_GPD7 0x030B0007 +#define GPIO_CNL_H_GPD8 0x030B0008 +#define GPIO_CNL_H_GPD9 0x030B0009 +#define GPIO_CNL_H_GPD10 0x030B000A +#define GPIO_CNL_H_GPD11 0x030B000B +#define GPIO_CNL_H_SLP_LANB 0x030B000C +#define GPIO_CNL_H_SLP_SUSB 0x030B000D +#define GPIO_CNL_H_SLP_WAKEB 0x030B000E +#define GPIO_CNL_H_SLP_DRAM_RESETB 0x030B000F + +#define GPIO_CNL_H_VGPIO0 0x030C0000 +#define GPIO_CNL_H_VGPIO1 0x030C0001 +#define GPIO_CNL_H_VGPIO2 0x030C0002 +#define GPIO_CNL_H_VGPIO3 0x030C0003 +#define GPIO_CNL_H_VGPIO4 0x030C0004 +#define GPIO_CNL_H_VGPIO5 0x030C0005 +#define GPIO_CNL_H_VGPIO6 0x030C0006 +#define GPIO_CNL_H_VGPIO7 0x030C0007 +#define GPIO_CNL_H_VGPIO8 0x030C0008 +#define GPIO_CNL_H_VGPIO9 0x030C0009 +#define GPIO_CNL_H_VGPIO10 0x030C000A +#define GPIO_CNL_H_VGPIO11 0x030C000B +#define GPIO_CNL_H_VGPIO12 0x030C000C +#define GPIO_CNL_H_VGPIO13 0x030C000D +#define GPIO_CNL_H_VGPIO14 0x030C000E +#define GPIO_CNL_H_VGPIO15 0x030C000F +#define GPIO_CNL_H_VGPIO16 0x030C0010 +#define GPIO_CNL_H_VGPIO17 0x030C0011 +#define GPIO_CNL_H_VGPIO18 0x030C0012 +#define GPIO_CNL_H_VGPIO19 0x030C0013 +#define GPIO_CNL_H_VGPIO20 0x030C0014 +#define GPIO_CNL_H_VGPIO21 0x030C0015 +#define GPIO_CNL_H_VGPIO22 0x030C0016 +#define GPIO_CNL_H_VGPIO23 0x030C0017 +#define GPIO_CNL_H_VGPIO24 0x030C0018 +#define GPIO_CNL_H_VGPIO25 0x030C0019 +#define GPIO_CNL_H_VGPIO26 0x030C001A +#define GPIO_CNL_H_VGPIO27 0x030C001B +#define GPIO_CNL_H_VGPIO28 0x030C001C +#define GPIO_CNL_H_VGPIO29 0x030C001D +#define GPIO_CNL_H_VGPIO30 0x030C001E +#define GPIO_CNL_H_VGPIO31 0x030C001F +#define GPIO_CNL_H_VGPIO32 0x030C0020 +#define GPIO_CNL_H_VGPIO33 0x030C0021 +#define GPIO_CNL_H_VGPIO34 0x030C0022 +#define GPIO_CNL_H_VGPIO35 0x030C0023 +#define GPIO_CNL_H_VGPIO36 0x030C0024 +#define GPIO_CNL_H_VGPIO37 0x030C0025 +#define GPIO_CNL_H_VGPIO38 0x030C0026 +#define GPIO_CNL_H_VGPIO39 0x030C0027 + +#define GPIO_CNL_H_SPI0_IO_2 0x030D0000 +#define GPIO_CNL_H_SPI0_IO_3 0x030D0001 +#define GPIO_CNL_H_SPI0_MOSI_IO_0 0x030D0002 +#define GPIO_CNL_H_SPI0_MOSI_IO_1 0x030D0003 +#define GPIO_CNL_H_SPI0_TPM_CSB 0x030D0004 +#define GPIO_CNL_H_SPI0_FLASH_0_CSB 0x030D0005 +#define GPIO_CNL_H_SPI0_FLASH_1_CSB 0x030D0006 +#define GPIO_CNL_H_SPI0_CLK 0x030D0007 +#define GPIO_CNL_H_SPI0_CLK_LOOPBK 0x030D0008 + +#define GPIO_CNL_H_HDA_BCLK 0x030E0000 +#define GPIO_CNL_H_HDA_RSTB 0x030E0001 +#define GPIO_CNL_H_HDA_SYNC 0x030E0002 +#define GPIO_CNL_H_HDA_SDO 0x030E0003 +#define GPIO_CNL_H_HDA_SDI_0 0x030E0004 +#define GPIO_CNL_H_HDA_SDI_1 0x030E0005 +#define GPIO_CNL_H_SSP1_SFRM 0x030E0006 +#define GPIO_CNL_H_SSP1_TXD 0x030E0007 + +#define GPIO_CNL_H_HDACPU_SDI 0x030F0000 +#define GPIO_CNL_H_HDACPU_SDO 0x030F0001 +#define GPIO_CNL_H_HDACPU_SCLK 0x030F0002 +#define GPIO_CNL_H_PM_SYNC 0x030F0003 +#define GPIO_CNL_H_PECI 0x030F0004 +#define GPIO_CNL_H_CPUPWRGD 0x030F0005 +#define GPIO_CNL_H_THRMTRIPB 0x030F0006 +#define GPIO_CNL_H_PLTRST_CPUB 0x030F0007 +#define GPIO_CNL_H_PM_DOWN 0x030F0008 +#define GPIO_CNL_H_TRIGGER_IN 0x030F0009 +#define GPIO_CNL_H_TRIGGER_OUT 0x030F000A + +#define GPIO_CNL_H_JTAG_TDO 0x03100000 +#define GPIO_CNL_H_JTAGX 0x03100001 +#define GPIO_CNL_H_PRDYB 0x03100002 +#define GPIO_CNL_H_PREQB 0x03100003 +#define GPIO_CNL_H_CPU_TRSTB 0x03100004 +#define GPIO_CNL_H_JTAG_TDI 0x03100005 +#define GPIO_CNL_H_JTAG_TMS 0x03100006 +#define GPIO_CNL_H_JTAG_TCK 0x03100007 +#define GPIO_CNL_H_ITP_PMODE 0x03100008 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h new file mode 100644 index 0000000000..9ce5875ca5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h @@ -0,0 +1,340 @@ +/** @file + GPIO pins, + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_CNL_LP_H_ +#define _GPIO_PINS_CNL_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// Unique ID used in GpioPad defines +/// +#define GPIO_CNL_LP_CHIPSET_ID 0x4 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_CNL_LP_GROUP_GPP_A 0x0400 +#define GPIO_CNL_LP_GROUP_GPP_B 0x0401 +#define GPIO_CNL_LP_GROUP_GPP_C 0x0402 +#define GPIO_CNL_LP_GROUP_GPP_D 0x0403 +#define GPIO_CNL_LP_GROUP_GPP_E 0x0404 +#define GPIO_CNL_LP_GROUP_GPP_F 0x0405 +#define GPIO_CNL_LP_GROUP_GPP_G 0x0406 +#define GPIO_CNL_LP_GROUP_GPP_H 0x0407 +#define GPIO_CNL_LP_GROUP_GPD 0x0408 +#define GPIO_CNL_LP_GROUP_VGPIO 0x0409 +#define GPIO_CNL_LP_GROUP_SPI 0x040A +#define GPIO_CNL_LP_GROUP_AZA 0x040B +#define GPIO_CNL_LP_GROUP_CPU 0x040C +#define GPIO_CNL_LP_GROUP_JTAG 0x040D +#define GPIO_CNL_LP_GROUP_HVMOS 0x040E + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_CNL_LP_GPP_A0 0x04000000 +#define GPIO_CNL_LP_GPP_A1 0x04000001 +#define GPIO_CNL_LP_GPP_A2 0x04000002 +#define GPIO_CNL_LP_GPP_A3 0x04000003 +#define GPIO_CNL_LP_GPP_A4 0x04000004 +#define GPIO_CNL_LP_GPP_A5 0x04000005 +#define GPIO_CNL_LP_GPP_A6 0x04000006 +#define GPIO_CNL_LP_GPP_A7 0x04000007 +#define GPIO_CNL_LP_GPP_A8 0x04000008 +#define GPIO_CNL_LP_GPP_A9 0x04000009 +#define GPIO_CNL_LP_GPP_A10 0x0400000A +#define GPIO_CNL_LP_GPP_A11 0x0400000B +#define GPIO_CNL_LP_GPP_A12 0x0400000C +#define GPIO_CNL_LP_GPP_A13 0x0400000D +#define GPIO_CNL_LP_GPP_A14 0x0400000E +#define GPIO_CNL_LP_GPP_A15 0x0400000F +#define GPIO_CNL_LP_GPP_A16 0x04000010 +#define GPIO_CNL_LP_GPP_A17 0x04000011 +#define GPIO_CNL_LP_GPP_A18 0x04000012 +#define GPIO_CNL_LP_GPP_A19 0x04000013 +#define GPIO_CNL_LP_GPP_A20 0x04000014 +#define GPIO_CNL_LP_GPP_A21 0x04000015 +#define GPIO_CNL_LP_GPP_A22 0x04000016 +#define GPIO_CNL_LP_GPP_A23 0x04000017 +#define GPIO_CNL_LP_ESPI_CLK_LOOPBK 0x04000018 + +#define GPIO_CNL_LP_GPP_B0 0x04010000 +#define GPIO_CNL_LP_GPP_B1 0x04010001 +#define GPIO_CNL_LP_GPP_B2 0x04010002 +#define GPIO_CNL_LP_GPP_B3 0x04010003 +#define GPIO_CNL_LP_GPP_B4 0x04010004 +#define GPIO_CNL_LP_GPP_B5 0x04010005 +#define GPIO_CNL_LP_GPP_B6 0x04010006 +#define GPIO_CNL_LP_GPP_B7 0x04010007 +#define GPIO_CNL_LP_GPP_B8 0x04010008 +#define GPIO_CNL_LP_GPP_B9 0x04010009 +#define GPIO_CNL_LP_GPP_B10 0x0401000A +#define GPIO_CNL_LP_GPP_B11 0x0401000B +#define GPIO_CNL_LP_GPP_B12 0x0401000C +#define GPIO_CNL_LP_GPP_B13 0x0401000D +#define GPIO_CNL_LP_GPP_B14 0x0401000E +#define GPIO_CNL_LP_GPP_B15 0x0401000F +#define GPIO_CNL_LP_GPP_B16 0x04010010 +#define GPIO_CNL_LP_GPP_B17 0x04010011 +#define GPIO_CNL_LP_GPP_B18 0x04010012 +#define GPIO_CNL_LP_GPP_B19 0x04010013 +#define GPIO_CNL_LP_GPP_B20 0x04010014 +#define GPIO_CNL_LP_GPP_B21 0x04010015 +#define GPIO_CNL_LP_GPP_B22 0x04010016 +#define GPIO_CNL_LP_GPP_B23 0x04010017 +#define GPIO_CNL_LP_GSPI0_CLK_LOOPBK 0x04010018 +#define GPIO_CNL_LP_GSPI1_CLK_LOOPBK 0x04010019 + +#define GPIO_CNL_LP_GPP_C0 0x04020000 +#define GPIO_CNL_LP_GPP_C1 0x04020001 +#define GPIO_CNL_LP_GPP_C2 0x04020002 +#define GPIO_CNL_LP_GPP_C3 0x04020003 +#define GPIO_CNL_LP_GPP_C4 0x04020004 +#define GPIO_CNL_LP_GPP_C5 0x04020005 +#define GPIO_CNL_LP_GPP_C6 0x04020006 +#define GPIO_CNL_LP_GPP_C7 0x04020007 +#define GPIO_CNL_LP_GPP_C8 0x04020008 +#define GPIO_CNL_LP_GPP_C9 0x04020009 +#define GPIO_CNL_LP_GPP_C10 0x0402000A +#define GPIO_CNL_LP_GPP_C11 0x0402000B +#define GPIO_CNL_LP_GPP_C12 0x0402000C +#define GPIO_CNL_LP_GPP_C13 0x0402000D +#define GPIO_CNL_LP_GPP_C14 0x0402000E +#define GPIO_CNL_LP_GPP_C15 0x0402000F +#define GPIO_CNL_LP_GPP_C16 0x04020010 +#define GPIO_CNL_LP_GPP_C17 0x04020011 +#define GPIO_CNL_LP_GPP_C18 0x04020012 +#define GPIO_CNL_LP_GPP_C19 0x04020013 +#define GPIO_CNL_LP_GPP_C20 0x04020014 +#define GPIO_CNL_LP_GPP_C21 0x04020015 +#define GPIO_CNL_LP_GPP_C22 0x04020016 +#define GPIO_CNL_LP_GPP_C23 0x04020017 + +#define GPIO_CNL_LP_GPP_D0 0x04030000 +#define GPIO_CNL_LP_GPP_D1 0x04030001 +#define GPIO_CNL_LP_GPP_D2 0x04030002 +#define GPIO_CNL_LP_GPP_D3 0x04030003 +#define GPIO_CNL_LP_GPP_D4 0x04030004 +#define GPIO_CNL_LP_GPP_D5 0x04030005 +#define GPIO_CNL_LP_GPP_D6 0x04030006 +#define GPIO_CNL_LP_GPP_D7 0x04030007 +#define GPIO_CNL_LP_GPP_D8 0x04030008 +#define GPIO_CNL_LP_GPP_D9 0x04030009 +#define GPIO_CNL_LP_GPP_D10 0x0403000A +#define GPIO_CNL_LP_GPP_D11 0x0403000B +#define GPIO_CNL_LP_GPP_D12 0x0403000C +#define GPIO_CNL_LP_GPP_D13 0x0403000D +#define GPIO_CNL_LP_GPP_D14 0x0403000E +#define GPIO_CNL_LP_GPP_D15 0x0403000F +#define GPIO_CNL_LP_GPP_D16 0x04030010 +#define GPIO_CNL_LP_GPP_D17 0x04030011 +#define GPIO_CNL_LP_GPP_D18 0x04030012 +#define GPIO_CNL_LP_GPP_D19 0x04030013 +#define GPIO_CNL_LP_GPP_D20 0x04030014 +#define GPIO_CNL_LP_GPP_D21 0x04030015 +#define GPIO_CNL_LP_GPP_D22 0x04030016 +#define GPIO_CNL_LP_GPP_D23 0x04030017 + +#define GPIO_CNL_LP_GPP_E0 0x04040000 +#define GPIO_CNL_LP_GPP_E1 0x04040001 +#define GPIO_CNL_LP_GPP_E2 0x04040002 +#define GPIO_CNL_LP_GPP_E3 0x04040003 +#define GPIO_CNL_LP_GPP_E4 0x04040004 +#define GPIO_CNL_LP_GPP_E5 0x04040005 +#define GPIO_CNL_LP_GPP_E6 0x04040006 +#define GPIO_CNL_LP_GPP_E7 0x04040007 +#define GPIO_CNL_LP_GPP_E8 0x04040008 +#define GPIO_CNL_LP_GPP_E9 0x04040009 +#define GPIO_CNL_LP_GPP_E10 0x0404000A +#define GPIO_CNL_LP_GPP_E11 0x0404000B +#define GPIO_CNL_LP_GPP_E12 0x0404000C +#define GPIO_CNL_LP_GPP_E13 0x0404000D +#define GPIO_CNL_LP_GPP_E14 0x0404000E +#define GPIO_CNL_LP_GPP_E15 0x0404000F +#define GPIO_CNL_LP_GPP_E16 0x04040010 +#define GPIO_CNL_LP_GPP_E17 0x04040011 +#define GPIO_CNL_LP_GPP_E18 0x04040012 +#define GPIO_CNL_LP_GPP_E19 0x04040013 +#define GPIO_CNL_LP_GPP_E20 0x04040014 +#define GPIO_CNL_LP_GPP_E21 0x04040015 +#define GPIO_CNL_LP_GPP_E22 0x04040016 +#define GPIO_CNL_LP_GPP_E23 0x04040017 + +#define GPIO_CNL_LP_GPP_F0 0x04050000 +#define GPIO_CNL_LP_GPP_F1 0x04050001 +#define GPIO_CNL_LP_GPP_F2 0x04050002 +#define GPIO_CNL_LP_GPP_F3 0x04050003 +#define GPIO_CNL_LP_GPP_F4 0x04050004 +#define GPIO_CNL_LP_GPP_F5 0x04050005 +#define GPIO_CNL_LP_GPP_F6 0x04050006 +#define GPIO_CNL_LP_GPP_F7 0x04050007 +#define GPIO_CNL_LP_GPP_F8 0x04050008 +#define GPIO_CNL_LP_GPP_F9 0x04050009 +#define GPIO_CNL_LP_GPP_F10 0x0405000A +#define GPIO_CNL_LP_GPP_F11 0x0405000B +#define GPIO_CNL_LP_GPP_F12 0x0405000C +#define GPIO_CNL_LP_GPP_F13 0x0405000D +#define GPIO_CNL_LP_GPP_F14 0x0405000E +#define GPIO_CNL_LP_GPP_F15 0x0405000F +#define GPIO_CNL_LP_GPP_F16 0x04050010 +#define GPIO_CNL_LP_GPP_F17 0x04050011 +#define GPIO_CNL_LP_GPP_F18 0x04050012 +#define GPIO_CNL_LP_GPP_F19 0x04050013 +#define GPIO_CNL_LP_GPP_F20 0x04050014 +#define GPIO_CNL_LP_GPP_F21 0x04050015 +#define GPIO_CNL_LP_GPP_F22 0x04050016 +#define GPIO_CNL_LP_GPP_F23 0x04050017 + +#define GPIO_CNL_LP_GPP_G0 0x04060000 +#define GPIO_CNL_LP_GPP_G1 0x04060001 +#define GPIO_CNL_LP_GPP_G2 0x04060002 +#define GPIO_CNL_LP_GPP_G3 0x04060003 +#define GPIO_CNL_LP_GPP_G4 0x04060004 +#define GPIO_CNL_LP_GPP_G5 0x04060005 +#define GPIO_CNL_LP_GPP_G6 0x04060006 +#define GPIO_CNL_LP_GPP_G7 0x04060007 + +#define GPIO_CNL_LP_GPP_H0 0x04070000 +#define GPIO_CNL_LP_GPP_H1 0x04070001 +#define GPIO_CNL_LP_GPP_H2 0x04070002 +#define GPIO_CNL_LP_GPP_H3 0x04070003 +#define GPIO_CNL_LP_GPP_H4 0x04070004 +#define GPIO_CNL_LP_GPP_H5 0x04070005 +#define GPIO_CNL_LP_GPP_H6 0x04070006 +#define GPIO_CNL_LP_GPP_H7 0x04070007 +#define GPIO_CNL_LP_GPP_H8 0x04070008 +#define GPIO_CNL_LP_GPP_H9 0x04070009 +#define GPIO_CNL_LP_GPP_H10 0x0407000A +#define GPIO_CNL_LP_GPP_H11 0x0407000B +#define GPIO_CNL_LP_GPP_H12 0x0407000C +#define GPIO_CNL_LP_GPP_H13 0x0407000D +#define GPIO_CNL_LP_GPP_H14 0x0407000E +#define GPIO_CNL_LP_GPP_H15 0x0407000F +#define GPIO_CNL_LP_GPP_H16 0x04070010 +#define GPIO_CNL_LP_GPP_H17 0x04070011 +#define GPIO_CNL_LP_GPP_H18 0x04070012 +#define GPIO_CNL_LP_GPP_H19 0x04070013 +#define GPIO_CNL_LP_GPP_H20 0x04070014 +#define GPIO_CNL_LP_GPP_H21 0x04070015 +#define GPIO_CNL_LP_GPP_H22 0x04070016 +#define GPIO_CNL_LP_GPP_H23 0x04070017 + +#define GPIO_CNL_LP_GPD0 0x04080000 +#define GPIO_CNL_LP_GPD1 0x04080001 +#define GPIO_CNL_LP_GPD2 0x04080002 +#define GPIO_CNL_LP_GPD3 0x04080003 +#define GPIO_CNL_LP_GPD4 0x04080004 +#define GPIO_CNL_LP_GPD5 0x04080005 +#define GPIO_CNL_LP_GPD6 0x04080006 +#define GPIO_CNL_LP_GPD7 0x04080007 +#define GPIO_CNL_LP_GPD8 0x04080008 +#define GPIO_CNL_LP_GPD9 0x04080009 +#define GPIO_CNL_LP_GPD10 0x0408000A +#define GPIO_CNL_LP_GPD11 0x0408000B +#define GPIO_CNL_LP_SLP_LANB 0x0408000C +#define GPIO_CNL_LP_SLP_SUSB 0x0408000D +#define GPIO_CNL_LP_SLP_WAKEB 0x0408000E +#define GPIO_CNL_LP_SLP_DRAM_RESETB 0x0408000F + +#define GPIO_CNL_LP_VGPIO0 0x04090000 +#define GPIO_CNL_LP_VGPIO1 0x04090001 +#define GPIO_CNL_LP_VGPIO2 0x04090002 +#define GPIO_CNL_LP_VGPIO3 0x04090003 +#define GPIO_CNL_LP_VGPIO4 0x04090004 +#define GPIO_CNL_LP_VGPIO5 0x04090005 +#define GPIO_CNL_LP_VGPIO6 0x04090006 +#define GPIO_CNL_LP_VGPIO7 0x04090007 +#define GPIO_CNL_LP_VGPIO8 0x04090008 +#define GPIO_CNL_LP_VGPIO9 0x04090009 +#define GPIO_CNL_LP_VGPIO10 0x0409000A +#define GPIO_CNL_LP_VGPIO11 0x0409000B +#define GPIO_CNL_LP_VGPIO12 0x0409000C +#define GPIO_CNL_LP_VGPIO13 0x0409000D +#define GPIO_CNL_LP_VGPIO14 0x0409000E +#define GPIO_CNL_LP_VGPIO15 0x0409000F +#define GPIO_CNL_LP_VGPIO16 0x04090010 +#define GPIO_CNL_LP_VGPIO17 0x04090011 +#define GPIO_CNL_LP_VGPIO18 0x04090012 +#define GPIO_CNL_LP_VGPIO19 0x04090013 +#define GPIO_CNL_LP_VGPIO20 0x04090014 +#define GPIO_CNL_LP_VGPIO21 0x04090015 +#define GPIO_CNL_LP_VGPIO22 0x04090016 +#define GPIO_CNL_LP_VGPIO23 0x04090017 +#define GPIO_CNL_LP_VGPIO24 0x04090018 +#define GPIO_CNL_LP_VGPIO25 0x04090019 +#define GPIO_CNL_LP_VGPIO26 0x0409001A +#define GPIO_CNL_LP_VGPIO27 0x0409001B +#define GPIO_CNL_LP_VGPIO28 0x0409001C +#define GPIO_CNL_LP_VGPIO29 0x0409001D +#define GPIO_CNL_LP_VGPIO30 0x0409001E +#define GPIO_CNL_LP_VGPIO31 0x0409001F +#define GPIO_CNL_LP_VGPIO32 0x04090020 +#define GPIO_CNL_LP_VGPIO33 0x04090021 +#define GPIO_CNL_LP_VGPIO34 0x04090022 +#define GPIO_CNL_LP_VGPIO35 0x04090023 +#define GPIO_CNL_LP_VGPIO36 0x04090024 +#define GPIO_CNL_LP_VGPIO37 0x04090025 +#define GPIO_CNL_LP_VGPIO38 0x04090026 +#define GPIO_CNL_LP_VGPIO39 0x04090027 + +#define GPIO_CNL_LP_SPI0_IO_2 0x040A0000 +#define GPIO_CNL_LP_SPI0_IO_3 0x040A0001 +#define GPIO_CNL_LP_SPI0_MOSI_IO_0 0x040A0002 +#define GPIO_CNL_LP_SPI0_MOSI_IO_1 0x040A0003 +#define GPIO_CNL_LP_SPI0_TPM_CSB 0x040A0004 +#define GPIO_CNL_LP_SPI0_FLASH_0_CSB 0x040A0005 +#define GPIO_CNL_LP_SPI0_FLASH_1_CSB 0x040A0006 +#define GPIO_CNL_LP_SPI0_CLK 0x040A0007 +#define GPIO_CNL_LP_SPI0_CLK_LOOPBK 0x040A0008 + +#define GPIO_CNL_LP_HDA_BCLK 0x040B0000 +#define GPIO_CNL_LP_HDA_RSTB 0x040B0001 +#define GPIO_CNL_LP_HDA_SYNC 0x040B0002 +#define GPIO_CNL_LP_HDA_SDO 0x040B0003 +#define GPIO_CNL_LP_HDA_SDI_0 0x040B0004 +#define GPIO_CNL_LP_HDA_SDI_1 0x040B0005 +#define GPIO_CNL_LP_SSP1_SFRM 0x040B0006 +#define GPIO_CNL_LP_SSP1_TXD 0x040B0007 + +#define GPIO_CNL_LP_HDACPU_SDI 0x040C0000 +#define GPIO_CNL_LP_HDACPU_SDO 0x040C0001 +#define GPIO_CNL_LP_HDACPU_SCLK 0x040C0002 +#define GPIO_CNL_LP_PM_SYNC 0x040C0003 +#define GPIO_CNL_LP_PECI 0x040C0004 +#define GPIO_CNL_LP_CPUPWRGD 0x040C0005 +#define GPIO_CNL_LP_THRMTRIPB 0x040C0006 +#define GPIO_CNL_LP_PLTRST_CPUB 0x040C0007 +#define GPIO_CNL_LP_PM_DOWN 0x040C0008 +#define GPIO_CNL_LP_TRIGGER_IN 0x040C0009 +#define GPIO_CNL_LP_TRIGGER_OUT 0x040C000A + +#define GPIO_CNL_LP_JTAG_TDO 0x040D0000 +#define GPIO_CNL_LP_JTAGX 0x040D0001 +#define GPIO_CNL_LP_PRDYB 0x040D0002 +#define GPIO_CNL_LP_PREQB 0x040D0003 +#define GPIO_CNL_LP_CPU_TRSTB 0x040D0004 +#define GPIO_CNL_LP_JTAG_TDI 0x040D0005 +#define GPIO_CNL_LP_JTAG_TMS 0x040D0006 +#define GPIO_CNL_LP_JTAG_TCK 0x040D0007 +#define GPIO_CNL_LP_ITP_PMODE 0x040D0008 + +#define GPIO_CNL_LP_HVMOS_L_BKLTEN 0x040E0000 +#define GPIO_CNL_LP_HVMOS_L_BKLTCTL 0x040E0001 +#define GPIO_CNL_LP_HVMOS_L_VDDEN 0x040E0002 +#define GPIO_CNL_LP_HVMOS_SYS_PWROK 0x040E0003 +#define GPIO_CNL_LP_HVMOS_SYS_RESETB 0x040E0004 +#define GPIO_CNL_LP_HVMOS_MLK_RSTB 0x040E0005 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h new file mode 100644 index 0000000000..d3aad4172f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h @@ -0,0 +1,241 @@ +/** @file + GPIO pins + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_SKL_H_H_ +#define _GPIO_PINS_SKL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPD 0x0109 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A +#define GPIO_SKL_H_GPD0 0x01090000 +#define GPIO_SKL_H_GPD1 0x01090001 +#define GPIO_SKL_H_GPD2 0x01090002 +#define GPIO_SKL_H_GPD3 0x01090003 +#define GPIO_SKL_H_GPD4 0x01090004 +#define GPIO_SKL_H_GPD5 0x01090005 +#define GPIO_SKL_H_GPD6 0x01090006 +#define GPIO_SKL_H_GPD7 0x01090007 +#define GPIO_SKL_H_GPD8 0x01090008 +#define GPIO_SKL_H_GPD9 0x01090009 +#define GPIO_SKL_H_GPD10 0x0109000A +#define GPIO_SKL_H_GPD11 0x0109000B + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h new file mode 100644 index 0000000000..8d430afd14 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h @@ -0,0 +1,200 @@ +/** @file + GPIO pins + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_SKL_LP_H_ +#define _GPIO_PINS_SKL_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_LP_GROUP_GPP_A 0x0200 +#define GPIO_SKL_LP_GROUP_GPP_B 0x0201 +#define GPIO_SKL_LP_GROUP_GPP_C 0x0202 +#define GPIO_SKL_LP_GROUP_GPP_D 0x0203 +#define GPIO_SKL_LP_GROUP_GPP_E 0x0204 +#define GPIO_SKL_LP_GROUP_GPP_F 0x0205 +#define GPIO_SKL_LP_GROUP_GPP_G 0x0206 +#define GPIO_SKL_LP_GROUP_GPD 0x0207 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_LP_GPP_A0 0x02000000 +#define GPIO_SKL_LP_GPP_A1 0x02000001 +#define GPIO_SKL_LP_GPP_A2 0x02000002 +#define GPIO_SKL_LP_GPP_A3 0x02000003 +#define GPIO_SKL_LP_GPP_A4 0x02000004 +#define GPIO_SKL_LP_GPP_A5 0x02000005 +#define GPIO_SKL_LP_GPP_A6 0x02000006 +#define GPIO_SKL_LP_GPP_A7 0x02000007 +#define GPIO_SKL_LP_GPP_A8 0x02000008 +#define GPIO_SKL_LP_GPP_A9 0x02000009 +#define GPIO_SKL_LP_GPP_A10 0x0200000A +#define GPIO_SKL_LP_GPP_A11 0x0200000B +#define GPIO_SKL_LP_GPP_A12 0x0200000C +#define GPIO_SKL_LP_GPP_A13 0x0200000D +#define GPIO_SKL_LP_GPP_A14 0x0200000E +#define GPIO_SKL_LP_GPP_A15 0x0200000F +#define GPIO_SKL_LP_GPP_A16 0x02000010 +#define GPIO_SKL_LP_GPP_A17 0x02000011 +#define GPIO_SKL_LP_GPP_A18 0x02000012 +#define GPIO_SKL_LP_GPP_A19 0x02000013 +#define GPIO_SKL_LP_GPP_A20 0x02000014 +#define GPIO_SKL_LP_GPP_A21 0x02000015 +#define GPIO_SKL_LP_GPP_A22 0x02000016 +#define GPIO_SKL_LP_GPP_A23 0x02000017 +#define GPIO_SKL_LP_GPP_B0 0x02010000 +#define GPIO_SKL_LP_GPP_B1 0x02010001 +#define GPIO_SKL_LP_GPP_B2 0x02010002 +#define GPIO_SKL_LP_GPP_B3 0x02010003 +#define GPIO_SKL_LP_GPP_B4 0x02010004 +#define GPIO_SKL_LP_GPP_B5 0x02010005 +#define GPIO_SKL_LP_GPP_B6 0x02010006 +#define GPIO_SKL_LP_GPP_B7 0x02010007 +#define GPIO_SKL_LP_GPP_B8 0x02010008 +#define GPIO_SKL_LP_GPP_B9 0x02010009 +#define GPIO_SKL_LP_GPP_B10 0x0201000A +#define GPIO_SKL_LP_GPP_B11 0x0201000B +#define GPIO_SKL_LP_GPP_B12 0x0201000C +#define GPIO_SKL_LP_GPP_B13 0x0201000D +#define GPIO_SKL_LP_GPP_B14 0x0201000E +#define GPIO_SKL_LP_GPP_B15 0x0201000F +#define GPIO_SKL_LP_GPP_B16 0x02010010 +#define GPIO_SKL_LP_GPP_B17 0x02010011 +#define GPIO_SKL_LP_GPP_B18 0x02010012 +#define GPIO_SKL_LP_GPP_B19 0x02010013 +#define GPIO_SKL_LP_GPP_B20 0x02010014 +#define GPIO_SKL_LP_GPP_B21 0x02010015 +#define GPIO_SKL_LP_GPP_B22 0x02010016 +#define GPIO_SKL_LP_GPP_B23 0x02010017 +#define GPIO_SKL_LP_GPP_C0 0x02020000 +#define GPIO_SKL_LP_GPP_C1 0x02020001 +#define GPIO_SKL_LP_GPP_C2 0x02020002 +#define GPIO_SKL_LP_GPP_C3 0x02020003 +#define GPIO_SKL_LP_GPP_C4 0x02020004 +#define GPIO_SKL_LP_GPP_C5 0x02020005 +#define GPIO_SKL_LP_GPP_C6 0x02020006 +#define GPIO_SKL_LP_GPP_C7 0x02020007 +#define GPIO_SKL_LP_GPP_C8 0x02020008 +#define GPIO_SKL_LP_GPP_C9 0x02020009 +#define GPIO_SKL_LP_GPP_C10 0x0202000A +#define GPIO_SKL_LP_GPP_C11 0x0202000B +#define GPIO_SKL_LP_GPP_C12 0x0202000C +#define GPIO_SKL_LP_GPP_C13 0x0202000D +#define GPIO_SKL_LP_GPP_C14 0x0202000E +#define GPIO_SKL_LP_GPP_C15 0x0202000F +#define GPIO_SKL_LP_GPP_C16 0x02020010 +#define GPIO_SKL_LP_GPP_C17 0x02020011 +#define GPIO_SKL_LP_GPP_C18 0x02020012 +#define GPIO_SKL_LP_GPP_C19 0x02020013 +#define GPIO_SKL_LP_GPP_C20 0x02020014 +#define GPIO_SKL_LP_GPP_C21 0x02020015 +#define GPIO_SKL_LP_GPP_C22 0x02020016 +#define GPIO_SKL_LP_GPP_C23 0x02020017 +#define GPIO_SKL_LP_GPP_D0 0x02030000 +#define GPIO_SKL_LP_GPP_D1 0x02030001 +#define GPIO_SKL_LP_GPP_D2 0x02030002 +#define GPIO_SKL_LP_GPP_D3 0x02030003 +#define GPIO_SKL_LP_GPP_D4 0x02030004 +#define GPIO_SKL_LP_GPP_D5 0x02030005 +#define GPIO_SKL_LP_GPP_D6 0x02030006 +#define GPIO_SKL_LP_GPP_D7 0x02030007 +#define GPIO_SKL_LP_GPP_D8 0x02030008 +#define GPIO_SKL_LP_GPP_D9 0x02030009 +#define GPIO_SKL_LP_GPP_D10 0x0203000A +#define GPIO_SKL_LP_GPP_D11 0x0203000B +#define GPIO_SKL_LP_GPP_D12 0x0203000C +#define GPIO_SKL_LP_GPP_D13 0x0203000D +#define GPIO_SKL_LP_GPP_D14 0x0203000E +#define GPIO_SKL_LP_GPP_D15 0x0203000F +#define GPIO_SKL_LP_GPP_D16 0x02030010 +#define GPIO_SKL_LP_GPP_D17 0x02030011 +#define GPIO_SKL_LP_GPP_D18 0x02030012 +#define GPIO_SKL_LP_GPP_D19 0x02030013 +#define GPIO_SKL_LP_GPP_D20 0x02030014 +#define GPIO_SKL_LP_GPP_D21 0x02030015 +#define GPIO_SKL_LP_GPP_D22 0x02030016 +#define GPIO_SKL_LP_GPP_D23 0x02030017 +#define GPIO_SKL_LP_GPP_E0 0x02040000 +#define GPIO_SKL_LP_GPP_E1 0x02040001 +#define GPIO_SKL_LP_GPP_E2 0x02040002 +#define GPIO_SKL_LP_GPP_E3 0x02040003 +#define GPIO_SKL_LP_GPP_E4 0x02040004 +#define GPIO_SKL_LP_GPP_E5 0x02040005 +#define GPIO_SKL_LP_GPP_E6 0x02040006 +#define GPIO_SKL_LP_GPP_E7 0x02040007 +#define GPIO_SKL_LP_GPP_E8 0x02040008 +#define GPIO_SKL_LP_GPP_E9 0x02040009 +#define GPIO_SKL_LP_GPP_E10 0x0204000A +#define GPIO_SKL_LP_GPP_E11 0x0204000B +#define GPIO_SKL_LP_GPP_E12 0x0204000C +#define GPIO_SKL_LP_GPP_E13 0x0204000D +#define GPIO_SKL_LP_GPP_E14 0x0204000E +#define GPIO_SKL_LP_GPP_E15 0x0204000F +#define GPIO_SKL_LP_GPP_E16 0x02040010 +#define GPIO_SKL_LP_GPP_E17 0x02040011 +#define GPIO_SKL_LP_GPP_E18 0x02040012 +#define GPIO_SKL_LP_GPP_E19 0x02040013 +#define GPIO_SKL_LP_GPP_E20 0x02040014 +#define GPIO_SKL_LP_GPP_E21 0x02040015 +#define GPIO_SKL_LP_GPP_E22 0x02040016 +#define GPIO_SKL_LP_GPP_E23 0x02040017 +#define GPIO_SKL_LP_GPP_F0 0x02050000 +#define GPIO_SKL_LP_GPP_F1 0x02050001 +#define GPIO_SKL_LP_GPP_F2 0x02050002 +#define GPIO_SKL_LP_GPP_F3 0x02050003 +#define GPIO_SKL_LP_GPP_F4 0x02050004 +#define GPIO_SKL_LP_GPP_F5 0x02050005 +#define GPIO_SKL_LP_GPP_F6 0x02050006 +#define GPIO_SKL_LP_GPP_F7 0x02050007 +#define GPIO_SKL_LP_GPP_F8 0x02050008 +#define GPIO_SKL_LP_GPP_F9 0x02050009 +#define GPIO_SKL_LP_GPP_F10 0x0205000A +#define GPIO_SKL_LP_GPP_F11 0x0205000B +#define GPIO_SKL_LP_GPP_F12 0x0205000C +#define GPIO_SKL_LP_GPP_F13 0x0205000D +#define GPIO_SKL_LP_GPP_F14 0x0205000E +#define GPIO_SKL_LP_GPP_F15 0x0205000F +#define GPIO_SKL_LP_GPP_F16 0x02050010 +#define GPIO_SKL_LP_GPP_F17 0x02050011 +#define GPIO_SKL_LP_GPP_F18 0x02050012 +#define GPIO_SKL_LP_GPP_F19 0x02050013 +#define GPIO_SKL_LP_GPP_F20 0x02050014 +#define GPIO_SKL_LP_GPP_F21 0x02050015 +#define GPIO_SKL_LP_GPP_F22 0x02050016 +#define GPIO_SKL_LP_GPP_F23 0x02050017 +#define GPIO_SKL_LP_GPP_G0 0x02060000 +#define GPIO_SKL_LP_GPP_G1 0x02060001 +#define GPIO_SKL_LP_GPP_G2 0x02060002 +#define GPIO_SKL_LP_GPP_G3 0x02060003 +#define GPIO_SKL_LP_GPP_G4 0x02060004 +#define GPIO_SKL_LP_GPP_G5 0x02060005 +#define GPIO_SKL_LP_GPP_G6 0x02060006 +#define GPIO_SKL_LP_GPP_G7 0x02060007 +#define GPIO_SKL_LP_GPD0 0x02070000 +#define GPIO_SKL_LP_GPD1 0x02070001 +#define GPIO_SKL_LP_GPD2 0x02070002 +#define GPIO_SKL_LP_GPD3 0x02070003 +#define GPIO_SKL_LP_GPD4 0x02070004 +#define GPIO_SKL_LP_GPD5 0x02070005 +#define GPIO_SKL_LP_GPD6 0x02070006 +#define GPIO_SKL_LP_GPD7 0x02070007 +#define GPIO_SKL_LP_GPD8 0x02070008 +#define GPIO_SKL_LP_GPD9 0x02070009 +#define GPIO_SKL_LP_GPD10 0x0207000A +#define GPIO_SKL_LP_GPD11 0x0207000B + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h b/S= ilicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h new file mode 100644 index 0000000000..6730b3baf9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h @@ -0,0 +1,54 @@ +/** @file + Macros that simplify accessing PCH devices's PCI registers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchLimits.h" +#include "PchReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + +// +// Include device register definitions +// +#include "PcieRegs.h" +#include "Register/PchRegs.h" +#include "Register/PchRegsPcr.h" +#include "Register/PchRegsP2sb.h" +#include "Register/PchRegsHda.h" +#include "Register/PchRegsHsio.h" +#include "Register/PchRegsLan.h" +#include "Register/PchRegsLpc.h" +#include "Register/PchRegsPmc.h" +#include "Register/PchRegsPcie.h" +#include "Register/PchRegsSata.h" +#include "Register/PchRegsSmbus.h" +#include "Register/PchRegsSpi.h" +#include +#include "Register/PchRegsGpio.h" +#include "Register/PchRegsThermalCnl.h" +#include "Register/PchRegsGpioCnl.h" +#include "Register/PchRegsSerialIoCnl.h" +#include "Register/PchRegsSerialIo.h" +#include "Register/PchRegsTraceHub.h" +#include "Register/PchRegsScsCnl.h" +#include "Register/PchRegsIsh.h" +#include "Register/PchRegsDmi.h" +#include "Register/PchRegsItss.h" +#include "Register/PchRegsPsth.h" +#include "Register/PchRegsFia.h" +#include "Register/PchRegsDci.h" + +#endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h b/Sili= con/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h new file mode 100644 index 0000000000..3b8e5147db --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h @@ -0,0 +1,38 @@ +/** @file + Header file for HD Audio configuration. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_H_ +#define _PCH_HDA_H_ + + +enum PCH_HDAUDIO_DMIC_TYPE { + PchHdaDmicDisabled =3D 0, + PchHdaDmic2chArray =3D 1, + PchHdaDmic4chArray =3D 2, + PchHdaDmic1chArray =3D 3 +}; + +typedef enum { + PchHdaLinkFreq6MHz =3D 0, + PchHdaLinkFreq12MHz =3D 1, + PchHdaLinkFreq24MHz =3D 2, + PchHdaLinkFreq48MHz =3D 3, + PchHdaLinkFreq96MHz =3D 4, + PchHdaLinkFreqInvalid +} PCH_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + PchHdaIDispMode2T =3D 0, + PchHdaIDispMode1T =3D 1, + PchHdaIDispMode4T =3D 2, + PchHdaIDispMode8T =3D 3, + PchHdaIDispMode16T =3D 4, + PchHdaIDispTModeInvalid +} PCH_HDAUDIO_IDISP_TMODE; + +#endif // _PCH_HDA_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h new file mode 100644 index 0000000000..743dd84b2b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h @@ -0,0 +1,80 @@ +/** @file + This file contains definitions of PCH Info HOB. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_INFO_HOB_H_ +#define _PCH_INFO_HOB_H_ + +extern EFI_GUID gPchInfoHobGuid; + +#define PCH_INFO_HOB_REVISION 2 + +#pragma pack (push,1) +/** + This structure is used to provide the information of PCH controller. + + Revision 1: + - Initial version. + Revision 2: + - Add CridSupport, CridOrgRid, and CridNewRid. + Revision 3: + - Added LaneReversal Field +**/ +typedef struct { + /** + This member specifies the revision of the PCH Info HOB. This field is = used + to indicate backwards compatible changes to the protocol. Platform cod= e that + consumes this protocol must read the correct revision value to correct= ly interpret + the content of the protocol fields. + **/ + UINT8 Revision; + UINT8 PcieControllerCfg[6]; + + /** + GbE over PCIe port number when GbE is enabled + >0 - Root port number (1-based) + 0 - GbE over PCIe disabled + This information needs to be passed through HOB as FIA registers + are not accessible with POSTBOOT_SAI + **/ + UINT8 GbePciePortNumber; + UINT32 PciePortFuses; + /** + Bit map for PCIe Root Port Lane setting. If bit is set it means that + corresponding Root Port has its lane enabled. + BIT0 - RP0, BIT1 - RP1, ... + This information needs to be passed through HOB as FIA registers + are not accessible with POSTBOOT_SAI + **/ + UINT32 PciePortLaneEnabled; + /** + Publish Hpet BDF and IoApic BDF information for VTD. + **/ + UINT32 HpetBusNum : 8; + UINT32 HpetDevNum : 5; + UINT32 HpetFuncNum : 3; + UINT32 IoApicBusNum : 8; + UINT32 IoApicDevNum : 5; + UINT32 IoApicFuncNum : 3; + /** + Publish the CRID information. + **/ + UINT32 CridOrgRid : 8; + UINT32 CridNewRid : 8; + UINT32 CridSupport : 1; + UINT32 Rsvdbits : 15; + /** + This member specifies if lane reversal is enabled on the specific + Pcie Root port controller. + **/ + UINT8 PcieControllerLaneReversal[6]; +} PCH_INFO_HOB; + +#pragma pack (pop) + +#endif // _PCH_INFO_HOB_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h b/S= ilicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h new file mode 100644 index 0000000000..929f9f02d4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h @@ -0,0 +1,53 @@ +/** @file + Build time limits of PCH resources. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LIMITS_H_ +#define _PCH_LIMITS_H_ + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS 24 +#define PCH_MAX_PCIE_CONTROLLERS 6 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS 16 +// +// RST PCIe Storage Cycle Router limits +// +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 + +// +// SATA limits +// +#define PCH_MAX_SATA_CONTROLLERS 3 +#define PCH_MAX_SATA_PORTS 8 + +// +// USB limits +// +#define PCH_MAX_USB2_PORTS 16 +#define PCH_MAX_USB3_PORTS 10 + +// +// SerialIo limits +// +#define PCH_MAX_SERIALIO_CONTROLLERS 12 +#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 6 +#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 3 +#define PCH_MAX_SERIALIO_UART_CONTROLLERS 3 + +// +// Number of eSPI slaves +// +#define PCH_MAX_ESPI_SLAVES 2 + +#endif // _PCH_LIMITS_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageD= etectHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageD= etectHob.h new file mode 100644 index 0000000000..1097e58332 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageDetectHo= b.h @@ -0,0 +1,47 @@ +/** @file + Definitions required to create PcieStorageInfoHob + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIE_STORAGE_DETECT_HOB_ +#define _PCH_PCIE_STORAGE_DETECT_HOB_ + +#include "PchLimits.h" + +#define PCIE_STORAGE_INFO_HOB_REVISION 1 + +extern EFI_GUID gPchPcieStorageDetectHobGuid; + +typedef enum { + RstLinkWidthX1 =3D 1, + RstLinkWidthX2 =3D 2, + RstLinkWidthX4 =3D 4 +} RST_LINK_WIDTH; + +// +// Stores information about connected PCIe storage devices used later by = BIOS setup and RST remapping +// +#pragma pack(1) +typedef struct { + UINT8 Revision; + + // + // Stores the number of root ports occupied by a connected storage devic= e, values from RST_LINK_WIDTH are supported + // + UINT8 PcieStorageLinkWidth[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // Programming interface value for a given device, 0x02 - NVMe or RAID, = 0x1 - AHCI storage, 0x0 - no device connected + // + UINT8 PcieStorageProgrammingInterface[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // Stores information about cycle router number under a given PCIe contr= oller + // + UINT8 RstCycleRouterMap[PCH_MAX_PCIE_CONTROLLERS]; +} PCIE_STORAGE_INFO_HOB; +#pragma pack() +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..213ca91d2d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h @@ -0,0 +1,47 @@ +/** @file + PCH configuration based on PCH policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include "ConfigBlock/PcieRpConfig.h" +#include "ConfigBlock/SataConfig.h" +#include "ConfigBlock/IoApicConfig.h" +#include "ConfigBlock/DmiConfig.h" +#include "ConfigBlock/FlashProtectionConfig.h" +#include "ConfigBlock/HdAudioConfig.h" +#include "ConfigBlock/InterruptConfig.h" +#include "ConfigBlock/IshConfig.h" +#include "ConfigBlock/LanConfig.h" +#include "ConfigBlock/LockDownConfig.h" +#include "ConfigBlock/P2sbConfig.h" +#include "ConfigBlock/PmConfig.h" +#include "ConfigBlock/ScsConfig.h" +#include "ConfigBlock/SerialIoConfig.h" +#include "ConfigBlock/SerialIrqConfig.h" +#include "ConfigBlock/ThermalConfig.h" +#include "ConfigBlock/EspiConfig.h" +#include "ConfigBlock/CnviConfig.h" + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicy= Common.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCo= mmon.h new file mode 100644 index 0000000000..37b2301770 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.= h @@ -0,0 +1,59 @@ +/** @file + PCH configuration based on PCH policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PREMEM_POLICY_COMMON_H_ +#define _PCH_PREMEM_POLICY_COMMON_H_ + +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include "ConfigBlock/DciConfig.h" +#include "ConfigBlock/WatchDogConfig.h" +#include "ConfigBlock/PchTraceHubConfig.h" +#include "ConfigBlock/SmbusConfig.h" +#include "ConfigBlock/LpcConfig.h" +#include "ConfigBlock/HsioPcieConfig.h" +#include "ConfigBlock/HsioSataConfig.h" +#include "ConfigBlock/HsioConfig.h" + +#pragma pack (push,1) + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an upd= ate in the revision number +**/ +#define PCH_PREMEM_POLICY_REVISION 1 + +/** + PCH Policy PPI\n + All PCH config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +typedef struct _PCH_PREMEM_POLICY { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +} PCH_PREMEM_POLICY; + +#pragma pack (pop) + +#endif // _PCH_PREMEM_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedReso= urces.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResourc= es.h new file mode 100644 index 0000000000..f5106ffebb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResources.h @@ -0,0 +1,53 @@ +/** @file + PCH preserved MMIO resource definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ + +/** + + Detailed recommended static allocation + +-----------------------------------------------------------------------= --+ + | = | + | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF = | + +-----------------------------------------------------------------------= --+ + | Size | Start | End | Usage = | + | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode = | + | 488 KB | 0xFE036000 | 0xFE0AFFFF | Unused = | + | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR = | + | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR = | + | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused = | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR = | + | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + +-----------------------------------------------------------------------= --+ +**/ +#define PCH_PRESERVED_BASE_ADDRESS 0xFC800000 ///< Pch preserved = MMIO base address +#define PCH_PRESERVED_MMIO_SIZE 0x02000000 ///< 28MB +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO bas= e address +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO = base address +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO = base address +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO = base address +#define PCH_SERIAL_IO_MMIO_SIZE 0x00016000 ///< 88KB +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB M= MIO base address +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///< TraceHub FW MM= IO base address +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00200000 ///< 2MB +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp= address for misc usage, +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatfor= mSpecific.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatfo= rmSpecific.h new file mode 100644 index 0000000000..8e1495d16f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatformSpecif= ic.h @@ -0,0 +1,23 @@ +/** @file + PCH Reset Platform Specific definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_ +#define _PCH_RESET_PLATFORM_SPECIFIC_H_ + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof (PCH_PLATFORM_SPECIFI= C_RESET_STRING) / sizeof (UINT16)) + +extern EFI_GUID gPchGlobalResetGuid; + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + +#endif // _PCH_RESET_PLATFORM_SPECIFIC_H_ + --=20 2.16.2.windows.1