From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by groups.io with SMTP; Fri, 16 Aug 2019 17:51:17 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:51:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="179829676" Received: from orsmsx108.amr.corp.intel.com ([10.22.240.6]) by orsmga003.jf.intel.com with ESMTP; 16 Aug 2019 17:51:17 -0700 Received: from orsmsx122.amr.corp.intel.com (10.22.225.227) by ORSMSX108.amr.corp.intel.com (10.22.240.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 16 Aug 2019 17:51:17 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.96]) by ORSMSX122.amr.corp.intel.com ([169.254.11.139]) with mapi id 14.03.0439.000; Fri, 16 Aug 2019 17:51:16 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Include headers Thread-Topic: [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Include headers Thread-Index: AQHVVJEQK0Esc0SHWkmBjw8zcmQQkab+goZw Date: Sat, 17 Aug 2019 00:51:16 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE12857@ORSMSX114.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-4-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-4-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGU0ZmQ1NGYtNmM2Mi00NzgyLWFjOTItYzQzNTYyNjA5ODM2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRTNwTzQyWXBnY3FoTEVPWmI3bW80Q2JadTNXT1o4S3dlM28rc0hDMHg4QllhSHlsU0lBMnNtYXRxQUF6NnZNdiJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:15 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Gao, Liming ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Incl= ude headers REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files common to ME modules. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h | = 124 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/D= xeMePolicyLib.h | 59 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Inclu= de/Library/PeiMePolicyLib.h | 87 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h | = 172 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h | = 17 ++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h | = 19 +++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h | = 41 +++++ 7 files changed, 519 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePe= iConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePei= Config.h new file mode 100644 index 0000000000..102fb43bd1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiCon +++ fig.h @@ -0,0 +1,124 @@ +/** @file + ME config block for PEI phase + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _ME_PEI_CONFIG_H_ +#define _ME_PEI_CONFIG_H_ + +#include + +#define ME_PEI_PREMEM_CONFIG_REVISION 2 extern EFI_GUID=20 +gMePeiPreMemConfigGuid; + +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif + +#pragma pack (push,1) + +/** + ME Pei Pre-Memory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Change DidInitStat bit width. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 HeciTimeouts : 1; ///< 0: Disable; 1: Ena= ble - HECI Send/Receive Timeouts. + /** + (Test) + 0: Disabled + 1: ME DID init stat 0 - Success + 2: ME DID init stat 1 - No Memory in Channels + 3: ME DID init stat 2 - Memory Init Error + **/ + UINT32 DidInitStat : 2; + /** + (Test) + 0: Set to 0 to enable polling for CPU replacement + 1: Set to 1 will disable polling for CPU replacement + **/ + UINT32 DisableCpuReplacedPolling : 1; + UINT32 SendDidMsg : 1; ///< (Test) 0: Disa= ble; 1: Enable - Enable/Disable to send DID message. + /** + (Test) + 0: Set to 0 to enable retry mechanism for HECI APIs + 1: Set to 1 will disable retry mechanism for HECI APIs + **/ + UINT32 DisableHeciRetry : 1; + /** + (Test) + 0: ME BIOS will check each messages before sending + 1: ME BIOS always sends messages without checking + **/ + UINT32 DisableMessageCheck : 1; + /** + (Test) + The SkipMbpHob policy determines whether ME BIOS Payload data will be = requested during boot + in a MBP message. If set to 1, BIOS will send the MBP message with Ski= pMbp flag + set causing CSME to respond with MKHI header only and no MBP data + 0: ME BIOS will keep MBP and create HOB for MBP data + 1: ME BIOS will skip MBP data + **/ + UINT32 SkipMbpHob : 1; + UINT32 HeciCommunication2 : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable HECI2. + UINT32 KtDeviceEnable : 1; ///< (Test) 0: Disa= ble; 1: Enable - Enable/Disable Kt Device. + UINT32 RsvdBits : 22; ///< Reserved for future u= se & Config block alignment + UINT32 Heci1BarAddress; ///< HECI1 BAR address. + UINT32 Heci2BarAddress; ///< HECI2 BAR address. + UINT32 Heci3BarAddress; ///< HECI3 BAR address. +} ME_PEI_PREMEM_CONFIG; +#pragma pack (pop) + + +#define ME_PEI_CONFIG_REVISION 2 +extern EFI_GUID gMePeiConfigGuid; + +#pragma pack (push,1) + +/** + ME Pei Post-Memory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Add MctpBroadcastCycle test setting. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send = in PEI; 2: Send in DXE - Send EOP at specific phase. + /** + HECI3 state from Mbp for reference in S3 path only + 0: Disabled; 1: Enabled + **/ + UINT32 Heci3Enabled : 1; + UINT32 DisableD0I3SettingForHeci : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable D0i3 for HECI. + /** + Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send Me= UnconfigOnRtcClearDisable Msg with parameter 0. + It will cause ME to unconfig if RTC is cleared. + - 0: Disable + - 1: Enable + - 2: Cmos is clear, status unkonwn + - 3: Reserved + **/ + UINT32 MeUnconfigOnRtcClear : 2; + UINT32 MctpBroadcastCycle : 1; ///< (Test) 0: = Disable; 1: Enable - Program registers for MCTP Cycle. + UINT32 RsvdBits : 25; ///< Reserved for future = use & Config block alignment +} ME_PEI_CONFIG; + +#pragma pack (pop) + +#endif // _ME_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePol= icyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolic= yLib.h new file mode 100644 index 0000000000..46f7f86021 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyL +++ ib.h @@ -0,0 +1,59 @@ +/** @file + Prototype of the DxeMePolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _DXE_ME_POLICY_LIB_H_ +#define _DXE_ME_POLICY_LIB_H_ + +#include + +/** + This function prints the ME DXE phase policy. + + @param[in] DxeMePolicy - ME DXE Policy protocol **/ VOID=20 +MePrintPolicyProtocol ( + IN ME_POLICY_PROTOCOL *DxeMePolicy + ); + +/** + MeCreatePolicyDefaults creates the default setting of ME Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[in, out] DxeMePolicy The pointer to get ME Policy proto= col instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +MeCreatePolicyDefaults ( + IN OUT ME_POLICY_PROTOCOL **DxeMePolicy + ); + +/** + MeInstallPolicyProtocol installs ME Policy. + While installed, RC assumes the Policy is ready and finalized. So=20 +please update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] DxeMePolicy The pointer to ME Policy Protocol = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +MeInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN ME_POLICY_PROTOCOL *DxeMePolicy + ); + +#endif // _DXE_ME_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePol= icyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolic= yLib.h new file mode 100644 index 0000000000..5db4714346 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyL +++ ib.h @@ -0,0 +1,87 @@ +/** @file + Prototype of the MePolicyLibPei library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PEI_ME_POLICY_LIB_H_ +#define _PEI_ME_POLICY_LIB_H_ + +#include +#include + +/** + This function prints the PEI phase PreMem policy. + + @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI insta= nce +**/ +VOID +EFIAPI +MePrintPolicyPpiPreMem ( + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi + ); + +/** + This function prints the PEI phase policy. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +MePrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get Me config block table total size. + + @retval Size of Me config block table +**/ +UINT16 +EFIAPI +MeGetConfigBlockTotalSize ( + VOID + ); + +/** + Get ME config block table total size. + + @retval Size of ME config block table +**/ +UINT16 +EFIAPI +MeGetConfigBlockTotalSizePreMem ( + VOID + ); + +/** + MeAddConfigBlocksPreMem add all ME config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add ME config block= s + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +MeAddConfigBlocksPreMem ( + IN VOID *ConfigBlockTableAddress + ); + +/** + MeAddConfigBlocks add all ME config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add ME config block= s + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +MeAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _PEI_ME_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h b/Si= licon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h new file mode 100644 index 0000000000..f29f9bc8bd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h @@ -0,0 +1,172 @@ +/** @file + Chipset definition for ME Devices. + + Conventions: + + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - Registers / bits that are different between PCH generations are denote= d by + "_ME_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "PCH_H_" in reg= ister/bit names. + Registers / bits that are specific to PCH-LP denoted by "PCH_LP_" in r= egister/bit names. + e.g., "_ME_PCH_H_", "_ME_PCH_LP_" + Registers / bits names without _PCH_H_ or _PCH_LP_ apply for both H an= d LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be= just named + as "_ME_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _ME_CHIPSET_H_ +#define _ME_CHIPSET_H_ + +#define ME_SEGMENT 0 +#define ME_BUS 0 +#define ME_DEVICE_NUMBER 22 +#define HECI_MIN_FUNC 0 +#define HECI_MAX_FUNC 5 + +#define HECI_FUNCTION_NUMBER 0x00 +#define HECI2_FUNCTION_NUMBER 0x01 +#define IDER_FUNCTION_NUMBER 0x02 +#define SOL_FUNCTION_NUMBER 0x03 +#define HECI3_FUNCTION_NUMBER 0x04 +#define HECI4_FUNCTION_NUMBER 0x05 + +#define IDER_BUS_NUMBER ME_BUS +#define IDER_DEVICE_NUMBER ME_DEVICE_NUMBER +#define SOL_BUS_NUMBER ME_BUS +#define SOL_DEVICE_NUMBER ME_DEVICE_NUMBER + + /// +/// Convert to HECI# defined in BWG from Fun# /// #define=20 +HECI_NAME_MAP(a) ((a < 2) ? (a + 1) : (a - 1)) + +/// +/// ME-related Chipset Definition +/// +#define HeciEnable() MeDeviceControl (HECI1, Enabled); +#define Heci2Enable() MeDeviceControl (HECI2, Enabled); +#define Heci3Enable() MeDeviceControl (HECI3, Enabled); +#define Heci4Enable() MeDeviceControl (HECI4, Enabled); +#define IderEnable() MeDeviceControl (IDER, Enabled); +#define SolEnable() MeDeviceControl (SOL, Enabled); + +#define HeciDisable() MeDeviceControl (HECI1, Disabled); +#define Heci2Disable() MeDeviceControl (HECI2, Disabled); #define=20 +Heci3Disable() MeDeviceControl (HECI3, Disabled); +#define IderDisable() MeDeviceControl (IDER, Disabled); +#define SolDisable() MeDeviceControl (SOL, Disabled); + +#define DisableAllMeDevices() \ + HeciDisable (); \ + Heci2Disable (); \ + Heci3Disable (); \ + IderDisable (); \ + SolDisable (); + +/// +/// HECI Device Id Definitions +/// + #define IS_PCH_H_HECI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI_DEVICE_ID) \ + ) + + #define IS_PCH_LP_HECI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI_DEVICE_ID) \ + ) + + #define IS_HECI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI_DEVICE_ID(DeviceId) \ + ) + +/// +/// HECI2 Device Id Definitions +/// +#define IS_PCH_H_HECI2_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI2_DEVICE_ID) \ + ) + +#define IS_PCH_LP_HECI2_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI2_DEVICE_ID) \ + ) + +#define IS_HECI2_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI2_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI2_DEVICE_ID(DeviceId) \ + ) + +/// +/// HECI3 Device Id Definitions +/// +#define IS_PCH_H_HECI3_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI3_DEVICE_ID) \ + ) + +#define IS_PCH_LP_HECI3_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI3_DEVICE_ID) \ + ) + +#define IS_HECI3_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI3_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI3_DEVICE_ID(DeviceId) \ + ) + +/// +/// HECI4 Device Id Definitions +/// +#define IS_PCH_H_HECI4_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI4_DEVICE_ID) \ + ) + +#define IS_PCH_LP_HECI4_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI4_DEVICE_ID) \ + ) + +#define IS_HECI4_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI4_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI4_DEVICE_ID(DeviceId) \ + ) + +/// +/// SoL Device Id Definitions +/// +#define IS_PCH_H_SOL_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_SOL_DEVICE_ID) \ + ) + +#define IS_PCH_LP_SOL_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_SOL_DEVICE_ID) \ + ) + +#define IS_PCH_SOL_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SOL_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SOL_DEVICE_ID(DeviceId) \ + ) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h new file mode 100644 index 0000000000..a24973ce32 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h @@ -0,0 +1,17 @@ +/** @file + This file contains definitions of ME Policy HOB. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _ME_POLICY_HOB_H_ +#define _ME_POLICY_HOB_H_ + +#include + +extern EFI_GUID gMePolicyHobGuid; +extern EFI_GUID gMePreMemPolicyHobGuid; + +#endif // _ME_POLICY_HOB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h new file mode 100644 index 0000000000..2d8ef1cf7a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h @@ -0,0 +1,19 @@ +/** @file + MKHI Messages + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _MKHI_MSGS_H +#define _MKHI_MSGS_H + +/// +/// End of Post +/// +#define EOP_DISABLED 0 +#define EOP_SEND_IN_PEI 1 +#define EOP_SEND_IN_DXE 2 + +#endif // _MKHI_MSGS_H diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolic= y.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h new file mode 100644 index 0000000000..518041cb58 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h @@ -0,0 +1,41 @@ +/** @file + Interface definition details between ME and platform drivers during DXE = phase. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _ME_POLICY_H_ +#define _ME_POLICY_H_ + +#include + +/** + ME Policy Protocol. + All ME Policy Protocol change history listed here. + +**/ +#define ME_POLICY_PROTOCOL_REVISION 1 + +extern EFI_GUID gDxeMePolicyGuid; + +#pragma pack (push,1) + +/** + ME policy provided by platform for DXE phase + This protocol provides an interface to get Intel ME Configuration=20 +information + + Revision 1: + - Initial version. +**/ +typedef struct _ME_POLICY_PROTOCOL { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part=20 +of AddConfigBlock() */ } ME_POLICY_PROTOCOL; + +#pragma pack (pop) + +#endif // _ME_POLICY_H_ -- 2.16.2.windows.1