From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Fri, 16 Aug 2019 17:51:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:51:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="177349720" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by fmsmga008.fm.intel.com with ESMTP; 16 Aug 2019 17:51:31 -0700 Received: from orsmsx155.amr.corp.intel.com (10.22.240.21) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 16 Aug 2019 17:51:31 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.96]) by ORSMSX155.amr.corp.intel.com ([169.254.7.26]) with mapi id 14.03.0439.000; Fri, 16 Aug 2019 17:51:30 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include headers Thread-Topic: [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include headers Thread-Index: AQHVVJERLeg7khjX8kCwLcQ1V8QJBqb+gqnw Date: Sat, 17 Aug 2019 00:51:30 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE12888@ORSMSX114.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-3-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-3-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTA0NzRjMDAtYmFlNi00M2E2LWEyNTItOWY4OGM2MjU3MTBlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiWkdmUUZMNUJ5bko5RlpYZ0kxZlRKWjJcLzZPTnlBU2ROYVhGYjE2RFdRMVhGZWtEQ1huZjVVQ3VXaVJUVW1paGIifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:15 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Gao, Liming ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Inc= lude headers REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files common to CPU modules. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h = | 45 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPre= MemConfig.h | 106 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclocking= Config.h | 141 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfi= g.h | 54 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBas= icConfig.h | 179 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCus= tomConfig.h | 78 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTes= tConfig.h | 149 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h= | 66 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h = | 16 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h = | 113 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h = | 88 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h = | 23 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h = | 100 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h = | 261 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h = | 90 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h = | 118 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h = | 84 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h = | 123 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProtocol.= h | 50 ++++ 19 files changed, 1884 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuCo= nfig.h new file mode 100644 index 0000000000..47a98131d0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.= h @@ -0,0 +1,45 @@ +/** @file + CPU Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_CONFIG_H_ +#define _CPU_CONFIG_H_ + +#define CPU_CONFIG_REVISION 3 + +extern EFI_GUID gCpuConfigGuid; + +#pragma pack (push,1) + +/** + CPU Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Deprecate and move SkipMpInit to CpuConfigLibPreMemConfig. + Revision 3: + - Move DebugInterfaceEnable from CPU_TEST_CONFIG. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Enable or Disable Advanced Encryption Standard (AES) feature. + For some countries, this should be disabled for legal reasons. + - 0: Disable + - 1: Enable + **/ + UINT32 AesEnable : 1; + UINT32 SkipMpInit : 1; ///< @deprecated since r= evision 2. For Fsp only, Silicon Initialization will skip MP Initialization= (including BSP) if enabled. For non-FSP, this should always be 0. + UINT32 DebugInterfaceEnable : 1; ///< Enable or Disable p= rocessor debug features; 0: Disable; 1: Enable. + UINT32 RsvdBits : 28; ///< Reserved for future= use + EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcod= e patch that is suitable for this processor. +} CPU_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= ConfigLibPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Co= nfigBlock/CpuConfigLibPreMemConfig.h new file mode 100644 index 0000000000..ce965a7510 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigL= ibPreMemConfig.h @@ -0,0 +1,106 @@ +/** @file + CPU Security PreMemory Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ +#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ + +#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 5 + +extern EFI_GUID gCpuConfigLibPreMemConfigGuid; + +#pragma pack (push,1) + +/** + CPU Config Library PreMemory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Update for JTAG Power Gate comment. + Revision 3: + - Add PeciSxReset and PeciC10Reset + Revision 4: + - Add SkipMpInit + Revision 5: + - Add DpSscMarginEnable +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Thre= ading; 0: Disable; 1: Enable. + /** + Sets the boot frequency starting from reset vector. + - 0: Maximum battery performance. + - 1: Maximum non-turbo performance. + - 2: Turbo performance. + @note If Turbo is selected BIOS will start in max non-turbo mode and swi= tch to Turbo mode. + **/ + UINT32 BootFrequency : 2; + /** + Number of processor cores to enable. + - 0: All cores + - 1: 1 core + - 2: 2 cores + - 3: 3 cores + **/ + UINT32 ActiveCoreCount : 3; + UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated i= n C10 state. True: keeps the JTAG power up during C10 and deeper power stat= es for debug purpose. 0: False<\b>; 1: True. + UINT32 BistOnReset : 1; ///< (Test) Enable or Disa= ble BIST on Reset; 0: Disable; 1: Enable. + /** + Enable or Disable Virtual Machine Extensions (VMX) feature. + - 0: Disable + - 1: Enable + **/ + UINT32 VmxEnable : 1; + /** + Processor Early Power On Configuration FCLK setting. + - 0: 800 MHz (ULT/ULX). + - 1: 1 GHz (DT/Halo). Not supported on ULT/ULX. + - 2: 400 MHz. + - 3: Reserved. + **/ + UINT32 FClkFrequency : 2; + /** + Enables a mailbox command to resolve rare PECI related Sx issues. + @note This should only be used on systems that observe PECI Sx issues. + - 0: Disable + - 1: Enable + **/ + UINT32 PeciSxReset : 1; + /** + Enables the mailbox command to resolve PECI reset issues during Pkg-C1= 0 exit. + If Enabled, BIOS will send the CPU message to disable peci reset on C1= 0 exit. + The default value is 0: Disable for CNL, and 1: Enable f= or all other CPU's + - 0: Disable + - 1: Enable + **/ + UINT32 PeciC10Reset : 1; + /** + For Fsp only, Silicon Initialization will skip MP Initialization + (including BSP) if enabled. For non-FSP, this should always be 0. + - 0: Disable + - 1: Enable + **/ + UINT32 SkipMpInit : 1; + /** + Enable DisplayPort SSC range reduction + @note This should only be used on systems that exceeds allowed SSC mod= ulation range as defined in VESA's spec. + - 0: Disable + - 1: Enable + **/ + UINT32 DpSscMarginEnable : 1; + UINT32 RsvdBits : 17; + /** + CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRati= o. 0: Disabled If disabled, doesn't override max-non turbo ratio. + **/ + UINT8 CpuRatio; + UINT8 Reserved[3]; ///< Reserved for alignment +} CPU_CONFIG_LIB_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= OverclockingConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Confi= gBlock/CpuOverclockingConfig.h new file mode 100644 index 0000000000..a0b8a208e6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclo= ckingConfig.h @@ -0,0 +1,141 @@ +/** @file + CPU Overclocking Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_OVERCLOCKING_PREMEM_CONFIG_H_ +#define _CPU_OVERCLOCKING_PREMEM_CONFIG_H_ + +#define CPU_OVERCLOCKING_CONFIG_REVISION 4 + +extern EFI_GUID gCpuOverclockingPreMemConfigGuid; + +#pragma pack (push,1) + +/** + CPU Overclocking Configuration Structure. + + Revision 1: + - Initial version. + Revision 2 + - Deprecate RingMinOcRatio + Revision 3 + - Change RingDownBin default to 'Enabled' + Revision 4 + - Add TvbRatioClipping, TvbVoltageOptimization + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Overclocking support. This controls whether OC mailbox transactions are = sent. + If disabled, all policies in this config block besides OcSupport and OcL= ock will be ignored. + 0: Disable; + 1: Enable. + @note If PcdOverclockEnable is disabled, this should also be disabled. + **/ + UINT32 OcSupport : 1; + UINT32 OcLock : 1; ///< If enabled, sets OC= lock bit in MSR 0x194[20], locking the OC mailbox and other OC configurati= on settings.; 0: Disable; 1: Enable (Lock). + /** + Core voltage mode, specifies which voltage mode the processor will be op= erating. + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range; + 1: Override, sets one voltage for for the entire frequency range, Pn-P0. + **/ + UINT32 CoreVoltageMode : 1; + UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize= possible ratio for SSE workload. + UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX3 ratio to maximiz= e possible ratio for SSE workload. + UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Volta= ge enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/= F curves are aware of BCLK frequency when calculated. + /** + Ring Downbin enable/disable. + When enabled, the CPU will force the ring ratio to be lower than the cor= e ratio. + Disabling will allow the ring and core ratios to run at the same frequen= cy. + Uses OC Mailbox command 0x19. + 0: Disables Ring Downbin feature. 1: Enables Ring downbin feature. + **/ + UINT32 RingDownBin : 1; + /** + Ring voltage mode, specifies which voltage mode the processor will be op= erating. + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range; + 1: Override, sets one voltage for for the entire frequency range, Pn-P0. + **/ + UINT32 RingVoltageMode : 1; + UINT32 RsvdBits : 10; ///< Reserved for future= use + + /** + Maximum core turbo ratio override allows to increase CPU core frequency = beyond the fused max turbo ratio limit (P0). + 0. no override/HW defaults.. Range 0-255. Max range varies by CPU= sku. + **/ + UINT8 CoreMaxOcRatio; + /** + The core voltage override which is applied to the entire range of cpu co= re frequencies. + Used when CoreVoltageMode =3D Override. + 0. no override. Range 0-2000 mV. + **/ + UINT16 CoreVoltageOverride; + /** + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the cpu is operating in turbo mode range. + Used when CoreVoltageMode =3D Adaptive. + 0. no override. Range 0-2000mV. + **/ + UINT16 CoreVoltageAdaptive; + /** + The core voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range. + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000. + **/ + INT16 CoreVoltageOffset; + /** + Maximum ring ratio override allows to increase CPU ring frequency beyond= the fused max ring ratio limit. + 0. no override/HW defaults.. Range 0-255. Max range varies by CPU= sku. + **/ + UINT8 RingMaxOcRatio; + /** + The ring voltage override which is applied to the entire range of cpu ri= ng frequencies. + Used when RingVoltageMode =3D Override. + 0. no override. Range 0-2000 mV. + **/ + UINT16 RingVoltageOverride; + /** + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the ring is operating in turbo mode range. + Used when RingVoltageMode =3D Adaptive. + 0. no override. Range 0-2000mV. + **/ + UINT16 RingVoltageAdaptive; + /** + The ring voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range. + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000. + **/ + INT16 RingVoltageOffset; + UINT8 RingMinOcRatio; ///< Deprecated since re= v 2. Minimum ring ratio override. 0: Hardware defaults. Range: 0-83. + UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offs= et. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL vo= ltage offset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 McPllVoltageOffset : 6; ///< Memory Controller P= LL voltage offset. 0: No offset. Range 0-63 in 17.5mv units. + /** + This service controls Core frequency reduction caused by high package te= mperatures for processors that + implement the Intel Thermal Velocity Boost (TVB) feature. It is required= to be disabled for supporting + overclocking at frequencies higher than the default max turbo frequency. + 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping. + **/ + UINT32 TvbRatioClipping : 1; + /** + This service controls thermal based voltage optimizations for processors= that implement the Intel + Thermal Velocity Boost (TVB) feature. + 0: Disables TVB voltage optimization. 1: Enables TVB voltage optimiza= tion. + **/ + UINT32 TvbVoltageOptimization : 1; + + UINT32 RsvdBits1 : 6; + /** + TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offs= et) to support TjMax in the range of 62 to 115 deg Celsius. + Default: 0 Hardware Defaults Range 0 to 63. + **/ + UINT8 TjMaxOffset; +} CPU_OVERCLOCKING_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_OVERCLOCKING_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PidTestConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBloc= k/CpuPidTestConfig.h new file mode 100644 index 0000000000..e45f335ff9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTest= Config.h @@ -0,0 +1,54 @@ +/** @file + CPU PID Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PID_TEST_CONFIG_H_ +#define _CPU_PID_TEST_CONFIG_H_ + +#define CPU_PID_TEST_CONFIG_REVISION 1 + +extern EFI_GUID gCpuPidTestConfigGuid; + +#pragma pack (push,1) + +/** + PID Tuning Configuration Structure. + Domain is mapped to Kp =3D 0, Ki =3D 1, Kd =3D 2. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT16 Ratl[3]; ///< RATL setting, in 1/= 256 units. Range is 0 - 65280 + UINT16 VrTdcVr0[3]; ///< VR Thermal Design C= urrent for VR0. In 1/256 units. Range is 0 - 65280 + UINT16 VrTdcVr1[3]; ///< VR Thermal Design C= urrent for VR1. In 1/256 units. Range is 0 - 65280 + UINT16 VrTdcVr2[3]; ///< VR Thermal Design C= urrent for VR2. In 1/256 units. Range is 0 - 65280 + UINT16 VrTdcVr3[3]; ///< VR Thermal Design C= urrent for VR3. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl1Msr[3]; ///< Power Budget Manage= ment Psys PL1 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl1MmioPcs[3]; ///< Power Budget Manage= ment Psys PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl2Msr[3]; ///< Power Budget Manage= ment Psys PL2 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl2MmioPcs[3]; ///< Power Budget Manage= ment Psys PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl1Msr[3]; ///< Power Budget Manage= ment Package PL1 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl1MmioPcs[3]; ///< Power Budget Manage= ment Package PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl2Msr[3]; ///< Power Budget Manage= ment Package PL2 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl2MmioPcs[3]; ///< Power Budget Manage= ment Package PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 DdrPl1Msr[3]; ///< DDR PL1 MSR. In 1/2= 56 units. Range is 0 - 65280 + UINT16 DdrPl1MmioPcs[3]; ///< DDR PL1 MMIO/PCS. I= n 1/256 units. Range is 0 - 65280 + UINT16 DdrPl2Msr[3]; ///< DDR PL2 MSR. In 1/2= 56 units. Range is 0 - 65280 + UINT16 DdrPl2MmioPcs[3]; ///< DDR PL2 MMIO/PCS. I= n 1/256 units. Range is 0 - 65280 + /** + Enable or Disable PID Tuning programming flow. + If disabled, all other policies in this config block are ignored. + **/ + UINT8 PidTuning; + UINT8 Rsvd; ///< Reserved for DWORD = alignment. +} CPU_PID_TEST_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_PID_TEST_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PowerMgmtBasicConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Con= figBlock/CpuPowerMgmtBasicConfig.h new file mode 100644 index 0000000000..2ad474b7e9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMg= mtBasicConfig.h @@ -0,0 +1,179 @@ +/** @file + CPU Power Management Basic Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_ +#define _CPU_POWER_MGMT_BASIC_CONFIG_H_ + +#define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 2 + +extern EFI_GUID gCpuPowerMgmtBasicConfigGuid; + +#pragma pack (push,1) + +/** + CPU Power Management Basic Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Added MinRingRatioLimit + - Added MaxRingRatioLimit +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Sets the boot frequency starting from reset vector. + - 0: Maximum battery performance. + - 1: Maximum non-turbo performance. + - 2: Turbo performance. + @note If Turbo is selected BIOS will start in max non-turbo mode and swi= tch to Turbo mode. + **/ + UINT32 BootFrequency : 2; + UINT32 SkipSetBootPState : 1; ///< Choose whether to s= kip SetBootPState function for all APs; 0: Do not skip; 1: Skip. + /** + Enable or Disable Intel Speed Shift Technology. + Enabling allows for processor control of P-state transitions. + 0: Disable; 1: Enable; Bit 1 is ignored. + @note Currently this feature is recommended to be enabled only on win10 + **/ + UINT32 Hwp : 2; + /** + Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved + HDC enables the processor to autonomously force components to enter into= an idle state to lower effective frequency. + This allows for increased package level C6 residency. + @note Currently this feature is recommended to be enabled only on win10 + **/ + UINT32 HdcControl : 2; + UINT32 PowerLimit2 : 1; ///< Enable or Disable s= hort duration Power Limit (PL2). 0: Disable; 1: Enable + UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0= x618[63]: Locks all Turbo power limit settings to read-only; 0: Disable<= /b>; 1: Enable (Lock). + UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cy= cle. Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0. + UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615= h lock; 0: Disable; 1: Enable (Lock). + UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601= h lock; 0: Disable; 1: Enable (Lock). + /** + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU= to throttle below P1. + For Y SKU, the recommended default for this policy is 1: Enabled,= which indicates throttling below P1 is allowed. + For all other SKUs the recommended default are 0: Disabled. + **/ + UINT32 TccOffsetClamp : 1; + UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock for= Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A= 2h; 0: Disabled; 1: Enabled (Lock). + UINT32 TurboMode : 1; ///< Enable or Disable T= urbo Mode. Disable; 1: Enable + UINT32 HwpInterruptControl : 1; ///< Set HW P-State Inte= rrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: Enabl= e. + + UINT32 RsvdBits : 9; ///< Reserved for future= use. + + /** + 1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking p= arts: LFM to Fused 1-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Rat= io Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. + **/ + UINT8 OneCoreRatioLimit; + /** + 2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking p= art: LFM to Fused 2-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 TwoCoreRatioLimit; + /** + 3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking p= art: LFM to Fused 3-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 ThreeCoreRatioLimit; + /** + 4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking p= art: LFM to Fused 4-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 FourCoreRatioLimit; + /** + 5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking p= art: LFM to Fused 5-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 FiveCoreRatioLimit; + /** + 6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking p= art: LFM to Fused 6-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 SixCoreRatioLimit; + /** + 7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking p= art: LFM to Fused 7-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 SevenCoreRatioLimit; + /** + 8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking p= art: LFM to Fused 8-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 EightCoreRatioLimit; + /** + TCC Activation Offset. Offset from factory set TCC activation temperatur= e at which the Thermal Control Circuit must be activated. + TCC will be activated at (TCC Activation Temperature - TCC Activation Of= fset), in degrees Celcius. + For Y SKU, the recommended default for this policy is 15 + For all other SKUs the recommended default are 0, causing TCC to = activate at TCC Activation temperature. + @note The policy is recommended for validation purpose only. + **/ + UINT8 TccActivationOffset; + /** + Intel Turbo Boost Max Technology 3.0 + Enabling it on processors with OS support will allow OS to exploit the d= iversity in max turbo frequency of the cores. + 0: Disable; 1: Enable; + **/ + UINT8 EnableItbm : 1; + /** + Intel Turbo Boost Max Technology 3.0 Driver + Enabling it will load the driver upon ACPI device with HID =3D INT3510. + 0: Disable; 1: Enable; + **/ + UINT8 EnableItbmDriver : 1; + UINT8 ReservedBits1 : 6; ///< Reserved for future= use. + UINT8 MinRingRatioLimit; ///< Minimum Ring Ratio = Limit. Range from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default + UINT8 MaxRingRatioLimit; ///< Maximum Ring Ratio = Limit. Range from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default + + /** + Package Long duration turbo mode power limit (PL1). + Default is the TDP power limit of processor. Units are based on POWER_MG= MT_CONFIG.CustomPowerUnit. + **/ + UINT16 PowerLimit1; + /** + Package Short duration turbo mode power limit (PL2). Allows for short ex= cursions above TDP power limit. + Default =3D 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG= .CustomPowerUnit. + **/ + UINT16 PowerLimit2Power; + /** + Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit. + Default: 0. Range 0-65535. Units are based on POWER_MGMT_CONFIG.C= ustomPowerUnit. + **/ + UINT16 PowerLimit3; + /** + Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power Limi= t, it will never be exceeded. + Power is premptively lowered before limit is reached. Default: 0.= Range 0-65535. + Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + **/ + UINT16 PowerLimit4; + /** + Package Long duration turbo mode power limit (PL1) time window in second= s. + Used in calculating the average power over time. + Default: 0 - AUTO, auto will program 28 seconds. + Range: 0 - 128s + **/ + UINT32 PowerLimit1Time; + UINT32 PowerLimit3Time; ///< Package PL3 time wi= ndow. Range from 3ms to 64ms. + /** + Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Averag= e Temperature Limit (RATL). + For Y SKU, the recommended default for this policy is 5000: 5 seconds= , For all other SKUs the recommended default are 0: Disabled + **/ + UINT32 TccOffsetTimeWindowForRatl; +} CPU_POWER_MGMT_BASIC_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PowerMgmtCustomConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Co= nfigBlock/CpuPowerMgmtCustomConfig.h new file mode 100644 index 0000000000..7eb91fa3ee --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMg= mtCustomConfig.h @@ -0,0 +1,78 @@ +/** @file + CPU Power Managment Custom Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ +#define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ + +#define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1 + +extern EFI_GUID gCpuPowerMgmtCustomConfigGuid; + +#pragma pack (push,1) + +/// +/// Defines the maximum number of custom ratio states supported. +/// +#define MAX_CUSTOM_RATIO_TABLE_ENTRIES 40 +#define MAX_16_CUSTOM_RATIO_TABLE_ENTRIES 16 + +/// +/// Defines the maximum number of custom ConfigTdp entries supported. +/// @warning: Changing this define would cause DWORD alignment issues in p= olicy structures. +/// +#define MAX_CUSTOM_CTDP_ENTRIES 3 + +/// +/// This structure is used to describe the custom processor ratio table de= sired by the platform. +/// +typedef struct { + UINT8 MaxRatio; ///< The maxi= mum ratio of the custom ratio table. + UINT8 NumberOfEntries; ///< The numb= er of custom ratio state entries, ranges from 2 to 40 for a valid custom ra= tio table. + UINT8 Rsvd0[2]; ///< Reserved= for DWORD alignment. + UINT32 Cpuid; ///< The CPU = ID for which this custom ratio table applies. + UINT8 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The proc= essor ratios in the custom ratio table. + /// + /// If there are more than 16 total entries in the StateRatio table, the= n use these 16 entries to fill max 16 table. + /// @note If NumberOfEntries is 16 or less, or the first entry of this t= able is 0, then this table is ignored, + /// and up to the top 16 values from the StateRatio table is used instea= d. + /// + UINT8 StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES]; +#if ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) = % 4) + UINT8 Rsvd1[4 - ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_= TABLE_ENTRIES) % 4)]; ///< If needed, add padding for dword alignment. +#endif +} PPM_CUSTOM_RATIO_TABLE; + +/// +/// PPM Custom ConfigTdp Settings +/// +typedef struct _PPM_CUSTOM_CTDP_TABLE { + UINT32 CustomPowerLimit1Time : 8; ///< Short term Power= Limit time window value for custom cTDP level. + UINT32 CustomTurboActivationRatio : 8; ///< Turbo Activation= Ratio for custom cTDP level. + UINT32 RsvdBits : 16; ///< Bits reserved fo= r DWORD alignment. + UINT16 CustomPowerLimit1; ///< Short term Power= Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.Cu= stomPowerUnit. + UINT16 CustomPowerLimit2; ///< Long term Power = Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.Cus= tomPowerUnit. +} PPM_CUSTOM_CTDP_TABLE; + +/** + CPU Power Management Custom Configuration Structure. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header + PPM_CUSTOM_RATIO_TABLE CustomRatioTable; = ///< Custom Processor Ratio Table Instance + PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; = ///< Custom ConfigTdp Settings Instance + UINT32 ConfigTdpLock : 1; = ///< Lock the ConfigTdp mode settings from runtime changes; 0: Dis= able; 1: Enable. + UINT32 ConfigTdpBios : 1; = ///< Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; = ///< Reserved for future use +} CPU_POWER_MGMT_CUSTOM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PowerMgmtTestConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Conf= igBlock/CpuPowerMgmtTestConfig.h new file mode 100644 index 0000000000..cb9b20249f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMg= mtTestConfig.h @@ -0,0 +1,149 @@ +/** @file + CPU Power Management Test Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_ +#define _CPU_POWER_MGMT_TEST_CONFIG_H_ + +#define CPU_POWER_MGMT_TEST_CONFIG_REVISION 3 + +extern EFI_GUID gCpuPowerMgmtTestConfigGuid; + +#pragma pack (push,1) + +/// +/// PPM Package C State Limit +/// +typedef enum { + PkgC0C1 =3D 0, + PkgC2, + PkgC3, + PkgC6, + PkgC7, + PkgC7s, + PkgC8, + PkgC9, + PkgC10, + PkgCMax, + PkgCpuDefault =3D 254, + PkgAuto =3D 255 +} MAX_PKG_C_STATE; + +/// +/// PPM Package C State Time Limit +/// +typedef enum { + TimeUnit1ns =3D 0, + TimeUnit32ns, + TimeUnit1024ns, + TimeUnit32768ns, + TimeUnit1048576ns, + TimeUnit33554432ns, + TimeUnitMax +} C_STATE_TIME_UNIT; + +/// +/// Custom Power Units. User can choose to enter in watts or 125 milliwatt= increments. +/// +typedef enum { + PowerUnitWatts =3D 0, ///< in Watts. + PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 po= wer units times 125 mW equals 11.250 W. + PowerUnitMax +} CUSTOM_POWER_UNIT; + +/// +/// PPM Interrupt Redirection Mode Selection +/// +typedef enum { + PpmIrmFixedPriority =3D 0, + PpmIrmRoundRobin, + PpmIrmHashVector, + PpmIrmReserved1, + PpmIrmPairFixedPriority, + PpmIrmPairRoundRobin, + PpmIrmPairHashVector, + PpmIrmNoChange +} PPM_IRM_SETTING; + +/** + CPU Power Management Test Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Update PkgCStateDemotion and PkgCStateUnDemotion to be Disable. + Revision 3: + - Add CstateLatencyControl0TimeUnit for CFL only + - Add CstateLatencyControl0Irtl for CFL only +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block Header + UINT32 Eist : 1; ///< Offset 28-31 Enabl= e or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable + UINT32 EnergyEfficientPState : 1; ///< Enabl= e or Disable Energy Efficient P-state will be applied in Turbo mode. Disabl= e; 1: Enable + UINT32 EnergyEfficientTurbo : 1; ///< Enabl= e or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable= ; 1: Enable + UINT32 TStates : 1; ///< Enabl= e or Disable T states; 0: Disable; 1: Enable. + UINT32 BiProcHot : 1; ///< Enabl= e or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. + UINT32 DisableProcHotOut : 1; ///< Enabl= e or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Ena= ble. + UINT32 ProcHotResponse : 1; ///< Enabl= e or Disable PROCHOT# Response; 0: Disable; 1: Enable. + UINT32 DisableVrThermalAlert : 1; ///< Enabl= e or Disable VR Thermal Alert; 0: Disable; 1: Enable. + UINT32 AutoThermalReporting : 1; ///< Enabl= e or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enabl= e. + UINT32 ThermalMonitor : 1; ///< Enabl= e or Disable Thermal Monitor; 0: Disable; 1: Enable. + UINT32 Cx : 1; ///< Enabl= e or Disable CPU power states (C-states). 0: Disable; 1: Enable + UINT32 PmgCstCfgCtrlLock : 1; ///< If en= abled, sets MSR 0xE2[15]; 0: Disable; 1: Enable. + UINT32 C1e : 1; ///< Enabl= e or Disable Enhanced C-states. 0: Disable; 1: Enable + UINT32 C1AutoDemotion : 1; ///< Enabl= e or Disable C6/C7 auto demotion to C1. 0: Disabled; 1: C1 Auto demotion= + UINT32 C1UnDemotion : 1; ///< Enabl= e or Disable C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion + UINT32 C3AutoDemotion : 1; ///< [Coff= eeLake Only] Enable or Disable C6/C7 auto demotion to C3 0: Disabled; 1= : C3 Auto demotion + UINT32 C3UnDemotion : 1; ///< [Coff= eeLake Only] Enable or Disable C3UnDemotion. 0: Disabled; 1: C3 Auto und= emotion + UINT32 PkgCStateDemotion : 1; ///< Enabl= e or Disable Package Cstate Demotion. [Cannonlake Y] 0: Disable; 1: Enab= le [CoffeeLake] Disable; 1: Enable + UINT32 PkgCStateUnDemotion : 1; ///< Enabl= e or Disable Package Cstate UnDemotion. 0: [Cannonlake Y] 0: Disable; 1= : Enable [CoffeeLake] Disable; 1: Enable + UINT32 CStatePreWake : 1; ///< Enabl= e or Disable CState-Pre wake. Disable; 1: Enable + UINT32 TimedMwait : 1; ///< Enabl= e or Disable TimedMwait Support. Disable; 1: Enable + UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Enabl= e or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. + UINT32 ProcHotLock : 1; ///< If en= abled, sets MSR 0x1FC[23]; 0: Disable; 1: Enable. + UINT32 RaceToHalt : 1; ///< Enabl= e or Disable Race To Halt feature; 0: Disable; 1: Enable . RTH will = dynamically increase CPU frequency in order to enter pkg C-State faster to = reduce overall power. (RTH is controlled through MSR 1FC bit 20) + UINT32 ConfigTdpLevel : 8; ///< Confi= guration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP= Up. + UINT16 CstateLatencyControl1Irtl; ///< Offset 32-33 Inter= rupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0]. + UINT16 CstateLatencyControl2Irtl; ///< Offset 34-35 Inter= rupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0]. + UINT16 CstateLatencyControl3Irtl; ///< Offset 36-37 Inter= rupt Response Time Limit of LatencyContol3 MSR 0x633[9:0]. + UINT16 CstateLatencyControl4Irtl; ///< Offset 38-39 Inter= rupt Response Time Limit of LatencyContol4 MSR 0x634[9:0]. + UINT16 CstateLatencyControl5Irtl; ///< Offset 40-41 Inter= rupt Response Time Limit of LatencyContol5 MSR 0x635[9:0]. + UINT16 CstateLatencyControl0Irtl; ///< Offset 42-43 Inter= rupt Response Time Limit of LatencyContol1 MSR 0x60A[9:0]. + MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 This = field is used to set the Max Pkg Cstate. Default set to Auto which limits t= he Max Pkg Cstate to deep C-state. + /** + @todo: The following enums have to be replaced with policies. + **/ + C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit; ///< Offset 45 TimeU= nit for Latency Control0 MSR 0x60A[12:10]; (CFL)2: 1024ns + C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 TimeU= nit for Latency Control1 MSR 0x60B[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 TimeU= nit for Latency Control2 MSR 0x60C[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 TimeU= nit for Latency Control3 MSR 0x633[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 TimeU= nit for Latency Control4 MSR 0x634[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 TimeU= nit for Latency Control5 MSR 0x635[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + /** + Offset 51 Default power unit in watts or in 125 milliwatt increments. + - 0: PowerUnitWatts. + - 1: PowerUnit125MilliWatts. + **/ + CUSTOM_POWER_UNIT CustomPowerUnit; + /** + Offset 52 Interrupt Redirection Mode Select. + - 0: Fixed priority. + - 1: Round robin. + - 2: Hash vector. + - 4: PAIR with fixed priority. + - 5: PAIR with round robin. + - 6: PAIR with hash vector. + - 7: No change. + **/ + PPM_IRM_SETTING PpmIrmSetting; + // Move the padding to previous offset to align the structure at 32-bit = address. + UINT8 Rsvd[4]; ///< Offset 53-56 Reserv= ed for future use and config block alignment +} CPU_POWER_MGMT_TEST_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_POWER_MGMT_TEST_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= TestConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/C= puTestConfig.h new file mode 100644 index 0000000000..b94eb5e263 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestCon= fig.h @@ -0,0 +1,66 @@ +/** @file + CPU Test Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_TEST_CONFIG_H_ +#define _CPU_TEST_CONFIG_H_ + +#define CPU_TEST_CONFIG_REVISION 4 + +extern EFI_GUID gCpuTestConfigGuid; + +#pragma pack (push,1) + +/** + CPU Test Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Fixed RsvdBits incorrect value. + Revision 3: + - Added CpuWakeUpTimer + Revision 4: + - Deprecate and move DebugInterfaceEnable to CPU_CONFIG. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 MlcStreamerPrefetcher : 1; ///< Enab= le or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + UINT32 MlcSpatialPrefetcher : 1; ///< Enab= le or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable. + UINT32 MonitorMwaitEnable : 1; ///< Enab= le or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. + UINT32 MachineCheckEnable : 1; ///< Enab= le or Disable initialization of machine check registers; 0: Disable; 1: = Enable. + UINT32 DebugInterfaceEnable : 1; ///< @dep= recated Enable or Disable processor debug features; 0: Disable; 1: E= nable. + UINT32 DebugInterfaceLockEnable : 1; ///< Lock= or Unlock debug interface features; 0: Disable; 1: Enable. + UINT32 ProcessorTraceOutputScheme : 1; ///< Cont= rol on Processor Trace output scheme; 0: Single Range Output; 1: ToP= A Output. + UINT32 ProcessorTraceEnable : 1; ///< Enab= le or Disable Processor Trace feature; 0: Disable; 1: Enable. + UINT32 ThreeStrikeCounterDisable : 1; ///< Disa= ble Three strike counter; 0: FALSE; 1: TRUE. + /** + This policy should be used to enable or disable Voltage Optimization f= eature. + Recommended defaults: + Enable - For Mobile SKUs(U/Y) + Disable - Rest of all SKUs other than Mobile. + **/ + UINT32 VoltageOptimization : 1; + UINT32 CpuWakeUpTimer : 1; ///< Ena= ble or Disable long CPU wake up timer. 0: Disabled (8s); 1: Enabled (180= s). + UINT32 RsvdBits : 21; ///< Res= erved for future use + /** + Base address of memory region allocated for Processor Trace. + Processor Trace requires 2^N alignment and size in bytes per thread, = from 4KB to 128MB. + - NULL: Disable + **/ + EFI_PHYSICAL_ADDRESS ProcessorTraceMemBase; + /** + Length in bytes of memory region allocated for Processor Trace. + Processor Trace requires 2^N alignment and size in bytes per thread, = from 4KB to 128MB. + - 0: Disable + **/ + UINT32 ProcessorTraceMemLength; +} CPU_TEST_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_TEST_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h b/S= ilicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h new file mode 100644 index 0000000000..48fdbdd012 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h @@ -0,0 +1,16 @@ +/** @file + Macros to simplify and abstract the interface to CPU configuration. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPUACCESS_H_ +#define _CPUACCESS_H_ + +#include "CpuRegs.h" +#include "CpuDataStruct.h" +#include "CpuPowerMgmt.h" + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h new file mode 100644 index 0000000000..2382e60dca --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h @@ -0,0 +1,113 @@ +/** @file + This file declares various data structures used in CPU reference code. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_DATA_STRUCT_H +#define _CPU_DATA_STRUCT_H + +// +// The reason for changing the state of the processor Only applies to Disa= bling processors. +// In future, we can add add/remove support +// +#define CPU_CAUSE_NOT_DISABLED 0x0000 +#define CPU_CAUSE_INTERNAL_ERROR 0x0001 +#define CPU_CAUSE_THERMAL_ERROR 0x0002 +#define CPU_CAUSE_SELFTEST_FAILURE 0x0004 +#define CPU_CAUSE_PREBOOT_TIMEOUT 0x0008 +#define CPU_CAUSE_FAILED_TO_START 0x0010 +#define CPU_CAUSE_CONFIG_ERROR 0x0020 +#define CPU_CAUSE_USER_SELECTION 0x0080 +#define CPU_CAUSE_BY_ASSOCIATION 0x0100 +#define CPU_CAUSE_UNSPECIFIED 0x8000 + +typedef UINT32 CPU_STATE_CHANGE_CAUSE; + +/// +/// Structure to hold the return value of AsmCpuid instruction +/// +typedef struct { + UINT32 RegEax; ///< Value of EAX. + UINT32 RegEbx; ///< Value of EBX. + UINT32 RegEcx; ///< Value of ECX. + UINT32 RegEdx; ///< Value of EDX. +} EFI_CPUID_REGISTER; + +/// +/// Structure to describe microcode header +/// +typedef struct { + UINT32 HeaderVersion; ///< Version number of the update header. + UINT32 UpdateRevision; ///< Unique version number for the update. + UINT32 Date; ///< Date of the update creation. + UINT32 ProcessorId; ///< Signature of the processor that requires thi= s update. + UINT32 Checksum; ///< Checksum of update data and header. + UINT32 LoaderRevision; ///< Version number of the microcode loader progr= am. + UINT32 ProcessorFlags; ///< Lower 4 bits denoting platform type informat= ion. + UINT32 DataSize; ///< Size of encoded data in bytes. + UINT32 TotalSize; ///< Total size of microcode update in bytes. + UINT8 Reserved[12]; ///< Reserved bits. +} CPU_MICROCODE_HEADER; + +/// +/// Structure to describe the extended signature table header of the micro= code update +/// +typedef struct { + UINT32 ExtendedSignatureCount; ///< Number of extended signature structu= res. + UINT32 ExtendedTableChecksum; ///< Checksum of update extended processo= r signature table. + UINT8 Reserved[12]; ///< Reserved bits. +} CPU_MICROCODE_EXTENDED_TABLE_HEADER; + +/// +/// Structure to describe the data of the extended table of the microcode = update +/// +typedef struct { + UINT32 ProcessorSignature; ///< Extended signature of the processor that= requires this update + UINT32 ProcessorFlag; ///< Lower 4 bits denoting platform type info= rmation + UINT32 ProcessorChecksum; ///< checksum of each of the extended update +} CPU_MICROCODE_EXTENDED_TABLE; + +#pragma pack(1) +/// +/// MSR_REGISTER definition as a Union of QWORDS, DWORDS and BYTES +/// +typedef union _MSR_REGISTER { + UINT64 Qword; ///< MSR value in 64 bit QWORD. + + /// + /// MSR value represented in two DWORDS + /// + struct { + UINT32 Low; ///< Lower DWORD of the 64 bit MSR value. + UINT32 High; ///< Higher DWORD of the 64 bit MSR value. + } Dwords; + + /// + /// MSR value represented in eight bytes. + /// + struct { + UINT8 FirstByte; ///< First byte of the 64 bit MSR value. + UINT8 SecondByte; ///< Second byte of the 64 bit MSR value. + UINT8 ThirdByte; ///< Third byte of the 64 bit MSR value. + UINT8 FouthByte; ///< Fourth byte of the 64 bit MSR value. + UINT8 FifthByte; ///< Fifth byte of the 64 bit MSR value. + UINT8 SixthByte; ///< Sixth byte of the 64 bit MSR value. + UINT8 SeventhByte; ///< Seventh byte of the 64 bit MSR value. + UINT8 EighthByte; ///< Eigth byte of the 64 bit MSR value. + } Bytes; +} MSR_REGISTER; + +/// +/// Store BIST data for BSP. +/// +typedef struct { + UINT32 ApicId; ///< APIC ID + UINT32 Health; ///< BIST result +} BIST_HOB_DATA; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h new file mode 100644 index 0000000000..4862d62975 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h @@ -0,0 +1,88 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define CPU NVS Area operation region. + // + +#ifndef _CPU_NVS_AREA_DEF_H_ +#define _CPU_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + UINT8 Revision; ///< Offset 0 CP= U GlobalNvs Revision + UINT32 PpmFlags; ///< Offset 1 PP= M Flags Values + UINT8 Reserved0[1]; ///< Offset 5:5 + UINT8 AutoCriticalTripPoint; ///< Offset 6 Au= to Critical Trip Point + UINT8 AutoPassiveTripPoint; ///< Offset 7 Au= to Passive Trip Point + UINT8 AutoActiveTripPoint; ///< Offset 8 Au= to Active Trip Point + UINT32 Cpuid; ///< Offset 9 CP= UID + UINT8 ConfigurablePpc; ///< Offset 13 Bo= ot Mode vlues for _PPC + UINT8 CtdpLevelsSupported; ///< Offset 14 Co= nfigTdp Number Of Levels + UINT8 ConfigTdpBootModeIndex; ///< Offset 15 CT= DP Boot Mode Index + UINT16 CtdpPowerLimit1[3]; ///< Offset 16 CT= DP Level 0 Power Limit1 + ///< Offset 18 CT= DP Level 1 Power Limit1 + ///< Offset 20 CT= DP Level 2 Power Limit1 + UINT16 CtdpPowerLimit2[3]; ///< Offset 22 CT= DP Level 0 Power Limit2 + ///< Offset 24 CT= DP Level 1 Power Limit2 + ///< Offset 26 CT= DP Level 2 Power Limit2 + UINT8 CtdpPowerLimitWindow[3]; ///< Offset 28 CT= DP Level 0 Power Limit1 Time Window + ///< Offset 29 CT= DP Level 1 Power Limit1 Time Window + ///< Offset 30 CT= DP Level 2 Power Limit1 Time Window + UINT8 CtdpCtc[3]; ///< Offset 31 CT= DP Level 0 CTC + ///< Offset 32 CT= DP Level 1 CTC + ///< Offset 33 CT= DP Level 2 CTC + UINT8 CtdpTar[3]; ///< Offset 34 CT= DP Level 0 TAR + ///< Offset 35 CT= DP Level 1 TAR + ///< Offset 36 CT= DP Level 2 TAR + UINT8 CtdpPpc[3]; ///< Offset 37 CT= DP Level 0 PPC + ///< Offset 38 CT= DP Level 1 PPC + ///< Offset 39 CT= DP Level 2 PPC + UINT8 Reserved1[1]; ///< Offset 40:40 + UINT8 C6MwaitValue; ///< Offset 41 Mw= ait Hint value for C6 + UINT8 C7MwaitValue; ///< Offset 42 Mw= ait Hint value for C7/C7s + UINT8 CDMwaitValue; ///< Offset 43 Mw= ait Hint value for C7/C8/C9/C10 + UINT8 Reserved2[2]; ///< Offset 44:45 + UINT16 C6Latency; ///< Offset 46 La= tency Value for C6 + UINT16 C7Latency; ///< Offset 48 La= tency Value for C7/C7S + UINT16 CDLatency; ///< Offset 50 La= tency Value for C8/C9/C10 + UINT16 CDIOLevel; ///< Offset 52 IO= LVL value for C8/C9/C10 + UINT16 CDPowerValue; ///< Offset 54 Po= wer value for C8/C9/C10 + UINT8 MiscPowerManagementFlags; ///< Offset 56 Mi= scPowerManagementFlags + UINT8 EnableDigitalThermalSensor; ///< Offset 57 Di= gital Thermal Sensor Enable + UINT8 BspDigitalThermalSensorTemperature; ///< Offset 58 Di= gital Thermal Sensor 1 Readingn for BSP + UINT8 ApDigitalThermalSensorTemperature; ///< Offset 59 Di= gital Thermal Sensor 2 Reading for AP1 + UINT8 DigitalThermalSensorSmiFunction; ///< Offset 60 DT= S SMI Function Call via DTS IO Trap + UINT8 PackageDTSTemperature; ///< Offset 61 Pa= ckage Temperature + UINT8 IsPackageTempMSRAvailable; ///< Offset 62 Pa= ckage Temperature MSR available + UINT8 Ap2DigitalThermalSensorTemperature; ///< Offset 63 Di= gital Thermal Sensor 3 Reading for AP2 + UINT8 Ap3DigitalThermalSensorTemperature; ///< Offset 64 Di= gital Thermal Sensor 4 Reading for AP3 + UINT64 BiosGuardMemAddress; ///< Offset 65 BI= OS Guard Memory Address for Tool Interface + UINT8 BiosGuardMemSize; ///< Offset 73 BI= OS Guard Memory Size for Tool Interface + UINT16 BiosGuardIoTrapAddress; ///< Offset 74 BI= OS Guard IoTrap Address for Tool Interface + UINT16 BiosGuardIoTrapLength; ///< Offset 76 BI= OS Guard IoTrap Length for Tool Interface + UINT16 DtsIoTrapAddress; ///< Offset 78 DT= S IO trap Address + UINT8 DtsIoTrapLength; ///< Offset 80 DT= S IO trap Length + UINT8 DtsAcpiEnable; ///< Offset 81 DT= S is in ACPI Mode Enabled + UINT8 SgxStatus; ///< Offset 82 SG= X Status + UINT64 EpcBaseAddress; ///< Offset 83 EP= C Base Address + UINT64 EpcLength; ///< Offset 91 EP= C Length + UINT8 HwpVersion; ///< Offset 99 HW= P Version + UINT8 HwpInterruptStatus; ///< Offset 100 HW= P Interrupt Status + UINT8 DtsInterruptStatus; ///< Offset 101 DT= S Interrupt Status + UINT8 HwpSmi; ///< Offset 102 SM= I to setup HWP LVT tables + UINT8 LowestMaxPerf; ///< Offset 103 Ma= x ratio of the slowest core. + UINT8 EnableItbm; ///< Offset 104 En= able/Disable Intel Turbo Boost Max Technology 3.0. + UINT8 EnableItbmDriver; ///< Offset 105 En= able/Disable Intel Turbo Boost Max Technology 3.0 Driver. + UINT8 ItbmInterruptStatus; ///< Offset 106 In= tel Turbo Boost Max Technology 3.0 interrupt status. + UINT8 ItbmSmi; ///< Offset 107 SM= I to resume periodic SMM for Intel Turbo Boost Max Technology 3.0. + UINT8 OcBins; ///< Offset 108 In= dicates bins of Oc support. MSR 194h FLEX_RATIO Bits (19:17) + UINT8 C3MwaitValue; ///< Offset 109 Mw= ait Hint value for C3 (CFL only) + UINT16 C3Latency; ///< Offset 110 La= tency Value for C3 (CFL only) +} CPU_NVS_AREA; + +#pragma pack(pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h new file mode 100644 index 0000000000..a9abd426f9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h @@ -0,0 +1,23 @@ +/** @file + CPU Policy structure definition which will contain several config blocks= during runtime. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_COMMON_H_ +#define _CPU_POLICY_COMMON_H_ + +#include "CpuPowerMgmt.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // _CPU_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h new file mode 100644 index 0000000000..af1f70b34f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h @@ -0,0 +1,100 @@ +/** @file + This file contains define definitions specific to processor + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _POWER_MGMT_DEFINITIONS_H_ +#define _POWER_MGMT_DEFINITIONS_H_ + +#define CSTATE_SUPPORTED 0x1 +#define ENHANCED_CSTATE_SUPPORTED 0x2 +#define C6_C7_SHORT_LATENCY_SUPPORTED 0x01 +#define C6_C7_LONG_LATENCY_SUPPORTED 0x02 +#define C7s_SHORT_LATENCY_SUPPORTED 0x03 +#define C7s_LONG_LATENCY_SUPPORTED 0x04 +// +// Voltage offset definitions +// +#define OC_LIB_OFFSET_ADAPTIVE 0 +#define OC_LIB_OFFSET_OVERRIDE 1 +// +// Platform Power Management Flags Bit Definitions: +// These defines are also used in CPU0CST.ASL to check platform configur= ation +// and build C-state table accordingly. +// +#define PPM_EIST BIT0 ///< Enhanced Intel Speed Step Tech= nology. +#define PPM_C1 BIT1 ///< C1 enabled, supported. +#define PPM_C1E BIT2 ///< C1E enabled. +#define PPM_C3 BIT3 ///< C3 enabled, supported. +#define PPM_C6 BIT4 ///< C6 enabled, supported. +#define PPM_C7 BIT5 ///< C7 enabled, supported. +#define PPM_C7S BIT6 ///< C7S enabled, supported +#define PPM_TM BIT7 ///< Adaptive Thermal Monitor. +#define PPM_TURBO BIT8 ///< Long duration turbo mode +#define PPM_CMP BIT9 ///< CMP. +#define PPM_TSTATES BIT10 ///< CPU throttling states +#define PPM_MWAIT_EXT BIT11 ///< MONITIOR/MWAIT Extensions supp= orted. +#define PPM_EEPST BIT12 ///< Energy efficient P-State Featu= re enabled +#define PPM_TSTATE_FINE_GRAINED BIT13 ///< Fine grained CPU Throttling st= ates +#define PPM_CD BIT14 ///< Deep Cstate - C8/C9/C10 +#define PPM_TIMED_MWAIT BIT15 ///< Timed Mwait support +#define C6_LONG_LATENCY_ENABLE BIT16 ///< 1=3DC6 Long and Short,0=3DC6 S= hort only +#define C7_LONG_LATENCY_ENABLE BIT17 ///< 1=3DC7 Long and Short,0=3DC7 S= hort only +#define C7s_LONG_LATENCY_ENABLE BIT18 ///< 1=3DC7s Long and Short,0=3DC7s= Short only +#define PPM_C8 BIT19 ///< 1=3D C8 enabled/supported +#define PPM_C9 BIT20 ///< 1=3D C9 enabled/supported +#define PPM_C10 BIT21 ///< 1=3D C10 enabled/supported +#define PPM_HWP BIT22 ///< 1=3D HWP enabled/supported +#define PPM_HWP_LVT BIT23 ///< 1=3D HWP LVT enabled/supported +#define PPM_OC_UNLOCKED BIT24 ///< 1=3D Overclocking fully unlock= ed + +#define PPM_C_STATES 0x7A ///< PPM_C1 + PPM_C3 + PPM_C6 + PP= M_C7 + PPM_C7S +#define C3_LATENCY 0x4E +#define C6_C7_SHORT_LATENCY 0x76 +#define C6_C7_LONG_LATENCY 0x94 +#define C8_LATENCY 0xFA +#define C9_LATENCY 0x14C +#define C10_LATENCY 0x3F2 + +// +// The following definitions are based on assumed location for the ACPI +// Base Address. Modify as necessary base on platform-specific requiremen= ts. +// +#define PCH_ACPI_PBLK 0x1810 +#define PCH_ACPI_LV2 0x1814 +#define PCH_ACPI_LV3 0x1815 +#define PCH_ACPI_LV4 0x1816 +#define PCH_ACPI_LV6 0x1818 +#define PCH_ACPI_LV5 0x1817 +#define PCH_ACPI_LV7 0x1819 + +// +// C-State Latency (us) and Power (mW) for C1 +// +#define C1_LATENCY 1 +#define C1_POWER 0x3E8 +#define C3_POWER 0x1F4 +#define C6_POWER 0x15E +#define C7_POWER 0xC8 +#define C8_POWER 0xC8 +#define C9_POWER 0xC8 +#define C10_POWER 0xC8 + + +#define PID_DOMAIN_KP 0 +#define PID_DOMAIN_KI 1 +#define PID_DOMAIN_KD 2 +#define MAILBOX_PARAM_1_OFFSET 8 + +/// +/// VR Domain Definitions +/// +#define CPU_VR_DOMAIN_SA 0x0 +#define CPU_VR_DOMAIN_IA 0x1 +#define CPU_VR_DOMAIN_RING 0x2 +#define CPU_VR_DOMAIN_GT 0x3 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h new file mode 100644 index 0000000000..68f2c019e2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h @@ -0,0 +1,261 @@ +/** @file + Register names for CPU registers + + Conventions + - Definitions beginning with "MSR_" are MSRs + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within t= he registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_REGS_H_ +#define _CPU_REGS_H_ + +#define MSR_CORE_THREAD_COUNT 0x00= 000035 +#define B_THREAD_COUNT_MASK 0xFF= FF +#define MSR_SPCL_CHIPSET_USAGE_ADDR 0x00= 0001FE +/// +/// Arch-specific MSR defines in SDM +/// @{ + +#define MSR_PLATFORM_INFO 0x00= 0000CE +#define N_PLATFORM_INFO_MIN_RATIO 40 +#define B_PLATFORM_INFO_RATIO_MASK 0xFF +#define N_PLATFORM_INFO_MAX_RATIO 8 +#define B_MSR_PLATFORM_INFO_BIOSGUARD_AVAIL BIT3= 5 +#define N_MSR_PLATFORM_INFO_CONFIG_TDP_NUM_LEVELS_OFFSET 33 +#define V_CONFIG_TDP_NUM_LEVELS_MASK (BIT= 34 | BIT33) +#define B_PLATFORM_INFO_TDC_TDP_LIMIT BIT2= 9 +#define N_PLATFORM_INFO_RATIO_LIMIT 28 +#define B_PLATFORM_INFO_RATIO_LIMIT BIT2= 8 +#define B_PLATFORM_INFO_SAMPLE_PART BIT2= 7 +#define B_PLATFORM_INFO_SMM_SAVE_CONTROL BIT1= 6 +#define N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30 +#define B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET BIT3= 0 +#define B_PLATFORM_INFO_TIMED_MWAIT_SUPPORTED BIT3= 7 +#define B_PLATFORM_INFO_EDRAM_EN BIT5= 7 + +// +// MSR_BROADWELL_PKG_CST_CONFIG_CONTROL: related defines +// +#define B_TIMED_MWAIT_ENABLE BIT3= 1 ///< @todo Remove when bitfield definition is available. +#define V_CSTATE_LIMIT_C1 0x01 +#define V_CSTATE_LIMIT_C3 0x02 +#define V_CSTATE_LIMIT_C6 0x03 +#define V_CSTATE_LIMIT_C7 0x04 +#define V_CSTATE_LIMIT_C7S 0x05 +#define V_CSTATE_LIMIT_C8 0x06 +#define V_CSTATE_LIMIT_C9 0x07 +#define V_CSTATE_LIMIT_C10 0x08 + +#define MSR_PMG_IO_CAPTURE_BASE 0x00= 0000E4 +#define B_MSR_PMG_CST_RANGE (BIT= 18 | BIT17 | BIT16) +#define V_IO_CAPT_LVL2 (0x0= << 16) ///< C3 +#define V_IO_CAPT_LVL3 (0x1= << 16) ///< C6 +#define V_IO_CAPT_LVL4 (0x2= << 16) ///< C7 +#define V_IO_CAPT_LVL5 (0x3= << 16) ///< C8 +#define V_IO_CAPT_LVL6 (0x4= << 16) ///< C9 +#define V_IO_CAPT_LVL7 (0x5= << 16) ///< C10 +#define V_IO_CAPT_LVL2_BASE_ADDR_MASK 0xFF= FF + +#define MSR_TEMPERATURE_TARGET 0x00= 0001A2 +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LOCK BIT3= 1 +#define N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT 24 +#define V_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_OFFSET_MASK 0x3F +#define N_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_OFFSET (16) +#define B_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_MASK (0xF= F << 16) +#define N_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET 8 +#define B_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET (0xF= F << 8) +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_TIME_WINDOW (0x7= F) +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_MASK 0xFF +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_CLAMP_BIT BIT7 + + +#define MSR_TURBO_RATIO_LIMIT 0x00= 0001AD +#define N_MSR_TURBO_RATIO_LIMIT_1C 0 +#define B_MSR_TURBO_RATIO_LIMIT_1C (0xF= F << 0) +#define N_MSR_TURBO_RATIO_LIMIT_2C 8 +#define B_MSR_TURBO_RATIO_LIMIT_2C (0xF= F << 8) +#define N_MSR_TURBO_RATIO_LIMIT_3C 16 +#define B_MSR_TURBO_RATIO_LIMIT_3C (0xF= F << 16) +#define N_MSR_TURBO_RATIO_LIMIT_4C 24 +#define B_MSR_TURBO_RATIO_LIMIT_4C (0xF= F << 24) +#define N_MSR_TURBO_RATIO_LIMIT_5C 32 +#define B_MSR_TURBO_RATIO_LIMIT_5C (0xF= F << 32) +#define N_MSR_TURBO_RATIO_LIMIT_6C 40 +#define B_MSR_TURBO_RATIO_LIMIT_6C (0xF= F << 40) +#define N_MSR_TURBO_RATIO_LIMIT_7C 48 +#define B_MSR_TURBO_RATIO_LIMIT_7C (0xF= F << 48) +#define N_MSR_TURBO_RATIO_LIMIT_8C 56 +#define B_MSR_TURBO_RATIO_LIMIT_8C (0xF= F << 56) + +#define MSR_IA32_FEATURE_CONFIG 0x00= 00013C +#define B_IA32_FEATURE_CONFIG_AES_DIS BIT1 +#define B_IA32_FEATURE_CONFIG_LOCK BIT0 + +// +// MSRs for SMM State Save Register +// +#define MSR_SMM_MCA_CAP 0x00= 00017D +#define B_TARGETED_SMI BIT5= 6 +#define N_TARGETED_SMI 56 +#define B_SMM_CPU_SVRSTR BIT5= 7 +#define N_SMM_CPU_SVRSTR 57 +#define B_SMM_CODE_ACCESS_CHK BIT5= 8 +#define N_SMM_CODE_ACCESS_CHK 58 +#define B_LONG_FLOW_INDICATION BIT5= 9 +#define N_LONG_FLOW_INDICATION 59 +#define MSR_SMM_FEATURE_CONTROL 0x00= 0004E0 +#define B_SMM_FEATURE_CONTROL_LOCK BIT0 +#define B_SMM_CPU_SAVE_EN BIT1 +#define B_SMM_CODE_CHK_EN BIT2 + +/// @} + + +/// +/// Bit defines for MSRs defined in UefiCpuPkg/Include/Register/Architectu= ralMsr.h. +/// @{ + +// +// Number of fixed MTRRs +// +#define V_FIXED_MTRR_NUMBER 11 + +// +// Number of variable MTRRs +// +#define V_MAXIMUM_VARIABLE_MTRR_NUMBER 10 + +// +// Bit defines for MSR_IA32_MTRR_DEF_TYPE +// +#define B_CACHE_MTRR_VALID BIT1= 1 +#define B_CACHE_FIXED_MTRR_VALID BIT1= 0 + +// +// Bit defines for MSR_IA32_DEBUG_INTERFACE +// +#define B_DEBUG_INTERFACE_ENABLE BIT0 +#define B_DEBUG_INTERFACE_LOCK BIT3= 0 +#define B_DEBUG_INTERFACE_DEBUG_STATUS BIT3= 1 + +/// @} + +/// +/// Other defines +/// +#ifndef TRIGGER_MODE_EDGE +#define TRIGGER_MODE_EDGE 0x00 +#endif +#ifndef TRIGGER_MODE_LEVEL +#define TRIGGER_MODE_LEVEL 0x01 +#endif + +#ifndef CPU_FEATURE_DISABLE +#define CPU_FEATURE_DISABLE 0 +#endif +#ifndef CPU_FEATURE_ENABLE +#define CPU_FEATURE_ENABLE 1 +#endif + +#define CACHE_UNCACHEABLE 0 +#define CACHE_WRITECOMBINING 1 +#define CACHE_WRITETHROUGH 4 +#define CACHE_WRITEPROTECTED 5 +#define CACHE_WRITEBACK 6 + + +// +// Processor Definitions +// +#define CPUID_FULL_STEPPING 0x0000000F +#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0 +#define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF +#define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0 +#define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0 +#define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670 + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_MILLI_SECOND +#define STALL_ONE_MILLI_SECOND 1000 +#endif + +#define BITS(x) (1 << (x)) + +/** +Notes : + 1. Bit position always starts at 0. + 2. Following macros are applicable only for Word aligned integers. +**/ +#define BIT(Pos, Value) (1 << (Pos) & (Value)) +#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width= )) - 1)) + +/// +/// Enums for CPU Family IDs +/// +typedef enum { + EnumCpuCflUltUlx =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, + EnumCpuCflDtHalo =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO, + EnumCpuCnlDtHalo =3D CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO, + EnumCpuMax =3D CPUID_FULL_FAMILY_MODEL +} CPU_FAMILY; + +/// +/// Enums for CPU Stepping IDs +/// +typedef enum { + /// + /// Coffeelake ULX/ULT Steppings + /// + EnumKblH0 =3D 9, + EnumCflD0 =3D 0xA, + + /// Whiskey Lake ULT Steppings + EnumCflW0 =3D 0xB, + EnumCflV0 =3D 0xC, + + EnumCflMaxUltUlxStep =3D EnumCflV0, + + /// + /// Coffeelake DT/Halo Steppings + /// + EnumCflU0 =3D 0xA, + EnumCflB0 =3D 0xB, + EnumCflP0 =3D 0xC, + EnumCflR0 =3D 0xD, + EnumCflMaxDtHaloStep =3D EnumCflR0, + + /// + /// Max Stepping + /// + EnumCpuSteppingMax =3D CPUID_FULL_STEPPING +} CPU_STEPPING; + +/// +/// Enums for CPU SKU IDs +/// +typedef enum { + EnumCpuUlt =3D 0, + EnumCpuTrad, + EnumCpuUlx, + EnumCpuHalo, + EnumCpuUnknown +} CPU_SKU; + +/// +/// Enums for CPU Generation +/// +typedef enum { + EnumCflCpu =3D 0, + EnumCpuUnknownGeneration =3D 255 +} CPU_GENERATION; +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMail= boxLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailbo= xLib.h new file mode 100644 index 0000000000..79dff36783 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.= h @@ -0,0 +1,90 @@ +/** @file + Header file for Cpu Mailbox Lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_MAILBOX_LIB_H_ +#define _CPU_MAILBOX_LIB_H_ + +// +// Mailbox Related Definitions +// + +/** + Generic Mailbox function for mailbox write commands. This function will + poll the mailbox interface for control, issue the write request, poll + for completion, and verify the write was succussful. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[in] MailboxData Overclocking mailbox interface data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status values are: + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_STATUS + - EFI_SUCCESS Command succeeded. + - EFI_INVALID_PARAMETER Invalid read data detected from pcode. + - EFI_UNSUPPORTED Unsupported MailboxType parameter. +**/ +EFI_STATUS +EFIAPI +MailboxWrite ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + IN UINT32 MailboxData, + OUT UINT32 *MailboxStatus + ); + +/** + Generic Mailbox function for mailbox read commands. This function will w= rite + the read request from MailboxType, and populate the read results in the = MailboxDataPtr. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[out] *MailboxDataPtr Pointer to the overclocking mailbox interfac= e data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status are + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_STATUS + - EFI_SUCCESS Command succeeded. + - EFI_INVALID_PARAMETER Invalid read data detected from pcode. + - EFI_UNSUPPORTED Unsupported MailboxType parameter. + +**/ +EFI_STATUS +EFIAPI +MailboxRead ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + OUT UINT32 *MailboxDataPtr, + OUT UINT32 *MailboxStatus + ); + +/** + Poll the run/busy bit of the mailbox until available or timeout expires. + + @param[in] MailboxType + + @retval EFI_STATUS + - EFI_SUCCESS Command succeeded. + - EFI_TIMEOUT Command timeout. +**/ +EFI_STATUS +EFIAPI +PollMailboxReady ( + IN UINT32 MailboxType + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlat= formLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatf= ormLib.h new file mode 100644 index 0000000000..a2dc83efb5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib= .h @@ -0,0 +1,118 @@ +/** @file + Header file for CpuPlatform Lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PLATFORM_LIB_H_ +#define _CPU_PLATFORM_LIB_H_ + +#include +#include +#include + +/** + Check CPU Type of the platform + + @retval CPU_FAMILY CPU type +**/ +CPU_FAMILY +EFIAPI +GetCpuFamily ( + VOID + ); + +/** + Return Cpu stepping type + + @retval CPU_STEPPING Cpu stepping type +**/ +CPU_STEPPING +EFIAPI +GetCpuStepping ( + VOID + ); + +/** + Return CPU Sku + + @retval UINT8 CPU Sku +**/ +UINT8 +EFIAPI +GetCpuSku ( + VOID + ); + +/** + Returns the processor microcode revision of the processor installed in t= he system. + + @retval Processor Microcode Revision +**/ +UINT32 +GetCpuUcodeRevision ( + VOID + ); + +/** + Check if this microcode is correct one for processor + + @param[in] Cpuid - processor CPUID + @param[in] MicrocodeEntryPoint - entry point of microcode + @param[in] Revision - revision of microcode + + @retval CorrectMicrocode if this microcode is correct +**/ +BOOLEAN +CheckMicrocode ( + IN UINT32 Cpuid, + IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint, + IN UINT32 *Revision + ); + +/** + Check on the processor if SGX is supported. + + @retval True if SGX supported or FALSE if not +**/ +BOOLEAN +IsSgxSupported ( + VOID + ); + +/** + Get processor generation + + @retval CPU_GENERATION Returns the executing thread's processor generat= ion. +**/ +CPU_GENERATION +GetCpuGeneration ( + VOID + ); + +/** + Check if Disable CPU Debug (DCD) bit is set from FIT CPU Debugging [Disa= bled]. + If it is set, CPU probe mode is disabled. + + @retval TRUE DCD is set + @retval FALSE DCD is clear +**/ +BOOLEAN +IsCpuDebugDisabled ( + VOID + ); + +/** + Is Whiskey Lake CPU. + + @retval TRUE The CPUID corresponds with a Whiskey Lake CPU + @retval FALSE The CPUID does not correspond with a Whiskey Lake CPU +**/ +BOOLEAN +IsWhlCpu ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPoli= cyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyL= ib.h new file mode 100644 index 0000000000..88f4353e91 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h @@ -0,0 +1,84 @@ +/** @file + Prototype of the CpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_LIB_H_ +#define _CPU_POLICY_LIB_H_ + +#include + +/** + Print whole CPU related config blocks of SI_PREMEM_POLICY_PPI and serial= out. + + @param[in] SiPreMemPolicyPpi The Si PreMem Policy PPI instan= ce +**/ +VOID +CpuPreMemPrintPolicy ( +IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi +); + +/** + Get CPU PREMEM config block table total size. + + @retval Size of CPU PREMEM config block table +**/ +UINT16 +EFIAPI +CpuGetPreMemConfigBlockTotalSize ( + VOID + ); + +/** + CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM conf= ig blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddPreMemConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +/** + Print whole CPU config blocks of SiPolicyPpi and serial out. + + @param[in] SiPolicyPpi The SI Policy PPI instance +**/ +VOID +CpuPrintPolicy ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get CPU config block table total size. + + @retval Size of CPU config block table +**/ +UINT16 +EFIAPI +CpuGetConfigBlockTotalSize ( + VOID + ); + +/** + CpuAddConfigBlocks add all Cpu config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU config bloc= ks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _PEI_CPU_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInf= o.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h new file mode 100644 index 0000000000..67f88ce987 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h @@ -0,0 +1,123 @@ +/** @file + Protocol used to report CPU information + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_INFO_H_ +#define _CPU_INFO_H_ + +#include + +typedef struct _CPU_INFO_PROTOCOL CPU_INFO_PROTOCOL; + + +extern EFI_GUID gCpuInfoProtocolGuid; + +// +// DXE_CPU_INFO_PROTOCOL revisions +// +#define CPU_INFO_PROTOCOL_REVISION 1 + +// +// Processor feature definitions. +// +#define TXT_SUPPORT BIT0 +#define VMX_SUPPORT BIT1 +#define XD_SUPPORT BIT2 +#define DCA_SUPPORT BIT3 +#define X2APIC_SUPPORT BIT4 +#define AES_SUPPORT BIT5 +#define HT_SUPPORT BIT6 +#define DEBUG_SUPPORT BIT7 +#define DEBUG_LOCK_SUPPORT BIT8 +#define PROC_TRACE_SUPPORT BIT9 +#define HDC_SUPPORT BIT10 + + +#pragma pack(1) +/// +/// Cache descriptor information +/// +typedef struct { + UINT8 Desc; ///< Cache Descriptor + UINT8 Level; ///< Cache Level + UINT8 Type; ///< Cache Type. 0: Dat= a, 1: Instruction, 3: Unified + UINT32 Size; ///< Cache Size. + UINT16 Associativity; ///< Cache Ways of Asso= ciativity. +} CACHE_DESCRIPTOR_INFO; + +/// +/// Processor information +/// +typedef struct { + UINT32 CpuSignature; ///< Processor signatu= re and version information. + UINT64 Features; ///< Features availabi= lity in the CPU based on reading ECX after doing Asmcpuid(EAX=3D1). + CHAR8 *BrandString; ///< Processor Brand S= tring. + UINT8 NumSupportedCores; ///< Total Number of S= upported Cores in CPU Package. If Dual core, 2 cores. + UINT8 NumSupportedThreadsPerCore; ///< Number of Support= ed Threads per Core. + UINT8 NumCores; ///< Number of Enabled= or Active Cores. + UINT8 NumHts; ///< Number of Enabled= Threads per Core. This will be 1 or 2. + UINT32 IntendedFreq; ///< Maximum non turbo= ratio in MHz + UINT32 ActualFreq; ///< Actual frequency = in MHz + UINT32 Voltage; ///< Current operating= voltage. + CACHE_DESCRIPTOR_INFO *CacheInfo; ///< Cache descriptor = information. + UINT8 MaxCacheSupported; ///< Maximum cache sup= ported. + UINT8 SmmbaseSwSmiNumber; ///< Software SMI Numb= er from Smbase. @Note: This is unused. + UINT16 NumberOfPStates; ///< Number of P-State= s. +} CPU_INFO; + +/// +/// This HOB is data structure representing two different address location= in SMRAM to hold SMRAM CPU DATA. +/// +typedef struct { + EFI_PHYSICAL_ADDRESS LockBoxData; ///< First location (address) of SMRA= M CPU DATA. + EFI_PHYSICAL_ADDRESS SmramCpuData; ///< Second location (Address) of SMR= AM CPU DATA. + UINT64 LockBoxSize; ///< Size of SMRAM CPU DATA. +} SMRAM_CPU_INFO; + +/// +/// SGX Information +/// +typedef struct { + UINT64 SgxSinitNvsData; ///< Sinit SE SVN Version saved and passed bac= k in next boot +} SGX_INFO; + +#pragma pack() + +/// +/// This protocol provides information about the common features available= in this CPU. +/// +struct _CPU_INFO_PROTOCOL { + /** + Revision for the protocol structure. + Any backwards compatible changes to this protocol will result in an upda= te in the revision number. + Major changes will require publication of a new protocol + + Revision 1: + - Initial version + **/ + UINT8 Revision; + /** + CPU Supported Feature. + - BIT0: If set then processor supports TXT. + - BIT1: If set then processor supports virtual mode extensions. + - BIT2: If set then processor supports execute disable bit. + - BIT3: If set then processor supports DCA. + - BIT4: If set then processor supports X2APIC. + - BIT5: If set then processor supports Advanced Encryption Standard. + - BIT6: If set then processor supports hyperthreading. + - BIT7: If set then processor supports debug interface. + - BIT8: If set then processor supports debug interface lock. + - BIT9: If set then processor supports processor trace. + - BIT10: If Set then processor supports supports HDC. + **/ + UINT64 CpuCommonFeatures; + CPU_INFO *CpuInfo; ///< Processor Basic Information + SMRAM_CPU_INFO *SmramCpuInfo; ///< SMRAM CPU Information + SGX_INFO *SgxInfo; ///< SGX Information +}; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPol= icyProtocol.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/Cpu= PolicyProtocol.h new file mode 100644 index 0000000000..ed056025b7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProt= ocol.h @@ -0,0 +1,50 @@ +/** @file + Protocol used for specifying platform related CPU information and policy= setting. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_PROTOCOL_H_ +#define _CPU_POLICY_PROTOCOL_H_ + +// +// DXE_CPU_POLICY_PROTOCOL revisions +// +#define DXE_CPU_POLICY_PROTOCOL_REVISION 1 + +extern EFI_GUID gDxeCpuPolicyProtocolGuid; + +#pragma pack (push,1) + +/** + The protocol allows the platform code to publish a set of configuration = information that the + CPU drivers will use to configure the processor in the DXE phase. + This Policy Protocol needs to be initialized for CPU configuration. + @note The Protocol has to be published before processor DXE drivers are = dispatched. +**/ +typedef struct { + /** + This member specifies the revision of the Cpu Policy protocol. This fiel= d is used to indicate backward + compatible changes to the protocol. Any such changes to this protocol wi= ll result in an update in the revision number. + + Revision 1: + - Initial version + **/ + /** + Policies to obtain CPU temperature. + - 0: ACPI thermal management uses EC reported temperature values= . + - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU tempe= rature values. + - 2: ACPI Thermal Management uses EC reported temperature values and DT= S SMM is used to handle Out of Spec condition. + **/ + UINT32 EnableDts : 2; + UINT32 RsvdBit : 30; ///< Reserved = bits, align to multiple 32; + + UINT8 Revision; ///< Current r= evision of policy. + UINT8 ReservedByte[3]; ///< Reserved = bytes, align to multiple 8. +} DXE_CPU_POLICY_PROTOCOL; + +#pragma pack (pop) + +#endif --=20 2.16.2.windows.1