From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by groups.io with SMTP; Fri, 16 Aug 2019 17:51:57 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:51:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="168201620" Received: from orsmsx109.amr.corp.intel.com ([10.22.240.7]) by orsmga007.jf.intel.com with ESMTP; 16 Aug 2019 17:51:56 -0700 Received: from orsmsx158.amr.corp.intel.com (10.22.240.20) by ORSMSX109.amr.corp.intel.com (10.22.240.7) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 16 Aug 2019 17:51:56 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.96]) by ORSMSX158.amr.corp.intel.com ([169.254.10.29]) with mapi id 14.03.0439.000; Fri, 16 Aug 2019 17:51:56 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers Thread-Topic: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers Thread-Index: AQHVVJET9cKn08xio0mrOJwC1xJKKqb+gshw Date: Sat, 17 Aug 2019 00:51:55 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE128EB@ORSMSX114.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-12-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-12-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTdmMTk5YjEtNDAzYS00MWVmLTgwMDYtNzk0YmNhOThkYzhkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMXgzQXFIa1hIYTU2V0VvYllXZnJiWW0wenZQUTNiQTFBTkFYZVhEbDFER0NCWnViM2V4YVVjOWJsTXExK3VnRiJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:16 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Gao, Liming ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Pri= vate/Protocol include headers REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the following header files: * Pch/Include/Private/Protocol Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea= .h | 31 ++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Pr= ivate/Protocol/PcieIoTrap.h | 37 ++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protoco= l/PchNvsArea.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Pro= tocol/PchNvsArea.h new file mode 100644 index 0000000000..75003c82ad --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc +++ hNvsArea.h @@ -0,0 +1,31 @@ +/** @file + This file defines the PCH NVS Area Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_NVS_AREA_H_ +#define _PCH_NVS_AREA_H_ + +// +// PCH NVS Area definition +// +#include + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchNvsAreaProtocolGuid; + +/** + This protocol is used to sync PCH information from POST to runtime ASL. + This protocol exposes the pointer of PCH NVS Area only. Please refer=20 +to + ASL definition for PCH NVS AREA. +**/ +typedef struct { + PCH_NVS_AREA *Area; +} PCH_NVS_AREA_PROTOCOL; + +#endif // _PCH_NVS_AREA_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protoco= l/PcieIoTrap.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Pro= tocol/PcieIoTrap.h new file mode 100644 index 0000000000..2cd6b85d29 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/Pc +++ ieIoTrap.h @@ -0,0 +1,37 @@ +/** @file + This file defines the PCH PCIE IoTrap Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_PCIE_IOTRAP_H_ +#define _PCH_PCIE_IOTRAP_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchPcieIoTrapProtocolGuid; + +// +// Forward reference for ANSI C compatibility // typedef struct=20 +_PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL; + +/// +/// Pcie Trap valid types +/// +typedef enum { + PciePmTrap, + PcieTrapTypeMaximum +} PCH_PCIE_TRAP_TYPE; + +/** + This protocol is used to provide the IoTrap address to trigger PCH=20 +PCIE call back events **/ struct _PCH_PCIE_IOTRAP_PROTOCOL { + UINT16 PcieTrapAddress; +}; + +#endif -- 2.16.2.windows.1