From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by groups.io with SMTP; Fri, 16 Aug 2019 17:52:08 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:52:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="261263813" Received: from orsmsx102.amr.corp.intel.com ([10.22.225.129]) by orsmga001.jf.intel.com with ESMTP; 16 Aug 2019 17:52:08 -0700 Received: from orsmsx160.amr.corp.intel.com (10.22.226.43) by ORSMSX102.amr.corp.intel.com (10.22.225.129) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 16 Aug 2019 17:52:07 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.96]) by ORSMSX160.amr.corp.intel.com ([169.254.13.75]) with mapi id 14.03.0439.000; Fri, 16 Aug 2019 17:52:07 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: Add Include headers Thread-Topic: [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: Add Include headers Thread-Index: AQHVVJEUdprTq/0j3U+5QKXD9JDsxqb+gtNA Date: Sat, 17 Aug 2019 00:52:06 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE12923@ORSMSX114.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-14-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-14-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWQyYTQ0ZmQtMGYzYS00Y2E4LTkzZDItN2U4NjRjNjg2NDExIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoib3JYM1hadStUdFwvY0JQcTBVK0tTK2JWQ0F2aEs5bUJoUWZCZ21DUXpNbU4xUWJndHN2R1NMN3luWjArT0NoVGYifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:16 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Gao, Liming ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent:= Add Include headers REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files common to System Agent (SA) modules. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/GnaConf= ig.h | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic= sDxeConfig.h | 53 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic= sPeiConfig.h | 96 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic= sPeiPreMemConfig.h | 70 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/IpuPreM= emConfig.h | 46 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryC= onfig.h | 534 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryD= xeConfig.h | 61 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/MiscDxe= Config.h | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/OverClo= ckingConfig.h | 51 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxe= Config.h | 135 +++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PciePei= Config.h | 60 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PciePei= PreMemConfig.h | 354 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscP= eiConfig.h | 61 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscP= eiPreMemConfig.h | 103 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Switcha= bleGraphicsConfig.h | 63 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VbiosDx= eConfig.h | 39 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdConf= ig.h | 42 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTable.h= | 77 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicy= Lib.h | 60 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicy= Lib.h | 87 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlatformL= ib.h | 88 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h = | 259 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Gra= phicsInitLib.h | 15 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Leg= acyRegion.h | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Pei= CpuTraceHubLib.h | 23 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/SaP= cieLib.h | 70 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/Sa= IotrapSmi.h | 36 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/Sa= NvsArea.h | 31 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConfigHob= .h | 89 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsAreaDe= f.h | 151 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopCompone= ntName2.h | 63 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPolicy.= h | 73 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRegio= n.h | 24 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemInfo.h = | 132 +++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h= | 66 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsGna.= h | 32 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHost= Bridge.h | 214 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIgd.= h | 50 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIpu.= h | 37 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsPeg.= h | 64 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h = | 106 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefinitions= .h | 23 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLib.h = | 25 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.h = | 51 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h = | 32 ++ 45 files changed, 3845 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GnaConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/C= onfigBlock/GnaConfig.h new file mode 100644 index 0000000000..020a4aeab5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gn= aConfig.h @@ -0,0 +1,33 @@ +/** @file + Policy definition for GNA Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GNA_CONFIG_H_ +#define _GNA_CONFIG_H_ +#pragma pack(push, 1) + +#define GNA_CONFIG_REVISION 1 +/** + GNA config block for configuring GNA.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 C= onfig Block Header + /** + Offset 28:0 + This policy enables the GNA Device (SA Device 8) if supported. + If FALSE, all other policies in this config block will be ignored. + 1=3DTRUE; + 0=3DFALSE. + **/ + UINT32 GnaEnable : 1; + UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved f= or future use +} GNA_CONFIG; +#pragma pack(pop) + +#endif // _GNA_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GraphicsDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/I= nclude/ConfigBlock/GraphicsDxeConfig.h new file mode 100644 index 0000000000..cc337a83f3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gr= aphicsDxeConfig.h @@ -0,0 +1,53 @@ +/** @file + Graphics DXE Policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_DXE_CONFIG_H_ +#define _GRAPHICS_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define GRAPHICS_DXE_CONFIG_REVISION 2 + +#define MAX_BCLM_ENTRIES 20 + +/** + This configuration block is to configure IGD related variables used in D= XE. + If Intel Gfx Device is not supported or disabled, all policies will be i= gnored. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. + Revision 2: + - Adding BCLM[MAX_BCLM_ENTRIES] +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header + UINT32 Size; ///< Offset 28 - 31: Thi= s field gives the size of the GOP VBT Data buffer + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: Thi= s field points to the GOP VBT data buffer + UINT8 PlatformConfig; ///< Offset 40: This fie= ld gives the Platform Configuration Information (0=3DPlatform is S0ix Capab= le for ULT SKUs only, 1=3DPlatform is not S0ix Capable, 2=3DForce Pl= atform is S0ix Capable for All SKUs) + UINT8 AlsEnable; ///< Offset 41: Ambient = Light Sensor Enable: 0=3DDisable, 2=3DEnable + UINT8 BacklightControlSupport; ///< Offset 42: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdBootType; ///< Offset 43: IGD Boot= Type CMOS option: 0=3DDefault, 0x01=3DCRT, 0x04=3DEFP, 0x08=3DLFP, = 0x20=3DEFP3, 0x40=3DEFP2, 0x80=3DLFP2 + UINT32 IuerStatusVal; ///< Offset 44 - 47: Off= set 16 This field holds the current status of all the supported Ultrabook e= vents (Intel(R) Ultrabook Event Status bits) + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This= field holds the GOP Driver Version. It is an Output Protocol and updated b= y the Silicon code + /** + Offset 80: IGD Panel Type CMOS option\n + 0=3DDefault, 1=3D640X480LVDS, 2=3D800X600LVDS, 3=3D1024X768LVDS= , 4=3D1280X1024LVDS, 5=3D1400X1050LVDS1\n + 6=3D1400X1050LVDS2, 7=3D1600X1200LVDS, 8=3D1280X768LVDS, 9=3D1680X1050= LVDS, 10=3D1920X1200LVDS, 13=3D1600X900LVDS\n + 14=3D1280X800LVDS, 15=3D1280X600LVDS, 16=3D2048X1536LVDS, 17=3D1366X76= 8LVDS + **/ + UINT8 IgdPanelType; + UINT8 IgdPanelScaling; ///< Offset 81: IGD Pane= l Scaling: 0=3DAUTO, 1=3DOFF, 6=3DForce scaling + UINT8 IgdBlcConfig; ///< Offset 82: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdDvmtMemSize; ///< Offset 83: IGD DVMT= Memory Size: 1=3D128MB, 2=3D256MB, 3=3DMAX + UINT8 GfxTurboIMON; ///< Offset 84: IMON Cur= rent Value: 14=3DMinimal, 31=3DMaximum + UINT8 Reserved[3]; ///< Offset 85: Reserved= for DWORD alignment. + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Back= light Brightness Level Duty cycle Mapping Table. +} GRAPHICS_DXE_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GraphicsPeiConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/I= nclude/ConfigBlock/GraphicsPeiConfig.h new file mode 100644 index 0000000000..276289ae81 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gr= aphicsPeiConfig.h @@ -0,0 +1,96 @@ +/** @file + Policy definition for Internal Graphics Config Block (PostMem) + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_PEI_CONFIG_H_ +#define _GRAPHICS_PEI_CONFIG_H_ +#pragma pack(push, 1) + +#define GRAPHICS_PEI_CONFIG_REVISION 4 +#define DDI_DEVICE_NUMBER 4 + +// +// DDI defines +// +typedef enum { + DdiDisable =3D 0x00, + DdiDdcEnable =3D 0x01, + DdiTbtLsxEnable =3D 0x02, +} DDI_DDC_TBT_VAL; + +typedef enum { + DdiHpdDisable =3D 0x00, + DdiHpdEnable =3D 0x01, +} DDI_HPD_VAL; + +typedef enum { + DdiPortADisabled =3D 0x00, + DdiPortAEdp =3D 0x01, + DdiPortAMipiDsi =3D 0x02, +} DDI_PORTA_SETTINGS; +/** + This structure configures the Native GPIOs for DDI port per VBT settings= . +**/ +typedef struct { + UINT8 DdiPortEdp; /// The setting of eDP port, this settings must mat= ch VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortDHpd; /// The HPD setting of DDI Port D, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortFHpd; /// The HPD setting of DDI Port F, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortDDdc; /// The DDC setting of DDI Port D, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortFDdc; /// The DDC setting of DDI Port F, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 Rsvd[3]; ///< Reserved for 4 bytes alignment +} DDI_CONFIGURATION; + +/** + This configuration block is to configure IGD related variables used in P= ostMem PEI. + If Intel Gfx Device is not supported, all policies can be ignored. + Revision 1: + - Initial version. + Revision 2: + - Added SkipS3CdClockInit. + Revision 3: + - Added DeltaT12PowerCycleDelay, BltBufferAddress, BltBufferSize. + Revision 4: + - Deprecated DeltaT12PowerCycleDelay. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + UINT32 RenderStandby : 1; ///< Offset 28:0 :(Te= st) This field is used to enable or disable RC6 (Render Standby): 0=3DF= ALSE, 1=3DTRUE + UINT32 PmSupport : 1; ///< Offset 28:1 :(Te= st) IGD PM Support TRUE/FALSE: 0=3DFALSE, 1=3DTRUE + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PA= VP TRUE/FALSE: 0=3DFALSE, 1=3DTRUE + /** + Offset 28:3 + CdClock Frequency select\n + CFL\n + 0 =3D 337.5 Mhz, 1 =3D 450 Mhz,\n + 2 =3D 540 Mhz, 3 =3D 675 Mhz,\n + + **/ + UINT32 CdClock : 3; + UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 : This = policy is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enabl= e + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This = policy is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enabl= e, 0- Disable + UINT32 GtFreqMax : 8; ///< Offset 28:8 : (T= est) Max GT frequency limited by user in multiples of 50MHz: Default va= lue which indicates normal frequency is 0xFF + UINT32 DisableTurboGt : 1; ///< Offset 28:9 : This = policy is used to enable/disable DisableTurboGt 0- Disable, 1- Enabl= e + UINT32 RsvdBits0 : 15; ///< Offser 28:15 :Reser= ved for future use + VOID* LogoPtr; ///< Offset 32 Address o= f Intel Gfx PEIM Logo to be displayed + UINT32 LogoSize; ///< Offset 36 Intel Gfx= PEIM Logo Size + VOID* GraphicsConfigPtr; ///< Offset 40 Address o= f the Graphics Configuration Table + DDI_CONFIGURATION DdiConfiguration; ///< Offset 44 DDI confi= guration, need to match with VBT settings. + UINT32 SkipS3CdClockInit : 1; ///< Offset 56 SKip full= CD clock initialization being done during S3 resume.0- Disable<\b>, 1- = Enable + UINT32 ReservedBits : 31; ///< Offset 56: 1 : Rese= rved for future use. + UINT16 DeltaT12PowerCycleDelay; ///< Offset 60 @deprecat= ed Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms<\b>,= 0xFFFF - Auto calculate to max 500 ms + UINT8 Reserved[2]; ///< Offset 62 Reserved = for future use. + VOID* BltBufferAddress; ///< Offset 64 Address o= f Blt buffer for PEIM Logo use + UINT32 BltBufferSize; ///< Offset 68 The size = for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size= of EFI_GRAPHICS_OUTPUT_BLT_PIXEL) +} GRAPHICS_PEI_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GraphicsPeiPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemA= gent/Include/ConfigBlock/GraphicsPeiPreMemConfig.h new file mode 100644 index 0000000000..4986fdab60 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gr= aphicsPeiPreMemConfig.h @@ -0,0 +1,70 @@ +/** @file + Policy definition for Internal Graphics Config Block (PreMem) + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_PEI_PREMEM_CONFIG_H_ +#define _GRAPHICS_PEI_PREMEM_CONFIG_H_ +#pragma pack(push, 1) + +#define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 2 + + +/** + This Configuration block is to configure GT related PreMem data/variable= s.\n + Revision 1: + - Initial version. + Revision 2: + - Added DeltaT12PowerCycleDelayPreMem. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + /** + Offset 28:0 + Selection of the primary display device: 0=3DiGFX, 1=3DPEG, 2=3DPCIe G= raphics on PCH, 3=3DAUTO, 4=3DSwitchable Graphics\n + When AUTO mode selected, the priority of display devices is: PCIe Grap= hics on PCH > PEG > iGFX + **/ + UINT32 PrimaryDisplay : 3; + /** + Offset 28:3 + Intel Gfx Support. It controls enabling/disabling iGfx device. + When AUTO mode selected, iGFX will be turned off when external graphic= s detected. + If FALSE, all other polices can be ignored. + 2 =3D AUTO; + 0 =3D FALSE; + 1 =3D TRUE. + **/ + UINT32 InternalGraphics : 2; + /** + Offset 28:5 + Pre-allocated memory for iGFX\n + 0 =3D 0MB,1 or 247 =3D 32MB,\n + 2 =3D 64MB,\n + 240 =3D 4MB, 241 =3D 8MB,\n + 242 =3D 12MB, 243 =3D 16MB,\n + 244 =3D 20MB, 245 =3D 24MB,\n + 246 =3D 28MB, 248 =3D 36MB,\n + 249 =3D 40MB, 250 =3D 44MB,\n + 251 =3D 48MB, 252 =3D 52MB,\n + 253 =3D 56MB, 254 =3D 60MB,\n + Note: enlarging pre-allocated memory for iGFX may need to reduce Mm= ioSize because of 4GB boundary limitation + **/ + UINT32 IgdDvmt50PreAlloc : 8; + UINT32 PanelPowerEnable : 1; ///< Offset 28:13 = :(Test) Control for enabling/disabling VDD force bit (Required only = for early enabling of eDP panel): 0=3DFALSE, 1=3DTRUE + UINT32 ApertureSize : 7; ///< Offser 28:14 = :Graphics aperture size (256MB is the recommended size as per BWG) : 0=3D12= 8MB, 1=3D256MB, 3=3D512MB, 7=3D1024MB, 15=3D2048MB. + UINT32 GtPsmiSupport : 1; ///< Offser 28:21 = :PSMI support On/Off: 0=3DFALSE, 1=3DTRUE + UINT32 PsmiRegionSize : 3; ///< Offser 28:22 = :Psmi region size: 0=3D32MB, 1=3D288MB, 2=3D544MB, 3=3D800MB, 4=3D10= 56MB + UINT32 RsvdBits0 : 7; ///< Offser 28:25 = :Reserved for future use + UINT32 GttMmAdr; ///< Offset 32 Tem= p Address of System Agent GTTMMADR : Default is 0xCF000000< / b> + UINT16 GttSize; ///< Offset 36 Sel= ection of iGFX GTT Memory size: 1=3D2MB, 2=3D4MB, 3=3D8MB + UINT8 Rsvd1[2]; ///< Offset 38 Res= erved for DWORD alignment + UINT32 GmAdr; ///< Offset 40 Tem= p Address of System Agent GMADR : Default is 0xD0000000< / b> + UINT16 DeltaT12PowerCycleDelayPreMem; ///< Offset 44 Pow= er Cycle Delay required for eDP as per VESA standard.0 - 0 ms<\b>, 0xFFF= F - Auto calculate to max 500 ms + UINT8 Reserved[2]; ///< Offset 46 Res= erved for future use. +} GRAPHICS_PEI_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_PEI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/IpuPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inc= lude/ConfigBlock/IpuPreMemConfig.h new file mode 100644 index 0000000000..79025d16fe --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Ip= uPreMemConfig.h @@ -0,0 +1,46 @@ +/** @file + IPU policy definitions (PreMem) + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPU_CONFIG_PREMEM_H_ +#define _IPU_CONFIG_PREMEM_H_ + +#pragma pack(push, 1) + +#define IPU_PREMEM_CONFIG_REVISION 1 + +#define SA_IMR_IPU_CAMERA 0 +#define SA_IMR_IPU_GEN 1 + +/** + IPU PreMem configuration\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block He= ader + /** + Offset 28:0 : + (Test) It enables the SA IPU Device if supported and not fused of= f. + If FALSE, all other policies in this config block will be ignored. + 1=3DTRUE; + 0=3DFALSE. + **/ + UINT32 SaIpuEnable:1; + /** + Offset 28:1 : + (Test) It configure the IPU IMR to IPU Camera or IPU Gen when IPU= is enabled. + If FALSE, all other policies in this config block will be ignored. + 0=3DIPU Camera; + 1=3DIPU Gen + **/ + UINT32 SaIpuImrConfiguration:1; + UINT32 RsvdBits0:30; /// Offset 28:2 :Reserved fo= r future use. +} IPU_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _IPU_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/MemoryConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Includ= e/ConfigBlock/MemoryConfig.h new file mode 100644 index 0000000000..8374ff5f68 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Me= moryConfig.h @@ -0,0 +1,534 @@ +/** @file + Policy definition of Memory Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMORY_CONFIG_H_ +#define _MEMORY_CONFIG_H_ + +#include + +#pragma pack(push, 1) + +#define SA_MRC_ITERATION_MAX (6) +#define SA_MRC_MAX_RCOMP (3) +#define SA_MRC_MAX_RCOMP_TARGETS (5) + +#define MEMORY_CONFIG_REVISION 3 + +/// +/// SMRAM Memory Range +/// +#define PEI_MR_SMRAM_ABSEG_MASK 0x01 +#define PEI_MR_SMRAM_HSEG_MASK 0x02 + +/// +/// SA SPD profile selections. +/// +typedef enum { + Default, ///< 0, Default SPD + UserDefined, ///< 1, User Defined profile + XMPProfile1, ///< 2, XMP Profile 1 + XMPProfile2, ///< 3, XMP Profile 2 + XMPProfileMax =3D 0xFF ///< Ensures SA_SPD is UINT8 +} SA_SPD; + +/// +/// Define the boot modes used by the SPD read function. +/// +typedef enum { + SpdCold, ///< Cold boot + SpdWarm, ///< Warm boot + SpdS3, ///< S3 resume + SpdFast, ///< Fast boot + SpdBootModeMax ///< Delimiter +} SPD_BOOT_MODE; + +typedef struct { + UINT8 SpdData[SA_MC_MAX_CHANNELS][SA_MC_MAX_SLOTS][SA_MC_MAX_SPD_SIZE]; +//Next Field Offset 2048 +} SPD_DATA_BUFFER; + +typedef struct { + UINT8 DqByteMap[SA_MC_MAX_CHANNELS][SA_MRC_ITERATION_MAX][2]; +//Next Field Offset 24 +} SA_MEMORY_DQ_MAPPING; + +typedef struct { + UINT8 DqsMapCpu2Dram[SA_MC_MAX_CHANNELS][SA_MC_MAX_BYTES_NO_ECC]; +//Next Field Offset 16 +} SA_MEMORY_DQS_MAPPING; + +typedef struct { + UINT16 RcompResistor[SA_MRC_MAX_RCOMP]; ///< Offset 0: Reference = RCOMP resistors on motherboard + UINT16 RcompTarget[SA_MRC_MAX_RCOMP_TARGETS]; ///< Offset 6: RCOMP targ= et values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv +//Next Field Offset 16 +} SA_MEMORY_RCOMP; + +typedef struct { + UINT16 Start; ///< Offset 0 + UINT16 End; ///< Offset 2 + UINT8 BootMode; ///< Offset 4 + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use +} SPD_OFFSET_TABLE; + +/// +/// SA memory address decode. +/// +typedef struct +{ + UINT8 Controller; ///< Offset 0 Zero based Controller number + UINT8 Channel; ///< Offset 1 Zero based Channel number + UINT8 Dimm; ///< Offset 2 Zero based DIMM number + UINT8 Rank; ///< Offset 3 Zero based Rank number + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number + UINT8 Bank; ///< Offset 5 Zero based Bank number + UINT16 Cas; ///< Offset 6 Zero based CAS number + UINT32 Ras; ///< Offset 8 Zero based RAS number +} SA_ADDRESS_DECODE; + +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress)= ; +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress)= ; +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress)= ; +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress,= UINT8 Value); +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress,= UINT16 Value); +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress,= UINT32 Value); +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, U= INT8 Value); +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, U= INT16 Value); +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, U= INT32 Value); +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, U= INT64 Value); +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, R= ETURN_STATUS *Status); +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, R= ETURN_STATUS *Status); +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, U= INT8 Value, RETURN_STATUS *Status); +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, U= INT16 Value, RETURN_STATUS *Status); +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, U= INT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID *GlobalData= ); +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destinatio= n, CONST VOID *Source, UINTN NumBytes); +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UI= NTN NumBytes, UINT8 Value); +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UI= NTN NumWords, UINT16 Value); +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UI= NTN NumDwords, UINT32 Value); +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplic= and, UINT32 Multiplier); +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend,= UINT64 Divisor, UINT64 *Remainder); +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE Bo= otMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3Table= Size, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 Lpd= drTableSize); +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, = SA_ADDRESS_DECODE *DramAddress); +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECOD= E *DramAddress, UINT64 Address); +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UIN= T32 Command, UINT32 *Value, UINT32 *Status); +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UIN= T32 Command, UINT32 Value, UINT32 *Status); +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd); +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd, UINT32 Value); +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData= , UINT32 CheckPoint, VOID *Scratch); +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData= , UINT16 DisplayDebugNumber); +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, U= INT8 Channel); +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UIN= T32 Level, char *Format, ...); +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData= , UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel= , UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWai= t, UINT32 RegFileParam); +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UIN= T8 OldMsb, UINT8 NewMsb); +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData= , UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 Ne= wValue, UINT8 UpdateHost); +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData= , UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 O= ffset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location)= ; +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location,= UINT64 Data); +typedef UINT32 (EFIAPI * SA_THERMAL_OVERRIDES) (VOID *GlobalData= ); +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData= , UINT32 MrcStatus); +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseA= ddress, UINT32 ResetValue); +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT32 PrmrrBase= Address, UINT32 PrmrrSize); + + +/// +/// Function calls into the SA. +/// +typedef struct { + SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU= I/O port 8-bit read. + SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU= I/O port 16-bit read. + SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU= I/O port 32-bit read. + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU= I/O port 8-bit write. + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU= I/O port 16-bit write. + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU= I/O port 32-bit write. + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Mem= ory Mapped I/O port 8-bit read. + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Mem= ory Mapped I/O port 16-bit read. + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Mem= ory Mapped I/O port 32-bit read. + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Mem= ory Mapped I/O port 64-bit read. + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Mem= ory Mapped I/O port 8-bit write. + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Mem= ory Mapped I/O port 16-bit write. + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Mem= ory Mapped I/O port 32-bit write. + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Mem= ory Mapped I/O port 64-bit write. + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smb= us 8-bit read. + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smb= us 16-bit read. + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smb= us 8-bit write. + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smb= us 16-bit write. + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get= PCI device address. + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get= PCI express device address. + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get= the current time value. + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The= current CPU time in milliseconds. + SA_MEMORY_COPY CopyMem; ///< Offset 88: - Per= form byte copy operation. + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Per= form byte initialization operation. + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Per= form word initialization operation. + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Per= form dword initialization operation. + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Lef= t shift the 64-bit data value by specified number of bits. + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Rig= ht shift the 64-bit data value by specified number of bits. + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Mul= tiply a 64-bit data value by a 32-bit data value. + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Div= ide a 64-bit data value by a 64-bit data value. + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Rea= d the SPD data over the SMBus, at the given SmBus SPD address and copy the = data to the data structure. + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get= the next random 32-bit number. + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Per= form a CPU mailbox read. + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Per= form a CPU mailbox write. + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get= the current memory voltage (VDD). + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set= the memory voltage (VDD) to the given value. + SA_CHECKPOINT CheckPoint; ///< Offset 144: - Che= ck point that is called at various points in the MRC. + SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typ= ically used to display to the I/O port 80h. + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Out= put a string to the debug stream/device. + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get= the current value of the specified RTC CMOS location. + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get= the current value of the specified MSR location. + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set= the current value of the specified MSR location. + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hoo= k function after returning from MrcStartMemoryConfiguration() + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Ass= ert or deassert DRAM_RESET# pin; this is used in JEDEC Reset. +} SA_FUNCTION_CALLS; + +/// +/// Function calls into the MRC. +/// +typedef struct { + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Retu= rns whether Channel is or is not present. + SA_PRINTF MrcPrintf; ///< Offset 4: - Prin= t to output stream/device. + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Chan= ge the margin. + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign= extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7). + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move= CMD/CTL/CLK/CKE PIs during training. + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Upda= te the Vref value and wait until it is stable. +} SA_MEMORY_FUNCTIONS; + +/** + Memory Configuration + The contents of this structure are CRC'd by the MRC for option change det= ection. + This structure is copied en mass to the MrcInput structure. If you add fi= elds here, you must update the MrcInput structure. + Revision 1: + - Initial version. + Revision 2: + - Removed GearType. + - Added Lp4DqsOscEn, RMTLoopCount, EnBER, DualDimmPerChannelBoardType. + Revision 3: + - Removed EvLoader, EvLoaderDelay. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + UINT16 Size; ///< Offset 28 The size of this structur= e, in bytes. Must be the first entry in this structure. + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MR= C + + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection= - for XMP supported DIMM: 0=3DDefault DIMM profile, 1=3DCustomized = profile, 2=3DXMP profile 1, 3=3DXMP profile 2. + + // The following parameters are used only when SpdProfileSelected is Use= rDefined (CUSTOM PROFILE) + UINT16 tCL; ///< Offset 32 User defined Memory Timin= g tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 31=3DMaximum. + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timin= g tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE= : 0=3DAUTO, 63=3DMaximum + UINT16 tRAS; ///< Offset 36 User defined Memory Timin= g tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 64=3DMaximum. + UINT16 tWR; ///< Offset 38 User defined Memory Timin= g tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24. + UINT16 tRFC; ///< Offset 40 User defined Memory Timin= g tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 1023=3DMaximum. + UINT16 tRRD; ///< Offset 42 User defined Memory Timin= g tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. + UINT16 tWTR; ///< Offset 44 User defined Memory Timin= g tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 28=3DMaximum. + UINT16 tRTP; ///< Offset 46 User defined Memory Timin= g tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12 + UINT16 tFAW; ///< Offset 48 User defined Memory Timin= g tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 63=3DMaximum. + UINT16 tCWL; ///< Offset 50 User defined Memory Timin= g tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 20=3DMaximum. + UINT16 tREFI; ///< Offset 52 User defined Memory Timin= g tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 65535=3DMaximum. + UINT16 PciIndex; ///< Offset 54 Pci index register addres= s: 0xCF8=3DDefault + UINT16 PciData; ///< Offset 56 Pci data register address= : 0xCFC=3DDefault + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in mil= livolts: 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1.3= 5V etc. + UINT16 Idd3n; ///< Offset 60 EPG Active standby curren= t (Idd3N) in milliamps from DIMM datasheet. + UINT16 Idd3p; ///< Offset 62 EPG Active power-down cur= rent (Idd3P) in milliamps from DIMM datasheet. + + UINT32 EccSupport:1; ///< Offset 64 DIMM Ecc Support = option - for Desktop only: 0=3DDisable, 1=3DEnable + UINT32 MrcSafeConfig:1; ///< - MRC Safe Mode: 0=3DDi= sable, 1=3DEnable + UINT32 RemapEnable:1; ///< - This option is used to c= ontrol whether to enable/disable memory remap above 4GB: 0=3DDisable, 1= =3DEnable. + UINT32 ScramblerSupport:1; ///< - Memory scrambler support= : 0=3DDisable, 1=3DEnable + UINT32 Vc1ReadMeter:1; ///< - VC1 Read Metering Enable= : 0=3DDisable, 1=3DEnable + UINT32 DdrThermalSensor:1; ///< - Ddr Thermal Sensor: 0=3D= Disable, 1=3DEnable + UINT32 LpddrMemWriteLatencySet:1; ///< - LPDDR3 Write Latency Set= option: 0=3DSet A, 1=3DSet B + UINT32 Off64Bits7to8Rsvd:2; ///< - Bit 7-8 Reserved + UINT32 SimicsFlag:1; ///< - Option to Enable SIMICS:= 0=3DDisable, 1=3DEnable + UINT32 Ddr4DdpSharedClock:1; ///< - Select if CLK0 is shared= between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared, 1=3DSh= ared + UINT32 SharedZqPin:1; ///< - Select if ZQ pin is shar= ed between Rank ranks. For CFL, this option only works for DDR4. the opti= on works for LPDDR4 and DDR4. 0=3DNot shared, 1=3DShared + // Thermal Management + UINT32 ThermalManagement:1; ///< - Memory Thermal Man= agement Support: 0=3DDisable, 1=3DEnable. + UINT32 PeciInjectedTemp:1; ///< - Enable/Disable mem= ory temperatures to be injected to the processor via PECI: 0=3DDisable, 1=3DEnable. + UINT32 ExttsViaTsOnBoard:1; ///< - Enable/Disable rou= ting TS-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH: 0=3DDisa= ble, 1=3DEnable. + UINT32 ExttsViaTsOnDimm:1; ///< - Enable/Disable rou= ting TS-on-DIMM's ALERT# to EXTTS# pin on the PCH: 0=3DDisable, 1=3D= Enable. + UINT32 VirtualTempSensor:1; ///< - Enable/Disable Vir= tual Temperature Sensor (VTS): 0=3DDisable, 1=3DEnable. + UINT32 Lp4DqsOscEn :1; ///< - LpDdrDqDqsReTraini= ng - DqDqsReTraining Enable: 0=3DDisable, 1=3DEnable + UINT32 DualDimmPerChannelBoardType:1; ///< - DualDimmPerChannel= BoardType - Option to indicate if the Memory Design for the board includes = two DIMMs per channel: 0=3DSingle DIMM Design, 1=3DDual DIMM Design + UINT32 ReservedBits1:13; + /** + Disables a DIMM slot in the channel even if a DIMM is present\n + Array index represents the channel number (0 =3D channel 0, 1 =3D chann= el 1)\n + 0x0 =3D DIMM 0 and DIMM 1 enabled\n + 0x1 =3D DIMM 0 disabled, DIMM 1 enabled\n + 0x2 =3D DIMM 0 enabled, DIMM 1 disabled\n + 0x3 =3D DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n + **/ + UINT8 DisableDimmChannel[SA_MC_MAX_CHANNELS]; ///< Offset 68 + /** + Selects the ratio to multiply the reference clock by for the DDR freque= ncy\n + When RefClk is 133MHz\n + 0x00 =3D Auto, 0x03 through 0x0C are valid values, all others ar= e invalid\n + When RefClk is 100MHz\n + 0x00 =3D Auto, 0x06 through 0x10 are valid values, all others ar= e invalid\n + **/ + UINT8 Ratio; ///< Offset 70 + UINT8 ProbelessTrace; ///< Offset 71 Probeless Trace: 0=3DD= isabled, 1=3DEnabled + UINT32 BClkFrequency; ///< Offset 72 Base reference clock valu= e, in Hertz: 100000000 =3D 100Hz, 125000000=3D125Hz, 167000000=3D167= Hz, 250000000=3D250Hz + /** + - Channel Hash Enable.\n + NOTE: BIT7 will interleave the channels at a 2 cache-line granularity,= BIT8 at 4 and BIT9 at 8\n + 0=3DBIT6, 1=3DBIT7, 2=3DBIT8, 3=3DBIT9 + **/ + UINT8 ChHashInterleaveBit; ///< Offset 76 Option to select interlea= ve Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW= are 0-7 for BITS 6 - 13) + UINT8 EnergyScaleFact; ///< Offset 77 Energy Scale Factor. 0=3D= Minimal, 7=3DMaximum, 4=3DDefault + BOOLEAN PerBankRefresh; ///< Offset 78 Enables and Disable= s the per bank refresh. This only impacts memory technologies that support= PBR: LPDDR3, LPDDR4. FALSE=3DDisabled, TRUE=3DEnabled + UINT8 McLock; ///< Offset 79 Enable/Disable memo= ry configuration register locking: 0=3DDisable, 1=3DEnable. + // Training Algorithms 1 + UINT32 ECT:1; ///< Offset 80 Enable/Disable Early Comm= and Training. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 SOT:1; ///< - Enable/Disable Sense Amp Offset = Training. Note it is not recommended to change this setting from the defaul= t value: 0=3DDisable, 1=3DEnable. + UINT32 ERDMPRTC2D:1; ///< - Enable/Disable Early ReadMPR Tim= ing Centering 2D. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 RDMPRT:1; ///< - Enable/Disable Read MPR Training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 RCVET:1; ///< - Enable/Disable Receive Enable Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 JWRL:1; ///< - Enable/Disable JEDEC Write Level= ing Training. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 EWRTC2D:1; ///< - Enable/Disable Early Write Time = Centering 2D Training. Note it is not recommended to change this setting fr= om the default value: 0=3DDisable, 1=3DEnable. + UINT32 ERDTC2D:1; ///< - Enable/Disable Early Read Time C= entering 2D Training. Note it is not recommended to change this setting fro= m the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC1D:1; ///< - Enable/Disable 1D Write Timing C= entering Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC1D:1; ///< - Enable/Disable 1D Write Voltage = Centering Training. Note it is not recommended to change this setting from = the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC1D:1; ///< - Enable/Disable 1D Read Timing Ce= ntering Training. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 DIMMODTT:1; ///< - Enable/Disable DIMM ODT Training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 DIMMRONT:1; ///< - Enable/Disable DIMM RON training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 WRDSEQT:1; ///< - Enable/Disable Write Drive Stren= gth / Equalization Training 2D. Note it is not recommended to change this s= etting from the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRSRT:1; ///< - Enable/Disable Write Slew Rate t= raning. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 RDODTT:1; ///< - Enable/Disable Read ODT Training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 RDEQT:1; ///< - Enable/Disable Read Equalization= Training. Note it is not recommended to change this setting from the defau= lt value: 0=3DDisable, 1=3DEnable. + UINT32 RDAPT:1; ///< - Enable/Disable Read Amplifier Po= wer Training. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC2D:1; ///< - Enable/Disable 2D Write Timing C= entering Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC2D:1; ///< - Enable/Disable 2D Read Timing Ce= ntering Training. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC2D:1; ///< - Enable/Disable 2D Write Voltage = Centering Training. Note it is not recommended to change this setting from = the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDVC2D:1; ///< - Enable/Disable 2D Read Voltage C= entering Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 CMDVC:1; ///< - Enable/Disable Command Vref Cent= ering Training. Note it is not recommended to change this setting from the = default value 0=3DDisable, 1=3DEnable. + UINT32 LCT:1; ///< - Enable/Disable Late Command Trai= ning. Note it is not recommended to change this setting from the default va= lue: 0=3DDisable, 1=3DEnable. + UINT32 RTL:1; ///< - Enable/Disable Round Trip Latenc= y function. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable. + UINT32 TAT:1; ///< - Enable/Disable Turn Around Time = function. Note it is not recommended to change this setting from the defaul= t value: 0=3DDisable, 1=3DEnable. + UINT32 RMT:1; ///< - Enable/Disable Rank Margin Tool = function: 0=3DDisable, 1=3DEnable. + UINT32 MEMTST:1; ///< - Enable/Disable Memory Test funct= ion: 0=3DDisable, 1=3DEnable. + UINT32 ALIASCHK:1; ///< - Enable/Disable DIMM SPD Alias Ch= eck: 0=3DDisable, 1=3DEnable + UINT32 RCVENC1D:1; ///< - Enable/Disable Receive Enable Ce= ntering Training (LPDDR Only). Note it is not recommended to change this se= tting from the default value: 0=3DDisable, 1=3DEnable + UINT32 RMC:1; ///< - Enable/Disable Retrain Margin Ch= eck. Note it is not recommended to change this setting from the default va= lue: 0=3DDisable, 1=3DEnable + UINT32 WRDSUDT:1; ///< - Enable/Disable Write Drive Stren= gth Up/Dn independently. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable + // Training Algorithms 2 + UINT32 CMDSR : 1; ///< Offset 84 - Enable/Disable CM= D Slew Rate Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDDSEQ : 1; ///< - Enable/Disable CMD Drive S= trength and Tx Equalization: 0=3DDisable, 1=3DEnable. + UINT32 CMDNORM : 1; ///< - Enable/Disable CMD Normali= zation: 0=3DDisable, 1=3DEnable. + UINT32 EWRDSEQ : 1; ///< - Enable/Disable Early DQ Wr= ite Drive Strength and Equalization Training: 0=3DDisable, 1=3DEnable. + UINT32 RDVC1D : 1; ///< - Enable/Disable Read Voltag= e Centering 1D + UINT32 TXTCO : 1; ///< - Enable/Disable Write TCO C= omp Training + UINT32 CLKTCO : 1; ///< - Enable/Disable Clock TCO C= omp Training + UINT32 ReservedBits2 :25; + + UINT32 OddRatioMode:1; ///< Offset 88 If Odd Ratio Mode is = enabled, QCLK frequency has an addition of 133/100 MHz: 0=3DDisable,= 1=3DEnable + UINT32 MrcTimeMeasure:1; ///< - Enables serial debug level t= o display the MRC execution times only: 0=3DDisable, 1=3DEnable + UINT32 MrcFastBoot:1; ///< - Enables the MRC fast boot pa= th for faster cold boot execution: 0=3DDisable, 1=3DEnable + UINT32 DqPinsInterleaved:1; ///< - Interleaving mode of DQ/DQS = pins for HSW_ULT which depends on board routing: 0=3DDisable, 1=3DEn= able + UINT32 RankInterleave:1; ///< - Rank Interleave Mode: 0=3DDi= sable, 1=3DEnable + UINT32 EnhancedInterleave:1; ///< - Enhanced Interleave Mode: 0= =3DDisable, 1=3DEnable + UINT32 WeaklockEn:1; ///< - Weak Lock Enable: 0=3DDisabl= e, 1=3DEnable + UINT32 CmdTriStateDis:1; ///< - CMD Tri-State Support: 0= =3DEnable, 1=3DDisable. Note: This should be set to 1 (Disable) if Comm= and RTT is not present on the platform. + UINT32 MemoryTrace:1; ///< - Memory Trace to second DDR c= hannel using Stacked Mode: 0=3DDisable, 1=3DEnable + UINT32 ChHashEnable:1; ///< - Channel Hash Enable: 0=3DDis= able, 1=3DEnable + UINT32 EnableExtts:1; ///< - Enable Extts: 0=3DDisable= , 1=3DEnable + UINT32 EnableCltm:1; ///< - Enable Closed Loop Thermal M= anagement: 0=3DDisable, 1=3DEnable + UINT32 EnableOltm:1; ///< - Enable Open Loop Thermal Man= agement: 0=3DDisable, 1=3DEnable + UINT32 EnablePwrDn:1; ///< - Enable Power Down control fo= r DDR: 0=3DPCODE control, 1=3DBIOS control + UINT32 EnablePwrDnLpddr:1; ///< - Enable Power Down for LPDDR:= 0=3DPCODE control, 1=3DBIOS control + UINT32 LockPTMregs:1; ///< - Lock PCU Thermal Management = registers: 0=3DDisable, 1=3DEnable + UINT32 UserPowerWeightsEn:1; ///< - Allows user to explicitly se= t power weight, scale factor, and channel power floor values: 0=3DDisabl= e, 1=3DEnable + UINT32 RaplLim2Lock:1; ///< - Lock DDR_RAPL_LIMIT register= : 0=3DDisable, 1=3DEnable + UINT32 RaplLim2Ena:1; ///< - Enable Power Limit 2: 0= =3DDisable, 1=3DEnable + UINT32 RaplLim1Ena:1; ///< - Enable Power Limit 1: 0= =3DDisable, 1=3DEnable + UINT32 SrefCfgEna:1; ///< - Enable Self Refresh: 0=3DDis= able, 1=3DEnable + UINT32 ThrtCkeMinDefeatLpddr:1; ///< - Throttler CKE min defeature = for LPDDR: 0=3DDisable, 1=3DEnable + UINT32 ThrtCkeMinDefeat:1; ///< - Throttler CKE min defeature:= 0=3DDisable, 1=3DEnable + UINT32 AutoSelfRefreshSupport:1; ///< - FALSE =3D No auto self refre= sh support, TRUE =3D auto self refresh support + UINT32 ExtTemperatureSupport:1; ///< - FALSE =3D No extended temper= ature support, TRUE =3D extended temperature support + UINT32 MobilePlatform:1; ///< - Memory controller device id = indicates: TRUE if mobile, FALSE if not. Note: This will be auto-det= ected and updated. + UINT32 Force1Dpc:1; ///< - TRUE means force one DIMM pe= r channel, FALSE means no limit + UINT32 ForceSingleRank:1; ///< - TRUE means use Rank0 only (i= n each DIMM): 0=3DDisable, 1=3DEnable + UINT32 RhPrevention:1; ///< - RH Prevention Enable/Disable= : 0=3DDisable, 1=3DEnable + UINT32 VttTermination:1; ///< - Vtt Termination for Data ODT= : 0=3DDisable, 1=3DEnable + UINT32 VttCompForVsshi:1; ///< - Enable/Disable Vtt Comparato= r For Vsshi: 0=3DDisable, 1=3DEnable + UINT32 ExitOnFailure:1; ///< - MRC option for exit on failu= re or continue on failure: 0=3DDisable, 1=3DEnable + + UINT32 VddSettleWaitTime; ///< Offset 92 Amount of time in microse= conds to wait for Vdd to settle on top of 200us required by JEDEC spec: = Default=3D0 + UINT16 FreqSaGvLow; ///< Offset 96 SA GV: 0 is Auto/default,= otherwise holds the frequency value: 0=3DDefault, 1067, 1200, 1333,= 1400, 1600, 1800, 1867. + UINT16 SrefCfgIdleTmr; ///< Offset 98 Self Refresh idle timer: = 512=3DMinimal, 65535=3DMaximum + UINT8 RhActProbability; ///< Offset 100 Activation probability f= or Hardware RHP + UINT8 SmramMask; ///< Offset 101 Reserved memory ranges f= or SMRAM + UINT16 Vc1ReadMeterThreshold; ///< Offset 102 VC1 Read Meter Thr= eshold (within Time Window): 0=3DMinimal, 0xFFFF=3DMaximum, 0x118=3DDefa= ult + UINT32 Vc1ReadMeterTimeWindow; ///< Offset 104 VC1 Read Meter Tim= e Window: 0=3DMinimal, 0x1FFFF=3DMaximum, 0x320=3DDefault + UINT64 BerAddress[4]; ///< Offset 108 - 139 BER Address(es): <= b>0=3DMinimal, 0xFFFFFFFFFFFFFFFF=3DMaximum (step is 0x40) + + UINT16 ChHashMask; ///< Offset 140 Channel Hash Mask: 0x000= 1=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT[19= :18, 13:12 ,9:7] set + UINT16 DdrFreqLimit; ///< Offset 142 Memory Frequency setting= : 3=3D1067, 5=3D1333, 7=3D1600, 9=3D1867, 11=3D2133, 13=3D2400, 15=3D266= 7 + UINT8 RaplLim2WindX; ///< Offset 144 Power Limit 2 Time Windo= w X value: 0=3DMinimal, 3=3DMaximum, 1=3DDefault + UINT8 RaplLim2WindY; ///< Offset 145 Power Limit 2 Time Windo= w Y value: 0=3DMinimal, 3=3DMaximum, 1=3DDefault + UINT8 RaplLim1WindX; ///< Offset 146 Power Limit 1 Time Windo= w X value: 0=3DMinimal, 3=3DMaximum + UINT8 RaplLim1WindY; ///< Offset 147 Power Limit 1 Time Windo= w Y value: 0=3DMinimal, 31=3DMaximum + UINT16 RaplLim2Pwr; ///< Offset 148 Power Limit 2: 0=3DMini= mal, 16383=3DMaximum, 222=3DDefault + UINT16 RaplLim1Pwr; ///< Offset 150 Power Limit 1: 0=3DM= inimal, 16383=3DMaximum + UINT8 WarmThresholdCh0Dimm0; ///< Offset 152 Warm Threshold (Channel = 0, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmThresholdCh0Dimm1; ///< Offset 153 Warm Threshold (Channel = 0, Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 WarmThresholdCh1Dimm0; ///< Offset 154 Warm Threshold (Channel = 1, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmThresholdCh1Dimm1; ///< Offset 155 Warm Threshold (Channel = 1, Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh0Dimm0; ///< Offset 156 Hot Threshold (Channel 0= , Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh0Dimm1; ///< Offset 157 Hot Threshold (Channel 0= , Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh1Dimm0; ///< Offset 158 Hot Threshold (Channel 1= , Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh1Dimm1; ///< Offset 159 Hot Threshold (Channel 1= , Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh0Dimm0; ///< Offset 160 Warm Budget (Channel 0, = Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh0Dimm1; ///< Offset 161 Warm Budget (Channel 0, = Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh1Dimm0; ///< Offset 162 Warm Budget (Channel 1, = Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh1Dimm1; ///< Offset 163 Warm Budget (Channel 1, = Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh0Dimm0; ///< Offset 164 Hot Budget (Channel 0, D= imm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh0Dimm1; ///< Offset 165 Hot Budget (Channel 0, D= imm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh1Dimm0; ///< Offset 166 Hot Budget (Channel 1, D= imm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh1Dimm1; ///< Offset 167 Hot Budget (Channel 1, D= imm 1): 0=3DMinimal, 255=3DMaximum + UINT8 IdleEnergyCh0Dimm0; ///< Offset 168 Idle Energy (Channel 0, = Dimm 0): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 IdleEnergyCh0Dimm1; ///< Offset 169 Idle Energy (Channel 0, = Dimm 1): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 IdleEnergyCh1Dimm0; ///< Offset 170 Idle Energy (Channel 1, = Dimm 0): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 IdleEnergyCh1Dimm1; ///< Offset 171 Idle Energy (Channel 1, = Dimm 1): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 PdEnergyCh0Dimm0; ///< Offset 172 Power Down Energy (Chann= el 0, Dimm 0): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 PdEnergyCh0Dimm1; ///< Offset 173 Power Down Energy (Chann= el 0, Dimm 1): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 PdEnergyCh1Dimm0; ///< Offset 174 Power Down Energy (Chann= el 1, Dimm 0): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 PdEnergyCh1Dimm1; ///< Offset 175 Power Down Energy (Chann= el 1, Dimm 1): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 ActEnergyCh0Dimm0; ///< Offset 176 Activation Energy (Chann= el 0, Dimm 0): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 ActEnergyCh0Dimm1; ///< Offset 177 Activation Energy (Chann= el 0, Dimm 1): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 ActEnergyCh1Dimm0; ///< Offset 178 Activation Energy (Chann= el 1, Dimm 0): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 ActEnergyCh1Dimm1; ///< Offset 179 Activation Energy (Chann= el 1, Dimm 1): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 RdEnergyCh0Dimm0; ///< Offset 180 Read Energy (Channel 0, = Dimm 0): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 RdEnergyCh0Dimm1; ///< Offset 181 Read Energy (Channel 0, = Dimm 1): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 RdEnergyCh1Dimm0; ///< Offset 182 Read Energy (Channel 1, = Dimm 0): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 RdEnergyCh1Dimm1; ///< Offset 183 Read Energy (Channel 1, = Dimm 1): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 WrEnergyCh0Dimm0; ///< Offset 184 Write Energy (Channel 0,= Dimm 0): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + UINT8 WrEnergyCh0Dimm1; ///< Offset 185 Write Energy (Channel 0,= Dimm 1): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + UINT8 WrEnergyCh1Dimm0; ///< Offset 186 Write Energy (Channel 1,= Dimm 0): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + UINT8 WrEnergyCh1Dimm1; ///< Offset 187 Write Energy (Channel 1,= Dimm 1): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + + + UINT8 MaxRttWr; ///< Offset 188 Maximum DIMM RTT_WR to u= se in power training: 0=3DODT Off, 1 =3D 120 ohms + UINT8 ThrtCkeMinTmr; ///< Offset 189 Throttler CKE min timer:= 0=3DMinimal, 0xFF=3DMaximum, 0x30=3DDefault + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 190 Throttler CKE min timer = for LPDDR: 0=3DMinimal, 0xFF=3DMaximum, 0x40=3DDefault + UINT8 BerEnable; ///< Offset 191 BER Enable and # of Addr= esses passed in: 0=3DMinimal, 8=3DMaximum + UINT8 CkeRankMapping; ///< Offset 192 Bits [7:4] - Channel 1, = bits [3:0] - Channel 0. 0xAA=3DDefault Bit [i] specifies which rank = CKE[i] goes to. + UINT8 StrongWkLeaker; ///< Offset 193 Strong Weak Leaker: 1=3D= Minimal, 7=3DMaximum + UINT8 CaVrefConfig; ///< Offset 194 0=3DVREF_CA goes to both= CH_A and CH_B, 1=3DVREF_CA to CH_A, VREF_DQ_A to CH_B, 2=3DVREF_CA to C= H_A, VREF_DQ_B to CH_B + UINT8 SaGv; ///< Offset 195 SA GV: 0=3DDisabled; 1= =3DFixedLow; CFL: 2=3DFixedHigh, CNL: 2=3DFixedMid; CFL: 3=3DEnabled= CNL: 3=3DFixedHigh; CNL: 4=3DEnabled + UINT8 RaplPwrFlCh1; ///< Offset 196 Power Channel 1 Floor va= lue: 0=3DMinimal, 255=3DMaximum + UINT8 RaplPwrFlCh0; ///< Offset 197 Power Channel 0 Floor va= lue: 0=3DMinimal, 255=3DMaximum + UINT8 NModeSupport; ///< Offset 198 Memory N Mode Support - = Enable user to select Auto, 1N or 2N: 0=3DAUTO, 1=3D1N, 2=3D2N. + UINT8 RefClk; ///< Offset 199 Selects the DDR base ref= erence clock. 0x01 =3D 100MHz, 0x00 =3D 133MHz + UINT8 EnCmdRate; ///< Offset 200 CMD Rate Enable: 0=3DDis= able, 1=3D1 CMD, 2=3D2 CMDs, 3=3D3 CMDs, 4=3D4 CMDs, 5=3D5 CMDs, 6= =3D6 CMDs, 7=3D7 CMDs + UINT8 Refresh2X; ///< Offset 201 Refresh 2x: 0=3DDisab= le, 1=3DEnable for WARM or HOT, 2=3DEnable for HOT only + UINT8 EpgEnable; ///< Offset 202 Enable Energy Performanc= e Gain. + UINT8 RhSolution; ///< Offset 203 Type of solution to be u= sed for RHP - 0/1 =3D HardwareRhp/Refresh2x + UINT8 UserThresholdEnable; ///< Offset 204 Flag to manually select = the DIMM CLTM Thermal Threshold, 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 UserBudgetEnable; ///< Offset 205 Flag to manually select = the Budget Registers for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0= =3DDefault + UINT8 TsodTcritMax; ///< Offset 206 TSOD Tcrit Maximum Value= to be Configure , 0=3DMinimal, 128=3DMaximum, , 105=3DDefault + + UINT8 TsodEventMode; ///< Offset 207 Flag to Enable Event Mod= e Interruption in TSOD Configuration Register, 0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodEventPolarity; ///< Offset 208 Event Signal Polarity in= TSOD Configuration Register, 0=3DLow, 1=3DHigh, 0=3DDefault + UINT8 TsodCriticalEventOnly; ///< Offset 209 Critical Trigger Only in= TSOD Configuration Register,0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodEventOutputControl; ///< Offset 210 Event Output Control in = TSOD Configuration Register,0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodAlarmwindowLockBit; ///< Offset 211 Alarm Windows Lock Bit i= n TSOD Configuration Register,0=3DUnlock, 1=3DLock, 0=3DDefault + UINT8 TsodCriticaltripLockBit;///< Offset 212 Critical Trip Lock Bit i= n TSOD Configuration Register,0=3DUnlock, 1=3DLock, 0=3DDefault + UINT8 TsodShutdownMode; ///< Offset 213 Shutdown Mode TSOD Confi= guration Register,0=3DEnable, 1=3DDisable, 0=3DDefault + UINT8 TsodThigMax; ///< Offset 214 Thigh Max Value In the = for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 TsodManualEnable; ///< Offset 215 Flag to manually select = the TSOD Register Values , 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 DllBwEn0; ///< Offset 216 DllBwEn value for 1067 + UINT8 DllBwEn1; ///< Offset 217 DllBwEn value for 1333 + UINT8 DllBwEn2; ///< Offset 218 DllBwEn value for 1600 + UINT8 DllBwEn3; ///< Offset 219 DllBwEn value for 1867 a= nd up + UINT8 RetrainOnFastFail; ///< Offset 220 Restart MRC in Cold mode= if SW MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled + UINT8 ForceOltmOrRefresh2x; ///< Offset 221 Force OLTM or 2X Refresh= when needed. 0 =3D Force OLTM, 1 =3D Force 2x Refresh + UINT8 PowerDownMode; ///< Offset 222 CKE Power Down Mode: = 0xFF=3DAUTO, 0=3DNo Power Down, 1=3D APD mode, 6=3DPPD-DLL Off mode + UINT8 PwdwnIdleCounter; ///< Offset 223 CKE Power Down Mode Idle= Counter: 0=3DMinimal, 255=3DMaximum, 0x80=3D0x80 DCLK + UINT8 IsvtIoPort; ///< Offset 224 ISVT IO Port Address: 0= =3DMinimal, 0xFF=3DMaximum, 0x99=3DDefault + UINT8 CmdRanksTerminated; ///< Offset 225 LPDDR4: Bitmask of= ranks that have CA bus terminated. 0x01=3DDefault, Rank0 is terminating= and Rank1 is non-terminating + UINT8 GdxcEnable; ///< Offset 226 GDXC MOT enable + UINT8 GdxcIotSize; ///< Offset 227 IOT size in multip= les of 8MEG + UINT8 GdxcMotSize; ///< Offset 228 MOT size in multip= les of 8MEG + UINT8 RMTLoopCount; ///< Offset 229 Indicates the Loop Count= to be used for Rank Margin Tool Testing: 1=3DMinimal, 32=3DMaximum, 0=3DAU= TO, 0=3DDefault + UINT16 FreqSaGvMid; ///< Offset 230 SA GV: 0 is Auto/default= , otherwise holds the frequency value expressed as an integer: 0=3DDefau= lt, 1600, 1800, 1867, 2000, 2133, etc. + + UINT32 RmtPerTask:1; ///< Offset 232 Bit 0: Rank Margin= Tool Per Task. 0 =3D Disabled, 1 =3D Enabled + UINT32 TrainTrace:1; ///< Offset 232 Bit 1: Trained sta= te tracing debug. 0 =3D Disabled, 1 =3D Enabled + UINT32 SafeMode:1; ///< Offset 232 Bit 2: Define if s= afe mode is enabled for MC/IO + UINT32 EnBER:1; ///< Offset 232 Bit 3: Define if E= nBER is enabled for Rank Margin Tool + UINT32 Ddr4MixedUDimm2DpcLimit:1; ///< Offset 232 Bit 4: Enable/Disa= ble 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. 0= =3D Disabled, 1 =3D Enabled + UINT32 FastBootRmt:1; ///< Offset 232 Bit 5: Enable/Disa= ble RMT on FastBoot. 0 =3D Disabled, 1 =3D Enabled + UINT32 MrcTrainOnWarm:1; ///< Offset 232 Bit 6: Force MRC t= raining on warm boot : 0 =3D Disabled, 1 =3D Enabled + UINT32 LongFlyByModeEnabled:1; ///< Offset 232 Bit 7: Long FlyBy = Mode Enabled : 0 =3D Disabled, 1 =3D Enabled + UINT32 Off232RsvdBits:24; ///< Offset 232 Bit 8-31: Reserved + + // TurnAround Timing + UINT8 tRd2RdSG; ///< Offset 236 - Read-to-Read Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2RdDG; ///< Offset 237 - Read-to-Read Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tRd2RdDR; ///< Offset 238 - Read-to-Read Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2RdDD; ///< Offset 239 - Read-to-Read Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2WrSG; ///< Offset 240 - Read-to-Write Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2WrDG; ///< Offset 241 - Read-to-Write Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tRd2WrDR; ///< Offset 242 - Read-to-Write Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2WrDD; ///< Offset 243 - Read-to-Write Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2RdSG; ///< Offset 244 - Write-to-Read Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 86=3DMaximum. + UINT8 tWr2RdDG; ///< Offset 245 - Write-to-Read Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tWr2RdDR; ///< Offset 246 - Write-to-Read Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2RdDD; ///< Offset 247 - Write-to-Read Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2WrSG; ///< Offset 248 - Write-to-Write Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2WrDG; ///< Offset 249 - Write-to-Write Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tWr2WrDR; ///< Offset 250 - Write-to-Write Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2WrDD; ///< Offset 251 - Write-to-Write Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT16 tRRD_L; ///< Offset 252 - User defined DDR= 4 Memory Timing tRRD_L value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 15=3DMaximum. + UINT16 tRRD_S; ///< Offset 254 - User defined DDR= 4 Memory Timing tRRD_S value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 15=3DMaximum. + UINT16 tWTR_L; ///< Offset 266 - User defined DDR= 4 Memory Timing tWTR_L value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 28=3DMaximum. + UINT16 tWTR_S; ///< Offset 268 - User defined DDR= 4 Memory Timing tWTR_S value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 28=3DMaximum. + +} MEMORY_CONFIGURATION; + +/// Memory Configuration +/// The contents of this structure are not CRC'd by the MRC for option cha= nge detection. +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Bl= ock Header + SA_FUNCTION_CALLS SaCall; ///< Offset 24 Function = calls into the SA. + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 200 Function = calls into the MRC. + SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SP= D data, will be used by the MRC when SPD SmBus address is zero. + SA_MEMORY_DQ_MAPPING *DqByteMap; ///< Offset 240 LPDDR3 DQ= byte mapping to CMD/CTL/CLK, from the CPU side. + SA_MEMORY_DQS_MAPPING *DqsMap; ///< Offset 244 LPDDR3 DQ= S byte swizzling between CPU and DRAM. + SA_MEMORY_RCOMP *RcompData; ///< Offset 248 DDR RCOMP= resistors and target values. + UINT64 PlatformMemorySize; ///< Offset 252 The minim= um platform memory size required to pass control into DXE + UINT32 CleanMemory:1; ///< Offset 260 Ask MRC t= o clear memory content: FALSE=3DDo not Clear Memory; TRUE=3DClear Me= mory + UINT32 MemTestOnWarmBoot:1; ///< Offset 260 Run Base = Memory Test On WarmBoot: 0=3DDisabled, 1=3DEnabled + UINT32 ReservedBits5:30; + /** + Sets the serial debug message level\n + 0x00 =3D Disabled\n + 0x01 =3D Errors only\n + 0x02 =3D Errors and Warnings\n + 0x03 =3D Errors, Warnings, and Info\n + 0x04 =3D Errors, Warnings, Info, and Events\n + 0x05 =3D Displays Memory Init Execution Time Summary only\n + **/ + UINT8 SerialDebugLevel; ///< Offset 264 + UINT8 Reserved11[3]; ///< Offset 265 Reserved +} MEMORY_CONFIG_NO_CRC; +#pragma pack(pop) + +#endif // _MEMORY_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/MemoryDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inc= lude/ConfigBlock/MemoryDxeConfig.h new file mode 100644 index 0000000000..9f01c172f2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Me= moryDxeConfig.h @@ -0,0 +1,61 @@ +/** @file + Memory DXE Policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMORY_DXE_CONFIG_H_ +#define _MEMORY_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define MEMORY_DXE_CONFIG_REVISION 1 + +/** + The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mec= hanical present bit map. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header +/** + Offset 28: + Dimm SPD address + Only Server support 2 channels * 3 slots per channel =3D 6 sockets total= ly + The Desktop and mobile only support 2 channels * 2 slots per channel =3D= 4 sockets totally + So there is mapping rule here for Desktop and mobile that there are no m= ore 4 DIMMS totally in a system: + Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0] + Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1] + Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2] + Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3] + Refer to SmbiosMemory.c for use + If change the mapping rule, please update the Revision number. +**/ + UINT8 *SpdAddressTable; +/** + Offset 36: + Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel A has 2 DIMMs, ChannelASlotMap =3D 0x03; + E.g. if channel A has only 1 DIMMs, ChannelASlotMap =3D 0x01; + Refer to SmbiosMemory.c +**/ + UINT8 ChannelASlotMap; +/** + Offset 37: + Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel B has 2 DIMMs, ChannelBSlotMap =3D 0x03; + E.g. if channel B has only 1 DIMMs, ChannelBSlotMap =3D 0x01; + Refer to SmbiosMemory.c +**/ + UINT8 ChannelBSlotMap; + UINT8 MrcTimeMeasure; ///< Offset 38: MRC execution ti= me measurement: 0=3DDisable, 1=3DEnable + UINT8 MrcFastBoot; ///< Offset 39: Fast boot: 0=3DD= isable, 1=3DEnable +} MEMORY_DXE_CONFIG; +#pragma pack(pop) + +#endif // _MEMORY_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/MiscDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/MiscDxeConfig.h new file mode 100644 index 0000000000..7a8894a5c0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mi= scDxeConfig.h @@ -0,0 +1,33 @@ +/** @file + MISC DXE policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MISC_DXE_CONFIG_H_ +#define _MISC_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define MISC_DXE_CONFIG_REVISION 2 + +/** + This data structure includes miscellaneous configuration variables such = SA thermal device + control. The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. + Revision 2: + - Added RmrrCsmeBaseAddress fields. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config= Block Header + EFI_PHYSICAL_ADDRESS *RmrrUsbBaseAddress; ///< Offset 28 The fiel= d is used to describe the platform USB Reserved memory for Intel VT-d suppo= rt. Platform code should provide this information for Intel VT-d DXE driver= use + UINT32 EnableAbove4GBMmio : 1; ///< Offset 29:0 Enable= /disable above 4GB MMIO resource support: 0=3DDisable, 1=3DEnable + UINT32 RsvdBits0 : 31; ///< Offset 29:1 Reserv= ed bits. + EFI_PHYSICAL_ADDRESS *RmrrCsmeBaseAddress; ///< The field is used = to describe the CSME Reserved memory. +} MISC_DXE_CONFIG; +#pragma pack(pop) + +#endif // _MISC_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/OverClockingConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/= Include/ConfigBlock/OverClockingConfig.h new file mode 100644 index 0000000000..b623f14c15 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Ov= erClockingConfig.h @@ -0,0 +1,51 @@ +/** @file + Policy definition for System Agent overclocking Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _OVERCLOCKING_PREMEM_CONFIG__H_ +#define _OVERCLOCKING_PREMEM_CONFIG__H_ +#pragma pack(push, 1) + +#define SA_OVERCLOCKING_CONFIG_REVISION 2 + +/** + Defines the overclocking configuration parameters for System Agent.\n + Revision 1: + - Initial version. + Revision 2: + - Add GT unslice support. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + /** + Offset 28:0 : + Enable disable of SA overclocking mailbox commands. + If disabled, or if PcdSaOcEnable is disabled, all other policies in this= config block are ignored. + 0=3DDisable, + 1=3DEnable + **/ + UINT32 OcSupport : 1; + UINT32 GtVoltageMode : 1; ///< Offset 28:1 :Specifies whethe= r GT voltage is operating in Adaptive or Override mode: 0=3DAdaptive= , 1=3DOverride + UINT32 RealtimeMemoryTiming : 1; ///< Offset 28:2 :Enable/Disable t= he message sent to the CPU to allow realtime memory timing changes after MR= C_DONE. 0=3DDisable, 1=3DEnable + UINT32 GtusVoltageMode : 1; ///< Offset 28:3 :Specifies whethe= r GT unslice voltage is operating in Adaptive or Override mode: 0=3DAdap= tive, 1=3DOverride + UINT32 RsvdBits0 : 28; ///< Offset 28:4 - 31 :Reserved fo= r future use + UINT8 GtMaxOcRatio; ///< Offset 32 Maximum GT turbo ra= tio override: 0=3DMinimal, 255=3DMaximum, 0=3DAUTO + UINT8 Rsvd0; ///< Offset 33 Reserved for DWORD = alignment + INT16 GtVoltageOffset; ///< Offset 34 The voltage offset = applied to GT slice. Valid range from -1000mv to 1000mv: 0=3DMinimal= , 1000=3DMaximum + UINT16 GtVoltageOverride; ///< Offset 36 The GT voltage over= ride which is applied to the entire range of GT frequencies 0=3DDefault<= /b> + UINT16 GtExtraTurboVoltage; ///< Offset 38 The adaptive voltag= e applied during turbo frequencies. Valid range from 0 to 2000mV: 0=3DMi= nimal, 2000=3DMaximum + INT16 SaVoltageOffset; ///< Offset 40 The voltage offset = applied to the SA. Valid range from -1000mv to 1000mv: 0=3DDefault + INT16 GtusVoltageOffset; ///< Offset 42 The voltage offset = applied to GT unslice. Valid range from -1000mv to 1000mv: 0=3DMinimal, 1000=3DMaximum + UINT16 GtusVoltageOverride; ///< Offset 44 The GT unslice volt= age override which is applied to the entire range of GT frequencies: 0= =3DDefault + UINT16 GtusExtraTurboVoltage; ///< Offset 46 The adaptive voltag= e applied during turbo frequencies. Valid range from 0 to 2000mV: 0=3DDe= fault + UINT8 GtusMaxOcRatio; ///< Offset 48 Maximum GTus turbo = ratio override: 0=3DMinimal, 6=3DMaximum, 0=3DAUTO + UINT8 Rsvd1[3]; ///< Offset 49-51 Reserved for DWO= RD alignment +} OVERCLOCKING_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _OVERCLOCKING_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/PcieDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/PcieDxeConfig.h new file mode 100644 index 0000000000..f0b9670f64 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pc= ieDxeConfig.h @@ -0,0 +1,135 @@ +/** @file + PCIE DXE policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_DXE_CONFIG_H_ +#define _PCIE_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define PCIE_DXE_CONFIG_REVISION 1 + +/// +/// Device List for special ASPM override +/// +typedef struct { + UINT16 VendorId; ///< Offset 0 PCI Configuration space offset 0 + UINT16 DeviceId; ///< Offset 2 PCI Configuration space offset 2 + UINT8 RevId; ///< Offset 4 PCI Configuration space offset 8= ; 0xFF means all steppings + UINT8 RootApmcMask; ///< Offset 5 Root ASPM override bit mask 0= =3DNo override + UINT8 EndpointApmcMask; ///< Offset 6 Endpoint ASPM override bit mask = 0=3DNo override + UINT8 Rsvd; ///< Offset 7 Reserved +} PCIE_ASPM_OVERRIDE_LIST; + +typedef struct { + UINT16 VendorId; ///< Offset 0 PCI Config space offset 0 + UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2 +/** + Offset 4: + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multi= plied with + the scale in bits 12:10 +**/ + UINT16 SnoopLatency; +/** + Offset 6: + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be m= ultiplied with + the scale in bits 12:10 +**/ + UINT16 NonSnoopLatency; + UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF means = all steppings + UINT8 Rsvd0[3]; ///< Offset 9 +} PCIE_LTR_DEV_INFO; + +/// +/// PCIE Power Optimizer config +/// +typedef struct { + UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency: <= b>0x0846=3D70us + UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop Latenc= y: 0x0846=3D70us + UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable + UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable + UINT8 Rsvd0[2]; ///< Offset 6 Reserved +} SA_PCIE_PWR_OPT; + + +/** + The PCI Express Configuration info includes PCI Resources Range Base and= Limits and the control + for PEG ASPM. + The data elements should be initialized by a Platform Module.\n + @note Optional. These policies will be ignored if there is no PEG= port present on board. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-2= 7 Config Block Header +/** + Offset 28: This field is used to describe the ASPM control for PEG Ports= \n + 0=3DASPM Disabled, 1=3DASPM L0s Enabled, 2=3DASPM L1 Enabled, 3=3DASPM L= 0sL1 Enabled, 4=3DASPM AUTO +**/ + UINT8 PegAspm[SA_PEG_MAX_FUN]; +/** + Offset 32: This field is used to describe the PEG L0s advanced control + 0=3DASPM L0s disabled, 1=3DASPM L0s enabled on RP, 2=3DASPM L0s enabled = on EP, 3=3DASPM L0s enabled on both RP and EP +**/ + UINT8 PegAspmL0s[SA_PEG_MAX_FUN]; +/** + Offset 36: PCIe Hot Plug Enable/Disable. It has 2 policies. + - Disabled (0x0) : No hotplug. + - Enabled (0x1) : Bios assist hotplug. +**/ + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN]; +/** + Offset 40: This field is used as a pointer to the ASPM device override t= able, default points to an\n + existing table mPcieAspmDevsOverride\n + Refer to DxeSaPolicyLib.c for the usage. + Note: This exclusion list helps avoid potential system hangs. +**/ + PCIE_ASPM_OVERRIDE_LIST *PcieAspmDevsOverride; +/** + Offset 48: This field is used as a pointer to the LTR device override ta= ble, default points to an existing + table mPcieLtrDevsOverride.\n + Refer to DxeSaPolicyLib.c for the usage. +**/ + PCIE_LTR_DEV_INFO *PcieLtrDevsOverride; + SA_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset 60: = This field is used to describe the PCIe LTR/OBFF relevant settings + UINT8 Rsvd1[3]; /// Reserved for= future use +} PCIE_DXE_CONFIG; +#pragma pack(pop) + +#endif // _PCIE_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/PciePeiConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/PciePeiConfig.h new file mode 100644 index 0000000000..7899504865 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pc= iePeiConfig.h @@ -0,0 +1,60 @@ +/** @file + Policy definition for PCIe Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_PEI_CONFIG_H_ +#define _PCIE_PEI_CONFIG_H_ + +#include +#include + +#pragma pack(push, 1) + +#define SA_PCIE_PEI_CONFIG_REVISION 1 + +/** + PCI Express and DMI controller configuration - PostMem\n + @note Optional. These policies will be ignored if there is no PEG = port present on board. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + /** + Offset 28:0 + (Test)DMI Extended Sync Control + - Disabled (0x0) : Disable DMI Extended Sync (Default) + - Enabled (0x1) : Enable DMI Extended Sync + **/ + UINT32 DmiExtSync : 1; + /** + Offset 28:1 + (Test)DMI IOT Control + - Disabled (0x0) : Disable DMI IOT (Default) + - Enabled (0x1) : Enable DMI IOT + **/ + UINT32 DmiIot : 1; + UINT32 RsvdBits1 : 30; ///<= Offset 28:2-31 :Reserved for future use. + UINT8 DmiAspm; ///<= Offset 32 This field is used to describe the ASPM control for DMI: 3=3D= PcieAspmL0sL1, 2=3DPcieAspmL1, 1=3DPcieAspmL0s, 0=3DPcieAspmDisabled. + UINT8 Rsvd1[3]; ///<= Offset 33 to 35 + UINT8 PegDeEmphasis[SA_PEG_MAX_FUN]; ///<= Offset 36 This field is used to describe the DeEmphasis control for PEG (-= 6 dB and -3.5 dB are the options)SA_PEG_MAX_FUN =3D 3 for CFL and SA_PEG_MA= X_FUN =3D 4 for CNL, offsets are adjusted accordingly + UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///<= (Test) Offset 39/40 This field is used to describe the PEG Max Pay = Load Size (0xFF: Auto, 0:128B, 1:256B) + /** + PCIe Slot Power Capabilities. SlotPowerLimitValue in combination with S= lotPowerLimitScale specifies the upper limit on power supplied by slot. + **/ + UINT8 PegSlotPowerLimitValue[SA_PEG_MAX_FUN]; ///<= Offset 42/44 8 bit value + UINT8 PegSlotPowerLimitScale[SA_PEG_MAX_FUN]; ///<= Offset 45/48 2 bit value: 00 =3D 1.0x, 01 =3D 0.1x, 10 =3D 0.01x an= d 11 =3D 0.001x + /** + Offset 48/52 + PCIe Physical Slot Number (13 bit value). Indicates the physical slot n= umber attached to the port. + **/ + UINT16 PegPhysicalSlotNumber[SA_PEG_MAX_FUN]; + UINT8 Rsvd2[2]; +} PCIE_PEI_CONFIG; +#pragma pack(pop) + +#endif // _PCIE_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/PciePeiPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent= /Include/ConfigBlock/PciePeiPreMemConfig.h new file mode 100644 index 0000000000..a53bf3c7bd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pc= iePeiPreMemConfig.h @@ -0,0 +1,354 @@ +/** @file + Policy definition for PCIe Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_PEI_PREMEM_CONFIG_H_ +#define _PCIE_PEI_PREMEM_CONFIG_H_ + +#include +#include + +#pragma pack(push, 1) + +#define SA_PCIE_PEI_PREMEM_CONFIG_REVISION 3 + +/// +/// SA GPIO Data Structure +/// +typedef struct { + GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad + UINT8 Value; ///< Offset 4: GPIO Value + UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignm= ent + UINT32 Active :1; ///< Offset 8: 0=3DActive Low; 1=3DActive = High + UINT32 RsvdBits0:31; +} SA_GPIO_INFO_PCIE; + +/// +/// SA Board PEG GPIO Info +/// +typedef struct { + SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO = assigned, must be a PCH GPIO pin + SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO = assigned, must be a PCH GPIO pin + BOOLEAN GpioSupport; ///< Offset 24: 1=3DSupported; 0= =3DNot Supported + UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 by= tes alignment +} PEG_GPIO_DATA; + + +/** + PCI Express and DMI controller configuration\n + @note Optional. These policies will be ignored if there is no PEG = port present on board. + Revision 1: + - Initial version. + Revision 2: + - Change PegGen3RxCtleOverride of PCIE_PEI_PREMEM_CONFIG from one bit to= UINT8 + - Change DmiGen3RxCtlePeaking default to 0 + Revision 3: + - Added PEG IMR support + - Added UINT8 PegImrEnable + - Added UINT16 PegImrSize + - Added UINT8 ImrRpSelection +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///<= Offset 0-27 Config Block Header + /** + Offset 28:0 : + (Test) DMI Link Speed Control + - Auto (0x0) : Maximum possible link speed (Default) + - Gen1 (0x1) : Limit Link to Gen1 Speed + - Gen2 (0x2) : Limit Link to Gen2 Speed + - Gen3 (0x3) : Limit Link to Gen3 Speed + **/ + UINT32 DmiMaxLinkSpeed : 2; + /** + Offset 28:2 : + (Test) DMI Equalization Phase 2 Enable Control + - Disabled (0x0) : Disable phase 2 + - Enabled (0x1) : Enable phase 2 + - Auto (0x2) : Use the current default method (Default) + **/ + UINT32 DmiGen3EqPh2Enable : 2; + /** + Offset 28:4 : + (Test) Selects the method for performing Phase3 of Gen3 Equaliza= tion on DMI + - Auto (0x0) : Use the current default method (Default) + - HwEq (0x1) : Use Adaptive Hardware Equalization + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code) + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1) + - Disabled (0x4) : Bypass Equalization Phase 3 + **/ + UINT32 DmiGen3EqPh3Method : 3; + /** + Offset 28:7 : + (Test) Program DMI Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 DmiGen3ProgramStaticEq : 1; + + /** + Offset 28:8 to 28:15 : + (Test) PEG Enable Control + - Disabled (0x0) : Disable PEG Port + - Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it) + - Auto (0x2) : If an endpoint is present, enable the PEG Port, D= isable otherwise (Default) + **/ + UINT32 Peg0Enable : 2; ///<= Enable/Disable PEG 0:1:0 Root Port + UINT32 Peg1Enable : 2; ///<= (Test) Enable/Disable PEG 0:1:1 Root Port + UINT32 Peg2Enable : 2; ///<= (Test) Enable/Disable PEG 0:1:2 Root Port + UINT32 Peg3Enable : 2; ///<= (Test) Enable/Disable PEG 0:6:0 Root Port. + + /** + Offset 28:16 : + (Test) PCIe Link Speed Control + - Auto (0x0) : Maximum possible Link speed (Default) + - Gen1 (0x1) : Limit Link to Gen1 Speed + - Gen2 (0x2) : Limit Link to Gen2 Speed + - Gen3 (0x3) : Limit Link to Gen3 Speed + **/ + UINT32 Peg0MaxLinkSpeed : 2; ///<= PCIe Link Speed Control for PEG 0:1:0 Root Port. + UINT32 Peg1MaxLinkSpeed : 2; ///<= (Test) PCIe Link Speed Control for PEG 0:1:1 Root Port. + UINT32 Peg2MaxLinkSpeed : 2; ///<= (Test) PCIe Link Speed Control for PEG 0:1:2 Root Port. + UINT32 Peg3MaxLinkSpeed : 2; ///<= (Test) PCIe Link Speed Control for PEG 0:6:0 Root Port. + UINT32 RsvdBits0 : 8; ///<= Offset 28:24 :Reserved for future use + + /** + Offset 32:0 : + (Test) PCIe Link Width Control + - Auto (0x0) : Maximum possible Link width (Default) + - X1 (0x1) : Limit Link to X1 Width + - X2 (0x2) : Limit Link to X2 Width + - X4 (0x3) : Limit Link to X4 Width + - X8 (0x4) : Limit Link to X8 Width + **/ + UINT32 Peg0MaxLinkWidth : 3; ///<= PCIe Link Width Control for PEG 0:1:0 Root Port. + UINT32 Peg1MaxLinkWidth : 3; ///<= (Test) PCIe Link Width Control for PEG 0:1:1 Root Port. + UINT32 Peg2MaxLinkWidth : 3; ///<= (Test) PCIe Link Width Control for PEG 0:1:2 Root Port. + UINT32 Peg3MaxLinkWidth : 3; ///<= (Test) PCIe Link Width Control for PEG 0:6:0 Root Port. + /** + Offset 32:12 to 32:15 : + Power down unused lanes on the PEG Root Port. + - Disabled (0x0) : No power saving. + - Auto (0x1) : Bios will power down unused lanes based on the ma= x possible link width + **/ + UINT32 Peg0PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:1:0 Root Port. + UINT32 Peg1PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:1:1 Root Port. + UINT32 Peg2PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:1:2 Root Port. + UINT32 Peg3PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:6:0 Root Port. + + /** + Offset 32:16 to 32:23 : + (Test) PCIe Equalization Phase 2 Enable Control + - Disabled (0x0) : Disable phase 2 + - Enabled (0x1) : Enable phase 2 + - Auto (0x2) : Use the current default method (Default) + **/ + UINT32 Peg0Gen3EqPh2Enable : 2; ///<= Phase2 EQ enable on the PEG 0:1:0 Root Port. + UINT32 Peg1Gen3EqPh2Enable : 2; ///<= (Test) Phase2 EQ enable on the PEG 0:1:1 Root Port. + UINT32 Peg2Gen3EqPh2Enable : 2; ///<= (Test) Phase2 EQ enable on the PEG 0:1:2 Root Port. + UINT32 Peg3Gen3EqPh2Enable : 2; ///<= (Test) Phase2 EQ enable on the PEG 0:6:0 Root Port. + UINT32 RsvdBits1 : 8; ///<= Offset 32:24 :Reserved for future use + /** + Offset 36:0 to 36:11 : + (Test) Select the method for performing Phase3 of Gen3 Equalizat= ion. + - Auto (0x0) : Use the current default method (Default) + - HwEq (0x1) : Use Adaptive Hardware Equalization + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code) + - Static (0x3) : Use the Static EQs provided in PegGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1) + - Disabled (0x4) : Bypass Equalization Phase 3 + **/ + UINT32 Peg0Gen3EqPh3Method : 3; ///<= Phase3 EQ method on the PEG 0:1:0 Root Port. + UINT32 Peg1Gen3EqPh3Method : 3; ///<= (Test) Phase3 EQ method on the PEG 0:1:1 Root Port. + UINT32 Peg2Gen3EqPh3Method : 3; ///<= (Test) Phase3 EQ method on the PEG 0:1:2 Root Port. + UINT32 Peg3Gen3EqPh3Method : 3; ///<= (Test) Phase3 EQ method on the PEG 0:6:0 Root Port. + /** + Offset 36:12 : + (Test) Program PEG Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 PegGen3ProgramStaticEq : 1; + /** + Offset 36:13 : + (Test) Always Attempt Gen3 Software Equalization + + When enabled, Gen3 Software Equalization will be executed every boot. = When disabled, it will be only executed if the CPU + or EP is changed, otherwise it is skipped and the previous EQ value wil= l be re-used. + + This setting will only have an effect if Software Equalization is enabl= ed and OEM Platform Code implements + save/restore of the PegDataPtr data (see below). If PegDataPtr is not = saved/restored RC forces this to be enabled. + + - Disabled (0x0) : Reuse EQ settings saved/restored from NVRAM w= henever possible (Default) + - Enabled (0x1) : Re-test and generate new EQ values every boot= , not recommended + **/ + UINT32 Gen3SwEqAlwaysAttempt : 1; + /** + Offset 36:14 to 36:16 : + (Test) Select number of TxEq presets to test in the PCIe/DMI Sof= tware Equalization Algorithm + - P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8 + - P0-P9 (0x1) : Test Presets 0-9 + - Auto (0x2) : Use the current default method (Default) + Auto will test Presets 7, 3, 5, and 8. It is possible for this default = to change over time; + using "Auto" will ensure Reference Code always uses the latest default s= ettings. + @warning Do not change from the default. Hard to detect issues are like= ly. + **/ + UINT32 Gen3SwEqNumberOfPresets : 3; + /** + Offset 36:17 to 36:18: + (Test) Offset 36 Enable use of the Voltage Offset and Centering = Test in the PCIe Software Equalization Algorithm + - Disabled (0x0) : Disable VOC Test + - Enabled (0x1) : Enable VOC Test + - Auto (0x2) : Use the current default (Default) + **/ + UINT32 Gen3SwEqEnableVocTest : 2; + /** + Offset 36:19 : + Select when PCIe ASPM programming will happen in relation to the Oprom + - Before (0x0) : Do PCIe ASPM programming before Oprom. (Default) + - After (0x1) : Do PCIe ASPM programming after Oprom. This will = require an SMI handler to save/restore ASPM settings. + **/ + UINT32 InitPcieAspmAfterOprom : 1; + /** + Offset 36:20 : + (Test) PCIe Rx Compliance Testing Mode + - Disabled (0x0) : Normal Operation - Disable PCIe Rx= Compliance testing (Default) + - Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controller = is in Rx Compliance Testing Mode; it should only be set when doing PCIe com= pliance testing + **/ + UINT32 PegRxCemTestingMode : 1; + + /** + Offset 36:21 to 36:24 : + (Test) PCIe Rx Compliance Loopback Lane + + When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) wil= l be + used for RxCEMLoopback. + + Default is Lane 0. + **/ + UINT32 PegRxCemLoopbackLane : 4; + /** + Offset 36:25 to 36:28 : + (Test) Generate PCIe BDAT Margin Table. Set this policy to enabl= e the generation and addition of PCIe margin data to the BDAT table. + - Disabled (0x0) : Normal Operation - Disable PCIe BDAT = margin data generation (Default) + - PortData (0x1) : Port Data - Generate PCIe BDAT= margin data + **/ + UINT32 PegGenerateBdatMarginTable : 4; + /** + Offset 36:29 : + (Test) PCIe Non-Protocol Awareness for Rx Compliance Testing + - Disabled (0x0) : Normal Operation - Disable non-= protocol awareness (Default) + - Enabled (0x1) : Non-Protocol Awareness Enabled - Enable non-p= rotocol awareness for compliance testing + **/ + UINT32 PegRxCemNonProtocolAwareness : 1; + /** + Offset 36:30 : + (Test) PCIe Disable Spread Spectrum Clocking. This feature shoul= d be TRUE only for compliance testing + - False (0x0) : Normal Operation - SSC e= nabled (Default) + - True (0x1) : Disable SSC - Disab= le SSC for compliance testing + **/ + UINT32 PegDisableSpreadSpectrumClocking : 1; + + UINT32 RsvdBits2 : 1; + + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<= Offset 40 Used for programming DMI Gen3 preset values per lane. Range: 0-9= , 8 is default for each lane + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<= Offset 44 Used for programming DMI Gen3 preset values per lane. Range: 0-9= , 7 is default for each lane + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<= Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is= default for each lane + /** + Offset 52 : + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15)= . This setting + has to be specified based upon platform design and must follow the guid= eline. Default is 0. + **/ + + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]; + + UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE]; ///<= Offset 54 (Test) Used for programming PEG Gen3 preset values per la= ne. Range: 0-9, 8 is default for each lane + UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE]; ///<= Offset 70 (Test) Used for programming PEG Gen3 preset values per la= ne. Range: 0-9, 7 is default for each lane + UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE]; ///<= Offset 86 (Test) Hint value per lane for the PEG Gen3 End Point. Ra= nge: 0-6, 2 is default for each lane + /** + Offset 102: + PCIe Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15= ). This setting + has to be specified based upon platform design and must follow the guid= eline. Default is 12. + **/ + UINT8 PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE]; + /** + Offset 110: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 1000. + @warning Do not change from the default. Hard to detect issues are like= ly. + @note An attack on this policy could result in an apparent hang, + but the system will eventually boot. This variable should be protecte= d. + **/ + UINT16 Gen3SwEqJitterDwellTime; + /** + Offset 112: + This is a memory data pointer for saved preset search results. The refe= rence code will store + the Gen3 Preset Search results in the SaPegHob. In order to skip the Ge= n3 + preset search on boots where the PEG card configuration has not changed= since the previous boot, + platform code can save the contents of the SaPegHob in DXE (When it pre= sent and for size reported by Header.HobLength) + and provide a pointer to a restored copy of that data. Default value is= NULL, which results in a full + preset search every boot. + + @note An attack on this policy could prevent the PCIe display from work= ing until a boot when + PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable u= sed to save the + preset search results should be protected in a way that it can only be = modified by the + platform manufacturer. + **/ + VOID *PegDataPtr; + /** + Offset 116: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 1. + @warning Do not change from the default. Hard to detect issues are like= ly. + **/ + UINT16 Gen3SwEqJitterErrorTarget; + + /** + Offset 118: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 10000. + @warning Do not change from the default. Hard to detect issues are like= ly. + @note An attack on this policy could result in an apparent hang, + but the system will eventually boot. This variable should be protecte= d. + **/ + UINT16 Gen3SwEqVocDwellTime; + + /** + Offset 120: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 2. + @warning Do not change from the default. Hard to detect issues are like= ly. + **/ + UINT16 Gen3SwEqVocErrorTarget; + /** + Offset 122: + PCIe Hot Plug Enable/Disable. It has 2 policies. + - Disabled (0x0) : No hotplug. + - Enabled (0x1) : Bios assist hotplug. + **/ + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN]; + UINT8 DmiDeEmphasis; ///<= Offset 125 This field is used to describe the DeEmphasis control for DMI (= -6 dB and -3.5 dB are the options) + UINT8 Rsvd0[2]; ///<= Offset 126 + /** + Offset 128: + This contains the PCIe PERST# GPIO information. This structure is requ= ired + for PCIe Gen3 operation. The reference code will use the information in= this structure in + order to reset PCIe Gen3 devices during equalization, if necessary. Re= fer to the Platform + Developer's Guide (PDG) for additional details. + **/ + PEG_GPIO_DATA PegGpioData; + + /** + Offset 156 + (Test) PCIe Override RxCTLE. This feature should only be true to= disable RxCTLE adaptive behavior for compliance testing + - False (0x0) : Normal Operation - RxCTL= E adaptive behavior enabled (Default) + - True (0x1) : Override RxCTLE - Disab= le RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmod= ified + From CFL onwards, modularity is introduced to this setup option so that = the RxCTLE adaptive behavior could be controlled at the controller level. + Making this variable a UINT8 to accomodate the values of all controllers= as bit definition + **/ + UINT8 PegGen3RxCtleOverride; + UINT8 Reserved1; + UINT16 Reserved2; + +} PCIE_PEI_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _PCIE_PEI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/SaMiscPeiConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inc= lude/ConfigBlock/SaMiscPeiConfig.h new file mode 100644 index 0000000000..12648b836b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Sa= MiscPeiConfig.h @@ -0,0 +1,61 @@ +/** @file + Policy details for miscellaneous configuration in System Agent + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_MISC_PEI_CONFIG_H_ +#define _SA_MISC_PEI_CONFIG_H_ + +#pragma pack(push, 1) + +#ifndef SA_MC_MAX_SOCKETS +#define SA_MC_MAX_SOCKETS 4 +#endif + +#define SA_MISC_PEI_CONFIG_REVISION 1 + +/// +/// Subsystem Vendor ID / Subsystem ID +/// +typedef struct _SA_DEFAULT_SVID_SID{ + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} SA_DEFAULT_SVID_SID; + +/** + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Post-Mem.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + /** + Offset 28:0 + This policy is used to control enable or disable System Agent Thermal de= vice (0,4,0). + The default value is 1: TRUE for WHL, and 0: FALSE for all= other CPU's + **/ + UINT32 Device4Enable:1; + /** + Offset 28:1 + (Test)This policy is used to control enable or disable System Age= nt Chap device (0,7,0). + 0=3DFALSE, + 1=3DTRUE. + **/ + UINT32 ChapDeviceEnable:1; + /** + Offset 28:2 + For Platforms supporting Intel(R) SIPP, this policy is use control enabl= e/disable Compatibility Revision ID (CRID) feature. + 0=3DFALSE, + 1=3DTRUE + **/ + UINT32 CridEnable:1; + UINT32 SkipPamLock:1; ///< Offset 28:3 :To skip PAM= register locking. @note It is still recommended to set PCI Config space B0= : D0: F0: Offset 80h[0]=3D1 in platform code even Silicon code skipped this= .\n 0=3DAll PAM registers will be locked in Silicon code, 1=3DSkip l= ock PAM registers in Silicon code. + UINT32 EdramTestMode:2; ///< Offset 28:4 :EDRAM Test = Mode. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, 2- = EDRAM HW Mode + UINT32 RsvdBits0 :26; ///< Offset 28:7 :Reserved fo= r future use +} SA_MISC_PEI_CONFIG; +#pragma pack(pop) + +#endif // _SA_MISC_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/SaMiscPeiPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAge= nt/Include/ConfigBlock/SaMiscPeiPreMemConfig.h new file mode 100644 index 0000000000..2c831404ef --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Sa= MiscPeiPreMemConfig.h @@ -0,0 +1,103 @@ +/** @file + Policy details for miscellaneous configuration in System Agent + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_ +#define _SA_MISC_PEI_PREMEM_CONFIG_H_ + +#pragma pack(push, 1) + +#ifndef SA_MC_MAX_SOCKETS +#define SA_MC_MAX_SOCKETS 4 +#endif + +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 3 + +/** + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Pre-Mem phase like programming + different System Agent BARs, TsegSize, IedSize, MmioSize required etc. + Revision 1: + - Initial version. + Revision 2: + - add BdatTestType, default is RMT + Revision 3: + - Remove SgSubSystemId. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 SpdAddressTable[SA_MC_MAX_SOCKETS];///< Offset 28 Memory DIMMs' = SPD address for reading SPD data. example: SpdAddressTable[0]=3D0xA2(C0D= 0), SpdAddressTable[1]=3D0xA0(C0D1), SpdAddressTable[2]=3D0xA2(C1D0), SpdAd= dressTable[3]=3D0xA0(C1D1) + VOID *S3DataPtr; ///< Offset 32 Memory data sa= ve pointer for S3 resume. The memory space should be allocated and filled w= ith proper S3 resume data on a resume path + UINT32 MchBar; ///< Offset 36 Address of Sys= tem Agent MCHBAR: 0xFED10000 + UINT32 DmiBar; ///< Offset 40 Address of Sys= tem Agent DMIBAR: 0xFED18000 + UINT32 EpBar; ///< Offset 44 Address of Sys= tem Agent EPBAR: 0xFED19000 + UINT32 SmbusBar; ///< Offset 48 Address of Sys= tem Agent SMBUS BAR: 0xEFA0 + UINT32 GdxcBar; ///< Offset 52 Address of Sys= tem Agent GDXCBAR: 0xFED84000 + /** + Offset 56 Size of TSEG in bytes. (Must be power of 2) + 0x400000: 4MB for Release build (When IED enabled, it will be 8= MB) + 0x1000000 : 16MB for Debug build (Regardless IED enabled or disab= led) + **/ + UINT32 TsegSize; + UINT32 EdramBar; ///< Offset 60 Address of Sys= tem Agent EDRAMBAR: 0xFED80000 + /** + Offset 64 + (Test) Size of IED region in bytes. + 0 : IED Disabled (no memory occupied) + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) + Note: Enabling IED may also enlarge TsegSize together. + **/ + UINT32 IedSize; + UINT8 UserBd; ///< Offset 68 0=3DMobile/= Mobile Halo, 1=3DDesktop/DT Halo, 5=3DULT/ULX/Mobile Halo, 7=3DUP Serve= r + UINT8 SgMode; ///< Offset 69 SgMode: 0= =3DDisabled, 1=3DSG Muxed, 2=3DSG Muxless, 3=3DPEG + UINT16 SgDelayAfterPwrEn; ///< Offset 70 Dgpu Delay aft= er Power enable using Setup option: 0=3DMinimal, 1000=3DMaximum, 300=3D3= 00 microseconds + UINT16 SgDelayAfterHoldReset; ///< Offset 72 Dgpu Delay aft= er Hold Reset using Setup option: 0=3DMinimal, 1000=3DMaximum, 100=3D100= microseconds + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 74:= 0 :1=3DSkip External Gfx Device Scan; 0=3DScan for external graphics dev= ices. Set this policy to skip External Graphics card scanning if the pl= atform uses Internal Graphics only. + UINT32 BdatEnable:1; ///< Offset 74:1 :This field = enables the generation of the BIOS DATA ACPI Tables: 0=3DFALSE, 1=3D= TRUE. + UINT32 TxtImplemented:1; ///< OFfset 74:2 :This field = currently is used to tell MRC if it should run after TXT initializatoin com= pleted: 0=3DRun without waiting for TXT, 1=3DRun after TXT initializ= ation by callback + /** + Offset 74:3 : + (Test) Scan External Discrete Graphics Devices for Legacy Only V= GA OpROMs + + When enabled, if the primary graphics device is an external discrete gr= aphics device, Si will scan the + graphics device for legacy only VGA OpROMs. If the primary graphics de= vice only implements legacy VBIOS, then the + LegacyOnlyVgaOpRomDetected field in the SA_DATA_HOB will be set to 1. + + This is intended to ease the implementation of a BIOS feature to automa= tically enable CSM if the Primary Gfx device + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling = CSM won't result in no video being displayed. + This is useful for platforms that implement PCIe slots that allow the e= nd user to install an arbitrary Gfx device. + + This setting will only take effect if SkipExtGfxScan =3D=3D 0. It is i= gnored otherwise. + + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Defaul= t) + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM + **/ + UINT32 ScanExtGfxForLegacyOpRom:1; + UINT32 RsvdBits0 :28; ///< OFfset 74:4 :Reserved fo= r future use + UINT8 LockPTMregs; ///< (Test) Offset 78 = Lock PCU Thermal Management registers: 0=3DFALSE, 1=3DTRUE + UINT8 BdatTestType; ///< Offset 79 When BdatEnabl= e is set to TRUE, this option selects the type of data which will be popula= ted in the BIOS Data ACPI Tables: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMarg= in 2D. + UINT8 Rsvd1[4]; ///< Offset 80 Reserved for f= uture use + /** + Offset 84 : + Size of reserved MMIO space for PCI devices\n + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D1280M= B, 1536=3D1536MB, 1792=3D1792MB, + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, 3072=3D307= 2MB\n + When AUTO mode selected, the MMIO size will be calculated by required = MMIO size from PCIe devices detected. + **/ + UINT16 MmioSize; + INT16 MmioSizeAdjustment; ///< Offset 86 Increase (give= n positive value) or Decrease (given negative value) the Reserved MMIO size= when Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno adjustment + UINT64 AcpiReservedMemoryBase; ///< Offset 88 The Base addre= ss of a Reserved memory buffer allocated in previous boot for S3 resume use= d. Originally it is retrieved from AcpiVariableCompatibility variable. + UINT64 SystemMemoryLength; ///< Offset 96 Total system m= emory length from previous boot, this is required for S3 resume. Originally= it is retrieved from AcpiVariableCompatibility variable. + UINT32 AcpiReservedMemorySize; ///< Offset 104 The Size of a= Reserved memory buffer allocated in previous boot for S3 resume used. Orig= inally it is retrieved from AcpiVariableCompatibility variable. + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 108= Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanEx= tGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED! + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 112= Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom fea= ture. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >=3D 16MB! + + // Since the biggest element is UINT64, this structure should be aligned= with 64 bits. + UINT8 Rsvd[4]; ///< Reserved for config bloc= k alignment. +} SA_MISC_PEI_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/SwitchableGraphicsConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/System= Agent/Include/ConfigBlock/SwitchableGraphicsConfig.h new file mode 100644 index 0000000000..cc6179a61c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Sw= itchableGraphicsConfig.h @@ -0,0 +1,63 @@ +/** @file + Switchable Graphics policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SWITCHABLE_GRAPHICS_CONFIG_H_ +#define _SWITCHABLE_GRAPHICS_CONFIG_H_ + +#define SWITCHABLE_GRAPHICS_CONFIG_REVISION 1 + +#define GP_ENABLE 1 +#define GP_DISABLE 0 + +#pragma pack(push, 1) +/// +/// GPIO Support +/// +typedef enum { + NotSupported =3D 0, + PchGpio, + I2CGpio, +} GPIO_SUPPORT; + +/// +/// SA GPIO Data Structure +/// +typedef struct { + UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO + BOOLEAN Active; ///< Offset 1 0=3DActive Low; 1=3DActive High + UINT8 Rsvd0[2]; ///< Offset 2 Reserved + UINT32 GpioNo; ///< Offset 4 GPIO pad +} SA_GPIO_INFO; + +/** + SA PCIE RTD3 GPIO Data Structure +**/ +typedef struct { + SA_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD RE= SET GPIO value and level information + SA_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe PWR En= able GPIO value and level information + UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3 = Device Wake GPIO Number + UINT8 GpioSupport; ///< Offset 20 Depends on board design the G= PIO configuration may be different: 0=3DNot Supported, 1=3DPCH Based= , 2=3DI2C based + UINT8 Rsvd0[3]; ///< Offset 21 +} SA_PCIE_RTD3_GPIO; + +/** + This Configuration block configures SA PCI Express 0/1/2 RTD3 GPIOs & Ro= ot Port. + Swithable Gfx/Hybrid Gfx uses the same GPIOs & Root port as PCI Express = 0/1/2 RTD3. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block He= ader + SA_PCIE_RTD3_GPIO SaRtd3Pcie0Gpio; ///< Offset 28 RTD3 GPIOs used f= or PCIe0 + SA_PCIE_RTD3_GPIO SaRtd3Pcie1Gpio; ///< Offset 52 RTD3 GPIOs used f= or PCIe1 + SA_PCIE_RTD3_GPIO SaRtd3Pcie2Gpio; ///< Offset 76 RTD3 GPIOs used f= or PCIe2 + UINT8 RootPortIndex; ///< Offset 124 Root Port Index = number used for SG + UINT8 Rsvd0[3]; ///< Offset 125 Reserved for DWO= RD Alignment +} SWITCHABLE_GRAPHICS_CONFIG; +#pragma pack(pop) +#endif // _SWITCHABLE_GRAPHICS_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/VbiosDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Incl= ude/ConfigBlock/VbiosDxeConfig.h new file mode 100644 index 0000000000..690ad8630a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Vb= iosDxeConfig.h @@ -0,0 +1,39 @@ +/** @file + VBIOS DXE policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _VBIOS_DXE_CONFIG_H_ +#define _VBIOS_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define VBIOS_DXE_CONFIG_REVISION 1 + +/** + This data structure includes Switchable Graphics VBIOS configuration. + If Switchable Graphics/Hybrid Gfaphics feature is not supported, all the= policies in this configuration block can be ignored. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 LoadVbios : 1; ///< Offset 28:0 :This field = is used to describe if the dGPU VBIOS needs to be loaded: 0=3DNot load, 1=3DLoad + UINT8 ExecuteVbios : 1; ///< Offset 28:1 :This field = is used to describe if the dGPU VBIOS need to be executed: 0=3DNot execu= te, 1=3DExecute +/** + Offset 28:2 : + This field is used to identify the source location of dGPU VBIOS\n + 1 =3D secondary display device VBIOS Source is PCI Card\n + 0 =3D secondary display device VBIOS Source is FW Volume\n +**/ + UINT8 VbiosSource : 1; + UINT8 RsvdBits0 : 5; ///< Offset 28:3 Reserved for= future use + UINT8 Rsvd[3]; ///< Offset 29 : Reserved for= DWORD alignment +} VBIOS_DXE_CONFIG; +#pragma pack(pop) + +#endif // _VBIOS_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/VtdConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/C= onfigBlock/VtdConfig.h new file mode 100644 index 0000000000..adde1f836b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Vt= dConfig.h @@ -0,0 +1,42 @@ +/** @file + VT-d policy definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _VTD_CONFIG_H_ +#define _VTD_CONFIG_H_ + +#pragma pack(push, 1) + +#define VTD_CONFIG_REVISION 2 + +/** + The data elements should be initialized by a Platform Module. + The data structure is for VT-d driver initialization\n + Revision 1: + - Initial version. + Revision 2: + - Add DMA_CONTROL_GUARANTEE bit in the DMAR table +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block Header + /** + Offset 28:0 : + VT-D Support can be verified by reading CAP ID register as expalined i= n BIOS Spec. + This policy is for debug purpose only. + If VT-D is not supported, all other policies in this config block will= be ignored. + 0 =3D To use Vt-d; + 1 =3D Avoids programming Vtd bars, Vtd overrides and DMAR table. + **/ + UINT32 VtdDisable : 1; + UINT32 X2ApicOptOut : 1; ///< Offset 28:1 :This= field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnab= le/Set and 0=3DDisable/Clear + UINT32 DmaControlGuarantee : 1; ///< Offset 28:2 :This= field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1= =3DEnable/Set and 0=3DDisable/Clear + UINT32 RsvdBits0 : 29; ///< Offset 28:3 :Rese= rved bits for future use + UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< Offset 32: This f= ield is used to describe the base addresses for VT-d function: BaseAddre= ss[0]=3D0xFED90000, BaseAddress[1]=3D0xFED92000, BaseAddress[2]=3D0xFED9100= 0 +} VTD_CONFIG; +#pragma pack(pop) + +#endif // _VTD_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRema= ppingTable.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRe= mappingTable.h new file mode 100644 index 0000000000..a1d88cb5a2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTa= ble.h @@ -0,0 +1,77 @@ +/** @file + This code defines ACPI DMA Remapping table related definitions. + See the System Agent BIOS specification for definition of the table. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DMA_REMAPPING_TABLE_H_ +#define _DMA_REMAPPING_TABLE_H_ + +#include +#include +#include +#include + +#pragma pack(1) +/// +/// DMAR table signature +/// +#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///< "DMAR" +#define EFI_ACPI_DMAR_TABLE_REVISION 1 +#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10 +#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18 +#define MAX_PCI_DEPTH 5 + +typedef struct { + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER DeviceScopeStructureHeader; + EFI_ACPI_DMAR_PCI_PATH PciPath; // device, func= tion +} EFI_ACPI_DEV_SCOPE_STRUCTURE; + +typedef struct { + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; +} EFI_ACPI_DRHD_ENGINE1_STRUCT; + +typedef struct { + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader; + // + // @todo use PCD + // + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; +} EFI_ACPI_DRHD_ENGINE3_STRUCT; + +typedef struct { + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; +} EFI_ACPI_RMRR_USB_STRUC; + +typedef struct { + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD +} EFI_ACPI_RMRR_IGD_STRUC; + +typedef struct { + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // CSME +} EFI_ACPI_RMRR_CSME_STRUC; + +typedef struct { + EFI_ACPI_DMAR_ANDD_HEADER AnddHeader; + UINT8 AcpiObjectName[20]; +} EFI_ACPI_ANDD_STRUC; + +typedef struct { + EFI_ACPI_DMAR_HEADER DmarHeader; + EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1; + EFI_ACPI_DRHD_ENGINE3_STRUCT DrhdEngine3; + EFI_ACPI_RMRR_USB_STRUC RmrrUsb; + EFI_ACPI_RMRR_IGD_STRUC RmrrIgd; + EFI_ACPI_RMRR_CSME_STRUC RmrrCsme; +} EFI_ACPI_DMAR_TABLE; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library= /DxeSaPolicyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/= Library/DxeSaPolicyLib.h new file mode 100644 index 0000000000..663b0f2202 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaP= olicyLib.h @@ -0,0 +1,60 @@ +/** @file + Prototype of the DxeSaPolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SA_POLICY_LIB_H_ +#define _DXE_SA_POLICY_LIB_H_ + +#include + +/** + This function prints the DXE phase policy. + + @param[in] SaPolicy - SA DXE Policy protocol +**/ +VOID +SaPrintPolicyProtocol ( + IN SA_POLICY_PROTOCOL *SaPolicy + ) +; + +/** + CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SaPolicy The pointer to get SA Policy Proto= col instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CreateSaDxeConfigBlocks( + IN OUT SA_POLICY_PROTOCOL **SaPolicy +); + +/** + SaInstallPolicyProtocol installs SA Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SaPolicy The pointer to SA Policy Protocol = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +SaInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN SA_POLICY_PROTOCOL *SaPolicy + ) +; + +#endif // _DXE_SA_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library= /PeiSaPolicyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/= Library/PeiSaPolicyLib.h new file mode 100644 index 0000000000..c29d67a305 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaP= olicyLib.h @@ -0,0 +1,87 @@ +/** @file + Prototype of the PeiSaPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SA_POLICY_LIB_H_ +#define _PEI_SA_POLICY_LIB_H_ + +#include +#include + +/** + This function prints the PEI phase PreMem policy. + + @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI insta= nce +**/ +VOID +EFIAPI +SaPrintPolicyPpiPreMem ( + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi + ); + +/** + This function prints the PEI phase policy. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +SaPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get SA config block table total size. + + @retval Size of SA config block table +**/ +UINT16 +EFIAPI +SaGetConfigBlockTotalSize ( + VOID + ); + +/** + Get SA config block table total size. + + @retval Size of SA config block table +**/ +UINT16 +EFIAPI +SaGetConfigBlockTotalSizePreMem ( + VOID + ); + +/** + SaAddConfigBlocksPreMem add all SA config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add SA config block= s + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +SaAddConfigBlocksPreMem ( + IN VOID *ConfigBlockTableAddress + ); + +/** + SaAddConfigBlocks add all SA config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add SA config block= s + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +SaAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _PEI_SA_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library= /SaPlatformLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/L= ibrary/SaPlatformLib.h new file mode 100644 index 0000000000..a1289abe81 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlat= formLib.h @@ -0,0 +1,88 @@ +/** @file + Header file for SaPlatformLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PLATFORM_LIB_H_ +#define _SA_PLATFORM_LIB_H_ + +#include +#include + +/** + Determine if PCH Link is DMI/OPI + + @param[in] CpuModel CPU model + + @retval TRUE DMI + @retval FALSE OPI +**/ +BOOLEAN +IsPchLinkDmi ( + IN CPU_FAMILY CpuModel + ); + +/** + Returns the number of DMI lanes for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxDmiLanes ( + ); + + +/** + Returns the number of DMI bundles for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxDmiBundles ( + ); + + +/** + Returns the function numbers for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegFuncs ( + ); + + +/** + Returns the number of DMI lanes for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegLanes ( + ); + + +/** + Returns the number of DMI bundles for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegBundles ( + ); + +/** + Checks if PEG port is present + + @retval TRUE PEG is presented + @retval FALSE PEG is not presented +**/ +BOOLEAN +IsPegPresent ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfo= Hob.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h new file mode 100644 index 0000000000..da285bbcba --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h @@ -0,0 +1,259 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the c= ontroller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is di= sabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is ena= bled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be= detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of p= resence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pa= ir and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank p= air. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef bmCold +#define bmCold 0 // Cold boot +#endif +#ifndef bmWarm +#define bmWarm 1 // Warm boot +#endif +#ifndef bmS3 +#define bmS3 2 // S3 resume +#endif +#ifndef bmFast +#define bmFast 3 // Fast boot +#endif + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's comma= nd rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS l= atency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minim= um CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minim= um four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minim= um active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minim= um RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minim= um Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minim= um per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minim= um row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minim= um internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minim= um write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum= CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the = same bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when sw= itching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when sw= itching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when sw= itching between DIMMs. +} MRC_TA_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the= definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DD= R3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20= bytes + UINT8 RankInDimm; ///< The number of ranks in th= is DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType i= nformation needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType infor= mation needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusW= idth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing in= formation needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed= of the device, in MHz. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this ch= annel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs tha= t exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values= . + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output char= acteristics. + MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Aroun= d Timings + MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Aroun= d Timings + MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Aroun= d Timings + MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Aroun= d Timings +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this c= ontroller should be used. + UINT16 DeviceId; ///< The PCI device id of thi= s memory controller. + UINT8 RevisionId; ///< The PCI revision id of t= his memory controller. + UINT8 ChannelCount; ///< Number of valid channels= that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channe= l level definitions. + MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to = CHANNEL_INFO. Read-to-Read Turn Around Timings + MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to = CHANNEL_INFO. Read-to-Write Turn Around Timings + MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to = CHANNEL_INFO. Write-to-Read Turn Around Timings + MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to = CHANNEL_INFO. Write-to-Write Turn Around Timings +} CONTROLLER_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of t= his memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or = LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed= of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock = speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK= value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable= DIMMs are detected, this will indicate which XMP Profiles are common among= all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddre= ss fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT32 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + UINT32 GdxcIotBase; + UINT32 GdxcIotSize; + UINT32 GdxcMotBase; + UINT32 GdxcMotSize; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/GraphicsInitLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent= /Include/Private/Library/GraphicsInitLib.h new file mode 100644 index 0000000000..ff7cfa838f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/GraphicsInitLib.h @@ -0,0 +1,15 @@ +/** @file + Graphics header file + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_INIT_H_ +#define _GRAPHICS_INIT_H_ + +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/LegacyRegion.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/In= clude/Private/Library/LegacyRegion.h new file mode 100644 index 0000000000..497c860824 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/LegacyRegion.h @@ -0,0 +1,33 @@ +/** @file + This code supports a private implementation of the Legacy Region protoco= l. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _LEGACY_REGION_H_ +#define _LEGACY_REGION_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Install Driver to produce Legacy Region protocol. + + @param[in] ImageHandle Handle for the image of this driver + + @retval EFI_SUCCESS - Legacy Region protocol installed + @retval Other - No protocol installed, unload driver. +**/ +EFI_STATUS +LegacyRegionInstall ( + IN EFI_HANDLE ImageHandle + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/PeiCpuTraceHubLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAge= nt/Include/Private/Library/PeiCpuTraceHubLib.h new file mode 100644 index 0000000000..8bf46528ab --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/PeiCpuTraceHubLib.h @@ -0,0 +1,23 @@ +/** @file + Header file for North TraceHub Lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _NORTH_TRACEHUB_LIB_H_ +#define _NORTH_TRACEHUB_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/SaPcieLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/Private/Library/SaPcieLib.h new file mode 100644 index 0000000000..19dd634a35 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/SaPcieLib.h @@ -0,0 +1,70 @@ +/** @file + Defines and prototypes for the System Agent PCIe library module + This library is expected to share between DXE and SMM drivers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PCIE_LIB_H_ +#define _SA_PCIE_LIB_H_ + +#include +#include + +#define MAX_SUPPORTED_ROOT_BRIDGE_NUMBER 3 +#define MAX_SUPPORTED_DEVICE_NUMBER 192 + +/** + Enumerate all end point devices connected to root bridge ports and recor= d their MMIO base address + + @exception EFI_UNSUPPORTED PCIe capability structure not found + @retval EFI_SUCCESS All done successfully +**/ +EFI_STATUS +EnumerateAllPcieDevices ( + VOID + ); + +/** + Sets Common Clock, TCx-VC0 mapping, and Max Payload for PCIe +**/ +VOID +SaPcieConfigBeforeOpRom ( + VOID + ); + +/** + This function does all SA ASPM initialization +**/ +VOID +SaAspm ( + VOID + ); + +/** + This function checks PEG end point device for extended tag capability an= d enables them if they are. +**/ +VOID +EnableExtendedTag ( + VOID + ); + +/** + This function handles SA S3 resume +**/ +VOID +SaS3Resume ( + VOID + ); + +/** + Wrapper function for all SA S3 resume tasks which can be a callback func= tion. +**/ +VOID +SaS3ResumeCallback ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Protocol/SaIotrapSmi.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/In= clude/Private/Protocol/SaIotrapSmi.h new file mode 100644 index 0000000000..2c765b09b8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protoc= ol/SaIotrapSmi.h @@ -0,0 +1,36 @@ +/** @file + This file defines the SA Iotrap SMI Protocol to provide the + I/O address for registered Iotrap SMI. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_ +#define _SA_IOTRAP_SMI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gSaIotrapSmiProtocolGuid; + +#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1 + +// +// SA IO Trap SMI Protocol definition (Private protocol for RC internal us= e only) +// +typedef struct { +/* + Protocol revision number + Any backwards compatible changes to this protocol will result in an updat= e in the revision number + Major changes will require publication of a new protocol + + Revision 1: + - First version +*/ + UINT8 Revision; + UINT16 SaIotrapSmiAddress; +} SA_IOTRAP_SMI_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Protocol/SaNvsArea.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Incl= ude/Private/Protocol/SaNvsArea.h new file mode 100644 index 0000000000..1bae2d95e5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protoc= ol/SaNvsArea.h @@ -0,0 +1,31 @@ +/** @file + Definition of the System Agent global NVS area protocol. + This protocol publishes the address and format of a global ACPI NVS buff= er + used as a communications buffer between SMM/DXE/PEI code and ASL code. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SYSTEM_AGENT_NVS_AREA_H_ +#define _SYSTEM_AGENT_NVS_AREA_H_ + +// +// SA NVS Area definition +// +#include + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gSaNvsAreaProtocolGuid; + +/// +/// System Agent Global NVS Area Protocol +/// +typedef struct { + SYSTEM_AGENT_NVS_AREA *Area; ///< System Agent Global NVS Area St= ructure +} SYSTEM_AGENT_NVS_AREA_PROTOCOL; + +#endif // _SYSTEM_AGENT_NVS_AREA_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /SaConfigHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Pri= vate/SaConfigHob.h new file mode 100644 index 0000000000..f1b72488ca --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConf= igHob.h @@ -0,0 +1,89 @@ +/** @file + The GUID definition for SaConfigHob + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_CONFIG_HOB_H_ +#define _SA_CONFIG_HOB_H_ + +#include +#include + +extern EFI_GUID gSaConfigHobGuid; + +#pragma pack (push,1) +/// +#define DPR_DIRECTORY_MAX 2 ///< DPR Maximum Size +/// DPR directory entry definition +/// +typedef struct { + UINT8 Type; ///< DPR Directory Type + UINT8 Size; ///< DPR Size in MB + UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear= ) + UINT16 Reserved; ///< Must be 0 +} DPR_DIRECTORY_ENTRY; + +/// +/// The data elements should be initialized by a Platform Module. +/// The data structure is for VT-d driver initialization +/// +typedef struct { + BOOLEAN VtdDisable; ///< 1 =3D Avoi= ds programming Vtd bars, Vtd overrides and DMAR table + UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< This field= is used to describe the base addresses for VT-d function + BOOLEAN X2ApicOptOut; ///< This field= is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnable/= Set and 0=3DDisable/Clear + BOOLEAN InterruptRemappingSupport; ///< This field= is used to indicate Interrupt Remapping supported or not +} SA_VTD_CONFIGURATION_HOB; + +/// +/// SA GPIO Data Structure +/// +typedef struct { + UINT8 ExpanderNo; ///< =3DExpander No For I2C based GPIO + UINT32 GpioNo; ///< GPIO pad + BOOLEAN Active; ///< 0=3DActive Low; 1=3DActive High +} SA_GPIO; + +/// +/// SA PCIE RTD3 GPIO Data Structure +/// +typedef struct { + UINT8 GpioSupport; ///< 0=3DNot Supported; 1=3DPCH bas= ed; 2=3DI2C Based + SA_GPIO HoldRst; ///< Offset 8 This field contain PC= Ie HLD RESET GPIO value and level information + SA_GPIO PwrEnable; ///< This field contain PCIe PWR En= able GPIO value and level information + UINT32 WakeGpioNo; ///< This field contain PCIe RTD3 D= evice Wake GPIO number +} PCIE_RTD3_GPIO; + +/// +/// SG Info HOB +/// +typedef struct { + SG_MODE SgMode; + UINT8 RootPortIndex; + PCIE_RTD3_GPIO Rtd3Pcie0Gpio; + PCIE_RTD3_GPIO Rtd3Pcie1Gpio; + PCIE_RTD3_GPIO Rtd3Pcie2Gpio; + UINT16 DelayAfterPwrEn; + UINT16 DelayAfterHoldReset; +} SA_RTD3; + +/// +/// System Agent Config Hob +/// +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< = GUID Hob type structure for gSaConfigHobGuid + DPR_DIRECTORY_ENTRY DprDirectory[DPR_DIRECTORY_MAX]; ///< = DPR directory entry definition + BOOLEAN InitPcieAspmAfterOprom; ///< = 1=3Dinitialize PCIe ASPM after Oprom; 0=3Dbefore (This will be set basing o= n policy) + SA_RTD3 SaRtd3; ///< = SG Info HOB + UINT8 ApertureSize; ///< = Aperture size value + UINT8 IpuAcpiMode; ///< = IPU ACPI mode: 0=3DDisabled, 1=3DIGFX Child device, 2=3DACPI device + SA_VTD_CONFIGURATION_HOB VtdData; ///< = VT-d Data HOB + BOOLEAN CridEnable; ///< = This field inidicates if CRID is enabled or disabled (to support Intel(R) S= IPP) + BOOLEAN SkipPamLock; ///< = 0=3DAll PAM registers will be locked in System Agent code, 1=3DDo not lock = PAM registers in System Agent code. + UINT8 PowerDownUnusedBundles[SA_PEG_MAX_FUN]; ///< = PCIe power down unused bundles support + UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///< = PEG Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B) +} SA_CONFIG_HOB; +#pragma pack (pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /SaNvsAreaDef.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Pr= ivate/SaNvsAreaDef.h new file mode 100644 index 0000000000..095942d483 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsA= reaDef.h @@ -0,0 +1,151 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define SA NVS Area operatino region. + // + +#ifndef _SA_NVS_AREA_DEF_H_ +#define _SA_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + UINT32 IgdOpRegionAddress; ///< Offset 0 IG= D OpRegion base address + UINT8 GfxTurboIMON; ///< Offset 4 IM= ON Current Value + UINT8 IgdState; ///< Offset 5 IG= D State (Primary Display =3D 1) + UINT8 IgdBootType; ///< Offset 6 IG= D Boot Display Device + UINT8 IgdPanelType; ///< Offset 7 IG= D Panel Type CMOS option + UINT8 IgdPanelScaling; ///< Offset 8 IG= D Panel Scaling + UINT8 IgdBiaConfig; ///< Offset 9 IG= D BIA Configuration + UINT8 IgdSscConfig; ///< Offset 10 IG= D SSC Configuration + UINT8 IgdDvmtMemSize; ///< Offset 11 IG= D DVMT Memory Size + UINT8 IgdFunc1Enable; ///< Offset 12 IG= D Function 1 Enable + UINT8 IgdHpllVco; ///< Offset 13 HP= LL VCO + UINT8 IgdSciSmiMode; ///< Offset 14 GM= CH SMI/SCI mode (0=3DSCI) + UINT8 IgdPAVP; ///< Offset 15 IG= D PAVP data + UINT8 CurrentDeviceList; ///< Offset 16 Cu= rrent Attached Device List + UINT16 CurrentDisplayState; ///< Offset 17 Cu= rrent Display State + UINT16 NextDisplayState; ///< Offset 19 Ne= xt Display State + UINT8 NumberOfValidDeviceId; ///< Offset 21 Nu= mber of Valid Device IDs + UINT32 DeviceId1; ///< Offset 22 De= vice ID 1 + UINT32 DeviceId2; ///< Offset 26 De= vice ID 2 + UINT32 DeviceId3; ///< Offset 30 De= vice ID 3 + UINT32 DeviceId4; ///< Offset 34 De= vice ID 4 + UINT32 DeviceId5; ///< Offset 38 De= vice ID 5 + UINT32 DeviceId6; ///< Offset 42 De= vice ID 6 + UINT32 DeviceId7; ///< Offset 46 De= vice ID 7 + UINT32 DeviceId8; ///< Offset 50 De= vice ID 8 + UINT32 DeviceId9; ///< Offset 54 De= vice ID 9 + UINT32 DeviceId10; ///< Offset 58 De= vice ID 10 + UINT32 DeviceId11; ///< Offset 62 De= vice ID 11 + UINT32 DeviceId12; ///< Offset 66 De= vice ID 12 + UINT32 DeviceId13; ///< Offset 70 De= vice ID 13 + UINT32 DeviceId14; ///< Offset 74 De= vice ID 14 + UINT32 DeviceId15; ///< Offset 78 De= vice ID 15 + UINT32 DeviceIdX; ///< Offset 82 De= vice ID for eDP device + UINT32 NextStateDid1; ///< Offset 86 Ne= xt state DID1 for _DGS + UINT32 NextStateDid2; ///< Offset 90 Ne= xt state DID2 for _DGS + UINT32 NextStateDid3; ///< Offset 94 Ne= xt state DID3 for _DGS + UINT32 NextStateDid4; ///< Offset 98 Ne= xt state DID4 for _DGS + UINT32 NextStateDid5; ///< Offset 102 Ne= xt state DID5 for _DGS + UINT32 NextStateDid6; ///< Offset 106 Ne= xt state DID6 for _DGS + UINT32 NextStateDid7; ///< Offset 110 Ne= xt state DID7 for _DGS + UINT32 NextStateDid8; ///< Offset 114 Ne= xt state DID8 for _DGS + UINT32 NextStateDidEdp; ///< Offset 118 Ne= xt state DID for eDP + UINT8 LidState; ///< Offset 122 Li= d State (Lid Open =3D 1) + UINT32 AKsv0; ///< Offset 123 Fi= rst four bytes of AKSV (manufacturing mode) + UINT8 AKsv1; ///< Offset 127 Fi= fth byte of AKSV (manufacturing mode) + UINT8 BrightnessPercentage; ///< Offset 128 Br= ightness Level Percentage + UINT8 AlsEnable; ///< Offset 129 Am= bient Light Sensor Enable + UINT8 AlsAdjustmentFactor; ///< Offset 130 Am= bient Light Adjusment Factor + UINT8 LuxLowValue; ///< Offset 131 LU= X Low Value + UINT8 LuxHighValue; ///< Offset 132 LU= X High Value + UINT8 ActiveLFP; ///< Offset 133 Ac= tive LFP + UINT8 IpuAcpiMode; ///< Offset 134 IP= U ACPI device type (0=3DDisabled, 1=3DAVStream virtual device as child of G= FX) + UINT8 EdpValid; ///< Offset 135 Ch= eck for eDP display device + UINT8 SgMode; ///< Offset 136 SG= Mode (0=3DDisabled, 1=3DSG Muxed, 2=3DSG Muxless, 3=3DDGPU Only) + UINT8 SgFeatureList; ///< Offset 137 SG= Feature List + UINT8 Pcie0GpioSupport; ///< Offset 138 PC= Ie0 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie0HoldRstExpanderNo; ///< Offset 139 PC= Ie0 HLD RST IO Expander Number + UINT32 Pcie0HoldRstGpioNo; ///< Offset 140 PC= Ie0 HLD RST GPIO Number + UINT8 Pcie0HoldRstActiveInfo; ///< Offset 144 PC= Ie0 HLD RST GPIO Active Information + UINT8 Pcie0PwrEnExpanderNo; ///< Offset 145 PC= Ie0 PWR Enable IO Expander Number + UINT32 Pcie0PwrEnGpioNo; ///< Offset 146 PC= Ie0 PWR Enable GPIO Number + UINT8 Pcie0PwrEnActiveInfo; ///< Offset 150 PC= Ie0 PWR Enable GPIO Active Information + UINT8 Pcie1GpioSupport; ///< Offset 151 PC= Ie1 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie1HoldRstExpanderNo; ///< Offset 152 PC= Ie1 HLD RST IO Expander Number + UINT32 Pcie1HoldRstGpioNo; ///< Offset 153 PC= Ie1 HLD RST GPIO Number + UINT8 Pcie1HoldRstActiveInfo; ///< Offset 157 PC= Ie1 HLD RST GPIO Active Information + UINT8 Pcie1PwrEnExpanderNo; ///< Offset 158 PC= Ie1 PWR Enable IO Expander Number + UINT32 Pcie1PwrEnGpioNo; ///< Offset 159 PC= Ie1 PWR Enable GPIO Number + UINT8 Pcie1PwrEnActiveInfo; ///< Offset 163 PC= Ie1 PWR Enable GPIO Active Information + UINT8 Pcie2GpioSupport; ///< Offset 164 PC= Ie2 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie2HoldRstExpanderNo; ///< Offset 165 PC= Ie2 HLD RST IO Expander Number + UINT32 Pcie2HoldRstGpioNo; ///< Offset 166 PC= Ie2 HLD RST GPIO Number + UINT8 Pcie2HoldRstActiveInfo; ///< Offset 170 PC= Ie2 HLD RST GPIO Active Information + UINT8 Pcie2PwrEnExpanderNo; ///< Offset 171 PC= Ie2 PWR Enable IO Expander Number + UINT32 Pcie2PwrEnGpioNo; ///< Offset 172 PC= Ie2 PWR Enable GPIO Number + UINT8 Pcie2PwrEnActiveInfo; ///< Offset 176 PC= Ie2 PWR Enable GPIO Active Information + UINT16 DelayAfterPwrEn; ///< Offset 177 De= lay after power enable for PCIe + UINT16 DelayAfterHoldReset; ///< Offset 179 De= lay after Hold Reset for PCIe + UINT8 Pcie0EpCapOffset; ///< Offset 181 PC= Ie0 Endpoint Capability Structure Offset + UINT32 XPcieCfgBaseAddress; ///< Offset 182 An= y Device's PCIe Config Space Base Address + UINT16 GpioBaseAddress; ///< Offset 186 GP= IO Base Address + UINT32 NvIgOpRegionAddress; ///< Offset 188 NV= IG opregion address + UINT32 NvHmOpRegionAddress; ///< Offset 192 NV= HM opregion address + UINT32 ApXmOpRegionAddress; ///< Offset 196 AM= DA opregion address + UINT8 Peg0LtrEnable; ///< Offset 200 La= tency Tolerance Reporting Enable + UINT8 Peg0ObffEnable; ///< Offset 201 Op= timized Buffer Flush and Fill + UINT8 Peg1LtrEnable; ///< Offset 202 La= tency Tolerance Reporting Enable + UINT8 Peg1ObffEnable; ///< Offset 203 Op= timized Buffer Flush and Fill + UINT8 Peg2LtrEnable; ///< Offset 204 La= tency Tolerance Reporting Enable + UINT8 Peg2ObffEnable; ///< Offset 205 Op= timized Buffer Flush and Fill + UINT8 Peg3LtrEnable; ///< Offset 206 La= tency Tolerance Reporting Enable + UINT8 Peg3ObffEnable; ///< Offset 207 Op= timized Buffer Flush and Fill + UINT16 PegLtrMaxSnoopLatency; ///< Offset 208 SA= Peg Latency Tolerance Reporting Max Snoop Latency + UINT16 PegLtrMaxNoSnoopLatency; ///< Offset 210 SA= Peg Latency Tolerance Reporting Max No Snoop Latency + UINT8 Peg0PowerDownUnusedBundles; ///< Offset 212 Pe= g0 Unused Bundle Control + UINT8 Peg1PowerDownUnusedBundles; ///< Offset 213 Pe= g1 Unused Bundle Control + UINT8 Peg2PowerDownUnusedBundles; ///< Offset 214 Pe= g2 Unused Bundle Control + UINT8 Peg3PowerDownUnusedBundles; ///< Offset 215 Pe= g3 Unused Bundle Control + UINT8 PackageCstateLimit; ///< Offset 216 Th= e lowest C-state for the package + UINT8 PwrDnBundlesGlobalEnable; ///< Offset 217 Pe= gx Unused Bundle Control Global Enable (0=3DDisabled, 1=3DEnabled) + UINT64 Mmio64Base; ///< Offset 218 Ba= se of above 4GB MMIO resource + UINT64 Mmio64Length; ///< Offset 226 Le= ngth of above 4GB MMIO resource + UINT32 CpuIdInfo; ///< Offset 234 CP= U ID info to get Family Id or Stepping + UINT8 Pcie1EpCapOffset; ///< Offset 238 PC= Ie1 Endpoint Capability Structure Offset + UINT8 Pcie2EpCapOffset; ///< Offset 239 PC= Ie2 Endpoint Capability Structure Offset + UINT8 Pcie0SecBusNum; ///< Offset 240 PC= Ie0 Secondary Bus Number (PCIe0 Endpoint Bus Number) + UINT8 Pcie1SecBusNum; ///< Offset 241 PC= Ie1 Secondary Bus Number (PCIe0 Endpoint Bus Number) + UINT8 Pcie2SecBusNum; ///< Offset 242 PC= Ie2 Secondary Bus Number (PCIe0 Endpoint Bus Number) + UINT32 Mmio32Base; ///< Offset 243 Ba= se of below 4GB MMIO resource + UINT32 Mmio32Length; ///< Offset 247 Le= ngth of below 4GB MMIO resource + UINT32 Pcie0WakeGpioNo; ///< Offset 251 PC= Ie0 RTD3 Device Wake GPIO Number + UINT32 Pcie1WakeGpioNo; ///< Offset 255 PC= Ie1 RTD3 Device Wake GPIO Number + UINT32 Pcie2WakeGpioNo; ///< Offset 259 PC= Ie2 RTD3 Device Wake GPIO Number + UINT8 VtdDisable; ///< Offset 263 VT= -d Enable/Disable + UINT32 VtdBaseAddress1; ///< Offset 264 VT= -d Base Address 1 + UINT32 VtdBaseAddress2; ///< Offset 268 VT= -d Base Address 2 + UINT32 VtdBaseAddress3; ///< Offset 272 VT= -d Base Address 3 + UINT16 VtdEngine1Vid; ///< Offset 276 VT= -d Engine#1 Vendor ID + UINT16 VtdEngine2Vid; ///< Offset 278 VT= -d Engine#2 Vendor ID + UINT8 Pcie3SecBusNum; ///< Offset 280 PC= Ie3 Secondary Bus Number (PCIe3 Endpoint Bus Number) + UINT8 Pcie3GpioSupport; ///< Offset 281 PC= Ie3 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie3HoldRstExpanderNo; ///< Offset 282 PC= Ie3 HLD RST IO Expander Number + UINT32 Pcie3HoldRstGpioNo; ///< Offset 283 PC= Ie3 HLD RST GPIO Number + UINT8 Pcie3HoldRstActiveInfo; ///< Offset 287 PC= Ie3 HLD RST GPIO Active Information + UINT8 Pcie3PwrEnExpanderNo; ///< Offset 288 PC= Ie3 PWR Enable IO Expander Number + UINT32 Pcie3PwrEnGpioNo; ///< Offset 289 PC= Ie3 PWR Enable GPIO Number + UINT8 Pcie3PwrEnActiveInfo; ///< Offset 293 PC= Ie3 PWR Enable GPIO Active Information + UINT32 Pcie3WakeGpioNo; ///< Offset 294 PC= Ie3 RTD3 Device Wake GPIO Number + UINT8 Pcie3EpCapOffset; ///< Offset 298 PC= Ie3 Endpoint Capability Structure Offset + UINT8 RootPortIndex; ///< Offset 299 Ro= otPort Number + UINT32 RootPortAddress; ///< Offset 300 Ro= otPortAddress + UINT8 Reserved0[196]; ///< Offset 304:499 +} SYSTEM_AGENT_NVS_AREA; + +#pragma pack(pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/GopComponentName2.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Incl= ude/Protocol/GopComponentName2.h new file mode 100644 index 0000000000..a9db25404f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopCo= mponentName2.h @@ -0,0 +1,63 @@ +/** @file + Protocol to retrieve the GOP driver version + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GOP_COMPONENT_NAME2_H_ +#define _GOP_COMPONENT_NAME2_H_ + + +typedef struct _GOP_COMPONENT_NAME2_PROTOCOL GOP_COMPONENT_NAME2_PROTOCOL= ; + +/// +/// GOP Component protocol for retrieving driver name +/// +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + +/// +/// GOP Component protocol for retrieving controller name +/// +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +/// +/// GOP Component protocol for retrieving driver version +/// +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN CHAR8 *Language, + OUT CHAR16 **DriverVersion + ); + +/** + GOP Component protocol\n + This protocol will be installed by GOP driver and can be used to retriev= e GOP information. +**/ +struct _GOP_COMPONENT_NAME2_PROTOCOL { + GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; ///< Pr= otocol function to get driver name + GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; ///< Pr= otocol function to get driver version + GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; ///< Pr= otocol function to get controller name + CHAR8 *SupportedLanguages; ///< Nu= mber of Supported languages. +}; + +extern EFI_GUID gGopComponentName2ProtocolGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/GopPolicy.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Prot= ocol/GopPolicy.h new file mode 100644 index 0000000000..866f60b9c2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPo= licy.h @@ -0,0 +1,73 @@ +/** @file + Interface definition for GopPolicy Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GOP_POLICY_PROTOCOL_H_ +#define _GOP_POLICY_PROTOCOL_H_ + + +#define GOP_POLICY_PROTOCOL_REVISION_01 0x01 +#define GOP_POLICY_PROTOCOL_REVISION_03 0x03 + +typedef enum { + LidClosed, + LidOpen, + LidStatusMax +} LID_STATUS; + +typedef enum { + Docked, + UnDocked, + DockStatusMax +} DOCK_STATUS; + +/// +/// Function to retrieve LID status +/// +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_LID_STATUS) ( + OUT LID_STATUS * CurrentLidStatus + ); + +/// +/// Function to retrieve Dock status +/// +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_DOCK_STATUS) ( + OUT DOCK_STATUS CurrentDockStatus +); + +/// +/// Function to retrieve VBT table address and size +/// +typedef +EFI_STATUS +(EFIAPI *GET_VBT_DATA) ( + OUT EFI_PHYSICAL_ADDRESS * VbtAddress, + OUT UINT32 *VbtSize + ); + +/** + System Agent Graphics Output Protocol (GOP) - Policy Protocol\n + Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs= for EFI boot\n + When GOP Driver is used this protocol can be consumed by GOP driver or p= latform code for GOP relevant initialization\n + All functions in this protocol should be initialized by platform code ba= sing on platform implementation\n +**/ +typedef struct { + UINT32 Revision; ///< Protocol revision + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol function = to get Lid Status. Platform code should provide this function basing on des= ign. + GET_VBT_DATA GetVbtData; ///< Protocol function = to get Vbt Data address and size. Platform code should provide this functio= n basing on design. + GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function pointer = for get platform dock status. + EFI_GUID GopOverrideGuid; ///< A GUID provided b= y BIOS in case GOP is to be overridden. +} GOP_POLICY_PROTOCOL; + +extern EFI_GUID gGopPolicyProtocolGuid; +extern EFI_GUID gIntelGraphicsVbtGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/IgdOpRegion.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Pr= otocol/IgdOpRegion.h new file mode 100644 index 0000000000..ef2edfe122 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOp= Region.h @@ -0,0 +1,24 @@ +/** @file + This file is part of the IGD OpRegion Implementation. The IGD OpRegion = is + an interface between system BIOS, ASL code, and Graphics drivers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IGD_OPREGION_PROTOCOL_H_ +#define _IGD_OPREGION_PROTOCOL_H_ + +#include + +extern EFI_GUID gIgdOpRegionProtocolGuid; + +/// +/// IGD OpRegion Protocol +/// +typedef struct { + IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure +} IGD_OPREGION_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/MemInfo.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoc= ol/MemInfo.h new file mode 100644 index 0000000000..031e55b9b4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemIn= fo.h @@ -0,0 +1,132 @@ +/** @file + This protocol provides the memory information data, such as + total physical memory size, memory frequency, memory size + of each dimm and rank. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEM_INFO_PROTOCOL_H_ +#define _MEM_INFO_PROTOCOL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gMemInfoProtocolGuid; + +// +// Protocol definitions +// +#define NODE_NUM 1 +#define CH_NUM 2 +#define DIMM_NUM 2 +#define RANK_NUM 2 +#define SLOT_NUM (CH_NUM * DIMM_NUM) +#define PROFILE_NUM 4 // number of memory profiles supported +#define XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be= detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of p= resence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pa= ir and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank p= air. +#endif + +#pragma pack(1) +/// +/// Memory timing Structure +/// +typedef struct { + UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM'= s command rate mode. + UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM'= s CAS latency. + UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM'= s minimum CAS write latency time. + UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM= 's minimum four activate window delay time. + UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM= 's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM= 's minimum RAS# to CAS# delay time and Row Precharge delay time + UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM= 's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM= 's minimum refresh recovery delay time. + UINT16 tRPab; ///< Offset 20 Number of tCK cycles for the channel DIMM= 's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Offset 22 Number of tCK cycles for the channel DIMM= 's minimum row active to row active delay time. + UINT16 tRTP; ///< Offset 24 Number of tCK cycles for the channel DIMM= 's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Offset 26 Number of tCK cycles for the channel DIMM= 's minimum write recovery time. + UINT16 tWTR; ///< Offset 28 Number of tCK cycles for the channel DIMM= 's minimum internal write to read command delay time. + UINT16 tRRD_L; ///< Offset 30 Number of tCK cycles for the channel DIMM= 's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Offset 32 Number of tCK cycles for the channel DIMM= 's minimum row active to row active delay time for different bank groups. + UINT16 tWTR_L; ///< Offset 34 Number of tCK cycles for the channel DIMM= 's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Offset 36 Number of tCK cycles for the channel DIMM= 's minimum internal write to read command delay time for different bank gro= ups. + UINT8 Rsvd[2]; ///< Offset 38 +} MEMORY_TIMING; + +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the sa= me bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when swit= ching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when swit= ching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when swit= ching between DIMMs +} TURNAROUND_TIMING; + +// @todo use the MemInfoHob data instead of duplicate structure. +/// +/// Memory information Data Structure +/// +typedef struct { + MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timmi= ng information for the DIMM + UINT32 memSize; ///< Offset 128 Tot= al physical memory size + UINT16 ddrFreq; ///< Offset 132 DDR= Current Frequency + UINT16 ddrFreqMax; ///< Offset 134 DDR= Maximum Frequency + UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Siz= e of each DIMM + UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144 The= voltage setting for the DIMM + UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152 The= enumeration value from MrcDimmSts + UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156 No.= of ranks in a dimm + UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160 SPD= data of each DIMM + UINT8 RefClk; ///< Offset 192 Ref= erence Clock + UINT8 Ratio; ///< Offset 193 Clo= ck Multiplier + BOOLEAN EccSupport; ///< Offset 194 ECC= supported or not + UINT8 Profile; ///< Offset 195 Cur= rently running memory profile + UINT8 XmpProfileEnable; ///< Offset 196: 0 = =3D no XMP DIMMs in system + UINT8 DdrType; ///< Offset 197: Cu= rrent DDR type, see DDR_TYPE_xxx defines above + UINT8 Reserved[2]; ///< Offset 198 Res= erved bytes for future use + UINT32 DefaultXmptCK[XMP_PROFILE_NUM]; ///< Offset 200 The= Default XMP tCK values read from SPD. + TURNAROUND_TIMING tRd2Rd[CH_NUM]; ///< Read-to-Read = Turn Around Timings + TURNAROUND_TIMING tRd2Wr[CH_NUM]; ///< Read-to-Write = Turn Around Timings + TURNAROUND_TIMING tWr2Rd[CH_NUM]; ///< Write-to-Read = Turn Around Timings + TURNAROUND_TIMING tWr2Wr[CH_NUM]; ///< Write-to-Write= Turn Around Timings +} MEMORY_INFO_DATA; +#pragma pack() + +/// +/// Memory information Protocol definition +/// +typedef struct { + MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure +} MEM_INFO_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/SaPolicy.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Proto= col/SaPolicy.h new file mode 100644 index 0000000000..7b68f3072b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPol= icy.h @@ -0,0 +1,66 @@ +/** @file + Interface definition details between System Agent and platform drivers d= uring DXE phase. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_POLICY_H_ +#define _SA_POLICY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gSaPolicyProtocolGuid; +extern EFI_GUID gGraphicsDxeConfigGuid; +extern EFI_GUID gMiscDxeConfigGuid; +extern EFI_GUID gPcieDxeConfigGuid; +extern EFI_GUID gMemoryDxeConfigGuid; +extern EFI_GUID gVbiosDxeConfigGuid; + +/** + Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external + modules maybe have consumed this macro in their source code. Directly + update the SA_POLICY_PROTOCOL_REVISION version number may cause those + external modules to auto mark themselves wrong version info. + Always create new version macro for new Policy protocol interface. +**/ +#define SA_POLICY_PROTOCOL_REVISION 1 + +#define SA_PCIE_DEV_END_OF_TABLE 0xFFFF + +#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Snoop Latency +#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Non-Snoop Latency + + +/** + SA DXE Policy + + The SA_POLICY_PROTOCOL producer drvier is recommended to + set all the SA_POLICY_PROTOCOL size buffer zero before init any member pa= rameter, + this clear step can make sure no random value for those unknow new versio= n parameters. + + Make sure to update the Revision if any change to the protocol, including= the existing + internal structure definations.\n + Note: Here revision will be bumped up when adding/removing any config bl= ock under this structure.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31 +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +} SA_POLICY_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsGna.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsGna.h new file mode 100644 index 0000000000..6f3541e3e9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sGna.h @@ -0,0 +1,32 @@ +/** @file + Register names for GNA block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_GNA_H_ +#define _SA_REGS_GNA_H_ + +// +// Device 8 Equates +// +#define SA_GNA_BUS_NUM 0x00 +#define SA_GNA_DEV_NUM 0x08 +#define SA_GNA_FUN_NUM 0x00 +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsHostBridge.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/Register/SaRegsHostBridge.h new file mode 100644 index 0000000000..2cc0e5be68 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sHostBridge.h @@ -0,0 +1,214 @@ +/** @file + Register names for Host Bridge block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_HOST_BRIDGE_H_ +#define _SA_REGS_HOST_BRIDGE_H_ + +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +#define V_SA_MC_VID 0x8086 +#define R_SA_MC_DEVICE_ID 0x02 +#define R_SA_MC_CAPID0_B 0xE8 + +/// +/// Maximum number of SDRAM channels supported by the memory controller +/// +#define SA_MC_MAX_CHANNELS 2 + +/// +/// Maximum number of DIMM sockets supported by each channel +/// +#define SA_MC_MAX_SLOTS 2 + +/// +/// Maximum number of sides supported per DIMM +/// +#define SA_MC_MAX_SIDES 2 + +/// +/// Maximum number of DIMM sockets supported by the memory controller +/// +#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS) + +/// +/// Maximum memory supported by the memory controller +/// 4 GB in terms of KB +/// +#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024) + +/// +/// Define the maximum number of data bytes on a system with no ECC memory= support. +/// +#define SA_MC_MAX_BYTES_NO_ECC (8) + +/// +/// Define the maximum number of SPD data bytes on a DIMM. +/// +#define SA_MC_MAX_SPD_SIZE (512) +// +// Maximum DMI lanes and bundles supported (x8 and 4 lanes) +// +#define SA_DMI_MAX_LANE 0x04 +#define SA_DMI_MAX_BUNDLE 0x02 + +#define SA_DMI_CFL_MAX_LANE 0x04 +#define SA_DMI_CFL_MAX_BUNDLE 0x02 +// +// KabyLake CPU Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_MB_ULT_1 0x5904 ///< Kabylake Ult (OPI) (2+1F= /1.5F/2F/3/3E) Mobile SA DID +// +// KabyLake CPU Halo SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_HALO_2 0x5910 ///< Kabylake Halo (4+2/4E/3F= E) SA DID +// +// KabyLake CPU Desktop SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_DT_2 0x591F ///< Kabylake Desktop (4+1.5F= /2/4) SA DID +// +// KabyLake CPU Server SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_SVR_2 0x5918 ///< Kabylake Server (4+1/2/4= E) SA DID + +// +// CoffeeLake CPU Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_ULT_1 0x3ED0 ///< CoffeeLake Mobile (C= FL-U 4+3e) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_2 0x3ECC ///< CoffeeLake Mobile (C= FL-U 2+3e) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_3 0x3E34 ///< CoffeeLake Mobile (C= FL-U 4+(1 or 2)) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_4 0x3E35 ///< CoffeeLake Mobile (C= FL-U 2+(1 or 2)) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_6 0x3ECC ///< CoffeeLake Mobile (C= FL-U 2+3e) SA DID + +// +// CoffeeLake CPU Desktop SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_DT_1 0x3EC2 ///< CoffeeLake Desktop (= 6+2) SA DID +#define V_SA_DEVICE_ID_CFL_DT_2 0x3E1F ///< CoffeeLake Desktop (= 4+2) SA DID +#define V_SA_DEVICE_ID_CFL_DT_3 0x3E0F ///< CoffeeLake Desktop (= 2+2) SA DID +#define V_SA_DEVICE_ID_CFL_DT_4 0x3E30 ///< CoffeeLake Desktop (= 8+2) SA DID + +// +// CoffeeLake CPU Halo SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_HALO_1 0x3EC4 ///< CoffeeLake Halo (6+2= ) SA DID +#define V_SA_DEVICE_ID_CFL_HALO_2 0x3E10 ///< CoffeeLake Halo (4+2= ) SA DID +#define V_SA_DEVICE_ID_CFL_HALO_3 0x3E20 ///< CoffeeLake Halo (8+2= ) SA DID + +// +// CoffeeLake CPU WS SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_WS_1 0x3EC6 ///< CoffeeLake WorkStati= on (6+2) SA DID +#define V_SA_DEVICE_ID_CFL_WS_2 0x3E18 ///< CoffeeLake WrokStati= on (4+2) SA DID +#define V_SA_DEVICE_ID_CFL_WS_3 0x3E31 ///< CoffeeLake WrokStati= on (8+2) SA DID + +// +// CPU Server SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_SVR_1 0x3ECA ///< CoffeeLake Server (6= +0) SA DID +#define V_SA_DEVICE_ID_CFL_SVR_2 0x3E32 ///< CoffeeLake Server (8= +0) SA DID +#define V_SA_DEVICE_ID_CFL_SVR_3 0x3E33 ///< CoffeeLake Server (4= +0) SA DID +/** + Description: + - This is the base address for the Host Memory Mapped Configuration space= . There is no physical memory within this 32KB window that can be addresse= d. The 32KB reserved by this register does not alias to any PCI 2.3 compli= ant memory mapped space. On reset, the Host MMIO Memory Mapped Configuatio= n space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, = offset48h, bit 0]. + - All the bits in this register are locked in LT mode. + - The register space contains memory control, initialization, timing, and= buffer strength registers; clocking registers; and power and thermal manag= ement registers. +**/ +#define R_SA_MCHBAR (0x48) +/** + Description: + - All the bits in this register are LT lockable. +**/ +#define R_SA_GGC (0x50) +#define N_SA_GGC_GMS_OFFSET (0x8) +#define B_SA_GGC_GMS_MASK (0xff00) +#define N_SA_GGC_GGMS_OFFSET (0x6) +#define B_SA_GGC_GGMS_MASK (0xc0) +#define V_SA_GGC_GGMS_8MB 3 +/** + Description: + - Allows for enabling/disabling of PCI devices and functions that are wit= hin the CPU package. The table below the bit definitions describes the beha= vior of all combinations of transactions to devices controlled by this regi= ster. + All the bits in this register are LT Lockable. +**/ +#define R_SA_DEVEN (0x54) +#define B_SA_DEVEN_D2EN_MASK (0x10) +/** + Description: + This is the base address for the PCI Express configuration space. This = window of addresses contains the 4KB of configuration space for each PCI Ex= press device that can potentially be part of the PCI Express Hierarchy asso= ciated with the Uncore. There is no actual physical memory within this win= dow of up to 256MB that can be addressed. The actual size of this range is= determined by a field in this register. + Each PCI Express Hierarchy requires a PCI Express BASE register. The Un= core supports one PCI Express Hierarchy. The region reserved by this regis= ter does not alias to any PCI2.3 compliant memory mapped space. For exampl= e, the range reserved for MCHBAR is outside of PCIEXBAR space. + On reset, this register is disabled and must be enabled by writing a 1 t= o the enable field in this register. This base address shall be assigned o= n a boundary consistent with the number of buses (defined by the length fie= ld in this register), above TOLUD and still within 39-bit addressable memor= y space. + The PCI Express Base Address cannot be less than the maximum address wri= tten to the Top of physical memory register (TOLUD). Software must guarant= ee that these ranges do not overlap with known ranges located above TOLUD. + Software must ensure that the sum of the length of the enhanced configur= ation region + TOLUD + any other known ranges reserved above TOLUD is not g= reater than the 39-bit addessable limit of 512GB. In general, system imple= mentation and the number of PCI/PCI Express/PCI-X buses supported in the hi= erarchy will dictate the length of the region. + All the bits in this register are locked in LT mode. +**/ +#define R_SA_PCIEXBAR (0x60) + +/** + Description: + - This register controls the read, write and shadowing attributes of the = BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory = attributes on 13 legacy memory segments of various sizes in the 768KB to 1M= B address range. Seven Programmable Attribute Map (PAM) registers are used= to support these features. Cacheability of these areas is controlled via = the MTRR register in the core. + - Two bits are used to specify memory attributes for each memory segment.= These bits apply to host accesses to the PAM areas. These attributes are= : + - RE - Read Enable. When RE=3D1, the host read accesses to the correspon= ding memory segment are claimed by the Uncore and directed to main memory. = Conversely, when RE=3D0, the host read accesses are directed to DMI. + - WE - Write Enable. When WE=3D1, the host write accesses to the corresp= onding memory segment are claimed by the Uncore and directed to main memory= . Conversely, when WE=3D0, the host read accesses are directed to DMI. + - The RE and WE attributes permit a memory segment to be Read Only, Write= Only, Read/Write or Disabled. For example, if a memory segment has RE=3D1= and WE=3D0, the segment is Read Only. +**/ +#define R_SA_PAM0 (0x80) + +/// +/// Description: +/// The SMRAMC register controls how accesses to Compatible SMRAM spaces = are treated. The Open, Close and Lock bits function only when G_SMRAME bit= is set to 1. Also, the Open bit must be reset before the Lock bit is set. +/// +#define R_SA_SMRAMC (0x88) +#define B_SA_SMRAMC_D_LCK_MASK (0x10) +#define B_SA_SMRAMC_D_CLS_MASK (0x20) +#define B_SA_SMRAMC_D_OPEN_MASK (0x40) +/// +/// Description: +/// This register contains the Top of low memory address. +/// +#define R_SA_TOLUD (0xbc) +#define R_SA_MC_CAPID0_A_OFFSET 0xE4 +// +// MCHBAR IO Register Offset Equates +// +#define R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET 0x5DA8 + +#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel reco= mmended maximum value for Snoop Latency (70us) +#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel reco= mmended maximum value for Non-Snoop Latency (70us) +/// +/// Vt-d Engine base address. +/// +#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT1 for = IGD +#define R_SA_MCHBAR_VTD3_OFFSET 0x5410 ///< HW UNIT3 for all other -= PEG, USB, SATA etc +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsIgd.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsIgd.h new file mode 100644 index 0000000000..f8b794a9fb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sIgd.h @@ -0,0 +1,50 @@ +/** @file + Register names for IGD block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_IGD_H_ +#define _SA_REGS_IGD_H_ + +/// +/// Device 2 Register Equates +/// +// +// The following equates must be reviewed and revised when the specificati= on is ready. +// +#define SA_IGD_BUS 0x00 +#define SA_IGD_DEV 0x02 +#define SA_IGD_FUN_0 0x00 +#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3) +#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN + +#define V_SA_IGD_VID 0x8086 +#define SA_GT_APERTURE_SIZE_256MB 1 ///< 256MB is the recommanded = GT Aperture Size as per BWG. + +#define V_SA_PCI_DEV_2_GT2_CFL_ULT_1_ID 0x3EA0 ///< Dev2 CFL-U GT2 +#define V_SA_PCI_DEV_2_GT1_CFL_ULT_1_ID 0x3EA1 ///< Dev2 CFL-U GT1 +#define R_SA_IGD_VID 0x00 +#define R_SA_IGD_DID 0x02 +#define R_SA_IGD_CMD 0x04 + +#define R_SA_IGD_SWSCI_OFFSET 0x00E8 +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsIpu.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsIpu.h new file mode 100644 index 0000000000..b26c79ec95 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sIpu.h @@ -0,0 +1,37 @@ +/** @file + Register names for IPU block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_IPU_H_ +#define _SA_REGS_IPU_H_ + +// +// Device 5 Equates +// +#define SA_IPU_BUS_NUM 0x00 +#define SA_IPU_DEV_NUM 0x05 +#define SA_IPU_FUN_NUM 0x00 + +// +// GPIO native features pins data +// +#define SA_GPIO_IMGUCLK_NUMBER_OF_PINS 2 +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsPeg.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsPeg.h new file mode 100644 index 0000000000..b7e9416fc6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sPeg.h @@ -0,0 +1,64 @@ +/** @file + Register names for PEG block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_PEG_H_ +#define _SA_REGS_PEG_H_ +// +// Device 1 Memory Mapped IO Register Offset Equates +// +#define SA_PEG_BUS_NUM 0x00 +#define SA_PEG_DEV_NUM 0x01 +#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM +#define SA_PEG0_FUN_NUM 0x00 +#define SA_PEG1_DEV_NUM SA_PEG_DEV_NUM +#define SA_PEG1_FUN_NUM 0x01 +#define SA_PEG2_DEV_NUM SA_PEG_DEV_NUM +#define SA_PEG2_FUN_NUM 0x02 +// +// Temporary Device & Function Number used for Switchable Graphics DGPU +// +#define SA_TEMP_DGPU_DEV 0x00 +#define SA_TEMP_DGPU_FUN 0x00 + +// +// SA PCI Express* Port configuration +// +#define SA_PEG_MAX_FUN 0x03 +#define SA_PEG_MAX_LANE 0x10 +#define SA_PEG_MAX_BUNDLE 0x08 + +// +// Silicon and SKU- specific MAX defines +// +#define SA_PEG_CNL_H_MAX_FUN SA_PEG_MAX_FUN // CNL-H- SKU s= upports 4 controllers with 20 PEG lanes and 10 bundles +#define SA_PEG_CNL_H_MAX_LANE SA_PEG_MAX_LANE +#define SA_PEG_CNL_H_MAX_BUNDLE SA_PEG_MAX_BUNDLE +#define SA_PEG_NON_CNL_H_MAX_FUN 0x03 // All non-CNL-= H- SKU supports 3 controllers with 16 PEG lanes and 8 bundles +#define SA_PEG_NON_CNL_H_MAX_LANE 0x10 +#define SA_PEG_NON_CNL_H_MAX_BUNDLE 0x08 + + + +#define R_SA_PEG_VID_OFFSET 0x00 ///< Vendor ID +#define R_SA_PEG_DID_OFFSET 0x02 ///< Device ID +#define R_SA_PEG_SS_OFFSET 0x8C ///< Subsystem ID +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAcces= s.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h new file mode 100644 index 0000000000..b98f1732ba --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h @@ -0,0 +1,106 @@ +/** @file + Macros to simplify and abstract the interface to PCI configuration. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SAACCESS_H_ +#define _SAACCESS_H_ + +#include "SaRegs.h" +#include "SaCommonDefinitions.h" + +/// +/// SystemAgent Base Address definition +/// +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_MILLI_SECOND +#define STALL_ONE_MILLI_SECOND 1000 +#endif + +// +// SA Segement Number +// +#define SA_SEG_NUM 0x00 + +#define V_SA_DEVICE_ID_INVALID 0xFFFF + + +/// +/// The value before AutoConfig match the setting of PCI Express Base Spec= ification 1.1, please be careful for adding new feature +/// +typedef enum { + PcieAspmDisabled, + PcieAspmL0s, + PcieAspmL1, + PcieAspmL0sL1, + PcieAspmAutoConfig, + PcieAspmMax +} SA_PCIE_ASPM_CONFIG; + +/// +/// SgMode settings +/// +typedef enum { + SgModeDisabled =3D 0, + SgModeReserved, + SgModeMuxless, + SgModeDgpu, + SgModeMax +} SG_MODE; + +// +// Macros that judge which type a device ID belongs to +// +#define IS_SA_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_MB_ULT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_3) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_4) \ + ) + +/// +/// Device IDs that are Desktop specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_DT_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_3) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_4) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_WS_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_WS_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_WS_3) \ + ) + +/// +/// Device IDS that are Server specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_SVR_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_SVR_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_SVR_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_SVR_3) \ + ) + +/// +/// Device IDs that are Halo specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_HALO(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_HALO_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_3) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_IOT_1) \ + ) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommo= nDefinitions.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaC= ommonDefinitions.h new file mode 100644 index 0000000000..ab9224e573 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefini= tions.h @@ -0,0 +1,23 @@ +/** @file + This header file provides common definitions just for System Agent using= to avoid including extra module's file. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_COMMON_DEFINITIONS_H_ +#define _SA_COMMON_DEFINITIONS_H_ + +#define ERROR_BY_16 (0xEE15) +#define ERROR_NOT_BY_16 (0xED15) + +#define MAX_PCIE_ASPM_OVERRIDE 500 +#define MAX_PCIE_LTR_OVERRIDE 500 + +#define DISABLED 0 +#define ENABLED 1 + +#define SA_VTD_ENGINE_NUMBER 3 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciEx= pressLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciEx= pressLib.h new file mode 100644 index 0000000000..87aa105df2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLi= b.h @@ -0,0 +1,25 @@ +/** @file + Header file for the PCI Express library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PCI_EXPRESS_LIB_H_ +#define _SA_PCI_EXPRESS_LIB_H_ + + +/** + Gets the base address of PCI Express. + + This internal functions retrieves PCI Express Base Address. + + @return The base address of PCI Express. +**/ +VOID* +GetPciExpressBaseAddress ( + VOID +); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolic= yCommon.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicy= Common.h new file mode 100644 index 0000000000..086c60bfed --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon= .h @@ -0,0 +1,51 @@ +/** @file + Main System Agent Policy structure definition which will contain several= config blocks during runtime. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_POLICY_COMMON_H_ +#define _SA_POLICY_COMMON_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gSiPolicyPpiGuid; +extern EFI_GUID gSaMiscPeiConfigGuid; +extern EFI_GUID gGraphicsPeiConfigGuid; +extern EFI_GUID gSaPciePeiConfigGuid; +extern EFI_GUID gGnaConfigGuid; +extern EFI_GUID gVtdConfigGuid; +extern EFI_GUID gSaOverclockingPreMemConfigGuid; +extern EFI_GUID gSiPreMemPolicyPpiGuid; +extern EFI_GUID gSaMiscPeiPreMemConfigGuid; +extern EFI_GUID gSaPciePeiPreMemConfigGuid; +extern EFI_GUID gGraphicsPeiPreMemConfigGuid; +extern EFI_GUID gIpuPreMemConfigGuid; +extern EFI_GUID gSwitchableGraphicsConfigGuid; +extern EFI_GUID gCpuTraceHubConfigGuid; +extern EFI_GUID gMemoryConfigGuid; +extern EFI_GUID gMemoryConfigNoCrcGuid; + +#endif // _SA_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.= h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h new file mode 100644 index 0000000000..593b907d2a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h @@ -0,0 +1,32 @@ +/** @file + Register names for System Agent (SA) registers + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_H_ +#define _SA_REGS_H_ + +#include +#include +#include +#include +#include + +#endif --=20 2.16.2.windows.1