From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Fri, 16 Aug 2019 17:52:37 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:52:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="261263861" Received: from orsmsx102.amr.corp.intel.com ([10.22.225.129]) by orsmga001.jf.intel.com with ESMTP; 16 Aug 2019 17:52:24 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.96]) by ORSMSX102.amr.corp.intel.com ([169.254.3.11]) with mapi id 14.03.0439.000; Fri, 16 Aug 2019 17:52:24 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add library instances Thread-Topic: [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add library instances Thread-Index: AQHVVJEVY8cVc1zBzkCvhf27tsguzKb+gujQ Date: Sat, 17 Aug 2019 00:52:23 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE12973@ORSMSX114.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-16-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-16-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTYxZjFiNzAtNDhjZC00MTAxLWE4NzItMWRkMDBkMTE4NmEzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoidlhxWTg4RG1oTXVYVFhwVlMwMHBxV0RiUlNRMVlIdk9qSmNQWXJxRWFkSFM0TFpOazhtendpSmhPbHp2cFcraiJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:16 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Gao, Liming ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add lib= rary instances REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds CPU library class instances. * BaseCpuMailboxLibNull - Generic CPU mailbox interaction services. * PeiCpuPolicyLib - CPU policy configuration services. * PeiCpuPolicyLibPreMem - CPU policy pre-memory configuration services. * PeiDxeSmmCpuPlatformLib - CPU platform services. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseC= puMailboxLibNull.inf | 22 + Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLib.inf | 65 +++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLibPreMem.inf | 43 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/Pei= DxeSmmCpuPlatformLib.inf | 39 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLibrary.h | 30 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/Cpu= PlatformLibrary.h | 28 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseC= puMailboxLibNull.c | 90 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPol= icy.c | 293 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPol= icyPreMem.c | 108 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLib.c | 434 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLibPreMem.c | 160 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/Cpu= PlatformLibrary.c | 415 +++++++++++++++++++ 12 files changed, 1727 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxL= ibNull/BaseCpuMailboxLibNull.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/L= ibrary/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf new file mode 100644 index 0000000000..4fcfca4670 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/= BaseCpuMailboxLibNull.inf @@ -0,0 +1,22 @@ +## @file +# Component description file for Cpu Mailbox Null Lib +# +# Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseCpuMailboxLibNull +FILE_GUID =3D 74F470BC-1769-4732-B9C0-EE9AB0B12411 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D CpuMailboxLib + +[Packages] +MdePkg/MdePkg.dec + +[Sources] +BaseCpuMailboxLibNull.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCp= uPolicyLib/PeiCpuPolicyLib.inf new file mode 100644 index 0000000000..c986e35360 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLib.inf @@ -0,0 +1,65 @@ +## @file +# Component description file for the PeiCpuPolicyLib library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiCpuPolicyLib +FILE_GUID =3D 5baafc8f-25c6-4d19-b141-585757509372 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D CpuPolicyLib + + +[LibraryClasses] +DebugLib +IoLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +CpuPlatformLib +PciSegmentLib +SaPlatformLib +SiConfigBlockLib +PostCodeLib +PcdLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +PeiCpuPolicyLib.c +PeiCpuPolicyLibrary.h +CpuPrintPolicy.c +PeiCpuPolicyLibPreMem.c +CpuPrintPolicyPreMem.c + +[Ppis] +gSiPolicyPpiGuid ## CONSUMES +gSiPreMemPolicyPpiGuid ## CONSUMES + +[FixedPcd] +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + +[Pcd] +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## Produces + +[Guids] +gCpuConfigGuid ## PRODUCES +gCpuSgxConfigGuid ## PRODUCES +gCpuPowerMgmtBasicConfigGuid ## PRODUCES +gCpuPowerMgmtCustomConfigGuid ## PRODUCES +gCpuTestConfigGuid ## PRODUCES +gCpuPidTestConfigGuid ## PRODUCES +gCpuPowerMgmtTestConfigGuid ## PRODUCES +gCpuConfigLibPreMemConfigGuid ## PRODUCES +gCpuSecurityPreMemConfigGuid ## PRODUCES +gCpuOverclockingPreMemConfigGuid ## CONSUMES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLibPreMem.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library= /PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.inf new file mode 100644 index 0000000000..52dc989f74 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLibPreMem.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for the PeiCpuPolicyLibPreMem library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiCpuPolicyLibPreMem +FILE_GUID =3D 5F4C2CF1-9DFE-4D99-9318-98FD31C8517D +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D CpuPolicyLibPreMem + +[LibraryClasses] +DebugLib +IoLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +CpuPlatformLib +SiConfigBlockLib +PostCodeLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +PeiCpuPolicyLib.c +PeiCpuPolicyLibrary.h +CpuPrintPolicy.c + +[Ppis] +gSiPreMemPolicyPpiGuid ## CONSUMES + +[Guids] +gCpuSecurityPreMemConfigGuid ## PRODUCES +gCpuOverclockingPreMemConfigGuid ## PRODUCES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPla= tformLib/PeiDxeSmmCpuPlatformLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/C= pu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf new file mode 100644 index 0000000000..0a56e42817 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/PeiDxeSmmCpuPlatformLib.inf @@ -0,0 +1,39 @@ +## @file +# Component description file for CPU Platform Lib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmCpuPlatformLib +FILE_GUID =3D 11647130-6AA4-41A4-A3A8-5FA296ABD977 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D CpuPlatformLib + +[LibraryClasses] +BaseLib +BaseMemoryLib +DebugLib +IoLib +PcdLib +CpuLib +TimerLib +SynchronizationLib +PciSegmentLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +[Sources] +CpuPlatformLibrary.h +CpuPlatformLibrary.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/Pei= CpuPolicyLib/PeiCpuPolicyLibrary.h new file mode 100644 index 0000000000..6e993053fc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLibrary.h @@ -0,0 +1,30 @@ +/** @file + Header file for the PeiCpuPolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CPU_POLICY_LIBRARY_H_ +#define _PEI_CPU_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_MICROCODE_PATCH_SIZE 0x20000 + +#endif // _PEI_CPU_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPla= tformLib/CpuPlatformLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Libr= ary/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h new file mode 100644 index 0000000000..0b780acd22 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/CpuPlatformLibrary.h @@ -0,0 +1,28 @@ +/** @file + Header file for Cpu Platform Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_ +#define _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxL= ibNull/BaseCpuMailboxLibNull.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Lib= rary/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.c new file mode 100644 index 0000000000..2af11ce8d0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/= BaseCpuMailboxLibNull.c @@ -0,0 +1,90 @@ +/** @file + Mailbox Library. + + Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + Generic Mailbox function for mailbox write commands. This function will + poll the mailbox interface for control, issue the write request, poll + for completion, and verify the write was successful. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[in] MailboxData Overclocking mailbox interface data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status values are: + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_SUCCESS Command succeeded. + @retval EFI_INVALID_PARAMETER Invalid read data detected from pcode. + @retval EFI_UNSUPPORTED Unsupported MailboxType parameter. +**/ +EFI_STATUS +EFIAPI +MailboxWrite ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + IN UINT32 MailboxData, + OUT UINT32 *MailboxStatus + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Generic Mailbox function for mailbox read commands. This function will w= rite + the read request from MailboxType, and populate the read results in the = MailboxDataPtr. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[out] *MailboxDataPtr Pointer to the overclocking mailbox interfac= e data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status are + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_SUCCESS Command succeeded. + @retval EFI_INVALID_PARAMETER Invalid read data detected from pcode. + @retval EFI_UNSUPPORTED Unsupported MailboxType parameter. +**/ +EFI_STATUS +EFIAPI +MailboxRead ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + OUT UINT32 *MailboxDataPtr, + OUT UINT32 *MailboxStatus + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Poll the run/busy bit of the mailbox until available or timeout expires. + + @param[in] MailboxType + + @retval EFI_SUCCESS Command succeeded. + @retval EFI_TIMEOUT Command timeout. +**/ +EFI_STATUS +EFIAPI +PollMailboxReady ( + IN UINT32 MailboxType + ) +{ + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /CpuPrintPolicy.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPo= licyLib/CpuPrintPolicy.c new file mode 100644 index 0000000000..38cf383e8d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPri= ntPolicy.c @@ -0,0 +1,293 @@ +/** @file + This file is PeiCpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include +#include + +/** + Print CPU_CONFIG and serial out. + + @param[in] CpuConfig Pointer to a CPU_CONFIG +**/ +VOID +CpuConfigPrint ( + IN CONST CPU_CONFIG *CpuConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ CPU Config ------------------\n"= )); + DEBUG ((DEBUG_INFO, " CPU_CONFIG : AesEnable : 0x%x\n", CpuConfig->AesEn= able)); + DEBUG ((DEBUG_INFO, " CPU_CONFIG : MicrocodePatchAddress : 0x%x\n", CpuC= onfig->MicrocodePatchAddress)); + DEBUG ((DEBUG_INFO, " CPU_CONFIG : DebugInterfaceEnable : 0x%X\n", CpuCo= nfig->DebugInterfaceEnable)); +} + +/** + Print CPU_POWER_MGMT_BASIC_CONFIG and serial out. + + @param[in] CpuPowerMgmtBasicConfig Pointer to a CPU_POWER_MGMT_BASIC_C= ONFIG +**/ +VOID +CpuPowerMgmtBasicConfigPrint ( + IN CONST CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Basic Config ----= --------------\n")); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG : OneCoreRatioLimit : = 0x%X , TwoCoreRatioLimit =3D 0x%X , ThreeCoreRatioLimit =3D 0x%X , FourCore= RatioLimit =3D 0x%X, FiveCoreRatioLimit =3D 0x%X, SixCoreRatioLimit =3D 0x%= X, SevenCoreRatioLimit =3D 0x%X, EightCoreRatioLimit =3D 0x%X \n", CpuPowe= rMgmtBasicConfig->OneCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->TwoCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->FourCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->FiveCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->SixCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->SevenCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->EightCoreRatioLimit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: Hwp : 0x%x\n", CpuPow= erMgmtBasicConfig->Hwp)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: SkipSetBootPState : 0= x%x\n", CpuPowerMgmtBasicConfig->SkipSetBootPState)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: HdcControl : 0x%X\n",= CpuPowerMgmtBasicConfig->HdcControl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: (Intel Turbo Boost Ma= x Technology 3.0)EnableItbm : 0x%X\n", CpuPowerMgmtBasicConfig->EnableItbm)= ); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: EnableItbmDriver : 0x= %X\n", CpuPowerMgmtBasicConfig->EnableItbmDriver)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit2 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit2)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TurboPowerLimitLock := 0x%x\n", CpuPowerMgmtBasicConfig->TurboPowerLimitLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3DutyCycle = : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3Lock : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit3Lock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit4Lock : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit4Lock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetClamp : 0x%X= \n", CpuPowerMgmtBasicConfig->TccOffsetClamp)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetLock : 0x%X\= n", CpuPowerMgmtBasicConfig->TccOffsetLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TurboMode : 0x%x\n", = CpuPowerMgmtBasicConfig->TurboMode)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccActivationOffset := 0x%X\n", CpuPowerMgmtBasicConfig->TccActivationOffset)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit1 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit1)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit2Power : 0x= %x\n", CpuPowerMgmtBasicConfig->PowerLimit2Power)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit3)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit4 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit4)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit1Time : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit1Time)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3Time : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit3Time)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetTimeWindowFo= rRatl : 0x%X\n", CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: HwpInterruptControl := 0x%x\n", CpuPowerMgmtBasicConfig->HwpInterruptControl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: MinRingRatioLimit : 0= x%x\n", CpuPowerMgmtBasicConfig->MinRingRatioLimit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: MaxRingRatioLimit : 0= x%x\n", CpuPowerMgmtBasicConfig->MaxRingRatioLimit)); +} + +/** + Print CPU_POWER_MGMT_CUSTOM_CONFIG and serial out. + + @param[in] CpuPowerMgmtCustomConfig Pointer to a CPU_POWER_MGMT_CUSTOM= _CONFIG +**/ +VOID +CpuPowerMgmtCustomConfigPrint ( + IN CONST CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig + ) +{ + UINT32 Index =3D 0; + DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Custom Config ---= ---------------\n")); + DEBUG ((DEBUG_INFO, "\n CustomRatioTable... \n")); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidNumber : 0x%x\n",= CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidCpuid : 0x%x\n", = CpuPowerMgmtCustomConfig->CustomRatioTable.Cpuid)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidMaxRatio : 0x%x\n= ", CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio)); + for (Index =3D 0; Index < MAX_CUSTOM_RATIO_TABLE_ENTRIES; Index++) { + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: StateRatio[%d] : 0= x%x\n", Index, CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index]= )); + } + for (Index =3D 0; Index < MAX_16_CUSTOM_RATIO_TABLE_ENTRIES; Index++) { + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: StateRatioMax16[%d= ] : 0x%x\n", Index, CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatioMa= x16[Index])); + } + for (Index =3D 0; Index < MAX_CUSTOM_CTDP_ENTRIES; Index++) { + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omPowerLimit1 : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomPowerLimit1) + ); + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omPowerLimit2 : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomPowerLimit2) + ); + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omPowerLimit1Time : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomPowerLimit1Time) + ); + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omTurboActivationRatio : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomTurboActivationRatio) + ); + } + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: ConfigTdpLock : 0x%x= \n", CpuPowerMgmtCustomConfig->ConfigTdpLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: ConfigTdpBios : 0x%x= \n", CpuPowerMgmtCustomConfig->ConfigTdpBios)); +} + +/** + Print CPU_TEST_CONFIG and serial out. + + @param[in] CpuTestConfig Pointer to a CPU_TEST_CONFIG +**/ +VOID +CpuTestConfigPrint ( + IN CONST CPU_TEST_CONFIG *CpuTestConfig + ) +{ + UINT8 PcdCpuApLoopMode; + + PcdCpuApLoopMode =3D PcdGet8 (PcdCpuApLoopMode); + + DEBUG ((DEBUG_INFO, "------------------ CPU Test Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MlcStreamerPrefetcher : 0x%X\n", = CpuTestConfig->MlcStreamerPrefetcher)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MlcSpatialPrefetcher : 0x%X\n", C= puTestConfig->MlcSpatialPrefetcher)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MonitorMwaitEnable : 0x%X\n", Cpu= TestConfig->MonitorMwaitEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MachineCheckEnable : 0x%X\n", Cpu= TestConfig->MachineCheckEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: DebugInterfaceLockEnable : 0x%X\n= ", CpuTestConfig->DebugInterfaceLockEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceOutputScheme : 0x%X= \n", CpuTestConfig->ProcessorTraceOutputScheme)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceEnable : 0x%X\n", C= puTestConfig->ProcessorTraceEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceMemBase : 0x%llX\n"= , CpuTestConfig->ProcessorTraceMemBase)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceMemLength : 0x%X\n"= , CpuTestConfig->ProcessorTraceMemLength)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ThreeStrikeCounterDisable : 0x%X\= n", CpuTestConfig->ThreeStrikeCounterDisable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: VoltageOptimization : 0x%X\n", Cp= uTestConfig->VoltageOptimization)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: CpuWakeUpTimer : 0x%X\n", CpuTest= Config->CpuWakeUpTimer)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: PcdCpuApLoopMode: 0x%X\n", PcdCpu= ApLoopMode)); +} + +/** + Print CPU_PID_TEST_CONFIG and serial out. + + @param[in] CpuPidTestConfig Pointer to a CPU_PID_TEST_CONFIG +**/ +VOID +CpuPidTestConfigPrint ( + IN CONST CPU_PID_TEST_CONFIG *CpuPidTestConfig + ) +{ + UINT32 Index =3D 0; + DEBUG ((DEBUG_INFO, "------------------ CPU PID Test Config ------------= ------\n")); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PidTuning : 0x%X\n", Index, = CpuPidTestConfig->PidTuning)); + if ( CpuPidTestConfig->PidTuning =3D=3D 1) { + for (Index =3D PID_DOMAIN_KP; Index <=3D PID_DOMAIN_KD; Index++) { + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : Ratl[%X] : 0x%X\n", In= dex, CpuPidTestConfig->Ratl[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr0[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr0[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr1[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr1[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr2[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr2[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr3[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr3[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl1Msr[%X] : 0x= %X\n", Index, CpuPidTestConfig->PbmPsysPl1Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl1MmioPcs[%X] = : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl1MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl2Msr[%X] : 0x= %X\n", Index, CpuPidTestConfig->PbmPsysPl2Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl2MmioPcs[%X] = : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl2MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl1Msr[%X] : 0x%= X\n", Index, CpuPidTestConfig->PbmPkgPl1Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl1MmioPcs[%X] := 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl1MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl2Msr[%X] : 0x%= X\n", Index, CpuPidTestConfig->PbmPkgPl2Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl2MmioPcs[%X] := 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl2MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl1Msr[%X] : 0x%X\n= ", Index, CpuPidTestConfig->DdrPl1Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl1MmioPcs[%X] : 0x= %X\n", Index, CpuPidTestConfig->DdrPl1MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl2Msr[%X] : 0x%X\n= ", Index, CpuPidTestConfig->DdrPl2Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl2MmioPcs[%X] : 0x= %X\n", Index, CpuPidTestConfig->DdrPl2MmioPcs[Index])); + } + } +} + +/** + Print CPU_POWER_MGMT_TEST_CONFIG and serial out. + + @param[in] CpuPowerMgmtTestConfig Pointer to a CPU_POWER_MGMT_TEST_CON= FIG +**/ +VOID +CpuPowerMgmtTestConfigPrint ( + IN CONST CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig + ) +{ + CPU_GENERATION CpuGeneration; + CpuGeneration =3D GetCpuGeneration(); + DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Test Config -----= -------------\n")); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: Eist : 0x%x\n", CpuPow= erMgmtTestConfig->Eist)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: EnergyEfficientPState = : 0x%x\n", CpuPowerMgmtTestConfig->EnergyEfficientPState)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: EnergyEfficientTurbo := 0x%x\n", CpuPowerMgmtTestConfig->EnergyEfficientTurbo)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: TStates : 0x%x\n", Cpu= PowerMgmtTestConfig->TStates)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: BiProcHot : 0x%x\n", C= puPowerMgmtTestConfig->BiProcHot)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: DisableProcHotOut : 0x= %x\n", CpuPowerMgmtTestConfig->DisableProcHotOut)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ProcHotResponse : 0x%x= \n", CpuPowerMgmtTestConfig->ProcHotResponse)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: DisableVrThermalAlert = : 0x%x\n", CpuPowerMgmtTestConfig->DisableVrThermalAlert)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: AutoThermalReporting := 0x%x\n", CpuPowerMgmtTestConfig->AutoThermalReporting)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ThermalMonitor : 0x%x\= n", CpuPowerMgmtTestConfig->ThermalMonitor)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: Cx : 0x%x\n", CpuPower= MgmtTestConfig->Cx)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PmgCstCfgCtrlLock : 0x= %x\n", CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1e : 0x%x\n", CpuPowe= rMgmtTestConfig->C1e)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1Autodemotion : 0x%x\= n", CpuPowerMgmtTestConfig->C1AutoDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1Undemotion : 0x%x\n"= , CpuPowerMgmtTestConfig->C1UnDemotion)); + if(CpuGeneration =3D=3D EnumCflCpu){ + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C3AutoDemotion : 0x%= x\n", CpuPowerMgmtTestConfig->C3AutoDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C3UnDemotion : 0x%x\= n", CpuPowerMgmtTestConfig->C3UnDemotion)); + } + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCState Demotion : 0= x%x\n", CpuPowerMgmtTestConfig->PkgCStateDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCstateUndemotion : = 0x%x\n", CpuPowerMgmtTestConfig->PkgCStateUnDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CStatePreWake : 0x%x\n= ", CpuPowerMgmtTestConfig->CStatePreWake)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: TimedMwait : 0x%x\n", = CpuPowerMgmtTestConfig->TimedMwait)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstCfgCtrIoMwaitRedire= ction : 0x%x\n", CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ProcHotLock : 0x%x\n",= CpuPowerMgmtTestConfig->ProcHotLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ConfigTdpLevel : 0x%x\= n", CpuPowerMgmtTestConfig->ConfigTdpLevel)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: RaceToHalt : 0x%x\n",= CpuPowerMgmtTestConfig->RaceToHalt)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl0I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl0T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl1I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl2I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl3I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl4I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl5I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCStateLimit : 0x%x\= n", CpuPowerMgmtTestConfig->PkgCStateLimit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl1T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl2T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl3T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl4T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl5T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CustomPowerUnit : 0x%x= \n", CpuPowerMgmtTestConfig->CustomPowerUnit)); + DEBUG ((DEBUG_INFO, " PpmIrmSetting : 0x%x\n", CpuPowerMgmtTestConfig->P= pmIrmSetting)); +} +/** + Print whole CPU config blocks of SI_POLICY_PPI and serial out in PostMem= . + + @param[in] SiPolicyPpi The SI Policy PPI instance +**/ +VOID +CpuPrintPolicy ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + EFI_STATUS Status; + CPU_CONFIG *CpuConfig; + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CPU_TEST_CONFIG *CpuTestConfig; + CPU_PID_TEST_CONFIG *CpuPidTestConfig; + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf= igGuid, (VOID *) &CpuPowerMgmtBasicConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomCon= figGuid, (VOID *) &CpuPowerMgmtCustomConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (V= OID *) &CpuTestConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPidTestConfigGuid,= (VOID *) &CpuPidTestConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfi= gGuid, (VOID *) &CpuPowerMgmtTestConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "\n ------------------------ SiCpuPolicy Print Begin= in PostMem----------------- \n")); + DEBUG ((DEBUG_INFO, " Revision=3D %x\n", SiPolicyPpi->TableHeader.Header= .Revision)); + + CpuConfigPrint(CpuConfig); + CpuPowerMgmtBasicConfigPrint(CpuPowerMgmtBasicConfig); + CpuPowerMgmtCustomConfigPrint(CpuPowerMgmtCustomConfig); + CpuTestConfigPrint(CpuTestConfig); + CpuPidTestConfigPrint(CpuPidTestConfig); + CpuPowerMgmtTestConfigPrint(CpuPowerMgmtTestConfig); + DEBUG ((DEBUG_INFO, "\n ------------------------ SiCpuPolicy Print End i= n PostMem ----------------- \n\n")); +DEBUG_CODE_END(); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /CpuPrintPolicyPreMem.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/Pe= iCpuPolicyLib/CpuPrintPolicyPreMem.c new file mode 100644 index 0000000000..0bcb34c99c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPri= ntPolicyPreMem.c @@ -0,0 +1,108 @@ +/** @file + This file is PeiCpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include + +/** + Print CPU_CONFIG_LIB_PREMEM_CONFIG and serial out. + + @param[in] CpuConfigLibPreMemConfig Pointer to a CPU_CONFIG_LIB_PREM= EM_CONFIG + +**/ +VOID +CpuConfigLibPreMemConfigPrint ( + IN CONST CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig + ) +{ + CPU_GENERATION CpuGeneration; + CpuGeneration =3D GetCpuGeneration(); + DEBUG ((DEBUG_INFO, "------------------ CPU Config Lib PreMem Config ---= ---------------\n")); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : HyperThreading =3D 0= x%x\n", CpuConfigLibPreMemConfig->HyperThreading)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : BootFrequency =3D 0x= %x\n", CpuConfigLibPreMemConfig->BootFrequency)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : ActiveCoreCount =3D = 0x%x\n", CpuConfigLibPreMemConfig->ActiveCoreCount)); + if(CpuGeneration =3D=3D EnumCflCpu){ + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : FClkFrequency =3D = 0x%x\n", CpuConfigLibPreMemConfig->FClkFrequency)); + } + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : JtagC10PowerGateDisa= ble =3D 0x%x\n", CpuConfigLibPreMemConfig->JtagC10PowerGateDisable)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : BistOnReset =3D 0x%x= \n", CpuConfigLibPreMemConfig->BistOnReset)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : VmxEnable =3D 0x%x\n= ", CpuConfigLibPreMemConfig->VmxEnable)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : CpuRatio =3D 0x%x\n"= , CpuConfigLibPreMemConfig->CpuRatio)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : PeciSxReset =3D 0x%x= \n", CpuConfigLibPreMemConfig->PeciSxReset)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : PeciC10Reset =3D 0x%= x\n", CpuConfigLibPreMemConfig->PeciC10Reset)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : SkipMpInit =3D 0x%x\= n", CpuConfigLibPreMemConfig->SkipMpInit)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : DpSscMarginEnable = =3D 0x%x\n", CpuConfigLibPreMemConfig->DpSscMarginEnable)); +} + +/** + Print CPU_OVERCLOCKING_PREMEM_CONFIG and serial out. + + @param[in] CpuOverClockingConfig Pointer to a CPU_OVERCLOCKING_CONFIG +**/ +VOID +CpuOverClockingPreMemConfigPrint ( + IN CONST CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ CPU OverClocking Config --------= ----------\n")); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: OcSupport : 0x%X\= n", CpuOverClockingPreMemConfig->OcSupport)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: OcLock : 0x%X\n",= CpuOverClockingPreMemConfig->OcLock)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageMode := 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageMode)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreMaxOcRatio := 0x%X\n", CpuOverClockingPreMemConfig->CoreMaxOcRatio)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageOverri= de : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageOverride)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageAdapti= ve : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageAdaptive)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageOffset= : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageMode := 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageMode)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageOverri= de : 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageOverride)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageAdapti= ve : 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageAdaptive)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageOffset= : 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingMaxOcRatio := 0x%X\n", CpuOverClockingPreMemConfig->RingMaxOcRatio)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingDownBin := 0x%X\n", CpuOverClockingPreMemConfig->RingDownBin)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: Avx2RatioOffset := 0x%X\n", CpuOverClockingPreMemConfig->Avx2RatioOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: Avx3RatioOffset := 0x%X\n", CpuOverClockingPreMemConfig->Avx3RatioOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: BclkAdaptiveVolta= ge : 0x%X\n", CpuOverClockingPreMemConfig->BclkAdaptiveVoltage)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CorePllVoltageOff= set : 0x%X\n", CpuOverClockingPreMemConfig->CorePllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: GtPllVoltageOffse= t : 0x%X\n", CpuOverClockingPreMemConfig->GtPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingPllVoltageOff= set : 0x%X\n", CpuOverClockingPreMemConfig->RingPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: SaPllVoltageOffse= t : 0x%X\n", CpuOverClockingPreMemConfig->SaPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: McPllVoltageOffse= t : 0x%X\n", CpuOverClockingPreMemConfig->McPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: TjMaxOffset = : 0x%X\n", CpuOverClockingPreMemConfig->TjMaxOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: TvbRatioClipping = : 0x%X\n", CpuOverClockingPreMemConfig->TvbRatioClipping)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: TvbVoltageOptimiz= ation : 0x%X\n", CpuOverClockingPreMemConfig->TvbVoltageOptimization)); +} + + +/** + Print whole CPU Config blocks of SI_PREMEM_POLICY_PPI and serial out in = PreMem. + + @param[in] SiPreMemPolicyPpi The SI Pre-Mem Policy PPI instance +**/ +VOID +CpuPreMemPrintPolicy ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + EFI_STATUS Status; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverclockingPreMemConfig; + + DEBUG ((DEBUG_INFO, "\n------------------------ CPU - SiPreMemPolicyPpi = Print Begin in PreMem -----------------\n")); + + DEBUG ((DEBUG_INFO, " Revision=3D %x\n", SiPreMemPolicyPpi->TableHeader.= Header.Revision)); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking= PreMemConfigGuid, (VOID *) &CpuOverclockingPreMemConfig); + ASSERT_EFI_ERROR (Status); + CpuConfigLibPreMemConfigPrint(CpuConfigLibPreMemConfig); + CpuOverClockingPreMemConfigPrint(CpuOverclockingPreMemConfig); + + DEBUG ((DEBUG_INFO, "\n------------------------ CPU - SiPreMemPolicyPpi = Print End -----------------\n\n")); +DEBUG_CODE_END(); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuP= olicyLib/PeiCpuPolicyLib.c new file mode 100644 index 0000000000..181b72fec5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLib.c @@ -0,0 +1,434 @@ +/** @file + This file is PeiCpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef FSP_FLAG +/** + Get the next microcode patch pointer. + + @param[in, out] MicrocodeData - Input is a pointer to the last microcode= patch address found, + and output points to the next patch addr= ess found. + + @retval EFI_SUCCESS - Patch found. + @retval EFI_NOT_FOUND - Patch not found. +**/ +EFI_STATUS +EFIAPI +RetrieveMicrocode ( + IN OUT CPU_MICROCODE_HEADER **MicrocodeData + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINTN TotalSize; + + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) =3D=3D 0) || (FixedPcdGet32= (PcdFlashMicrocodeFvSize) =3D=3D 0)) { + return EFI_NOT_FOUND; + } + + /// + /// Microcode binary in SEC + /// + MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashM= icrocodeFvBase))->HeaderLength + + sizeof (EFI_FFS_FILE_HEADER); + + MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINT= N) FixedPcdGet32 (PcdFlashMicrocodeFvSize); + + if (*MicrocodeData =3D=3D NULL) { + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; + } else { + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) = { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")= ); + return EFI_NOT_FOUND; + } + + TotalSize =3D (UINTN) ((*MicrocodeData)->TotalSize); + if (TotalSize =3D=3D 0) { + TotalSize =3D 2048; + } + + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + T= otalSize); + if (*MicrocodeData >=3D (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd= ) || (*MicrocodeData)->TotalSize =3D=3D (UINT32) -1) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >=3D MicrocodeEnd \n"= )); + return EFI_NOT_FOUND; + } + } + return EFI_SUCCESS; +} + +/** + Get the microcode patch pointer. + + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL i= f not found. +**/ +EFI_PHYSICAL_ADDRESS +PlatformCpuLocateMicrocodePatch ( + VOID + ) +{ + EFI_STATUS Status; + CPU_MICROCODE_HEADER *MicrocodeData; + EFI_CPUID_REGISTER Cpuid; + UINT32 UcodeRevision; + UINTN MicrocodeBufferSize; + VOID *MicrocodeBuffer =3D NULL; + + AsmCpuid ( + CPUID_VERSION_INFO, + &Cpuid.RegEax, + &Cpuid.RegEbx, + &Cpuid.RegEcx, + &Cpuid.RegEdx + ); + + UcodeRevision =3D GetCpuUcodeRevision (); + MicrocodeData =3D NULL; + while (TRUE) { + /// + /// Find the next patch address + /// + Status =3D RetrieveMicrocode (&MicrocodeData); + DEBUG ((DEBUG_INFO, "MicrocodeData =3D %x\n", MicrocodeData)); + + if (Status !=3D EFI_SUCCESS) { + break; + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision= )) { + break; + } + } + + if (EFI_ERROR (Status)) { + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; + } + + /// + /// Check that microcode patch size is <=3D 128K max size, + /// then copy the patch from FV to temp buffer for faster access. + /// + MicrocodeBufferSize =3D (UINTN) MicrocodeData->TotalSize; + + if (MicrocodeBufferSize <=3D MAX_MICROCODE_PATCH_SIZE) { + MicrocodeBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferS= ize)); + if (MicrocodeBuffer !=3D NULL) { + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); + + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; + } else { + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode= Patch.\n")); + } + } else { + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed= size of 128K.\n")); + } + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; +} +#endif + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_CONFIG *CpuConfig; + CpuConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuConfig->Header.GuidHob.Name =3D %g\n", &CpuConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", CpuConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + CPU configuration + ********************************/ + CpuConfig->AesEnable =3D CPU_FEATURE_ENABLE; +#ifndef FSP_FLAG + CpuConfig->MicrocodePatchAddress =3D PlatformCpuLocateMicrocodePatch (); +#endif //FSP_FLAG +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuSgxConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + + /******************************** + CPU SGX configuration + ********************************/ +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPowerMgmtBasicConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + CPU_SKU CpuSku; + MSR_REGISTER TempMsr; + + CpuPowerMgmtBasicConfig =3D ConfigBlockPointer; + CpuSku =3D GetCpuSku(); + + DEBUG ((DEBUG_INFO, "CpuPowerMgmtBasicConfig->Header.GuidHob.Name =3D %g= \n", &CpuPowerMgmtBasicConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPowerMgmtBasicConfig->Header.GuidHob.Header.HobL= ength =3D 0x%x\n", CpuPowerMgmtBasicConfig->Header.GuidHob.Header.HobLength= )); + + /******************************** + CPU Power Management Basic configuration + ********************************/ + CpuPowerMgmtBasicConfig->Hwp =3D TRUE; + CpuPowerMgmtBasicConfig->HdcControl =3D TRUE; + CpuPowerMgmtBasicConfig->PowerLimit2 =3D TRUE; + CpuPowerMgmtBasicConfig->PowerLimit3Lock =3D TRUE; + CpuPowerMgmtBasicConfig->TccOffsetLock =3D FALSE; + CpuPowerMgmtBasicConfig->EnableItbm =3D TRUE; + CpuPowerMgmtBasicConfig->EnableItbmDriver =3D FALSE; + + /// + /// Initialize RATL (Runtime Average Temperature Limit) Config for ULX. + /// + if (CpuSku =3D=3D EnumCpuUlx) { + CpuPowerMgmtBasicConfig->TccActivationOffset =3D 15; + CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl =3D 5000; // 5 sec + CpuPowerMgmtBasicConfig->TccOffsetClamp =3D CPU_FEATURE_EN= ABLE; + } + CpuPowerMgmtBasicConfig->TurboMode =3D TRUE; + + TempMsr.Qword =3D AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT); + CpuPowerMgmtBasicConfig->OneCoreRatioLimit =3D TempMsr.Bytes.FirstByte; + CpuPowerMgmtBasicConfig->TwoCoreRatioLimit =3D TempMsr.Bytes.SecondByte; + CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit =3D TempMsr.Bytes.ThirdByte= ; + CpuPowerMgmtBasicConfig->FourCoreRatioLimit =3D TempMsr.Bytes.FouthByte; + CpuPowerMgmtBasicConfig->FiveCoreRatioLimit =3D TempMsr.Bytes.FifthByte; + CpuPowerMgmtBasicConfig->SixCoreRatioLimit =3D TempMsr.Bytes.SixthByte; + CpuPowerMgmtBasicConfig->SevenCoreRatioLimit =3D TempMsr.Bytes.SeventhBy= te; + CpuPowerMgmtBasicConfig->EightCoreRatioLimit =3D TempMsr.Bytes.EighthByt= e; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPowerMgmtCustomConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CpuPowerMgmtCustomConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuPowerMgmtCustomConfig->Header.GuidHob.Name =3D %= g\n", &CpuPowerMgmtCustomConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPowerMgmtCustomConfig->Header.GuidHob.Header.Hob= Length =3D 0x%x\n", CpuPowerMgmtCustomConfig->Header.GuidHob.Header.HobLeng= th)); + + /******************************** + CPU Power Management Custom configuration + ********************************/ + CpuPowerMgmtCustomConfig->CustomRatioTable.Cpuid =3D (UINT16) ((GetCpuFa= mily() | GetCpuStepping()) & (0x0FFF)); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuTestConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_TEST_CONFIG *CpuTestConfig; + CPU_SKU CpuSku; + CpuTestConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuTestConfig->Header.GuidHob.Name =3D %g\n", &CpuT= estConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuTestConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", CpuTestConfig->Header.GuidHob.Header.HobLength)); + + CpuSku =3D GetCpuSku(); + /******************************** + CPU Test configuration + ********************************/ + + CpuTestConfig->MlcStreamerPrefetcher =3D CPU_FEATURE_ENABLE; + CpuTestConfig->MlcSpatialPrefetcher =3D CPU_FEATURE_ENABLE; + CpuTestConfig->MonitorMwaitEnable =3D CPU_FEATURE_ENABLE; + CpuTestConfig->MachineCheckEnable =3D CPU_FEATURE_ENABLE; + CpuTestConfig->DebugInterfaceLockEnable =3D CPU_FEATURE_ENABLE; + + if ((CpuSku =3D=3D EnumCpuUlx) || (CpuSku =3D=3D EnumCpuUlt)){ + /** + This policy should be used to enable or disable Voltage Optimization f= eature. Recommended defaults: + Enable - For Mobile SKUs(U/Y) + Disable - Rest of all SKUs other than Mobile. + **/ + CpuTestConfig->VoltageOptimization =3D CPU_FEATURE_ENABLE; + } + else { + CpuTestConfig->VoltageOptimization =3D CPU_FEATURE_DISABLE; + } +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPidTestConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_PID_TEST_CONFIG *CpuPidTestConfig; + CpuPidTestConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuPidTestConfig->Header.GuidHob.Name =3D %g\n", &C= puPidTestConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPidTestConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", CpuPidTestConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + CPU PID Test configuration + ********************************/ +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPowerMgmtTestConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + CPU_GENERATION CpuGeneration; + UINT16 CpuDid; + + CpuPowerMgmtTestConfig =3D ConfigBlockPointer; + CpuDid =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_= MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID)); + + DEBUG ((DEBUG_INFO, "CpuPowerMgmtTestConfig->Header.GuidHob.Name =3D %g\= n", &CpuPowerMgmtTestConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPowerMgmtTestConfig->Header.GuidHob.Header.HobLe= ngth =3D 0x%x\n", CpuPowerMgmtTestConfig->Header.GuidHob.Header.HobLength))= ; + + /******************************** + CPU Power Management Test configuration + ********************************/ + CpuPowerMgmtTestConfig->Eist =3D TRUE; + CpuPowerMgmtTestConfig->EnergyEfficientPState =3D TRUE; + CpuPowerMgmtTestConfig->EnergyEfficientTurbo =3D TRUE; + if ((CpuDid =3D=3D V_SA_DEVICE_ID_CFL_DT_1) || (CpuDid =3D=3D V_SA_DEVIC= E_ID_CFL_DT_2) + || (CpuDid =3D=3D V_SA_DEVICE_ID_CFL_DT_3) || (CpuDid =3D=3D V_SA_DEV= ICE_ID_CFL_DT_4)) { + /// + /// CFL-S 6+2, CFL S 8+2, CFl S 4+2, CFL S 2+2 + /// + CpuPowerMgmtTestConfig->EnergyEfficientTurbo =3D FALSE; + } + CpuPowerMgmtTestConfig->BiProcHot =3D TRUE; + CpuPowerMgmtTestConfig->DisableProcHotOut =3D TRUE; + CpuPowerMgmtTestConfig->AutoThermalReporting =3D TRUE; + CpuPowerMgmtTestConfig->ThermalMonitor =3D TRUE; + CpuPowerMgmtTestConfig->Cx =3D TRUE; + CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock =3D TRUE; + CpuPowerMgmtTestConfig->C1e =3D TRUE; + CpuPowerMgmtTestConfig->C1AutoDemotion =3D TRUE; + CpuPowerMgmtTestConfig->C1UnDemotion =3D TRUE; + CpuGeneration =3D GetCpuGeneration(); + if(CpuGeneration =3D=3D EnumCflCpu){ + CpuPowerMgmtTestConfig->C3AutoDemotion =3D TRUE; + CpuPowerMgmtTestConfig->C3UnDemotion =3D TRUE; + } + + CpuPowerMgmtTestConfig->CStatePreWake =3D TRUE; + CpuPowerMgmtTestConfig->RaceToHalt =3D TRUE; + CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit =3D TimeUnit1024ns= ; + CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit =3D TimeUnit1024ns= ; + CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit =3D TimeUnit1024ns= ; + CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit =3D TimeUnit1024ns= ; + CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit =3D TimeUnit1024ns= ; + CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit =3D TimeUnit1024ns= ; + CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl =3D C3_LATENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl =3D C6_C7_SHORT_LA= TENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl =3D C6_C7_LONG_LAT= ENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl =3D C8_LATENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl =3D C9_LATENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl =3D C10_LATENCY; + + CpuPowerMgmtTestConfig->PkgCStateLimit =3D PkgAuto; + CpuPowerMgmtTestConfig->CustomPowerUnit =3D PowerUnit125Mi= lliWatts; + CpuPowerMgmtTestConfig->PpmIrmSetting =3D PpmIrmPairFixe= dPriority; +} + +static COMPONENT_BLOCK_ENTRY mCpuIpBlocks [] =3D { + {&gCpuConfigGuid, sizeof (CPU_CONFIG), = CPU_CONFIG_REVISION, LoadCpuConfigDefault= }, + {&gCpuPowerMgmtBasicConfigGuid, sizeof (CPU_POWER_MGMT_BASIC_CONFI= G), CPU_POWER_MGMT_BASIC_CONFIG_REVISION, LoadCpuPowerMgmtBasi= cConfigDefault}, + {&gCpuPowerMgmtCustomConfigGuid, sizeof (CPU_POWER_MGMT_CUSTOM_CONF= IG), CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION, LoadCpuPowerMgmtCust= omConfigDefault}, + {&gCpuTestConfigGuid, sizeof (CPU_TEST_CONFIG), = CPU_TEST_CONFIG_REVISION, LoadCpuTestConfigDef= ault}, + {&gCpuPidTestConfigGuid, sizeof (CPU_PID_TEST_CONFIG), = CPU_PID_TEST_CONFIG_REVISION, LoadCpuPidTestConfig= Default}, + {&gCpuPowerMgmtTestConfigGuid, sizeof (CPU_POWER_MGMT_TEST_CONFIG= ), CPU_POWER_MGMT_TEST_CONFIG_REVISION, LoadCpuPowerMgmtTest= ConfigDefault}, +}; + +/** + Get CPU config block table total size. + + @retval Size of CPU config block table +**/ +UINT16 +EFIAPI +CpuGetConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mCpuIpBlocks[0], sizeof (mCpuI= pBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + CpuAddConfigBlocks add all Cpu config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU config bloc= ks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + EFI_STATUS Status; + DEBUG((DEBUG_INFO, "CPU Post-Mem Entry \n")); + PostCode (0xC00); + + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, &mCpuIpBlo= cks[0], sizeof (mCpuIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); + DEBUG ((DEBUG_INFO, "CpuAddConfigBlocks Done \n")); + PostCode (0xC09); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLibPreMem.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/P= eiCpuPolicyLib/PeiCpuPolicyLibPreMem.c new file mode 100644 index 0000000000..7d45e10236 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLibPreMem.c @@ -0,0 +1,160 @@ +/** @file + This file is PeiCpuPolicyLibPreMem library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include +#include +#include +#include + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuSecurityPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuConfigLibPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_GENERATION CpuGeneration; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + CPU_FAMILY CpuFamily; + CPU_SKU CpuSku; + BOOLEAN PegDisabled; + UINT64 MchBar; + UINT64 SaPciBase; + + CpuConfigLibPreMemConfig =3D ConfigBlockPointer; + CpuFamily =3D GetCpuFamily(); + CpuSku =3D GetCpuSku(); + + DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Name =3D %= g\n", &CpuConfigLibPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Header.Hob= Length =3D 0x%x\n", CpuConfigLibPreMemConfig->Header.GuidHob.Header.HobLeng= th)); + + /******************************** + CPU Config Lib PreMem configuration + ********************************/ + CpuConfigLibPreMemConfig->HyperThreading =3D CPU_FEATURE_ENABLE= ; + CpuConfigLibPreMemConfig->BootFrequency =3D 1; // Maximum n= on-turbo Performance + CpuConfigLibPreMemConfig->ActiveCoreCount =3D 0; // All cores= active + CpuConfigLibPreMemConfig->JtagC10PowerGateDisable =3D CPU_FEATURE_DISABL= E; + CpuConfigLibPreMemConfig->BistOnReset =3D CPU_FEATURE_DISABL= E; + CpuConfigLibPreMemConfig->VmxEnable =3D CPU_FEATURE_ENABLE= ; + CpuConfigLibPreMemConfig->CpuRatio =3D (RShiftU64 (AsmReadMsr64 (MSR_PLA= TFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK); + + CpuGeneration =3D GetCpuGeneration(); + if(CpuGeneration =3D=3D EnumCflCpu){ + /// + /// FCLK Frequency + /// + + SaPciBase =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DE= V, SA_MC_FUN, 0); + PciSegmentReadBuffer (SaPciBase + R_SA_MCHBAR, sizeof (MchBar), &MchBa= r); + MchBar &=3D ((UINT64) ~BIT0); + if (IsPchLinkDmi (CpuFamily) && (PciSegmentRead16 (PCI_SEGMENT_LIB_ADD= RESS (SA_SEG_NUM, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG0_FUN_NUM, PCI_VEND= OR_ID_OFFSET)) !=3D 0xFFFF)) { + PegDisabled =3D MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_= CPL_OFFSET) & BIT3; + } else { + PegDisabled =3D 1; + } + + /// + /// DT/Halo FCLK =3D 1GHz + /// Ulx/Ult FCLK =3D 800MHz + /// + if (((CpuSku =3D=3D EnumCpuHalo) && (!PegDisabled)) || (CpuSku =3D=3D = EnumCpuTrad)) { + CpuConfigLibPreMemConfig->FClkFrequency =3D 1; // 1Ghz + } + else { + CpuConfigLibPreMemConfig->FClkFrequency =3D 0; // 800MHz + } + /// + /// Disable Peci Reset on C10 exit on CFL based CPU's + /// Setting to 1 will activate the message that disables peci reset. + /// + CpuConfigLibPreMemConfig->PeciC10Reset =3D 1; + } +} + +/** + Load Overclocking pre-mem Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuOverclockingPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverclockingPreMemConfig; + CpuOverclockingPreMemConfig =3D ConfigBlockPointer; + + /******************************** + CPU Overclocking PreMem configuration + ********************************/ + DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Name = =3D %g\n", &CpuOverclockingPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Header.= HobLength =3D 0x%x\n", CpuOverclockingPreMemConfig->Header.GuidHob.Header.H= obLength)); +} + +static COMPONENT_BLOCK_ENTRY mCpuIpBlocksPreMem [] =3D { + {&gCpuConfigLibPreMemConfigGuid, sizeof (CPU_CONFIG_LIB_PREMEM_CONFIG= ), CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION, LoadCpuConfigLibPreMemConfigD= efault}, + {&gCpuOverclockingPreMemConfigGuid, sizeof (CPU_OVERCLOCKING_PREMEM_CONF= IG), CPU_OVERCLOCKING_CONFIG_REVISION, LoadCpuOverclockingPreMemConf= igDefault}, +}; + +/** + Get CPU PREMEM config block table total size. + + @retval Size of CPU PREMEM config block table +**/ +UINT16 +EFIAPI +CpuGetPreMemConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mCpuIpBlocksPreMem[0], sizeof = (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM conf= ig blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddPreMemConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + EFI_STATUS Status; + DEBUG((DEBUG_INFO, "CPU Pre-Mem Entry \n")); + PostCode (0xC00); + + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, &mCpuIpBlo= cksPreMem[0], sizeof (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY))= ; + DEBUG((DEBUG_INFO, "CpuAddPreMemConfigBlocks Done \n")); + PostCode (0xC0F); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPla= tformLib/CpuPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Libr= ary/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c new file mode 100644 index 0000000000..18f2028fa9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/CpuPlatformLibrary.c @@ -0,0 +1,415 @@ +/** @file + CPU Platform Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "CpuPlatformLibrary.h" +#include +#include + +#define SKIP_MICROCODE_CHECKSUM_CHECK 1 +#define C6DRAM_ENABLE 1 +#define C6DRAM_DISABLE 0 + +/** + Return CPU Family ID + + @retval CPU_FAMILY CPU Family ID +**/ +CPU_FAMILY +EFIAPI +GetCpuFamily ( + VOID + ) +{ + EFI_CPUID_REGISTER Cpuid; + /// + /// Read the CPUID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + return ((CPU_FAMILY) (Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL)); +} + +/** + Return Cpu stepping type + + @retval UINT8 Cpu stepping type +**/ +CPU_STEPPING +EFIAPI +GetCpuStepping ( + VOID + ) +{ + EFI_CPUID_REGISTER Cpuid; + /// + /// Read the CPUID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + return ((CPU_STEPPING) (Cpuid.RegEax & CPUID_FULL_STEPPING)); +} + +/** + Return CPU Sku + + @retval UINT8 CPU Sku +**/ +UINT8 +EFIAPI +GetCpuSku ( + VOID + ) +{ + UINT8 CpuType; + UINT16 CpuDid; + UINT32 CpuFamilyModel; + EFI_CPUID_REGISTER Cpuid; + BOOLEAN SkuFound; + + SkuFound =3D TRUE; + CpuType =3D EnumCpuUnknown; + + /// + /// Read the CPUID & DID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + CpuFamilyModel =3D Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL; + CpuDid =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_= BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID)); + + switch (CpuFamilyModel) { + case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX: + switch (CpuDid) { + case V_SA_DEVICE_ID_KBL_MB_ULT_1: // KBL ULT OPI + case V_SA_DEVICE_ID_CFL_ULT_1: // CFL ULT + case V_SA_DEVICE_ID_CFL_ULT_2: // CFL ULT + case V_SA_DEVICE_ID_CFL_ULT_3: // CFL ULT + case V_SA_DEVICE_ID_CFL_ULT_4: // CFL ULT + CpuType =3D EnumCpuUlt; + break; + + default: + SkuFound =3D FALSE; + break; + } + break; + + case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO: + switch (CpuDid) { + + case V_SA_DEVICE_ID_KBL_DT_2: // DT + case V_SA_DEVICE_ID_KBL_SVR_2: // Server + case V_SA_DEVICE_ID_CFL_DT_1: // DT + case V_SA_DEVICE_ID_CFL_DT_2: // DT + case V_SA_DEVICE_ID_CFL_DT_3: // DT + case V_SA_DEVICE_ID_CFL_DT_4: // DT + case V_SA_DEVICE_ID_CFL_WS_1: // WorkStation + case V_SA_DEVICE_ID_CFL_WS_2: // Workstation + case V_SA_DEVICE_ID_CFL_WS_3: // Workstation + case V_SA_DEVICE_ID_CFL_SVR_1: // Server + case V_SA_DEVICE_ID_CFL_SVR_2: // Server + case V_SA_DEVICE_ID_CFL_SVR_3: // Server + CpuType =3D EnumCpuTrad; + break; + + case V_SA_DEVICE_ID_KBL_HALO_2: // Halo + case V_SA_DEVICE_ID_CFL_HALO_1: // Halo + case V_SA_DEVICE_ID_CFL_HALO_2: // Halo + case V_SA_DEVICE_ID_CFL_HALO_3: // Halo + CpuType =3D EnumCpuHalo; + break; + + default: + SkuFound =3D FALSE; + break; + } + break; + + default: + SkuFound =3D FALSE; + break; + } +#ifdef CFL_SIMICS + CpuType =3D EnumCpuTrad; +#else + if (!SkuFound) { + DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0= x%08X!\n", CpuDid, CpuFamilyModel)); + ASSERT (FALSE); + } +#endif + + return CpuType; +} + +/** + Returns the processor microcode revision of the processor installed in t= he system. + + @retval Processor Microcode Revision +**/ +UINT32 +GetCpuUcodeRevision ( + VOID + ) +{ + AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL); + return (UINT32) RShiftU64 (AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID), 32); +} + +/** + Verify the DWORD type checksum + + @param[in] ChecksumAddr - The start address to be checkumed + @param[in] ChecksumLen - The length of data to be checksumed + + @retval EFI_SUCCESS - Checksum correct + @retval EFI_CRC_ERROR - Checksum incorrect +**/ +EFI_STATUS +Checksum32Verify ( + IN UINT32 *ChecksumAddr, + IN UINT32 ChecksumLen + ) +{ +#if SKIP_MICROCODE_CHECKSUM_CHECK + return EFI_SUCCESS; +#else + UINT32 Checksum; + UINT32 Index; + + Checksum =3D 0; + + for (Index =3D 0; Index < ChecksumLen; Index++) { + Checksum +=3D ChecksumAddr[Index]; + } + + return (Checksum =3D=3D 0) ? EFI_SUCCESS : EFI_CRC_ERROR; +#endif +} + +/** + This function checks the MCU revision to decide if BIOS needs to load + microcode. + + @param[in] MicrocodePointer - Microcode in memory + @param[in] Revision - Current CPU microcode revision + + @retval EFI_SUCCESS - BIOS needs to load microcode + @retval EFI_ABORTED - Don't need to update microcode +**/ +EFI_STATUS +CheckMcuRevision ( + IN CPU_MICROCODE_HEADER *MicrocodePointer, + IN UINT32 Revision + ) +{ + EFI_STATUS Status; + Status =3D EFI_ABORTED; + + if ((MicrocodePointer->UpdateRevision & 0x80000000) || + (MicrocodePointer->UpdateRevision > Revision) || + (Revision =3D=3D 0)) { + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** + Check if this microcode is correct one for processor + + @param[in] Cpuid - processor CPUID + @param[in] MicrocodeEntryPoint - entry point of microcode + @param[in] Revision - revision of microcode + + @retval CorrectMicrocode if this microcode is correct +**/ +BOOLEAN +CheckMicrocode ( + IN UINT32 Cpuid, + IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint, + IN UINT32 *Revision + ) +{ + EFI_STATUS Status; + UINT8 ExtendedIndex; + MSR_IA32_PLATFORM_ID_REGISTER Msr; + UINT32 ExtendedTableLength; + UINT32 ExtendedTableCount; + BOOLEAN CorrectMicrocode; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + + Status =3D EFI_NOT_FOUND; + ExtendedTableLength =3D 0; + CorrectMicrocode =3D FALSE; + + if (MicrocodeEntryPoint =3D=3D NULL) { + return FALSE; + } + + Msr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + + /// + /// Check if the microcode is for the Cpu and the version is newer + /// and the update can be processed on the platform + /// + if ((MicrocodeEntryPoint->HeaderVersion =3D=3D 0x00000001) && + !EFI_ERROR (CheckMcuRevision (MicrocodeEntryPoint, *Revision)) + ) { + if ((MicrocodeEntryPoint->ProcessorId =3D=3D Cpuid) && (MicrocodeEntry= Point->ProcessorFlags & (1 << (UINT8) Msr.Bits.PlatformId))) { + if (MicrocodeEntryPoint->DataSize =3D=3D 0) { + Status =3D Checksum32Verify ((UINT32 *) MicrocodeEntryPoint, 2048 = / sizeof (UINT32)); + } else { + Status =3D Checksum32Verify ( + (UINT32 *) MicrocodeEntryPoint, + (MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_= HEADER)) / sizeof (UINT32) + ); + } + + if (!EFI_ERROR (Status)) { + CorrectMicrocode =3D TRUE; + } + } else if ((MicrocodeEntryPoint->DataSize !=3D 0)) { + /// + /// Check the Extended Signature if the entended signature exist + /// Only the data size !=3D 0 the extended signature may exist + /// + ExtendedTableLength =3D MicrocodeEntryPoint->TotalSize - (MicrocodeE= ntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER)); + if (ExtendedTableLength !=3D 0) { + /// + /// Extended Table exist, check if the CPU in support list + /// + ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((= UINT8 *) (MicrocodeEntryPoint) + MicrocodeEntryPoint->DataSize + 48); + /// + /// Calulate Extended Checksum + /// + if ((ExtendedTableLength % 4) =3D=3D 0) { + Status =3D Checksum32Verify ((UINT32 *) ExtendedTableHeader, Ext= endedTableLength / sizeof (UINT32)); + if (!EFI_ERROR (Status)) { + /// + /// Checksum correct + /// + ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignature= Count; + ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (Exte= ndedTableHeader + 1); + for (ExtendedIndex =3D 0; ExtendedIndex < ExtendedTableCount; = ExtendedIndex++) { + /// + /// Verify Header + /// + if ((ExtendedTable->ProcessorSignature =3D=3D Cpuid) && (Ext= endedTable->ProcessorFlag & (1 << (UINT8) Msr.Bits.PlatformId))) { + Status =3D Checksum32Verify ( + (UINT32 *) ExtendedTable, + sizeof (CPU_MICROCODE_EXTENDED_TABLE) / sizeof = (UINT32) + ); + if (!EFI_ERROR (Status)) { + /// + /// Find one + /// + CorrectMicrocode =3D TRUE; + break; + } + } + + ExtendedTable++; + } + } + } + } + } + } + + return CorrectMicrocode; +} + +/** + Check on the processor if SGX is supported. + + @retval TRUE if SGX supported + @retval FALSE if SGX is not supported +**/ +BOOLEAN +IsSgxSupported ( + VOID + ) +{ + EFI_CPUID_REGISTER CpuidRegs; + + // + // Processor support SGX feature by reading CPUID.(EAX=3D7,ECX=3D0):EBX[= 2] + // + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, &CpuidRegs.RegEa= x,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.RegEdx); + + /// + /// SGX feature is supported with CPUID.(EAX=3D7,ECX=3D0):EBX[2]=3D1 + /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] =3D=3D 1 + /// + if (((CpuidRegs.RegEbx & BIT2)) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & BI= T12)) { + return TRUE; + } + return FALSE; +} + +/** + Get processor generation + + @retval CPU_GENERATION Returns the executing thread's processor generat= ion. +**/ +CPU_GENERATION +GetCpuGeneration ( + VOID + ) +{ + EFI_CPUID_REGISTER Cpuid; + CPU_FAMILY CpuFamilyModel; + CPU_GENERATION CpuGeneration; + + CpuGeneration =3D EnumCflCpu; + /// + /// Read the CPUID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + CpuFamilyModel =3D (CPU_FAMILY) (Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL)= ; + + switch (CpuFamilyModel) { + case EnumCpuCflUltUlx: + case EnumCpuCflDtHalo: + CpuGeneration =3D EnumCflCpu; + break; + + default: + CpuGeneration =3D EnumCpuUnknownGeneration; + ASSERT (FALSE); + break; + } + + return CpuGeneration; +} + +/** + Is Whiskey Lake CPU. + + @retval TRUE The CPUID corresponds with a Whiskey Lake CPU + @retval FALSE The CPUID does not correspond with a Whiskey Lake CPU +**/ +BOOLEAN +IsWhlCpu ( + VOID + ) +{ + CPU_FAMILY CpuFamily; + CPU_STEPPING CpuStepping; + + CpuFamily =3D GetCpuFamily (); + CpuStepping =3D GetCpuStepping (); + + // + // Check if it is Whiskey Lake CPU + // + if ((CpuFamily =3D=3D EnumCpuCflUltUlx) && ((CpuStepping =3D=3D EnumCflW= 0) || (CpuStepping =3D=3D EnumCflV0))) { + return TRUE; + } + + return FALSE; +} --=20 2.16.2.windows.1