Re: [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers

["Nate DeSimone" <nathaniel.l.desimone@intel.com>]

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

-----Original Message-----
From: Kubacki, Michael A 
Sent: Friday, August 16, 2019 5:16 PM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <liming.gao@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>
Subject: [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2083

Header files for the WhiskeylakeURvp board instance.

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Signed-off-by: Michael Kubacki <michael.a.kubacki@intel.com>
---
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h  | 131 ++++++++++++++++++++
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h      |  40 ++++++
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h | 105 ++++++++++++++++
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformInfo.h        |  44 +++++++
 Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h   |  12 ++
 5 files changed, 332 insertions(+)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformHookLib.h
new file mode 100644
index 0000000000..bd849b9ee2
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pei
+++ PlatformHookLib.h
@@ -0,0 +1,131 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_PLATFORM_HOOK_LIB_H_
+#define _PEI_PLATFORM_HOOK_LIB_H_
+
+#include <PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+
+
+//EC Command to provide one byte of debug indication #define 
+BSSB_DEBUG_INDICATION 0xAE
+/**
+  Configure EC for specific devices
+
+  @param[in] PchLan       - The PchLan of PCH_SETUP variable.
+  @param[in] BootMode     - The current boot mode.
+**/
+VOID
+EcInit (
+  IN UINT8                PchLan,
+  IN EFI_BOOT_MODE        BootMode
+  );
+
+/**
+  Checks if Premium PMIC present
+
+  @retval  TRUE  if present
+  @retval  FALSE it discrete/other PMIC **/ BOOLEAN 
+IsPremiumPmicPresent (
+  VOID
+  );
+
+/**
+  Pmic Programming to supprort LPAL Feature
+
+  @retval     NONE
+**/
+VOID
+PremiumPmicDisableSlpS0Voltage (
+  VOID
+  );
+
+/**
+Pmic Programming to supprort LPAL Feature
+  @retval     NONE
+**/
+VOID
+PremiumPmicEnableSlpS0Voltage(
+  VOID
+  );
+
+/**
+  Do platform specific programming pre-memory. For example, EC init, 
+Chipset programming
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInitPreMem (
+  VOID
+  );
+
+/**
+  Do platform specific programming post-memory.
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInit (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO Before Memory is ready.
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInit (
+  VOID
+  );
+
+/**
+Voltage Margining Routine
+
+@retval  EFI_SUCCESS   Operation success
+**/
+EFI_STATUS
+VoltageMarginingRoutine(
+  VOID
+  );
+
+/**
+  Detect recovery mode
+
+  @retval  EFI_SUCCESS       System in Recovery Mode
+  @retval  EFI_UNSUPPORTED   System doesn't support Recovery Mode
+  @retval  EFI_NOT_FOUND     System is not in Recovery Mode
+**/
+EFI_STATUS
+IsRecoveryMode (
+  VOID
+  );
+
+/**
+  Early board Configuration before Memory is ready.
+
+  @retval  EFI_SUCCESS  Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+  VOID
+  );
+#endif
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatformLib.h
new file mode 100644
index 0000000000..d65586dbb9
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pei
+++ PlatformLib.h
@@ -0,0 +1,40 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED  1
+
+typedef struct {
+  UINT8   Register;
+  UINT32  Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+  PCH_GPIO_DEV Use_Sel;
+  PCH_GPIO_DEV Use_Sel2;
+  PCH_GPIO_DEV Use_Sel3;
+  PCH_GPIO_DEV Io_Sel;
+  PCH_GPIO_DEV Io_Sel2;
+  PCH_GPIO_DEV Io_Sel3;
+  PCH_GPIO_DEV Lvl;
+  PCH_GPIO_DEV Lvl2;
+  PCH_GPIO_DEV Lvl3;
+  PCH_GPIO_DEV Inv;
+  PCH_GPIO_DEV Blink;
+  PCH_GPIO_DEV Rst_Sel;
+  PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoardConfig.h
new file mode 100644
index 0000000000..44b4059f8e
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pla
+++ tformBoardConfig.h
@@ -0,0 +1,105 @@
+/** @file
+  Header file for Platform Boards Configurations.
+
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <GpioConfig.h>
+#include <TbtBoardInfo.h>
+
+#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
+#define ALIGN16(size)          (IS_ALIGNED(size, 16) ? size : ((size + 16) & 0xFFF0))
+
+#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION  0x00000001 #define 
+BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001 #define 
+BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001 #define 
+BOARD_NO_BATTERY_SUPPORT 0 #define BOARD_REAL_BATTERY_SUPPORTED BIT0 
+#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
+
+#pragma pack(1)
+
+typedef struct {
+  CONFIG_BLOCK_HEADER  Header;               ///< Offset 0-27 Config Block Header
+} BOARD_CONFIG_BLOCK;
+
+typedef struct {
+  UINT8 GpioSupport;
+  UINT32 WakeGpioNo;
+  UINT8 HoldRstExpanderNo;
+  UINT32 HoldRstGpioNo;
+  BOOLEAN HoldRstActive;
+  UINT8 PwrEnableExpanderNo;
+  UINT32 PwrEnableGpioNo;
+  BOOLEAN PwrEnableActive;
+} SWITCH_GRAPHIC_GPIO;
+
+typedef struct {
+  UINT8 ClkReqNumber : 4;
+  UINT8 ClkReqSupported : 1;
+  UINT8 DeviceResetPadActiveHigh : 1;
+  UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+  UINT8 Section;
+  UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef enum {
+  BoardGpioTypePch,
+  BoardGpioTypeExpander,
+  BoardGpioTypeNotSupported = 0xFF
+} BOARD_GPIO_TYPE;
+
+typedef struct {
+  UINT8 Type;
+  UINT8 Reserved[3];  // alignment for COMMON_GPIO_CONFIG
+  union {
+    UINT32 Pin;
+    EXPANDER_GPIO_CONFIG Expander;
+  } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
+#define NOT_USED     0xFF
+#define FREE_RUNNING 0x80
+#define LAN_CLOCK    0x70
+#define PCIE_PEG     0x40
+#define PCIE_PCH     0x00
+
+typedef struct {
+  UINT32 ClockUsage;
+  UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+  UINT64 Blob;
+  BOARD_GPIO_CONFIG  BoardGpioConfig;
+  ROOT_PORT_CLK_INFO Info;
+  PCIE_CLOCK_CONFIG  PcieClock;
+} PCD64_BLOB;
+
+typedef union {
+  UINT32        Blob;
+  USB20_AFE     Info;
+} PCD32_BLOB;
+
+#ifndef IO_EXPANDER_DISABLED
+#define IO_EXPANDER_DISABLED      0xFF
+#endif
+
+#define SPD_DATA_SIZE 512
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformInfo.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformInfo.h
new file mode 100644
index 0000000000..0e0b6c4f6c
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Pla
+++ tformInfo.h
@@ -0,0 +1,44 @@
+/** @file
+  GUID used for Platform Info Data entries in the HOB list.
+
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PLATFORM_INFO_H_
+#define _PLATFORM_INFO_H_
+
+#pragma pack(1)
+
+///
+/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in 
+GpioConfig.h /// typedef UINT32 PCH_GPIO_PAD; //Copied from 
+GpioConfig.h (need to change it based on include)
+
+typedef struct {
+UINT8    Expander;
+UINT8    Pin;
+UINT16   Reserved; // Reserved for future use
+} IO_EXPANDER_PAD;
+
+typedef union {
+PCH_GPIO_PAD       PchGpio;
+IO_EXPANDER_PAD    IoExpGpio;
+} GPIO_PAD_CONFIG;
+
+typedef struct {
+UINT8                GpioType;    // 0: Disabled (no GPIO support), 1: PCH, 2: I/O Expander
+UINT8                Reserved[3]; // Reserved for future use
+GPIO_PAD_CONFIG      GpioData;
+} PACKED_GPIO_CONFIG;
+
+typedef union {
+PACKED_GPIO_CONFIG    PackedGpio;
+UINT64                Data64;
+} COMMON_GPIO_CONFIG;
+
+#pragma pack()
+
+#endif
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
new file mode 100644
index 0000000000..7d44acccc1
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whi
+++ skeylakeURvpId.h
@@ -0,0 +1,12 @@
+/** @file
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _WHISKEYLAKE_ERB_ID_H_
+#define _WHISKEYLAKE_ERB_ID_H_
+
+#define BoardIdWhiskeyLakeRvp          0x60
+#endif // _WHISKEYLAKE_RVP3_ID_H_
+
--
2.16.2.windows.1