From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by groups.io with SMTP; Fri, 16 Aug 2019 17:54:26 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:54:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="177350245" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by fmsmga008.fm.intel.com with ESMTP; 16 Aug 2019 17:54:21 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.96]) by ORSMSX104.amr.corp.intel.com ([169.254.4.30]) with mapi id 14.03.0439.000; Fri, 16 Aug 2019 17:54:19 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Gao, Liming" , "Kinney, Michael D" , "Sinha, Ankit" Subject: Re: [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Thread-Topic: [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Thread-Index: AQHVVJEc2/McEtN+qEyVGYijXVaqhKb+g2iQ Date: Sat, 17 Aug 2019 00:54:18 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE12B1A@ORSMSX114.amr.corp.intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> <20190817001603.30632-34-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-34-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODRkYjU5MzEtZjc0OC00YjNhLThiNTktMzU5ZmZiOGU4YWJlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiTmhNVGQyZGhSbUU4QnhkUVFuQlFiNDNKK2lMNlFcLzBmaXM4dUlQWXo1ZW9JSUU5bmwzVEdkck16aUp1dkYwXC9FIn0= x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A=20 Sent: Friday, August 16, 2019 5:16 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Gao, Liming ; Desimone, Nathanie= l L ; Kinney, Michael D ; Sinha, Ankit Subject: [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add libr= ary instances REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Common package library instances. * BaseAcpiTimerLib - Support for ACPI timer services. * BaseGpioExpanderLib - Support for the TCA6424 IO expander. * DxePolicyUpdateLib - Policy update in DXE. * DxeTbtPolicyLib - DXE Thunderbolt policy initialization. * PeiDTbtInitLib - PEI discrete Thunderbolt initialization services. * PeiFspPolicyInitLib - PEI Intel FSP policy initialization. * PeiI2cAccessLib - Provides I2C read and write services. * PeiPolicyInitLib - Policy initialization in PEI. * PeiPolicyUpdateLib - Policy update in PEI. * PeiSiliconPolicyUpdateLibFsp - PEI FSP silicon policy initialization. * PeiTbtPolicyLib - PEI Thunderbolt policy initialization. * SecFspWrapperPlatformSecLib - FSP wrapper PlatformSecLib instance. * TbtCommonLib - Common Thunderbolt services. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLi= b/DxeTbtPolicyLib.inf | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCo= mmonLib/TbtCommonLib.inf | 60 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLi= b/PeiTbtPolicyLib.inf | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTb= tInitLib/PeiDTbtInitLib.inf | 45 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPolicyInitLib.inf | 161 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 139 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecFspWrapperPlatformSecLib.inf | 97 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerL= ib.inf | 54 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpi= oExpanderLib.inf | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVe= rbTableLib.inf | 67 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAcces= sLib.inf | 39 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xePolicyUpdateLib.inf | 58 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInitLib.inf | 61 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPolicyUpdateLib.inf | 272 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLi= b/DxeTbtPolicyLibrary.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLi= b/PeiTbtPolicyLibrary.h | 19 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPolicyInitLib.h | 234 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiMiscPolicyUpdate.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiPchPolicyUpdate.h | 28 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSaPolicyUpdate.h | 30 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/FsptCoreUpd.h | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/Fsp.h | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVe= rbTables.h | 3014 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeMePolicyUpdate.h | 91 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeSaPolicyUpdate.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= CpuPolicyInit.h | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= MePolicyInit.h | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInit.h | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= SaPolicyInit.h | 58 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= SiPolicyInit.h | 22 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiCpuPolicyUpdate.h | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiMePolicyUpdate.h | 14 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPchPolicyUpdate.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSaPolicyUpdate.h | 53 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSiPolicyUpdate.h | 19 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLi= b/DxeTbtPolicyLib.c | 148 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCo= mmonLib/TbtCommonLib.c | 316 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLi= b/PeiTbtPolicyLib.c | 206 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTb= tInitLib/PeiDTbtInitLib.c | 567 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspCpuPolicyInitLib.c | 461 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspMePolicyInitLib.c | 121 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspMiscUpdInitLib.c | 77 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPchPolicyInitLib.c | 736 +++++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPolicyInitLib.c | 223 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspSaPolicyInitLib.c | 848 ++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspSecurityPolicyInitLib.c | 70 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspSiPolicyInitLib.c | 95 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 100 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiFspPolicyUpdateLib.c | 124 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiPchPolicyUpdate.c | 60 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 39 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSaPolicyUpdate.c | 85 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 87 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/FspWrapperPlatformSecLib.c | 163 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/PlatformInit.c | 54 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecGetPerformance.c | 90 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecPlatformInformation.c | 79 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecRamInitData.c | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecTempRamDone.c | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerL= ib.c | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpi= oExpanderLib.c | 310 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVe= rbTableLib.c | 132 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAcces= sLib.c | 115 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeCpuPolicyUpdate.c | 88 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeMePolicyUpdate.c | 105 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xePchPolicyUpdate.c | 39 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeSaPolicyUpdate.c | 57 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInit.c | 65 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInitPreMem.c | 60 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= SaPolicyInit.c | 114 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiCpuPolicyUpdate.c | 80 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiCpuPolicyUpdatePreMem.c | 108 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiMePolicyUpdate.c | 49 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiMePolicyUpdatePreMem.c | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPchPolicyUpdate.c | 523 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPchPolicyUpdatePreMem.c | 113 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSaPolicyUpdate.c | 242 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSaPolicyUpdatePreMem.c | 221 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSiPolicyUpdate.c | 168 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/PeiCoreEntry.nasm | 130 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/SecEntry.nasm | 361 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/Stack.nasm | 72 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerL= ib.uni | 15 + 83 files changed, 13144 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Dx= eTbtPolicyLib/DxeTbtPolicyLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf new file mode 100644 index 0000000000..0d2a6cceeb --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for Tbt functionality +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeTbtPolicyLib +FILE_GUID =3D 28ABF346-4E52-4BD3-b1FF-63BA7563C9D4 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D DxeTbtPolicyLib + + +[LibraryClasses] +BaseMemoryLib +UefiRuntimeServicesTableLib +UefiBootServicesTableLib +DebugLib +PostCodeLib +HobLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec +WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec +[Sources] +DxeTbtPolicyLib.c + + +[Guids] +gEfiEndOfDxeEventGroupGuid +gTbtInfoHobGuid + +[Protocols] +gDxeTbtPolicyProtocolGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iDxeSmmTbtCommonLib/TbtCommonLib.inf b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf new file mode 100644 index 0000000000..f2330b5b71 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm= TbtCommonLib/TbtCommonLib.inf @@ -0,0 +1,60 @@ +## @file +# Component information file for Tbt common library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D TbtCommonLib + FILE_GUID =3D 5F03614E-CB56-40B1-9989-A09E25BBA294 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D TbtCommonLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[LibraryClasses] + DebugLib + PchPcieRpLib + PciSegmentLib + TimerLib + BaseLib + GpioLib + GpioExpanderLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber + +[Sources] + TbtCommonLib.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iTbtPolicyLib/PeiTbtPolicyLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf new file mode 100644 index 0000000000..b74e641e16 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf @@ -0,0 +1,51 @@ +## @file +# Component description file for Tbt policy +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiTbtPolicyLib +FILE_GUID =3D 4A95FDBB-2535-49eb-9A79-D56D24257106 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D PeiTbtPolicyLib + + +[LibraryClasses] +BaseMemoryLib +PeiServicesLib +PeiServicesTablePointerLib +MemoryAllocationLib +DebugLib +PostCodeLib +HobLib +GpioLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] +gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSUMES + +[Sources] +PeiTbtPolicyLib.c + +[Guids] +gTbtInfoHobGuid + +[Ppis] +gEfiPeiReadOnlyVariable2PpiGuid +gPeiTbtPolicyPpiGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pr= ivate/PeiDTbtInitLib/PeiDTbtInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf new file mode 100644 index 0000000000..8e0dbe73ce --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P= eiDTbtInitLib/PeiDTbtInitLib.inf @@ -0,0 +1,45 @@ +## @file +# Component description file for PEI DTBT Init library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDTbtInitLib + FILE_GUID =3D 06768A8D-8152-403f-83C1-59584FD2B438 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiDTbtInitLib + +[LibraryClasses] + PeiServicesLib + DebugLib + PcdLib + TbtCommonLib + PciSegmentLib + PeiTbtPolicyLib + PchPmcLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Ppis] + gPeiTbtPolicyPpiGuid ## CONSUMES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + #gClientCommonModuleTokenSpaceGuid.PcdTbtSupport ## PRODUCES + +[Sources] + PeiDTbtInitLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf new file mode 100644 index 0000000000..bd39cd60b7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.inf @@ -0,0 +1,161 @@ +## @file +# Library functions for Fsp Policy Initialization Library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiFspPolicyInitLib + FILE_GUID =3D 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiFspPolicyInitLib.c + PeiFspSiPolicyInitLib.c + PeiFspPchPolicyInitLib.c + PeiFspCpuPolicyInitLib.c + PeiFspMePolicyInitLib.c + PeiFspSaPolicyInitLib.c + PeiFspSecurityPolicyInitLib.c + PeiFspMiscUpdInitLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + IoLib + PeiServicesLib + SmbusLib + ConfigBlockLib + PcdLib + MemoryAllocationLib + PchInfoLib + SpiLib + +[Pcd] + gSiPkgTokenSpaceGuid.PcdTsegSize + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES + +[Ppis] + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + gEfiSecPlatformInformation2PpiGuid ## CONSUMES + gEfiSecPlatformInformationPpiGuid ## CONSUMES + +[Guids] + gPchTraceHubPreMemConfigGuid ## CONSUMES + gSmbusPreMemConfigGuid ## CONSUMES + gDciPreMemConfigGuid ## CONSUMES + gPcieRpPreMemConfigGuid ## CONSUMES + gHdAudioPreMemConfigGuid ## CONSUMES + gIshPreMemConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gLpcPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gWatchDogPreMemConfigGuid ## CONSUMES + gLanConfigGuid ## CONSUMES + gPcieRpConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gHdAudioConfigGuid ## CONSUMES + gScsConfigGuid ## CONSUMES + gIshConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gUsbConfigGuid ## CONSUMES + gSerialIoConfigGuid ## CONSUMES + gInterruptConfigGuid ## CONSUMES + gLockDownConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## PRODUCES + gSaMiscPeiConfigGuid ## PRODUCES + gMemoryConfigGuid ## CONSUMES + gMemoryConfigNoCrcGuid ## CONSUMES + gSwitchableGraphicsConfigGuid ## CONSUMES + gGraphicsPeiPreMemConfigGuid ## CONSUMES + gSaPciePeiPreMemConfigGuid ## CONSUMES + gSaMiscPeiConfigGuid ## CONSUMES + gSaPciePeiConfigGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gCpuTraceHubConfigGuid ## CONSUMES + gIpuPreMemConfigGuid ## CONSUMES + gCnviConfigGuid ## CONSUMES + gHsioConfigGuid ## CONSUMES + gEspiConfigGuid ## CONSUMES + gGnaConfigGuid ## CONSUMES + gVtdConfigGuid ## CONSUMES + gSaOverclockingPreMemConfigGuid ## CONSUMES + gMePeiPreMemConfigGuid ## CONSUMES + gMePeiConfigGuid ## CONSUMES + gDmiConfigGuid ## CONSUMES + gFlashProtectionConfigGuid ## CONSUMES + gIoApicConfigGuid ## CONSUMES + gPmConfigGuid ## CONSUMES + gP2sbConfigGuid ## CONSUMES + gPchGeneralConfigGuid ## CONSUMES + gSerialIrqConfigGuid ## CONSUMES + gThermalConfigGuid ## CONSUMES + gCpuSecurityPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gCpuOverclockingPreMemConfigGuid ## CONSUMES + gCpuConfigLibPreMemConfigGuid ## CONSUMES + gCpuPowerMgmtBasicConfigGuid ## CONSUMES + gCpuPowerMgmtCustomConfigGuid ## CONSUMES + gCpuTestConfigGuid ## CONSUMES + gCpuPidTestConfigGuid ## CONSUMES + gCpuPowerMgmtTestConfigGuid ## CONSUMES + gFspNonVolatileStorageHobGuid ## CONSUMES + gSmramCpuDataHeaderGuid ## CONSUMES + gFspReservedMemoryResourceHobTsegGuid ## CONSUMES + gSiConfigGuid ## CONSUMES + gDebugConfigHobGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/= WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/Pei= SiliconPolicyUpdateLibFsp.inf new file mode 100644 index 0000000000..994cf93e33 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -0,0 +1,139 @@ +## @file +# Provide FSP wrapper platform related function. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLibFsp + FILE_GUID =3D 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiFspPolicyUpdateLib.c + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + PeiSaPolicyUpdate.c + PeiFspMiscUpdUpdateLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses.IA32] + FspWrapperApiLib + OcWdtLib + PchResetLib + FspWrapperPlatformLib + BaseMemoryLib + CpuPlatformLib + DebugLib + HdaVerbTableLib + HobLib + IoLib + PcdLib + PostCodeLib + SmbusLib + ConfigBlockLib + PeiSaPolicyLib + PchGbeLib + PchInfoLib + PchHsioLib + PchPcieRpLib + MemoryAllocationLib + DebugPrintErrorLevelLib + SiPolicyLib + PchGbeLib + TimerLib + GpioLib + PeiLib + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + +[Guids] + gFspNonVolatileStorageHobGuid ## CONSUMES + gTianoLogoGuid ## CONSUMES + gEfiMemoryOverwriteControlDataGuid + +[Depex] + gEdkiiVTdInfoPpiGuid diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/Wh= iskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFsp= WrapperPlatformSecLib.inf new file mode 100644 index 0000000000..06489a6336 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecFspWrapperPlatformSecLib.inf @@ -0,0 +1,97 @@ +## @file +# Provide FSP wrapper platform sec related function. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SecFspWrapperPlatformSecLib + FILE_GUID =3D 4E1C4F95-90EA-47de-9ACC-B8920189A1F5 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSecLib + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspWrapperPlatformSecLib.c + SecRamInitData.c + SecPlatformInformation.c + SecGetPerformance.c + SecTempRamDone.c + PlatformInit.c + +[Sources.IA32] + Ia32/SecEntry.nasm + Ia32/PeiCoreEntry.nasm + Ia32/Stack.nasm + Ia32/Fsp.h + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + LocalApicLib + SerialPortLib + FspWrapperPlatformLib + FspWrapperApiLib + BoardInitLib + SecBoardInitLib + TestPointCheckLib + IoLib + +[Ppis] + gEfiSecPlatformInformationPpiGuid ## CONSUMES + gPeiSecPerformancePpiGuid ## CONSUMES + gTopOfTemporaryRamPpiGuid ## PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## C= ONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONS= UMES + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress + +[FixedPcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/Ba= seAcpiTimerLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTim= erLib/BaseAcpiTimerLib.inf new file mode 100644 index 0000000000..e7eef24906 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiT= imerLib.inf @@ -0,0 +1,54 @@ +## @file +# Base ACPI Timer Library +# +# Provides basic timer support using the ACPI timer hardware. The perfor= mance +# counter features are provided by the processors time stamp counter. +# +# Note: The implementation uses the lower 24-bits of the ACPI timer and +# is compatible with both 24-bit and 32-bit ACPI timers. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseAcpiTimerLib + FILE_GUID =3D 564DE85F-049E-4481-BF7A-CA04D2788CF9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib|SEC PEI_CORE PEIM + CONSTRUCTOR =3D AcpiTimerLibConstructor + MODULE_UNI_FILE =3D BaseAcpiTimerLib.uni + +[Sources] + AcpiTimerLib.c + BaseAcpiTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + PcAtChipsetPkg/PcAtChipsetPkg.dec + UefiCpuPkg/UefiCpuPkg.dec ## OVERRIDE + +[LibraryClasses] + BaseLib + PcdLib + PciLib + IoLib + DebugLib + +[Pcd] + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask ## CONSU= MES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpande= rLib/BaseGpioExpanderLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Libra= ry/BaseGpioExpanderLib/BaseGpioExpanderLib.inf new file mode 100644 index 0000000000..ef5ede18cc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf @@ -0,0 +1,36 @@ +## @file +# Library producing Gpio Expander functionality. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BaseGpioExpanderLib + FILE_GUID =3D D10AE2A4-782E-427E-92FB-BB74505ED329 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D GpioExpanderLib + +[LibraryClasses] + BaseLib + IoLib + DebugLib + TimerLib + PchSerialIoLib + I2cAccessLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioExpanderLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PeiHdaVerbTableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library= /PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf new file mode 100644 index 0000000000..3c017577b6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf @@ -0,0 +1,67 @@ +## @file +# PEI Intel HD Audio Verb Table library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiHdaVerbTableLib + FILE_GUID =3D 821486A2-CF3B-4D24-BC45-AFE40D9737EB + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D HdaVerbTableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiHdaVerbTableLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + MemoryAllocationLib + PcdLib + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib= /PeiI2cAccessLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2= cAccessLib/PeiI2cAccessLib.inf new file mode 100644 index 0000000000..887cbf84f8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2c= AccessLib.inf @@ -0,0 +1,39 @@ +## @file +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiI2cAccessLib + FILE_GUID =3D 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PeiI2cAccessLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + SecurityPkg/SecurityPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiI2cAccessLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxePolicyUpdateLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Policy/Library/DxePolicyUpdateLib/DxePolicyUpdateLib.inf new file mode 100644 index 0000000000..16653f38bd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxePolicyUpdateLib.inf @@ -0,0 +1,58 @@ +## @file +# Component description file for DXE DxePolicyUpdateLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxePolicyUpdateLib + FILE_GUID =3D 690B3786-D215-4ABB-9EF2-7A80128560E0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D DxePolicyUpdateLib|DXE_DRIVER + +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + DxeMePolicyUpdate.c + DxeSaPolicyUpdate.c + DxePchPolicyUpdate.c + DxeCpuPolicyUpdate.c + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + BaseMemoryLib + PcdLib + DebugLib + IoLib + CpuPlatformLib + HobLib + ConfigBlockLib + PciSegmentLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + +[Guids] + gEfiGlobalVariableGuid ## CONSUMES + gEfiEndOfDxeEventGroupGuid ## CONSUMES + gMeInfoSetupGuid ## PRODUCES + gMePolicyHobGuid ## CONSUMES + gCpuSetupVariableGuid ## CONSUMES + gPchSetupVariableGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Poli= cy/Library/PeiPolicyInitLib/PeiPolicyInitLib.inf new file mode 100644 index 0000000000..293abf1904 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInitLib.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PeiPolicyInit library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPolicyInitLib + FILE_GUID =3D B494DF39-A5F8-48A1-B2D0-EF523AD91C55 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPolicyInitLib + +[LibraryClasses] + BaseMemoryLib + BaseLib + CpuPlatformLib + DebugLib + DebugPrintErrorLevelLib + HobLib + IoLib + MemoryAllocationLib + PeiServicesLib + PeiPolicyBoardConfigLib + PeiPolicyUpdateLib + PostCodeLib + SmbusLib + ConfigBlockLib + SiPolicyLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy ## CONSUMES + + +[Sources] + PeiPolicyInitPreMem.c + PeiPolicyInit.c + PeiPolicyInit.h + PeiCpuPolicyInit.h + PeiMePolicyInit.h + PeiSaPolicyInit.c + PeiSaPolicyInit.h + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf new file mode 100644 index 0000000000..3095a7333e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPolicyUpdateLib.inf @@ -0,0 +1,272 @@ +## @file +# Module Information file for PEI PolicyUpdateLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPolicyUpdateLib + FILE_GUID =3D 6EA9585C-3C15-47DA-9FFC-25E9E4EA4D0C + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPolicyUpdateLib|PEIM PEI_CORE SEC + +[LibraryClasses] + HobLib + BaseCryptLib + CpuPlatformLib + IoLib + PeiSaPolicyLib + ConfigBlockLib + PchGbeLib + PchInfoLib + PchPcieRpLib + HdaVerbTableLib + MemoryAllocationLib + PeiServicesTablePointerLib + PcdLib + Tpm2CommandLib + Tpm12CommandLib + Tpm2DeviceLib + Tpm12DeviceLib + PmcLib + SataLib + PchInfoLib + PciSegmentLib + SiPolicyLib + PeiServicesLib + SpiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + SecurityPkg/SecurityPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## CONSUMES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardBomId ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive ## CONSUMES + + # PCIE RTD3 GPIO + gBoardModuleTokenSpaceGuid.PcdRootPortDev ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdRootPortFunc ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive ## CONSUMES + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES + + # CA Vref Configuration + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMobileDramPresent ## CONSUMES + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe ## CONSUMES + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## CONSUMES + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## CONSUMES + + # Pch SerialIo I2c Pads Termination + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdEcPresent + + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSataLedEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdVrAlertEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable ## C= ONSUMES + gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable ## C= ONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid ## C= ONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## C= ONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CO= NSUMES + +[Sources] + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiCpuPolicyUpdatePreMem.c + PeiCpuPolicyUpdate.c + PeiMePolicyUpdatePreMem.c + PeiMePolicyUpdate.c + PeiSaPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + PeiSiPolicyUpdate.c + +[Ppis] + gWdtPpiGuid ## CONSUMES + gPchSpiPpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + gPeiTbtPolicyPpiGuid ## CONSUMES + +[Guids] + gTianoLogoGuid ## CONSUMES + gSiConfigGuid ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Dx= eTbtPolicyLib/DxeTbtPolicyLibrary.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h new file mode 100644 index 0000000000..a88385f36f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLibrary.h @@ -0,0 +1,25 @@ +/** @file + Header file for the DxeTBTPolicy library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_TBT_POLICY_LIBRARY_H_ +#define _DXE_TBT_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include + +#endif // _DXE_TBT_POLICY_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iTbtPolicyLib/PeiTbtPolicyLibrary.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h new file mode 100644 index 0000000000..462bf780e3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLibrary.h @@ -0,0 +1,19 @@ +/** @file + Header file for the PeiTBTPolicy library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_TBT_POLICY_LIBRARY_H_ +#define _PEI_TBT_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include + +#endif // _PEI_TBT_POLICY_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.h b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h new file mode 100644 index 0000000000..52f9fbed8b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.h @@ -0,0 +1,234 @@ +/** @file + Internal header file for Fsp Policy Initialization Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_FSP_POLICY_INIT_LIB_H_ +#define _PEI_FSP_POLICY_INIT_LIB_H_ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +/** + Performs FSP SI PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SI PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP CPU PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** +Performs FSP Security PEI Policy initialization. + +@param[in][out] FspmUpd Pointer to FSP UPD Data. + +@retval EFI_SUCCESS FSP UPD Data is updated. +@retval EFI_NOT_FOUND Fail to locate required PPI. +@retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInitPreMem( +IN OUT FSPM_UPD *FspmUpd +); + +/** + Performs FSP ME PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP ME PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP CPU PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** +Performs FSP Security PEI Policy post memory initialization. + +@param[in][out] FspsUpd Pointer to FSP UPD Data. + +@retval EFI_SUCCESS FSP UPD Data is updated. +@retval EFI_NOT_FOUND Fail to locate required PPI. +@retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInit( +IN OUT FSPS_UPD *FspsUpd +); + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ); + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +#endif // _PEI_FSP_POLICY_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h b/Platform/Intel/Whiskeylake= OpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyU= pdate.h new file mode 100644 index 0000000000..a0c8f2dae7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiMiscPolicyUpdate.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_MISC_POLICY_UPDATE_H_ +#define _PEI_MISC_POLICY_UPDATE_H_ + +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +#endif diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/WhiskeylakeO= penBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpd= ate.h new file mode 100644 index 0000000000..1ff16e2f32 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiPchPolicyUpdate.h @@ -0,0 +1,28 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/WhiskeylakeOp= enBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdat= e.h new file mode 100644 index 0000000000..9b8c28c469 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSaPolicyUpdate.h @@ -0,0 +1,30 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include + +#include +#include +#include + +extern EFI_GUID gTianoLogoGuid; + +#endif + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h new file mode 100644 index 0000000000..e7b5ed952b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/FsptCoreUpd.h @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __FSPT_CORE_UPD_H__ +#define __FSPT_CORE_UPD_H__ + +#pragma pack(1) + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionSize; + +/** Offset 0x0030 +**/ + UINT8 Reserved[16]; +} FSPT_CORE_UPD; + +#pragma pack() + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/WhiskeylakeOpenBoardPkg= /FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h new file mode 100644 index 0000000000..1c88285a1d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/Fsp.h @@ -0,0 +1,43 @@ +/** @file + Fsp related definitions + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __FSP_H__ +#define __FSP_H__ + +// +// Fv Header +// +#define FVH_SIGINATURE_OFFSET 0x28 +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH +#define FVH_HEADER_LENGTH_OFFSET 0x30 +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34 +#define FVH_EXTHEADER_SIZE_OFFSET 0x10 + +// +// Ffs Header +// +#define FSP_HEADER_GUID_DWORD1 0x912740BE +#define FSP_HEADER_GUID_DWORD2 0x47342284 +#define FSP_HEADER_GUID_DWORD3 0xB08471B9 +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527 +#define FFS_HEADER_SIZE_VALUE 0x18 + +// +// Section Header +// +#define SECTION_HEADER_TYPE_OFFSET 0x03 +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04 + +// +// Fsp Header +// +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PchHdaVerbTables.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/Pei= HdaVerbTableLib/PchHdaVerbTables.h new file mode 100644 index 0000000000..0d26e8ad7a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pch= HdaVerbTables.h @@ -0,0 +1,3014 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_VERB_TABLES_H_ +#define _PCH_HDA_VERB_TABLES_H_ + +#include + +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: CFL Display Audio Codec + // Revision ID =3D 0xFF + // Codec Vendor: 0x8086280B + // + 0x8086, 0x280B, + 0xFF, 0xFF, + // + // Display Audio Verb Table + // + // For GEN9, the Vendor Node ID is 08h + // Port to be exposed to the inbox driver in the vanilla mode: PORT C - = BIT[7:6] =3D 01b + 0x00878140, + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010 + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020 + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030 + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + // Disable the third converter and third Pin (NID 08h) + 0x00878140 +); + +// +//codecs verb tables +// +HDAUDIO_VERB_TABLE HdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40622005 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D20, + 0x01D71E62, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + // + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +); // HdaVerbTableAlc700 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc701 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC701) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0701 + // + 0x10EC, 0x0701, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC701 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40610041 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC1124 + 0x00172024, + 0x00172111, + 0x001722EC, + 0x00172310, + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C41, + 0x01D71D00, + 0x01D71E61, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B +); // HdaVerbTableAlc701 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC274) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0274 + // + 0x10EC, 0x0274, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC274 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6 + //The number of verb command block : 16 + + // NID 0x12 : 0x40000000 + // NID 0x13 : 0x411111F0 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x411111F0 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11020 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40451B05 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211010 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //,DA Codec Subsystem ID : 0x10EC10F6 + 0x001720F6, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + //Pin widget 0x14 - NPC + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S_OUT2 + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S_OUT1 + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + //Pin widget 0x18 - I2S_IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D1B, + 0x01D71E45, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C10, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205006F, + 0x02042C0B, + //Widget node 0x20 - 1 : + 0x02050035, + 0x02048968, + 0x05B50001, + 0x05B48540, + //Widget node 0x20 - 2 : + 0x05850000, + 0x05843888, + 0x05850000, + 0x05843888, + //Widget node 0x20 - 3 : + 0x0205004A, + 0x0204201B, + 0x0205004A, + 0x0204201B +); //HdaVerbTableAlc274 + +// +// CFL S Audio Codec +// +STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_IN= IT ( + // + // VerbTable: (Realtek ALC700) CFL S RVP + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C + //The number of verb command block : 17 + + // NID 0x12 : 0x90A60130 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x03011010 + // NID 0x17 : 0x90170120 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A1103E + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x03A11040 + // NID 0x1D : 0x40600001 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x0421102F + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC112C + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C30, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671C10, + 0x01671D10, + 0x01671E01, + 0x01671F03, + //Pin widget 0x17 - I2S-OUT + 0x01771C20, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C3E, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71C40, + 0x01B71D10, + 0x01B71EA1, + 0x01B71F03, + //Pin widget 0x1D - PC-BEEP + 0x01D71C01, + 0x01D71D00, + 0x01D71E60, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of= NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14) + 0x0205006B, + 0x02044260, + 0x0205006B, + 0x02044260, + //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700 + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent co= ntrol + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 4 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + + //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC= 1305 EQ setting + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x02042213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); + + +// +// WHL codecs verb tables +// +HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) WHL RVP + // Revision ID =3D 0xff + // Codec Verb Table for WHL PCH boards + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x02A19040 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40638029 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x02211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C40, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C29, + 0x01D71D80, + 0x01D71E63, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F02, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + + //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 byp= ass DAC02 DRE(NID5B bit14) + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + + //Widget node 0x20 -2: + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + + //Widget node 0x20 - 3 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + + //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC= 1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x0204E213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204422E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); // WhlHdaVerbTableAlc700 + +#endif // _PCH_HDA_VERB_TABLES_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeMePolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.h new file mode 100644 index 0000000000..8cbcace075 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeMePolicyUpdate.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_ME_POLICY_UPDATE_H_ +#define _DXE_ME_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PLATFORM_BOOT_TABLE_PTR_TYPE 0x1001 +#define PLATFORM_BOOT_RECORD_TYPE 0x1022 +// +// Timeout values based on HPET +// +#define HECI_MSG_DELAY 2000000 ///< show warning msg and = stay for 2 seconds. +#define CONVERSION_MULTIPLIER 1000000 ///< msec to nanosec multi= plier +#define PLATFORM_BOOT_TABLE_SIGNATURE SIGNATURE_32 ('P', 'B', 'P', 'T') + +// +// Platform Boot Performance Table Record +// + +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; + UINT32 Reserved; + UINT64 TimestampDelta1; + UINT64 TimestampDelta2; + UINT64 TimestampDelta3; +} PLATFORM_BOOT_TABLE_RECORD; + +// +// Platform boot Performance Table +// + +typedef struct { + EFI_ACPI_COMMON_HEADER Header; + PLATFORM_BOOT_TABLE_RECORD PlatformBoot; +} PLATFORM_BOOT_PERFORMANCE_TABLE; + +/** + Update ME Policy while MePlatformProtocol is installed. + + @param[in] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromMeSetup ( + IN ME_POLICY_PROTOCOL *MePolicyInstance + ); + +/** + Update ME Policy if Setup variable exists. + + @param[in, out] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromSetup ( + IN OUT ME_POLICY_PROTOCOL *MePolicyInstance + ); + +/** + Functions performs HECI exchange with FW to update MePolicy settings. + + @param[in] Event A pointer to the Event that triggered the callb= ack. + @param[in] Context A pointer to private data registered with the c= allback function. + +**/ +VOID +EFIAPI +UpdateMeSetupCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeSaPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.h new file mode 100644 index 0000000000..4521d83567 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeSaPolicyUpdate.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SA_POLICY_UPDATE_H_ +#define _DXE_SA_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiCpuPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy= /Library/PeiPolicyInitLib/PeiCpuPolicyInit.h new file mode 100644 index 0000000000..25c5213c2d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiCpuPolicyInit.h @@ -0,0 +1,37 @@ +/** @file + Header file for the PeiCpuPolicyInit. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CPU_POLICY_INIT_H_ +#define _PEI_CPU_POLICY_INIT_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This function performs CPU PEI Policy initialization in PreMem. + + @param[in, out] SiPreMemPolicyPpi The Si Pre-Mem Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiMePolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiMePolicyInit.h new file mode 100644 index 0000000000..7f3fde9fd8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiMePolicyInit.h @@ -0,0 +1,23 @@ +/** @file + Header file for the PeiMePolicyInit + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_ME_POLICY_INIT_H_ +#define _PEI_ME_POLICY_INIT_H_ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#endif // _PEI_ME_POLICY_INIT_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Li= brary/PeiPolicyInitLib/PeiPolicyInit.h new file mode 100644 index 0000000000..9c18f85735 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInit.h @@ -0,0 +1,23 @@ +/** @file + Header file for the PolicyInitPei PEIM. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_POLICY_INIT_H_ +#define _PEI_POLICY_INIT_H_ + +#include +#include +#include + +#include "PeiCpuPolicyInit.h" +#include "PeiMePolicyInit.h" +#include "PeiSaPolicyInit.h" +#include "PeiSiPolicyInit.h" +#include +#include +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiSaPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiSaPolicyInit.h new file mode 100644 index 0000000000..83b18bf533 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiSaPolicyInit.h @@ -0,0 +1,58 @@ +/** @file + Header file for the SaPolicyInitPei PEIM. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_POLICY_INIT_PEI_H_ +#define _SA_POLICY_INIT_PEI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Functions +// +/** +PCIe GPIO Write + +@param[in] Gpio - GPIO Number +@param[in] Active - GPIO Active Information; High/Low +@param[in] Level - Write GPIO value (0/1) + +**/ +VOID +PcieGpioWrite( +IN UINT32 Gpio, +IN BOOLEAN Active, +IN BOOLEAN Level +); + +/** +PcieCardResetWorkAround performs PCIe Card reset on root port + +@param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY_PPI + +@retval EFI_SUCCESS The policy is installed and initialized. +**/ +EFI_STATUS +PcieCardResetWorkAround( +IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiSiPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiSiPolicyInit.h new file mode 100644 index 0000000000..1a28f426d6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiSiPolicyInit.h @@ -0,0 +1,22 @@ +/** @file + Header file for the PeiSiPolicyInit + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_POLICY_INIT_PEI_H_ +#define _SI_POLICY_INIT_PEI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // _SI_POLICY_INIT_PEI_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h new file mode 100644 index 0000000000..254e58edb7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiCpuPolicyUpdate.h @@ -0,0 +1,32 @@ +/** @file + Header file for PEI CpuPolicyUpdate. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CPU_POLICY_UPDATE_H_ +#define _PEI_CPU_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiMePolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.h new file mode 100644 index 0000000000..37cd373c78 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiMePolicyUpdate.h @@ -0,0 +1,14 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_ME_POLICY_UPDATE_H_ +#define _PEI_ME_POLICY_UPDATE_H_ + +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h new file mode 100644 index 0000000000..5a69852801 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdate.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h new file mode 100644 index 0000000000..8cf24ed24d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdate.h @@ -0,0 +1,53 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include +#include + +#define WDT_TIMEOUT 60 + +// BClk Frequency Limitations (in Hz) +#define BCLK_MAX 538000000 +#define BCLK_100 100000000 +#define BCLK_GRANULARITY 1000000 +#define BCLK_100_KHZ 100000 + + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ); + +#endif + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSiPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h new file mode 100644 index 0000000000..38ea081166 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSiPolicyUpdate.h @@ -0,0 +1,19 @@ +/** @file + Header file for PEI SiPolicyUpdate. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SI_POLICY_UPDATE_H_ +#define _PEI_SI_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Dx= eTbtPolicyLib/DxeTbtPolicyLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c new file mode 100644 index 0000000000..c185cda4ce --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.c @@ -0,0 +1,148 @@ +/** @file + This file is DxeTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + + +/** + Update Tbt Policy Callback +**/ + +VOID +EFIAPI +UpdateTbtPolicyCallback ( + VOID + ) +{ + EFI_STATUS Status; + DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; + + DxeTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + DEBUG ((DEBUG_INFO, "UpdateTbtPolicyCallback\n")); + + Status =3D gBS->LocateProtocol ( + &gDxeTbtPolicyProtocolGuid, + NULL, + (VOID **) &DxeTbtConfig + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"))= ; + } else { + + } + + return; +} + +/** + Print DXE TBT Policy +**/ +VOID +TbtPrintDxePolicyConfig ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 Index; + DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; + + DEBUG ((DEBUG_INFO, "TbtPrintDxePolicyConfig Start\n")); + + DxeTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + Status =3D gBS->LocateProtocol ( + &gDxeTbtPolicyProtocolGuid, + NULL, + (VOID **) &DxeTbtConfig + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"))= ; + } + ASSERT_EFI_ERROR (Status); + // + // Print DTBT Policy + // + DEBUG ((DEBUG_ERROR, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D DXE TBT POLICY =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D \n")); + for (Index =3D 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) { + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieExtr= aBusRsvd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcie= ExtraBusRsvd)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemR= svd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieMemRs= vd)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemA= ddrRngMax =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPci= eMemAddrRngMax)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMem= Rsvd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPciePMem= Rsvd)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMem= AddrRngMax =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPc= iePMemAddrRngMax)); + } + + // + // Print TBT Common Policy + // + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAspm =3D %x\n", Dx= eTbtConfig->TbtCommonConfig.TbtAspm)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtL1SubStates =3D %x= \n", DxeTbtConfig->TbtCommonConfig.TbtL1SubStates)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotNotify =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.TbtHotNotify)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotSMI =3D %x\n", = DxeTbtConfig->TbtCommonConfig.TbtHotSMI)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtLtr =3D %x\n", Dxe= TbtConfig->TbtCommonConfig.TbtLtr)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtPtm =3D %x\n", Dxe= TbtConfig->TbtCommonConfig.TbtPtm)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtSetClkReq =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.TbtSetClkReq)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport =3D = %x\n", DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.SecurityMode =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.SecurityMode)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Gpio5Filter =3D %x\n"= , DxeTbtConfig->TbtCommonConfig.Gpio5Filter)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TrA0OsupWa =3D %x\n",= DxeTbtConfig->TbtCommonConfig.TrA0OsupWa)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch =3D %x\= n", DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3Tbt =3D %x\n", Dx= eTbtConfig->TbtCommonConfig.Rtd3Tbt)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay =3D %= x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq =3D %x\= n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay = =3D %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Win10Support =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.Win10Support)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity = =3D %x\n", DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.ControlIommu =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.ControlIommu)); + return; +} + +/** + Install Tbt Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallTbtPolicy ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + DXE_TBT_POLICY_PROTOCOL *DxeTbtPolicy; + + DEBUG ((DEBUG_INFO, "Install DXE TBT Policy\n")); + + DxeTbtPolicy =3D NULL; + //Alloc memory for DxeTbtPolicy + DxeTbtPolicy =3D (DXE_TBT_POLICY_PROTOCOL *) AllocateZeroPool (sizeof (D= XE_TBT_POLICY_PROTOCOL)); + if (DxeTbtPolicy =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gDxeTbtPolicyProtocolGuid, + EFI_NATIVE_INTERFACE, + DxeTbtPolicy + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Install Tbt Secure Boot List protocol failed\n")= ); + } + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iDxeSmmTbtCommonLib/TbtCommonLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg= /Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c new file mode 100644 index 0000000000..690c9acf95 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm= TbtCommonLib/TbtCommonLib.c @@ -0,0 +1,316 @@ +/** @file + PeiTbtInit library implementition with empty functions. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Selects the proper TBT Root port to assign resources + based on the user input value + + @param[in] SetupData Pointer to Setup data + + @retval TbtSelectorChosen Rootport number. +**/ +VOID +GetRootporttoSetResourcesforTbt ( + IN UINTN RpIndex, + OUT UINT8 *RsvdExtraBusNum, + OUT UINT16 *RsvdPcieMegaMem, + OUT UINT8 *PcieMemAddrRngMax, + OUT UINT16 *RsvdPciePMegaMem, + OUT UINT8 *PciePMemAddrRngMax, + OUT BOOLEAN *SetResourceforTbt + ) +{ + UINTN TbtRpNumber; + TbtRpNumber =3D (UINTN) PcdGet8 (PcdDTbtPcieRpNumber); + + if (RpIndex =3D=3D (TbtRpNumber - 1)) { + *RsvdExtraBusNum =3D PcdGet8 (PcdDTbtPcieExtraBusRsvd); + *RsvdPcieMegaMem =3D PcdGet16 (PcdDTbtPcieMemRsvd); + *PcieMemAddrRngMax =3D PcdGet8 (PcdDTbtPcieMemAddrRngMax); + *RsvdPciePMegaMem =3D PcdGet16 (PcdDTbtPciePMemRsvd); + *PciePMemAddrRngMax =3D PcdGet8 (PcdDTbtPciePMemAddrRngMax); + *SetResourceforTbt =3D TRUE; + } + else { + *SetResourceforTbt =3D FALSE; + } + } + +/** + Internal function to Wait for Tbt2PcieDone Bit.to Set or clear + @param[in] CommandOffsetAddress Tbt2Pcie Register Address + @param[in] TimeOut Time out with 100 ms garnularity + @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl= ear/Set) + @param[out] *Tbt2PcieValue Function Register value +**/ +BOOLEAN +InternalWaitforCommandCompletion( + IN UINT64 CommandOffsetAddress, + IN UINT32 TimeOut, + IN BOOLEAN Tbt2PcieDone, + OUT UINT32 *Tbt2PcieValue + ) +{ + BOOLEAN ReturnFlag; + UINT32 Tbt2PcieCheck; + + ReturnFlag =3D FALSE; + while (TimeOut-- > 0) { + *Tbt2PcieValue =3D PciSegmentRead32 (CommandOffsetAddress); + + if (0xFFFFFFFF =3D=3D *Tbt2PcieValue ) { + // + // Device is not here return now + // + ReturnFlag =3D FALSE; + break; + } + + if(Tbt2PcieDone) { + Tbt2PcieCheck =3D *Tbt2PcieValue & TBT2PCIE_DON_R; + } else { + Tbt2PcieCheck =3D !(*Tbt2PcieValue & TBT2PCIE_DON_R); + } + + if (Tbt2PcieCheck) { + ReturnFlag =3D TRUE; + break; + } + + MicroSecondDelay(TBT_MAIL_BOX_DELAY); + } + return ReturnFlag; +} +/** + Get Security Level. + @param[in] Bus Bus number Host Router (DTBT) + @param[in] Device Device number for Host Router (DTBT) + @param[in] Function Function number for Host Router (DTBT) + @param[in] Command Command for Host Router (DTBT) + @param[in] Timeout Time out with 100 ms garnularity +**/ +UINT8 +GetSecLevel ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + UINT8 ReturnFlag; + + ReturnFlag =3D 0xFF; + + DEBUG ((DEBUG_INFO, "GetSecLevel() \n")); + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); + + if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterVa= lue)) { + ReturnFlag =3D (UINT8) (0xFF & (RegisterValue >> 8)); + } + + PciSegmentWrite32 (Pcie2Tbt, 0); + + InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu= e); + DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag)); + + return ReturnFlag; +} + +/** + Set Security Level. + @param[in] Data Security State + @param[in] Bus Bus number for Host Router (DTBT) + @param[in] Device Device number for Host Router (DTBT) + @param[in] Function Function number for Host Router (DTBT) + @param[in] Command Command for Host Router (DTBT) + @param[in] Timeout Time out with 100 ms garnularity +**/ +BOOLEAN +SetSecLevel ( + IN UINT8 Data, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + BOOLEAN ReturnFlag; + + ReturnFlag =3D FALSE; + + DEBUG ((DEBUG_INFO, "SetSecLevel() \n")); + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + + PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B); + + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,= &RegisterValue); + DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue)); + PciSegmentWrite32 (Pcie2Tbt, 0); + + InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu= e); + DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag)); + return ReturnFlag; +} + +/** +Based on the Security Mode Selection, BIOS drives FORCE_PWR. + +@param[in] GpioNumber +@param[in] Value +**/ +VOID +ForceDtbtPower( + IN UINT8 GpioAccessType, + IN UINT8 Expander, + IN UINT32 GpioNumber, + IN BOOLEAN Value +) +{ + if (GpioAccessType =3D=3D 0x01) { + // PCH + GpioSetOutputValue (GpioNumber, (UINT32)Value); + } else if (GpioAccessType =3D=3D 0x02) { + // IoExpander {TCA6424A} + GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value); + } +} + +/** +Execute TBT Mail Box Command + +@param[in] Command TBT Command +@param[in] Bus Bus number for Host Router (DTBT) +@param[in] Device Device number for Host Router (DTBT) +@param[in] Function Function number for Host Router (DTBT) +@param[in] Timeout Time out with 100 ms garnularity +@Retval true if command executes succesfully +**/ +BOOLEAN +TbtSetPcie2TbtCommand( + IN UINT8 Command, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT32 Timeout +) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + BOOLEAN ReturnFlag; + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); + + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE= , &RegisterValue); + + PciSegmentWrite32(Pcie2Tbt, 0); + + return ReturnFlag; +} +/** + Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po= rt physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device = number. + @param[out] RpFun Return corresponding root port functio= n number. + + @retval EFI_SUCCESS Root port device and function is retri= eved + @retval EFI_INVALID_PARAMETER If Invalid Root Port Number or TYPE is= Passed +**/ +EFI_STATUS +EFIAPI +GetDTbtRpDevFun ( + IN BOOLEAN Type, + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFunc + ) +{ + EFI_STATUS Status; + UINTN TbtRpDev; + UINTN TbtRpFunc; + + Status =3D EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS if= valid input found. + // + // PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will be + // with device number 0x1 and Function number 0,1 and 2 respectively. + // + if (Type =3D=3D DTBT_TYPE_PEG) + { + // + // PEG Rootport + // + if (RpNumber <=3D 2) { + *RpDev =3D 0x01; + *RpFunc =3D RpNumber; + Status =3D EFI_SUCCESS; + } + } + if (Type =3D=3D DTBT_TYPE_PCH) + { + // + // PCH Rootport + // + if (RpNumber <=3D 23) { + Status =3D GetPchPcieRpDevFun (RpNumber, &TbtRpDev, &TbtRpFunc); + *RpDev =3D TbtRpDev; + *RpFunc =3D TbtRpFunc; + } + } + + ASSERT_EFI_ERROR (Status); + return Status; +} + +BOOLEAN +IsTbtHostRouter ( + IN UINT16 DeviceID + ) +{ + switch (DeviceID) { + case AR_HR_2C: + case AR_HR_4C: + case AR_HR_LP: + case AR_HR_C0_2C: + case AR_HR_C0_4C: + case TR_HR_2C: + case TR_HR_4C: + return TRUE; + } + + return FALSE; +} // IsTbtHostRouter + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iTbtPolicyLib/PeiTbtPolicyLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c new file mode 100644 index 0000000000..ffd8416660 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.c @@ -0,0 +1,206 @@ +/** @file + This file is PeiTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Update PEI TBT Policy Callback +**/ +VOID +EFIAPI +UpdatePeiTbtPolicy ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + PEI_TBT_POLICY *PeiTbtConfig; + + PeiTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + + DEBUG ((DEBUG_INFO, "UpdatePeiTbtPolicy \n")); + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **) &VariableServices + ); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + + // + // Update DTBT Policy + // + PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D PcdGet8 (PcdDTb= tControllerEn); + if (PcdGet8 (PcdDTbtControllerType) =3D=3D TYPE_PEG) + { + PeiTbtConfig-> DTbtControllerConfig.Type =3D (UINT8) TYPE_PEG; + PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D 1; // PEG RP 1 (F= unction no. 0) + } + else { + PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D PcdGet8 (PcdDTbtP= cieRpNumber); + PeiTbtConfig-> DTbtControllerConfig.Type =3D PcdGet8 (PcdDTbtControlle= rType); + } + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D (GPIO_PA= D) PcdGet32 (PcdDTbtCioPlugEventGpioPad); + if (GpioCheckFor2Tier(PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpi= o.GpioPad)) { + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo= rting =3D 0; + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = =3D SIGNATURE_32('X', 'T', 'B', 'T'); + } + else { + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo= rting =3D 1; + // + // Update Signature based on platform GPIO. + // + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = =3D SIGNATURE_32('X', 'T', 'B', 'T'); + } + PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D PcdGet8 (PcdDTbtBootOn); + PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D PcdGet8 (PcdDTbtUsbOn); + PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D PcdGet8 (PcdDTbtGpio3Fo= rcePwr); + PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D PcdGet16 (PcdDTbtGpi= o3ForcePwrDly); + + return; +} + +/** + Print PEI TBT Policy +**/ +VOID +EFIAPI +TbtPrintPeiPolicyConfig ( + VOID + ) +{ + DEBUG_CODE_BEGIN (); + EFI_STATUS Status; + PEI_TBT_POLICY *PeiTbtConfig; + + PeiTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + DEBUG ((DEBUG_INFO, "TbtPrintPolicyConfig Start\n")); + + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + + // + // Print DTBT Policy + // + DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print B= EGIN -----------------\n")); + DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", PEI_TBT_POLICY_REVISION)); + DEBUG ((DEBUG_INFO, "------------------------ PEI_TBT_CONFIG ----------= -------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", PEI_TBT_POLICY_REVISION)); + + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.DTbtControllerEn= =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.Type =3D %x\n", = PeiTbtConfig-> DTbtControllerConfig.Type)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRpNumber =3D= %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi= oPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi= oLevel =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLeve= l)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio= Pad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio= Level =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel)= ); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .GpioPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.Gp= ioPad)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .AcpiGpeSignature =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEve= ntGpio.AcpiGpeSignature)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .AcpiGpeSignaturePorting =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.Cio= PlugEventGpio.AcpiGpeSignaturePorting)); + + + // + // Print DTBT Common Policy + // + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D %x\n",= PeiTbtConfig->DTbtCommonConfig.TbtBootOn)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D %x\n", = PeiTbtConfig->DTbtCommonConfig.TbtUsbOn)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D %x= \n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D= %x\n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfig= uration =3D %x\n", PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfigurati= on)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.PcieRstSupport =3D %= x\n", PeiTbtConfig->DTbtCommonConfig.PcieRstSupport)); + + DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print E= ND -----------------\n")); + DEBUG_CODE_END (); + + return; +} + +/** + Install Tbt Policy + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallPeiTbtPolicy ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PeiTbtPolicyPpiDesc; + PEI_TBT_POLICY *PeiTbtConfig; + + DEBUG ((DEBUG_INFO, "Install PEI TBT Policy\n")); + + PeiTbtConfig =3D NULL; + + // + // Allocate memory for PeiTbtPolicyPpiDesc + // + PeiTbtPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (siz= eof (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (PeiTbtPolicyPpiDesc !=3D NULL); + if (PeiTbtPolicyPpiDesc =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Allocate memory and initialize all default to zero for PeiTbtPolicy + // + PeiTbtConfig =3D (PEI_TBT_POLICY *) AllocateZeroPool (sizeof (PEI_TBT_PO= LICY)); + ASSERT (PeiTbtConfig !=3D NULL); + if (PeiTbtConfig =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Initialize PPI + // + PeiTbtPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_= DESCRIPTOR_TERMINATE_LIST; + PeiTbtPolicyPpiDesc->Guid =3D &gPeiTbtPolicyPpiGuid; + PeiTbtPolicyPpiDesc->Ppi =3D PeiTbtConfig; + + Status =3D PeiServicesInstallPpi (PeiTbtPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Install PEI TBT Policy failed\n")); + } + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pr= ivate/PeiDTbtInitLib/PeiDTbtInitLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c new file mode 100644 index 0000000000..f33ddebdb3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P= eiDTbtInitLib/PeiDTbtInitLib.c @@ -0,0 +1,567 @@ +/** @file + Thunderbolt(TM) Pei Library + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** +Is host router (For dTBT) or End Point (For iTBT) present before sleep + +@param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER +@param[in] Controller - Controller begin offset of CMOS + +@Retval TRUE There is a TBT HostRouter presented before sleep +@Retval FALSE There is no TBT HostRouter presented before sleep + +BOOLEAN +IsHostRouterPresentBeforeSleep( +IN UINT8 ControllerType, +IN UINT8 Controller +) +{ + UINT8 SavedState; + + SavedState =3D (UINT8)GetTbtHostRouterStatus(); + if (ControllerType =3D=3D DTBT_CONTROLLER){ + return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) =3D=3D (= DTBT_SAVE_STATE_OFFSET << Controller)); + } else { + if (ControllerType =3D=3D ITBT_CONTROLLER) { + return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) =3D=3D= (ITBT_SAVE_STATE_OFFSET << Controller)); + } + } + return 0; +} +**/ + +/** +Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 mode wi= th PreBootAclEnable + +@param[in] Bus Bus number for Host Router (DTBT) +@param[in] Device Device number for Host Router (DTBT) +@param[in] Function Function number for Host Router (DTBT) +@param[in] Timeout Time out with 100 ms garnularity +@Retval true if command executes succesfully +**/ +BOOLEAN +TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT32 Timeout +) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + BOOLEAN ReturnFlag; + UINT32 Command; + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + +// If PreBootAcl is Enable, we need to enable DATA bit while sending SX EX= IT MAIL BOX Command + Command =3D (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED; + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); + + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,= &RegisterValue); + + PciSegmentWrite32(Pcie2Tbt, 0); + + return ReturnFlag; +} + +/** +Set the Sleep Mode if the HR is up. +@param[in] Bus Bus number for Host Router (DTBT) +@param[in] Device Device number for Host Router (DTBT) +@param[in] Function Function number for Host Router (DTBT) +**/ +VOID +TbtSetSxMode( +IN UINT8 Bus, +IN UINT8 Device, +IN UINT8 Function, +IN UINT8 TbtBootOn +) +{ + UINT64 TbtUsDevId; + UINT64 Tbt2Pcie; + UINT32 RegVal; + UINT32 MaxLoopCount; + UINTN Delay; + UINT8 RetCode; + EFI_BOOT_MODE BootMode; + EFI_STATUS Status; + + TbtUsDevId =3D PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0); + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + + MaxLoopCount =3D TBT_5S_TIMEOUT; // Wait 5 sec + Delay =3D 100 * 1000; + RetCode =3D 0x62; + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + if ((BootMode =3D=3D BOOT_ON_S4_RESUME) && (TbtBootOn =3D=3D 2)) { + MaxLoopCount =3D TBT_3S_TIMEOUT; + if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, Func= tion, MaxLoopCount)) { + // + // Nothing to wait, HR is not responsive + // + return; + } + } + else { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, Device= , Function, MaxLoopCount)) { + // + // Nothing to wait, HR is not responsive + // + return; + } + } + + DEBUG((DEBUG_INFO, "Wait for Dev ID !=3D 0xFF\n")); + + while (MaxLoopCount-- > 0) { + // + // Check what HR still here + // + RegVal =3D PciSegmentRead32(Tbt2Pcie); + if (0xFFFFFFFF =3D=3D RegVal) { + RetCode =3D 0x6F; + break; + } + // + // Check completion of TBT link + // + RegVal =3D PciSegmentRead32(TbtUsDevId); + if (0xFFFFFFFF !=3D RegVal) { + RetCode =3D 0x61; + break; + } + + MicroSecondDelay(Delay); + } + + DEBUG((DEBUG_INFO, "Return code =3D 0x%x\n", RetCode)); +} +/** + set tPCH25 Timing to 10 ms for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSetTPch25Timing ( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n")); + UINT32 PchPwrmBase; + + // + //During boot, reboot and wake tPCH25 Timing should be set to 10 ms + // + MmioOr32 ( + (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG), + (BIT0 | BIT1) + ); + + DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n")); + return EFI_SUCCESS; +} + +/** + Do ForcePower for DTBT Controller + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtForcePower ( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + + DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n")); + + if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) { + DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad =3D %x \n", PeiTbtConfig-= > DTbtControllerConfig.ForcePwrGpio.GpioPad)); + ForceDtbtPower(PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Gp= ioAccessType,PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Expander, Pei= TbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> DTbtC= ontrollerConfig.ForcePwrGpio.GpioLevel); + DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n")); + MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly *= 1000); + DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower =3D 0x%x ms \n", Pe= iTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); + } + + DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n")); + return EFI_SUCCESS; +} + +/** + Clear VGA Registers for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtClearVgaRegisters ( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + UINTN RpDev; + UINTN RpFunc; + EFI_STATUS Status; + UINT64 BridngeBaseAddress; + UINT16 Data16; + + DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, Pei= TbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + // + // VGA Enable and VGA 16-bit decode registers of Bridge control register= of Root port where + // Host router resides should be cleaned + // + + BridngeBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, (UIN= T32)RpFunc, 0); + Data16 =3D PciSegmentRead16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGI= STER_OFFSET); + Data16 &=3D (~(EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_1= 6)); + PciSegmentWrite16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSE= T, Data16); + + DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n")); + return Status; +} + +/** + Exectue Mail box command "Boot On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtBootOn( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + EFI_STATUS Status; + UINT32 OrgBusNumberConfiguration; + UINTN RpDev; + UINTN RpFunc; + + DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + OrgBusNumberConfiguration =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDR= ESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); + // + // Set Sec/Sub buses to 0xF0 + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); + // + //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup we = need to do the below: + //Bios should send "Boot On" message through PCIE2TBT register + //The Boot On command as described above would include the command a= nd acknowledge from FW (with the default timeout in BIOS), + //once the Boot On command is completed it is guaranteed that the Al= pineRidge(AR) device is there and the PCI tunneling was done by FW, + //next step from BIOS is enumeration using SMI + // + + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { + // + // Exectue Mail box command "Boot On / Pre-Boot ACL" + // + //Command may be executed only during boot/reboot and not during S= x exit flow + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 1) { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, TBT_5S_= TIMEOUT)) { + // + // Nothing to wait, HR is not responsive + // + DEBUG((DEBUG_INFO, " DTbtBootOn - Boot On message sent= failed \n")); + } + } + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2) { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, TBT_= 3S_TIMEOUT)) { + // + // Nothing to wait, HR is not responsive + // + DEBUG((DEBUG_INFO, " DTbtBootOn - Pre-Boot ACL message= sent failed \n")); + } + } + } + // + // Reset Sec/Sub buses to original value + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); + + DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n")); + return Status; +} + +/** + Exectue Mail box command "USB On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtUsbOn( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + EFI_STATUS Status; + UINTN RpDev; + UINTN RpFunc; + UINT32 OrgBusNumberConfiguration; + UINT64 TbtBaseAddress; + UINT32 MaxWaitIter; + UINT32 RegVal; + EFI_BOOT_MODE BootMode; + + DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE= SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); + // + // Set Sec/Sub buses to 0xF0 + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); + + // + //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setup = we need to do the below: + //Bios should send "Usb On" message through PCIE2TBT register + //The Usb On command as described above would include the command an= d acknowledge from FW (with the default timeout in BIOS), + //once the Usb On command is completed it is guaranteed that the Alp= ineRidge(AR) device is there and the PCI tunneling was done by FW, + //next step from BIOS is enumeration using SMI + // + if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) { + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { + MaxWaitIter =3D 50; // Wait 5 sec + TbtBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0); + // + // Driver clears the PCIe2TBT Valid bit to support two consicuti= ve mailbox commands + // + PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0); + DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R =3D 0x%lx \= n", TbtBaseAddress + PCIE2TBT_DTBT_R)); + while (MaxWaitIter-- > 0) { + RegVal =3D PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R); + if (0xFFFFFFFF =3D=3D RegVal) { + // + // Device is not here return now + // + DEBUG((DEBUG_INFO, "TBT device is not present \n")); + break; + } + + if (!(RegVal & TBT2PCIE_DON_R)) { + break; + } + MicroSecondDelay(100 * 1000); + } + } + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + // + // Exectue Mail box command "Usb On" + // + //Command may be executed only during boot/reboot and not during S= 3 exit flow + //In case of S4 Exit send USB ON cmd only if Host Router was inact= ive/not present during S4 entry + if ((BootMode =3D=3D BOOT_ON_S4_RESUME) ) { + // USB_ON cmd not required + } else { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, TBT_5S_T= IMEOUT)) { + // + // Nothing to wait, HR is not responsive + // + DEBUG((DEBUG_INFO, " TbtBootSupport - Usb On message s= ent failed \n")); + } + } + } + // + // Reset Sec/Sub buses to original value + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); + + DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n")); + return Status; +} + +/** + Exectue Mail box command "Sx Exit". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSxExitFlow( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + EFI_STATUS Status; + UINT32 OrgBusNumberConfiguration; + UINTN RpDev; + UINTN RpFunc; + UINT32 Count; + + DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n")); + + Status =3D EFI_SUCCESS; + Count =3D 0; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE= SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); + // + // Set Sec/Sub buses to 0xF0 + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); + + if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2)) { + // + // WA: When system with TBT 3.1 device, resume SX system need to w= ait device ready. In document that maximum time out should be 500ms. + // + while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, 0x0,= 0x08)) =3D=3D 0xffffffff) { //End Device will be with Device Number 0x0, F= unction Number 0x0. + MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec + Count++; + if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S bo= ard. + break; + } + } + + // + // Upon wake, if BIOS saved pre-Sx Host Router state as active (sy= stem went to sleep with + // attached devices), BIOS should: + // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. + // 2. If procedure above returns true, BIOS should perform "wait f= or fast link bring-up" loop + // 3. Continue regular wake flow. + // + // + // Exectue Mail box command and perform "wait for fast link bring-= up" loop + // + TbtSetSxMode(0xF0, 0, 0, PeiTbtConfig->DTbtCommonConfig.TbtBootOn)= ; + } + // + // Reset Sec/Sub buses to original value + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); + + DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n")); + return Status; +} + + +/** + Initialize Thunderbolt(TM) + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ +EFI_STATUS +EFIAPI +TbtInit ( + VOID + ) +{ + EFI_STATUS Status; + PEI_TBT_POLICY *PeiTbtConfig; + + // + // Get the TBT Policy + // + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + // + // Exectue Mail box command "Boot On" + // + Status =3D DTbtBootOn (PeiTbtConfig); + // + // Exectue Mail box command "Usb On" + // + Status =3D DTbtUsbOn (PeiTbtConfig); + // + //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register shou= ld be + //set to 11b - 10 ms (default value is 0b - 10 us) + // + Status =3D DTbtSetTPch25Timing (PeiTbtConfig); + // + // Configure Tbt Force Power + // + Status =3D DTbtForcePower (PeiTbtConfig); + // + // VGA Enable and VGA 16-bit decode registers of Bridge control register= of Root port where + // Host router resides should be cleaned + // + Status =3D DTbtClearVgaRegisters (PeiTbtConfig); + // + // Upon wake, if BIOS saved pre-Sx Host Router state as active (system w= ent to sleep with + // attached devices), BIOS should: + // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. + // 2. If procedure above returns true, BIOS should perform "wait for fas= t link bring-up" loop + // 3. Continue regular wake flow. + // + Status =3D DTbtSxExitFlow (PeiTbtConfig); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspCpuPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c new file mode 100644 index 0000000000..f38901f2ae --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspCpuPolicyInitLib.c @@ -0,0 +1,461 @@ +/** @file + Implementation of Fsp CPU Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP CPU PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n= ")); + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking= PreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + + /// + /// + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n")= ); + + // + // Overclocking PreMem policies + // + FspmUpd->FspmConfig.OcSupport =3D (UINT8) CpuOverClockingP= reMemConfig->OcSupport; + FspmUpd->FspmConfig.OcLock =3D (UINT8) CpuOverClockingP= reMemConfig->OcLock; + FspmUpd->FspmConfig.CoreMaxOcRatio =3D (UINT8) CpuOverClockingP= reMemConfig->CoreMaxOcRatio; + FspmUpd->FspmConfig.CoreVoltageMode =3D (UINT8) CpuOverClockingP= reMemConfig->CoreVoltageMode; + FspmUpd->FspmConfig.CoreVoltageOverride =3D (UINT16) CpuOverClocking= PreMemConfig->CoreVoltageOverride; + FspmUpd->FspmConfig.CoreVoltageAdaptive =3D (UINT16) CpuOverClocking= PreMemConfig->CoreVoltageAdaptive; + FspmUpd->FspmConfig.CoreVoltageOffset =3D (UINT16) CpuOverClocking= PreMemConfig->CoreVoltageOffset; + FspmUpd->FspmConfig.CorePllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->CorePllVoltageOffset; + FspmUpd->FspmConfig.RingMaxOcRatio =3D (UINT8) CpuOverClockingP= reMemConfig->RingMaxOcRatio; + FspmUpd->FspmConfig.RingVoltageOverride =3D (UINT16) CpuOverClocking= PreMemConfig->RingVoltageOverride; + FspmUpd->FspmConfig.RingVoltageAdaptive =3D (UINT16) CpuOverClocking= PreMemConfig->RingVoltageAdaptive; + FspmUpd->FspmConfig.RingVoltageOffset =3D (UINT16) CpuOverClocking= PreMemConfig->RingVoltageOffset; + FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->RingPllVoltageOffset; + FspmUpd->FspmConfig.GtPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->GtPllVoltageOffset; + FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->RingPllVoltageOffset; + FspmUpd->FspmConfig.SaPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->SaPllVoltageOffset; + FspmUpd->FspmConfig.McPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->McPllVoltageOffset; + FspmUpd->FspmConfig.RingDownBin =3D (UINT8) CpuOverClockingP= reMemConfig->RingDownBin; + FspmUpd->FspmConfig.RingVoltageMode =3D (UINT8) CpuOverClockingP= reMemConfig->RingVoltageMode; + FspmUpd->FspmConfig.Avx2RatioOffset =3D (UINT8) CpuOverClockingP= reMemConfig->Avx2RatioOffset; + FspmUpd->FspmConfig.Avx3RatioOffset =3D (UINT8) CpuOverClockingP= reMemConfig->Avx3RatioOffset; + FspmUpd->FspmConfig.BclkAdaptiveVoltage =3D (UINT8) CpuOverClockingP= reMemConfig->BclkAdaptiveVoltage; + FspmUpd->FspmConfig.TjMaxOffset =3D (UINT8) CpuOverClockingP= reMemConfig->TjMaxOffset; + FspmUpd->FspmConfig.TvbRatioClipping =3D (UINT8) CpuOverClockingP= reMemConfig->TvbRatioClipping; + FspmUpd->FspmConfig.TvbVoltageOptimization =3D (UINT8) CpuOverClockingP= reMemConfig->TvbVoltageOptimization; + + // + // Cpu Config Lib policies + // + FspmUpd->FspmConfig.HyperThreading =3D (UINT8) CpuConfigLibPr= eMemConfig->HyperThreading; + FspmUpd->FspmConfig.BootFrequency =3D (UINT8) CpuConfigLibPr= eMemConfig->BootFrequency; + FspmUpd->FspmConfig.ActiveCoreCount =3D (UINT8) CpuConfigLibPr= eMemConfig->ActiveCoreCount; + FspmUpd->FspmConfig.JtagC10PowerGateDisable =3D (UINT8) CpuConfigLibPr= eMemConfig->JtagC10PowerGateDisable; + FspmUpd->FspmConfig.FClkFrequency =3D (UINT8) CpuConfigLibPr= eMemConfig->FClkFrequency; + FspmUpd->FspmConfig.BistOnReset =3D (UINT8) CpuConfigLibPr= eMemConfig->BistOnReset; + FspmUpd->FspmConfig.VmxEnable =3D (UINT8) CpuConfigLibPr= eMemConfig->VmxEnable; + FspmUpd->FspmConfig.CpuRatio =3D (UINT8) CpuConfigLibPr= eMemConfig->CpuRatio; + FspmUpd->FspmConfig.PeciSxReset =3D (UINT8) CpuConfigLibPr= eMemConfig->PeciSxReset; + FspmUpd->FspmConfig.PeciC10Reset =3D (UINT8) CpuConfigLibPr= eMemConfig->PeciC10Reset; + FspmUpd->FspmConfig.SkipMpInit =3D (UINT8) CpuConfigLibPr= eMemConfig->SkipMpInit; + FspmUpd->FspmConfig.DpSscMarginEnable =3D (UINT8) CpuConfigLibPr= eMemConfig->DpSscMarginEnable; + + // + // DisableMtrrProgram <1> Disable Mtrrs program. <0> Program Mtrrs in FS= P + // + FspmUpd->FspmConfig.DisableMtrrProgram =3D (UINT8) 0; + + return EFI_SUCCESS; +} + +/** + This routine is used to get Sec Platform Information Record2 Pointer. + + @param[in] PeiServices Pointer to the PEI services table + + @retval GetSecPlatformInformation2 - The pointer of Sec Platform Informat= ion Record2 Pointer. + **/ + +EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformation2( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_SEC_PLATFORM_INFORMATION2_PPI *SecPlatformInformation2Ppi; + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2 =3D NULL; + UINT64 InformationSize; + EFI_STATUS Status; + + // + // Get BIST information from Sec Platform Information2 Ppi firstly + // + Status =3D PeiServicesLocatePpi ( + &gEfiSecPlatformInformation2PpiGuid, // GUID + 0, // Instance + NULL, // EFI_PEI_PPI_DESCRIP= TOR + (VOID ** ) &SecPlatformInformation2Ppi // PPI + ); + + DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi2 Status - %x\n",= Status)); + if (EFI_ERROR(Status)) { + return NULL; + } + + InformationSize =3D 0; + + Status =3D SecPlatformInformation2Ppi->PlatformInformation2 ( + (CONST EFI_PEI_SERVICES **) PeiS= ervices, + &InformationSize, + SecPlatformInformation2 + ); + + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + return NULL; + } + + SecPlatformInformation2 =3D AllocatePool((UINTN)InformationSize); + ASSERT (SecPlatformInformation2 !=3D NULL); + if (SecPlatformInformation2 =3D=3D NULL) { + return NULL; + } + + // + // Retrieve BIST data from SecPlatform2 + // + Status =3D SecPlatformInformation2Ppi->PlatformInformation2 ( + PeiServices, + &InformationSize, + SecPlatformInformation2 + ); + DEBUG((DEBUG_INFO, "SecPlatformInformation2Ppi->PlatformInformation2 Sta= tus - %x\n", Status)); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return NULL; + } + + return SecPlatformInformation2; +} + +/** + This routine is used to get Sec Platform Information Record Pointer. + + @param[in] PeiServices Pointer to the PEI services table + + @retval GetSecPlatformInformation2 - The pointer of Sec Platform Informat= ion Record Pointer. + **/ +EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformationInfoInForm= at2( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformInformationPpi; + EFI_SEC_PLATFORM_INFORMATION_RECORD *SecPlatformInformation =3D NULL; + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2; + UINT64 InformationSize; + EFI_STATUS Status; + + // + // Get BIST information from Sec Platform Information + // + Status =3D PeiServicesLocatePpi ( + &gEfiSecPlatformInformationPpiGuid, // GUID + 0, // Instance + NULL, // EFI_PEI_PPI_DESCRIP= TOR + (VOID ** ) &SecPlatformInformationPpi // PPI + ); + + DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi Status - %x\n", = Status)); + if (EFI_ERROR(Status)) { + return NULL; + } + + InformationSize =3D 0; + Status =3D SecPlatformInformationPpi->PlatformInformation ( + (CONST EFI_PEI_SERVICES **) PeiSe= rvices, + &InformationSize, + SecPlatformInformation + ); + + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + return NULL; + } + + SecPlatformInformation =3D AllocatePool((UINTN)InformationSize); + ASSERT (SecPlatformInformation !=3D NULL); + if (SecPlatformInformation =3D=3D NULL) { + return NULL; + } + + // + // Retrieve BIST data from SecPlatform + // + Status =3D SecPlatformInformationPpi->PlatformInformation ( + PeiServices, + &InformationSize, + SecPlatformInformation + ); + DEBUG((DEBUG_INFO, "FSP SecPlatformInformation2Ppi->PlatformInformation= Status - %x\n", Status)); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return NULL; + } + + SecPlatformInformation2 =3D AllocatePool(sizeof (EFI_SEC_PLATFORM_INFORM= ATION_RECORD2)); + ASSERT (SecPlatformInformation2 !=3D NULL); + if (SecPlatformInformation2 =3D=3D NULL) { + return NULL; + } + + SecPlatformInformation2->NumberOfCpus =3D 1; + SecPlatformInformation2->CpuInstance[0].CpuLocation =3D 0; + SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32= =3D SecPlatformInformation->x64HealthFlags.Uint32; + + FreePool(SecPlatformInformation); + + return SecPlatformInformation2; +} + + +/** + Performs FSP CPU PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + CPU_CONFIG *CpuConfig; + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CPU_TEST_CONFIG *CpuTestConfig; + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + UINTN Index; + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2; + EFI_PEI_SERVICES **PeiServices; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n")); + PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (); + // + // Locate gSiPolicyPpiGuid + // + SiPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf= igGuid, (VOID *) &CpuPowerMgmtBasicConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomCon= figGuid, (VOID *) &CpuPowerMgmtCustomConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (V= OID *) &CpuTestConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfi= gGuid, (VOID *) &CpuPowerMgmtTestConfig); + ASSERT_EFI_ERROR (Status); + /// + ///Production RC Policies + /// + + FspsUpd->FspsConfig.AesEnable =3D (UINT8) CpuConfig->Aes= Enable; + FspsUpd->FspsConfig.DebugInterfaceEnable =3D (UINT8) CpuConfig->Deb= ugInterfaceEnable; + + FspsUpd->FspsConfig.TurboMode =3D (UINT8) CpuPowerMgmtBa= sicConfig->TurboMode; + + /// + /// Test RC Policies + /// + FspsUpd->FspsTestConfig.MlcStreamerPrefetcher =3D (UINT8) CpuTestCo= nfig->MlcStreamerPrefetcher; + FspsUpd->FspsTestConfig.MlcSpatialPrefetcher =3D (UINT8) CpuTestCo= nfig->MlcSpatialPrefetcher; + FspsUpd->FspsTestConfig.MonitorMwaitEnable =3D (UINT8) CpuTestCo= nfig->MonitorMwaitEnable; + FspsUpd->FspsTestConfig.DebugInterfaceLockEnable =3D (UINT8) CpuTestCo= nfig->DebugInterfaceLockEnable; + FspsUpd->FspsTestConfig.ApIdleManner =3D PcdGet8 (PcdCpuAp= LoopMode); + FspsUpd->FspsTestConfig.ProcessorTraceOutputScheme =3D (UINT8) CpuTestCo= nfig->ProcessorTraceOutputScheme; + FspsUpd->FspsTestConfig.ProcessorTraceEnable =3D (UINT8) CpuTestCo= nfig->ProcessorTraceEnable; + FspsUpd->FspsTestConfig.ProcessorTraceMemBase =3D CpuTestConfig->Pr= ocessorTraceMemBase; + FspsUpd->FspsTestConfig.ProcessorTraceMemLength =3D (UINT32) CpuTestC= onfig->ProcessorTraceMemLength; + FspsUpd->FspsTestConfig.VoltageOptimization =3D (UINT8) CpuTestCo= nfig->VoltageOptimization; + FspsUpd->FspsTestConfig.ThreeStrikeCounterDisable =3D (UINT8) CpuTestCo= nfig->ThreeStrikeCounterDisable; + FspsUpd->FspsTestConfig.MachineCheckEnable =3D (UINT8) CpuTestCo= nfig->MachineCheckEnable; + FspsUpd->FspsTestConfig.CpuWakeUpTimer =3D (UINT8) CpuTestCo= nfig->CpuWakeUpTimer; + + FspsUpd->FspsTestConfig.OneCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->OneCoreRatioLimit; + FspsUpd->FspsTestConfig.TwoCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->TwoCoreRatioLimit; + FspsUpd->FspsTestConfig.ThreeCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->ThreeCoreRatioLimit; + FspsUpd->FspsTestConfig.FourCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->FourCoreRatioLimit; + FspsUpd->FspsTestConfig.FiveCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->FiveCoreRatioLimit; + FspsUpd->FspsTestConfig.SixCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->SixCoreRatioLimit; + FspsUpd->FspsTestConfig.SevenCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->SevenCoreRatioLimit; + FspsUpd->FspsTestConfig.EightCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->EightCoreRatioLimit; + FspsUpd->FspsTestConfig.Hwp =3D (UINT8) CpuPowerM= gmtBasicConfig->Hwp; + FspsUpd->FspsTestConfig.HdcControl =3D (UINT8) CpuPowerM= gmtBasicConfig->HdcControl; + FspsUpd->FspsTestConfig.PowerLimit1Time =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit1Time; + FspsUpd->FspsTestConfig.PowerLimit2 =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit2; + FspsUpd->FspsTestConfig.TurboPowerLimitLock =3D (UINT8) CpuPowerM= gmtBasicConfig->TurboPowerLimitLock; + FspsUpd->FspsTestConfig.PowerLimit3Time =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit3Time; + FspsUpd->FspsTestConfig.PowerLimit3DutyCycle =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit3DutyCycle; + FspsUpd->FspsTestConfig.PowerLimit3Lock =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit3Lock; + FspsUpd->FspsTestConfig.PowerLimit4Lock =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit4Lock; + FspsUpd->FspsTestConfig.TccActivationOffset =3D (UINT8) CpuPowerM= gmtBasicConfig->TccActivationOffset; + FspsUpd->FspsTestConfig.TccOffsetClamp =3D (UINT8) CpuPowerM= gmtBasicConfig->TccOffsetClamp; + FspsUpd->FspsTestConfig.TccOffsetLock =3D (UINT8) CpuPowerM= gmtBasicConfig->TccOffsetLock; + FspsUpd->FspsTestConfig.PowerLimit1 =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit1 * 125); + FspsUpd->FspsTestConfig.PowerLimit2Power =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit2Power * 125); + FspsUpd->FspsTestConfig.PowerLimit3 =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit3 * 125); + FspsUpd->FspsTestConfig.PowerLimit4 =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit4 * 125); + FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl =3D (UINT32) CpuPower= MgmtBasicConfig->TccOffsetTimeWindowForRatl; + FspsUpd->FspsTestConfig.HwpInterruptControl =3D (UINT8) CpuPowerM= gmtBasicConfig->HwpInterruptControl; + FspsUpd->FspsTestConfig.EnableItbm =3D (UINT8) CpuPowerM= gmtBasicConfig->EnableItbm; + FspsUpd->FspsTestConfig.EnableItbmDriver =3D (UINT8) CpuPowerM= gmtBasicConfig->EnableItbmDriver; + FspsUpd->FspsTestConfig.MinRingRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->MinRingRatioLimit; + FspsUpd->FspsTestConfig.MaxRingRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->MaxRingRatioLimit; + FspsUpd->FspsTestConfig.NumberOfEntries =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.NumberOfEntries; + FspsUpd->FspsTestConfig.Custom1PowerLimit1Time =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom2PowerLimit1Time =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom3PowerLimit1Time =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom1TurboActivationRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.Custom2TurboActivationRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.Custom3TurboActivationRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.ConfigTdpLock =3D (UINT8) CpuPower= MgmtCustomConfig->ConfigTdpLock; + FspsUpd->FspsTestConfig.ConfigTdpBios =3D (UINT8) CpuPower= MgmtCustomConfig->ConfigTdpBios; + FspsUpd->FspsTestConfig.MaxRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.MaxRatio; + for (Index =3D 0; Index < CpuPowerMgmtCustomConfig->CustomRatioTable.Num= berOfEntries; Index++) { + FspsUpd->FspsTestConfig.StateRatio[Index] =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.StateRatio[Index]; + } + for (Index =3D 0; Index < MAX_16_CUSTOM_RATIO_TABLE_ENTRIES; Index++) { + FspsUpd->FspsTestConfig.StateRatioMax16[Index] =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.StateRatioMax16[Index]; + } + FspsUpd->FspsTestConfig.Custom1PowerLimit1 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom1PowerLimit2 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit2 * 125); + FspsUpd->FspsTestConfig.Custom2PowerLimit1 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom2PowerLimit2 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit2 * 125); + FspsUpd->FspsTestConfig.Custom3PowerLimit1 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom3PowerLimit2 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit2 * 125); + + FspsUpd->FspsTestConfig.Eist =3D (UINT8) CpuPow= erMgmtTestConfig->Eist; + FspsUpd->FspsTestConfig.EnergyEfficientPState =3D (UINT8) CpuPow= erMgmtTestConfig->EnergyEfficientPState; + FspsUpd->FspsTestConfig.EnergyEfficientTurbo =3D (UINT8) CpuPow= erMgmtTestConfig->EnergyEfficientTurbo; + FspsUpd->FspsTestConfig.TStates =3D (UINT8) CpuPow= erMgmtTestConfig->TStates; + FspsUpd->FspsTestConfig.BiProcHot =3D (UINT8) CpuPow= erMgmtTestConfig->BiProcHot; + FspsUpd->FspsTestConfig.DisableProcHotOut =3D (UINT8) CpuPow= erMgmtTestConfig->DisableProcHotOut; + FspsUpd->FspsTestConfig.ProcHotResponse =3D (UINT8) CpuPow= erMgmtTestConfig->ProcHotResponse; + FspsUpd->FspsTestConfig.DisableVrThermalAlert =3D (UINT8) CpuPow= erMgmtTestConfig->DisableVrThermalAlert; + FspsUpd->FspsTestConfig.AutoThermalReporting =3D (UINT8) CpuPow= erMgmtTestConfig->AutoThermalReporting; + FspsUpd->FspsTestConfig.ThermalMonitor =3D (UINT8) CpuPow= erMgmtTestConfig->ThermalMonitor; + FspsUpd->FspsTestConfig.Cx =3D (UINT8) CpuPow= erMgmtTestConfig->Cx; + FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock =3D (UINT8) CpuPow= erMgmtTestConfig->PmgCstCfgCtrlLock; + FspsUpd->FspsTestConfig.C1e =3D (UINT8) CpuPow= erMgmtTestConfig->C1e; + FspsUpd->FspsTestConfig.C1StateAutoDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C1AutoDemotion; + FspsUpd->FspsTestConfig.C1StateUnDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C1UnDemotion; + FspsUpd->FspsTestConfig.C3StateAutoDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C3AutoDemotion; + FspsUpd->FspsTestConfig.C3StateUnDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C3UnDemotion; + FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl0TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl0Irtl; + FspsUpd->FspsTestConfig.PkgCStateDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->PkgCStateDemotion; + FspsUpd->FspsTestConfig.PkgCStateUnDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->PkgCStateUnDemotion; + FspsUpd->FspsTestConfig.CStatePreWake =3D (UINT8) CpuPow= erMgmtTestConfig->CStatePreWake; + FspsUpd->FspsTestConfig.TimedMwait =3D (UINT8) CpuPow= erMgmtTestConfig->TimedMwait; + FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection =3D (UINT8) CpuPow= erMgmtTestConfig->CstCfgCtrIoMwaitRedirection; + FspsUpd->FspsTestConfig.PkgCStateLimit =3D (UINT8) CpuPow= erMgmtTestConfig->PkgCStateLimit; + FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl1TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl2TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl3TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl4TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl5TimeUnit; + FspsUpd->FspsTestConfig.PpmIrmSetting =3D (UINT8) CpuPow= erMgmtTestConfig->PpmIrmSetting; + FspsUpd->FspsTestConfig.ProcHotLock =3D (UINT8) CpuPow= erMgmtTestConfig->ProcHotLock; + FspsUpd->FspsTestConfig.RaceToHalt =3D (UINT8) CpuPow= erMgmtTestConfig->RaceToHalt; + FspsUpd->FspsTestConfig.ConfigTdpLevel =3D (UINT8) CpuPow= erMgmtTestConfig->ConfigTdpLevel; + FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl1Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl2Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl3Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl4Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl5Irtl; + + // + // Get BIST information from Sec Platform Information + // + SecPlatformInformation2 =3D GetSecPlatformInformation2 (PeiServices); + if (SecPlatformInformation2 =3D=3D NULL) { + SecPlatformInformation2 =3D GetSecPlatformInformationInfoInFormat2 (Pe= iServices); + } + + ASSERT (SecPlatformInformation2 !=3D NULL); + + if (SecPlatformInformation2 !=3D NULL) { + FspsUpd->FspsConfig.CpuBistData =3D (UINT32)SecPlatformInformation2; + DEBUG((DEBUG_INFO, "SecPlatformInformation NumberOfCpus - %x\n", SecPl= atformInformation2->NumberOfCpus)); + DEBUG ((DEBUG_INFO, "SecPlatformInformation BIST - %x\n", SecPlatformI= nformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32)); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspMePolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c new file mode 100644 index 0000000000..97d9842aff --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspMePolicyInitLib.c @@ -0,0 +1,121 @@ +/** @file + Implementation of Fsp Me Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Performs FSP ME PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n")); + + // + // Locate gSiPreMemPolicyPpi + // + SiPreMemPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gMePeiPreMemConfigG= uid, (VOID *) &MePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + FspmUpd->FspmConfig.HeciTimeouts =3D (UINT8) MePei= PreMemConfig->HeciTimeouts; + // + // Test policies + // + FspmUpd->FspmTestConfig.DidInitStat =3D (UINT8) MePeiP= reMemConfig->DidInitStat; + FspmUpd->FspmTestConfig.DisableCpuReplacedPolling =3D (UINT8) MePeiP= reMemConfig->DisableCpuReplacedPolling; + FspmUpd->FspmTestConfig.SendDidMsg =3D (UINT8) MePeiP= reMemConfig->SendDidMsg; + FspmUpd->FspmTestConfig.DisableHeciRetry =3D (UINT8) MePeiP= reMemConfig->DisableHeciRetry; + FspmUpd->FspmTestConfig.DisableMessageCheck =3D (UINT8) MePeiP= reMemConfig->DisableMessageCheck; + FspmUpd->FspmTestConfig.SkipMbpHob =3D (UINT8) MePeiP= reMemConfig->SkipMbpHob; + + FspmUpd->FspmTestConfig.HeciCommunication2 =3D (UINT8) MePeiP= reMemConfig->HeciCommunication2; + FspmUpd->FspmTestConfig.KtDeviceEnable =3D (UINT8) MePeiP= reMemConfig->KtDeviceEnable; + + FspmUpd->FspmConfig.Heci1BarAddress =3D MePeiPreMemCon= fig->Heci1BarAddress; + FspmUpd->FspmConfig.Heci2BarAddress =3D MePeiPreMemCon= fig->Heci2BarAddress; + FspmUpd->FspmConfig.Heci3BarAddress =3D MePeiPreMemCon= fig->Heci3BarAddress; + + return EFI_SUCCESS; +} + +/** + Performs FSP ME PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n")); + // + // Locate gSiPolicyPpiGuid + // + SiPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI= D *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + + FspsUpd->FspsConfig.Heci3Enabled =3D (UINT8) MePeiConfi= g->Heci3Enabled; + FspsUpd->FspsConfig.MeUnconfigOnRtcClear =3D (UINT8) MePeiConfi= g->MeUnconfigOnRtcClear; + + // + // Test policies + // + FspsUpd->FspsTestConfig.MctpBroadcastCycle =3D (UINT8) MePeiConfi= g->MctpBroadcastCycle; + FspsUpd->FspsTestConfig.EndOfPostMessage =3D (UINT8) MePeiConfi= g->EndOfPostMessage; + FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci =3D (UINT8) MePeiConfi= g->DisableD0I3SettingForHeci; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspMiscUpdInitLib.c b/Platform/Intel/WhiskeylakeOpenBoar= dPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c new file mode 100644 index 0000000000..9545e3df0b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspMiscUpdInitLib.c @@ -0,0 +1,77 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#define STATUS_CODE_USE_RAM BIT0 +#define STATUS_CODE_USE_ISA_SERIAL BIT1 +#define STATUS_CODE_USE_USB BIT2 +#define STATUS_CODE_USE_USB3 BIT3 +#define STATUS_CODE_USE_SERIALIO BIT4 +#define STATUS_CODE_USE_TRACEHUB BIT5 +#define STATUS_CODE_CMOS_INVALID BIT6 +#define STATUS_CODE_CMOS_VALID BIT7 +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + DEBUG_CONFIG_DATA_HOB *DebugConfigData; + UINT8 DebugInterfaces; + + FspmUpd->FspmArchUpd.StackBase =3D (VOID *)(UINTN)(PcdGet32(PcdTemporary= RamBase) + PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize= ) + PcdGet32(PcdFspReservedBufferSize))); + FspmUpd->FspmArchUpd.StackSize =3D PcdGet32(PcdFspTemporaryRamSize); + + Status =3D PeiServicesGetBootMode (&(FspmUpd->FspmArchUpd.BootMode)); + if (EFI_ERROR (Status)) { + FspmUpd->FspmArchUpd.BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + } + + FspmUpd->FspmArchUpd.BootLoaderTolumSize =3D 0x0; + + // + // Initialize DebugConfigData + // + DebugInterfaces =3D 0x00; + Hob.Guid =3D GetFirstGuidHob (&gDebugConfigHobGuid); + if (Hob.Guid !=3D NULL) { + DebugConfigData =3D (DEBUG_CONFIG_DATA_HOB *) GET_GUID_HOB_DATA (Hob.G= uid); + if (DebugConfigData !=3D NULL) { + // Debug Interfaces + if (DebugConfigData->RamDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_RAM; } + if (DebugConfigData->UartDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_ISA_SERIAL; } + if (DebugConfigData->Usb3DebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_USB3; } + if (DebugConfigData->SerialIoDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_SERIALIO; } + if (DebugConfigData->TraceHubDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_TRACEHUB; } + FspmUpd->FspmConfig.PcdDebugInterfaceFlags =3D DebugInterfaces; + // Serial debug message baud rate + FspmUpd->FspmConfig.PcdSerialDebugBaudRate =3D DebugConfigData->Ser= ialDebugBaudRate; + //Serial debug message level + FspmUpd->FspmConfig.PcdSerialDebugLevel =3D DebugConfigData->Ser= ialDebug; + } + } + DEBUG ((DEBUG_INFO, "FspmConfig.PcdDebugInterfaceFlags is 0x%X\n", FspmU= pd->FspmConfig.PcdDebugInterfaceFlags)); + DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugBaudRate is 0x%X\= n", FspmUpd->FspmConfig.PcdSerialDebugBaudRate)); + DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugLevel is 0x%X\n",= FspmUpd->FspmConfig.PcdSerialDebugLevel)); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPchPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c new file mode 100644 index 0000000000..e2022929cd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPchPolicyInitLib.c @@ -0,0 +1,736 @@ +/** @file + Implementation of Fsp PCH Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN MaxPcieRootPorts; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig; + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n")); + DEBUG((DEBUG_INFO | DEBUG_INIT, "FspmUpd =3D 0x%x\n", FspmUpd)); + // + // Locate PchPreMemPolicyPpi + // + SiPreMemPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemC= onfigGuid, (VOID *) &PchTraceHubPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigG= uid, (VOID *) &SmbusPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGui= d, (VOID *) &DciPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConf= igGuid, (VOID *) &HsioPciePreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConf= igGuid, (VOID *) &HsioSataPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGui= d, (VOID *) &LpcPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemCo= nfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConf= igGuid, (VOID *) &WdtPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig= Guid, (VOID *) &PcieRpPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfi= gGuid, (VOID *) &HdaPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGui= d, (VOID *) &IshPreMemConfig); + ASSERT_EFI_ERROR (Status); + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ UpdatePeiPchPolicyPreMem\n")); + // + // Update PCIE RP policies + // +// MaxPcieRootPorts =3D 16; + + MaxPcieRootPorts =3D GetPchMaxPciePortNum (); +// MaxPcieRootPorts =3D 16; + FspmUpd->FspmConfig.PcieRpEnableMask =3D PcieRpPreMemConfig->RpEnabledMa= sk & ((1 << MaxPcieRootPorts) - 1); + FspmUpd->FspmConfig.PcieImrEnabled =3D PcieRpPreMemConfig->PcieImrEnable= d; + FspmUpd->FspmConfig.PcieImrSize =3D PcieRpPreMemConfig->PcieImrSize; + FspmUpd->FspmConfig.ImrRpSelection =3D PcieRpPreMemConfig->ImrRpSelectio= n; + // + // Update TraceHub policies + // + FspmUpd->FspmConfig.PchTraceHubMode =3D (UINT8) PchTraceHubPreMemConfig-= >EnableMode; + FspmUpd->FspmConfig.PchTraceHubMemReg0Size =3D (UINT8) PchTraceHubPreMem= Config->MemReg0Size; + FspmUpd->FspmConfig.PchTraceHubMemReg1Size =3D (UINT8) PchTraceHubPreMem= Config->MemReg1Size; + + // + // Update Smbus policies + // + FspmUpd->FspmConfig.SmbusEnable =3D (UINT8)SmbusPreMemConfig->Enable; + FspmUpd->FspmConfig.SmbusArpEnable =3D (UINT8)SmbusPreMemConfig->ArpEnab= le; + FspmUpd->FspmTestConfig.SmbusDynamicPowerGating =3D (UINT8)SmbusPreMemCo= nfig->DynamicPowerGating; + FspmUpd->FspmTestConfig.SmbusSpdWriteDisable =3D (UINT8)SmbusPreMemConfi= g->SpdWriteDisable; + FspmUpd->FspmConfig.PchSmbAlertEnable =3D (UINT8)SmbusPreMemConfig->SmbA= lertEnable; + FspmUpd->FspmConfig.PchSmbusIoBase =3D (UINT16)SmbusPreMemConfig->SmbusI= oBase; + FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses =3D (UINT8)SmbusPreMemConfi= g->NumRsvdSmbusAddresses; + FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr =3D (UINT32)SmbusPreMemConf= ig->RsvdSmbusAddressTable; + + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ1 UpdatePeiPchPolicyPreMem\n")); + // + // Update Dci policies + // + FspmUpd->FspmConfig.PlatformDebugConsent =3D (UINT8)DciPreMemConfig->Pla= tformDebugConsent; + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ11 UpdatePeiPchPolicyPreMem\n")); + FspmUpd->FspmConfig.DciUsb3TypecUfpDbg =3D (UINT8)DciPreMemConfig->DciUs= b3TypecUfpDbg; + // + // Update HSIO PCIE policies + // + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0; + } + + // + // Update HSIO SATA policies + // + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index ++) { + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph; + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph; + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph; + } + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ2 UpdatePeiPchPolicyPreMem\n")); + // Update LPC policies + // + FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding =3D (UINT8)LpcPreMemCon= fig->EnhancePort8xhDecoding; + + // + // Update Pch General Premem policies + // + FspmUpd->FspmConfig.PchPort80Route =3D (UINT8)PchGeneralPreMemConfig->Po= rt80Route; + + // + // Update Wdt policies + // + FspmUpd->FspmTestConfig.WdtDisableAndLock =3D (UINT8)WdtPreMemConfig->Di= sableAndLock; + + // + // HdAudioConfig + // + FspmUpd->FspmConfig.PchHdaEnable =3D (UINT8)HdaPreMemConfig->Enable; + + // + // IshConfig + // + FspmUpd->FspmConfig.PchIshEnable =3D (UINT8)IshPreMemConfig->Enable; + + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ3 UpdatePeiPchPolicyPreMem\n")); + return EFI_SUCCESS; +} + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN MaxPcieRootPorts; + UINT8 Data8; + SI_POLICY_PPI *SiPolicy; + PCH_LAN_CONFIG *LanConfig; + PCH_HDAUDIO_CONFIG *HdAudioConfig; + PCH_SCS_CONFIG *ScsConfig; + PCH_ISH_CONFIG *IshConfig; + PCH_SATA_CONFIG *SataConfig; + USB_CONFIG *UsbConfig; + PCH_SERIAL_IO_CONFIG *SerialIoConfig; + PCH_INTERRUPT_CONFIG *InterruptConfig; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_CNVI_CONFIG *CnviConfig; + PCH_HSIO_CONFIG *HsioConfig; + PCH_ESPI_CONFIG *EspiConfig; + PCH_PCIE_CONFIG *PcieRpConfig; + PCH_DMI_CONFIG *DmiConfig; + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_P2SB_CONFIG *P2sbConfig; + PCH_GENERAL_CONFIG *PchGeneralConfig; + PCH_PM_CONFIG *PmConfig; + PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig; + PCH_THERMAL_CONFIG *PchThermalConfig; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n")); + // + // Locate SiPolicyPpi + // + SiPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) = &LanConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID= *) &HdAudioConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) = &ScsConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) = &IshConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)= &SataConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) = &UsbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI= D *) &SerialIoConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VO= ID *) &InterruptConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOI= D *) &LockDownConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID = *) &PcieRpConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) = &DmiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGui= d, (VOID *) &FlashProtectionConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID = *) &IoApicConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *)= &P2sbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (V= OID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &= PmConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VO= ID *) &PchSerialIrqConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID= *) &PchThermalConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *)= &CnviConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHsioConfigGuid, (VOID *)= &HsioConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *)= &EspiConfig); + ASSERT_EFI_ERROR (Status); + + // + // Update LAN policies + // + FspsUpd->FspsConfig.PchLanEnable =3D (UINT8)LanConfig->Enable; + FspsUpd->FspsConfig.PchLanLtrEnable =3D (UINT8)LanConfig->LtrEnabl= e; + + // + // Update HDA policies + // + FspsUpd->FspsConfig.PchHdaDspEnable =3D (UINT8)HdAudioConfig= ->DspEnable; + FspsUpd->FspsConfig.PchHdaPme =3D (UINT8)HdAudioConfig= ->Pme; + FspsUpd->FspsConfig.PchHdaVcType =3D (UINT8)HdAudioConfig= ->VcType; + FspsUpd->FspsConfig.PchHdaLinkFrequency =3D (UINT8)HdAudioConfig= ->HdAudioLinkFrequency; + FspsUpd->FspsConfig.PchHdaIDispLinkFrequency =3D (UINT8)HdAudioConfig= ->IDispLinkFrequency; + FspsUpd->FspsConfig.PchHdaIDispLinkTmode =3D (UINT8)HdAudioConfig= ->IDispLinkTmode; + FspsUpd->FspsConfig.PchHdaDspUaaCompliance =3D (UINT8)HdAudioConfig= ->DspUaaCompliance; + FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect =3D (UINT8)HdAudioConfig= ->IDispCodecDisconnect; + FspsUpd->FspsConfig.PchHdaCodecSxWakeCapability =3D (UINT8)HdAudioConfig= ->CodecSxWakeCapability; + FspsUpd->FspsTestConfig.PchHdaResetWaitTimer =3D (UINT16)HdAudioConfi= g->ResetWaitTimer; + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum =3D HdAudioConfig->VerbT= ableEntryNum; + FspsUpd->FspsConfig.PchHdaVerbTablePtr =3D HdAudioConfig->VerbT= ablePtr; + FspsUpd->FspsConfig.PchHdaAudioLinkHda =3D (UINT8)HdAudioConfig= ->AudioLinkHda; + FspsUpd->FspsConfig.PchHdaAudioLinkDmic0 =3D (UINT8)HdAudioConfig= ->AudioLinkDmic0; + FspsUpd->FspsConfig.PchHdaAudioLinkDmic1 =3D (UINT8)HdAudioConfig= ->AudioLinkDmic1; + FspsUpd->FspsConfig.PchHdaAudioLinkSsp0 =3D (UINT8)HdAudioConfig= ->AudioLinkSsp0; + FspsUpd->FspsConfig.PchHdaAudioLinkSsp1 =3D (UINT8)HdAudioConfig= ->AudioLinkSsp1; + FspsUpd->FspsConfig.PchHdaAudioLinkSsp2 =3D (UINT8)HdAudioConfig= ->AudioLinkSsp2; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw1 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw1; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw2 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw2; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw3 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw3; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw4 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw4; + FspsUpd->FspsConfig.PchHdaSndwBufferRcomp =3D (UINT8)HdAudioConfig= ->SndwBufferRcomp; + + // + // Update SCS policies + // + FspsUpd->FspsConfig.ScsEmmcEnabled =3D (UINT8)ScsConfig->ScsEmmcEnabled; + FspsUpd->FspsConfig.ScsEmmcHs400Enabled =3D (UINT8)ScsConfig->ScsEmmcHs4= 00Enabled; + FspsUpd->FspsConfig.ScsSdCardEnabled =3D (UINT8)ScsConfig->ScsSdcardEnab= led; + FspsUpd->FspsConfig.SdCardPowerEnableActiveHigh =3D (UINT8)ScsConfig->Sd= CardPowerEnableActiveHigh; +#ifdef CFL_SIMICS + FspsUpd->FspsConfig.ScsUfsEnabled =3D 0; +#else + FspsUpd->FspsConfig.ScsUfsEnabled =3D (UINT8)ScsConfig->ScsUfsEnabled= ; +#endif + FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired =3D (UINT8)ScsConfig->= ScsEmmcHs400TuningRequired; + FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid =3D (UINT8)ScsConfig->= ScsEmmcHs400DllDataValid; + FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 =3D (UINT8)ScsConfig->= ScsEmmcHs400RxStrobeDll1; + FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll =3D (UINT8)ScsConfig->= ScsEmmcHs400TxDataDll; + FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength =3D (UINT8)ScsConfig->= ScsEmmcHs400DriverStrength; + + // + // Update ISH policies + // + FspsUpd->FspsConfig.PchIshSpiGpioAssign =3D (UINT8)IshConfig->SpiGpioA= ssign; + FspsUpd->FspsConfig.PchIshUart0GpioAssign =3D (UINT8)IshConfig->Uart0Gpi= oAssign; + FspsUpd->FspsConfig.PchIshUart1GpioAssign =3D (UINT8)IshConfig->Uart1Gpi= oAssign; + FspsUpd->FspsConfig.PchIshI2c0GpioAssign =3D (UINT8)IshConfig->I2c0Gpio= Assign; + FspsUpd->FspsConfig.PchIshI2c1GpioAssign =3D (UINT8)IshConfig->I2c1Gpio= Assign; + FspsUpd->FspsConfig.PchIshI2c2GpioAssign =3D (UINT8)IshConfig->I2c2Gpio= Assign; + FspsUpd->FspsConfig.PchIshGp0GpioAssign =3D (UINT8)IshConfig->Gp0GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp1GpioAssign =3D (UINT8)IshConfig->Gp1GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp2GpioAssign =3D (UINT8)IshConfig->Gp2GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp3GpioAssign =3D (UINT8)IshConfig->Gp3GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp4GpioAssign =3D (UINT8)IshConfig->Gp4GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp5GpioAssign =3D (UINT8)IshConfig->Gp5GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp6GpioAssign =3D (UINT8)IshConfig->Gp6GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp7GpioAssign =3D (UINT8)IshConfig->Gp7GpioA= ssign; + FspsUpd->FspsConfig.PchIshPdtUnlock =3D (UINT8)IshConfig->PdtUnloc= k; + + // + // Update PCIE RP RootPort policies + // + MaxPcieRootPorts =3D GetPchMaxPciePortNum (); + FspsUpd->FspsConfig.PcieRpDpcMask =3D 0; + FspsUpd->FspsConfig.PcieRpDpcExtensionsMask =3D 0; + FspsUpd->FspsConfig.PcieRpPtmMask =3D 0; + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { + FspsUpd->FspsConfig.PcieRpHotPlug[Index] =3D (UINT8)PcieRpConfig->Root= Port[Index].HotPlug; + FspsUpd->FspsConfig.PcieRpSlotImplemented[Index] =3D (UINT8)PcieRpConf= ig->RootPort[Index].SlotImplemented; + FspsUpd->FspsConfig.PcieRpPmSci[Index] =3D (UINT8)PcieRpConfig->RootPo= rt[Index].PmSci; + FspsUpd->FspsConfig.PcieRpExtSync[Index] =3D (UINT8)PcieRpConfig->Root= Port[Index].ExtSync; + FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] =3D (UINT8)PcieR= pConfig->RootPort[Index].TransmitterHalfSwing; + FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] =3D (UINT8)PcieRpConfig-= >RootPort[Index].ClkReqDetect; + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] =3D (UINT8)Pci= eRpConfig->RootPort[Index].AdvancedErrorReporting; + FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] =3D (UINT8)P= cieRpConfig->RootPort[Index].UnsupportedRequestReport; + FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] =3D (UINT8)PcieRpCon= fig->RootPort[Index].FatalErrorReport; + FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] =3D (UINT8)PcieRpC= onfig->RootPort[Index].NoFatalErrorReport; + FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] =3D (UINT8)Pci= eRpConfig->RootPort[Index].CorrectableErrorReport; + FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] =3D (UINT8)Pc= ieRpConfig->RootPort[Index].SystemErrorOnFatalError; + FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] =3D (UINT8= )PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError; + FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] =3D (UI= NT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError; + FspsUpd->FspsConfig.PcieRpMaxPayload[Index] =3D (UINT8)PcieRpConfig->R= ootPort[Index].MaxPayload; + if (PcieRpConfig->RootPort[Index].DpcEnabled) { + FspsUpd->FspsConfig.PcieRpDpcMask |=3D (BIT0<RootPort[Index].RpDpcExtensionsEnabled) { + FspsUpd->FspsConfig.PcieRpDpcExtensionsMask |=3D (BIT0<RootPort[Index].PtmEnabled) { + FspsUpd->FspsConfig.PcieRpPtmMask |=3D (BIT0<FspsConfig.PcieRpPcieSpeed[Index] =3D (UINT8)PcieRpConfig->Ro= otPort[Index].PcieSpeed; + FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] =3D (UINT8)PcieRpConf= ig->RootPort[Index].Gen3EqPh3Method; + FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] =3D (UINT8)PcieRpC= onfig->RootPort[Index].PhysicalSlotNumber; + FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] =3D (UINT8)PcieRpCo= nfig->RootPort[Index].CompletionTimeout; + FspsUpd->FspsConfig.PcieRpAspm[Index] =3D (UINT8)PcieRpConfig->RootPor= t[Index].Aspm; + FspsUpd->FspsConfig.PcieRpL1Substates[Index] =3D (UINT8)PcieRpConfig->= RootPort[Index].L1Substates; + FspsUpd->FspsConfig.PcieRpLtrEnable[Index] =3D (UINT8)PcieRpConfig->Ro= otPort[Index].LtrEnable; + FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] =3D (UINT8)PcieRpConfig= ->RootPort[Index].LtrConfigLock; + FspsUpd->FspsConfig.PcieRpAcsEnabled[Index] =3D (UINT8)PcieRpConfig->R= ootPort[Index].AcsEnabled; + FspsUpd->FspsConfig.PcieRpDetectTimeoutMs[Index] =3D (UINT16)PcieRpCon= fig->RootPort[Index].DetectTimeoutMs; + FspsUpd->FspsConfig.PcieRootPortGen2PllL1CgDisable[Index] =3D (UINT8)P= cieRpConfig->RootPort[Index].PcieRootPortGen2PllL1CgDisable; + + FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] =3D (UINT16)Pc= ieRpConfig->RootPort[Index].LtrMaxSnoopLatency; + FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] =3D (UINT16)= PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency; + + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] =3D (UIN= T8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode; + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] = =3D (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier; + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] =3D (UI= NT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue; + + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] =3D (= UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode; + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index]= =3D (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier= ; + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] =3D = (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue; + + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] =3D (UINT8)Pc= ieRpConfig->RootPort[Index].SlotPowerLimitScale; + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] =3D (UINT16)P= cieRpConfig->RootPort[Index].SlotPowerLimitValue; + FspsUpd->FspsTestConfig.PcieRpUptp[Index] =3D (UINT8)PcieRpConfig->Roo= tPort[Index].Uptp; + FspsUpd->FspsTestConfig.PcieRpDptp[Index] =3D (UINT8)PcieRpConfig->Roo= tPort[Index].Dptp; + + } + for (Index =3D 0; Index < GetPchMaxPcieClockNum (); Index ++) { + FspsUpd->FspsConfig.PcieClkSrcUsage[Index] =3D PcieRpConfig->PcieClock= [Index].Usage; + FspsUpd->FspsConfig.PcieClkSrcClkReq[Index] =3D PcieRpConfig->PcieCloc= k[Index].ClkReq; + } + + // + // Update PCIE RP EqPh3LaneParam policies + // + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { + FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] =3D (UINT8)PcieRpConfi= g->EqPh3LaneParam[Index].Cm; + FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] =3D (UINT8)PcieRpConfi= g->EqPh3LaneParam[Index].Cp; + } + + // + // Update PCIE RP SwEqCoeffList policies + // + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) { + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] =3D (UINT8)PcieRpConfig= ->SwEqCoeffList[Index].Cm; + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] =3D (UINT8)PcieRpConfig= ->SwEqCoeffList[Index].Cp; + } + + // + // Update PCIE RP policies + // + FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode =3D (UINT8)PcieRp= Config->EnablePort8xhDecode; + FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex =3D (UINT8)PcieRp= Config->PchPciePort8xhDecodePortIndex; + FspsUpd->FspsConfig.PcieDisableRootPortClockGating =3D (UINT8)PcieRpConf= ig->DisableRootPortClockGating; + FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite =3D (UINT8)PcieRpConf= ig->EnablePeerMemoryWrite; + FspsUpd->FspsConfig.PcieComplianceTestMode =3D (UINT8)PcieRpConf= ig->ComplianceTestMode; + FspsUpd->FspsConfig.PcieRpFunctionSwap =3D (UINT8)PcieRpConf= ig->RpFunctionSwap; + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D PcieRpConfig->Pci= eDeviceOverrideTablePtr; + + // + // Update Sata Policies + // + FspsUpd->FspsConfig.SataEnable =3D (UINT8)SataConfig= ->Enable; + FspsUpd->FspsTestConfig.SataTestMode =3D (UINT8)SataConfig= ->TestMode; + FspsUpd->FspsConfig.SataSalpSupport =3D (UINT8)SataConfig= ->SalpSupport; + FspsUpd->FspsConfig.SataPwrOptEnable =3D (UINT8)SataConfig->PwrOptEnable= ; + FspsUpd->FspsConfig.EsataSpeedLimit =3D (UINT8)SataConfig->EsataSpeedLi= mit; + FspsUpd->FspsConfig.SataLedEnable =3D (UINT8)SataConfig->LedEnable; + FspsUpd->FspsConfig.SataMode =3D (UINT8)SataConfig->SataMode; + FspsUpd->FspsConfig.SataSpeedLimit =3D (UINT8)SataConfig->SpeedLimit; + + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index++) { + FspsUpd->FspsConfig.SataPortsEnable[Index] =3D (UINT8)SataConfig->Port= Settings[Index].Enable; + FspsUpd->FspsConfig.SataPortsHotPlug[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].HotPlug; + FspsUpd->FspsConfig.SataPortsInterlockSw[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].InterlockSw; + FspsUpd->FspsConfig.SataPortsExternal[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].External; + FspsUpd->FspsConfig.SataPortsSpinUp[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].SpinUp; + FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] =3D (UINT8)SataCo= nfig->PortSettings[Index].SolidStateDrive; + FspsUpd->FspsConfig.SataPortsDevSlp[Index] =3D (UINT8)SataConfig->Port= Settings[Index].DevSlp; + FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] =3D (UINT8)SataCo= nfig->PortSettings[Index].EnableDitoConfig; + FspsUpd->FspsConfig.SataPortsDmVal[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].DmVal; + FspsUpd->FspsConfig.SataPortsDitoVal[Index] =3D (UINT16)SataConfig= ->PortSettings[Index].DitoVal; + FspsUpd->FspsConfig.SataPortsZpOdd[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].ZpOdd; + } + + FspsUpd->FspsConfig.SataRstRaidDeviceId =3D (UINT8)SataConfig= ->Rst.RaidDeviceId; + FspsUpd->FspsConfig.SataRstInterrupt =3D (UINT8)SataConfig= ->Rst.SataRstInterrupt; + FspsUpd->FspsConfig.SataRstRaid0 =3D (UINT8)SataConfig= ->Rst.Raid0; + FspsUpd->FspsConfig.SataRstRaid1 =3D (UINT8)SataConfig= ->Rst.Raid1; + FspsUpd->FspsConfig.SataRstRaid10 =3D (UINT8)SataConfig= ->Rst.Raid10; + FspsUpd->FspsConfig.SataRstRaid5 =3D (UINT8)SataConfig= ->Rst.Raid5; + FspsUpd->FspsConfig.SataRstIrrt =3D (UINT8)SataConfig= ->Rst.Irrt; + FspsUpd->FspsConfig.SataRstOromUiBanner =3D (UINT8)SataConfig= ->Rst.OromUiBanner; + FspsUpd->FspsConfig.SataRstOromUiDelay =3D (UINT8)SataConfig= ->Rst.OromUiDelay; + FspsUpd->FspsConfig.SataRstHddUnlock =3D (UINT8)SataConfig= ->Rst.HddUnlock; + FspsUpd->FspsConfig.SataRstLedLocate =3D (UINT8)SataConfig= ->Rst.LedLocate; + FspsUpd->FspsConfig.SataRstIrrtOnly =3D (UINT8)SataConfig= ->Rst.IrrtOnly; + FspsUpd->FspsConfig.SataRstSmartStorage =3D (UINT8)SataConfig= ->Rst.SmartStorage; + FspsUpd->FspsConfig.SataRstOptaneMemory =3D (UINT8)SataConfig= ->Rst.OptaneMemory; + FspsUpd->FspsConfig.SataRstLegacyOrom =3D (UINT8)SataConfig= ->Rst.LegacyOrom; + FspsUpd->FspsConfig.SataRstCpuAttachedStorage =3D (UINT8)SataConfig= ->Rst.CpuAttachedStorage; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + FspsUpd->FspsConfig.SataRstPcieEnable[Index] =3D (UINT8)Sata= Config->RstPcieStorageRemap[Index].Enable; + FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] =3D (UINT8)Sata= Config->RstPcieStorageRemap[Index].RstPcieStoragePort; + FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] =3D (UINT8)Sata= Config->RstPcieStorageRemap[Index].DeviceResetDelay; + } + + FspsUpd->FspsConfig.SataP0T1M =3D (UINT8)SataConfig->ThermalT= hrottling.P0T1M; + FspsUpd->FspsConfig.SataP0T2M =3D (UINT8)SataConfig->ThermalT= hrottling.P0T2M; + FspsUpd->FspsConfig.SataP0T3M =3D (UINT8)SataConfig->ThermalT= hrottling.P0T3M; + FspsUpd->FspsConfig.SataP0TDisp =3D (UINT8)SataConfig->ThermalT= hrottling.P0TDisp; + FspsUpd->FspsConfig.SataP1T1M =3D (UINT8)SataConfig->ThermalT= hrottling.P1T1M; + FspsUpd->FspsConfig.SataP1T2M =3D (UINT8)SataConfig->ThermalT= hrottling.P1T2M; + FspsUpd->FspsConfig.SataP1T3M =3D (UINT8)SataConfig->ThermalT= hrottling.P1T3M; + FspsUpd->FspsConfig.SataP1TDisp =3D (UINT8)SataConfig->ThermalT= hrottling.P1TDisp; + FspsUpd->FspsConfig.SataP0Tinact =3D (UINT8)SataConfig->ThermalT= hrottling.P0Tinact; + FspsUpd->FspsConfig.SataP0TDispFinit =3D (UINT8)SataConfig->ThermalT= hrottling.P0TDispFinit; + FspsUpd->FspsConfig.SataP1Tinact =3D (UINT8)SataConfig->ThermalT= hrottling.P1Tinact; + FspsUpd->FspsConfig.SataP1TDispFinit =3D (UINT8)SataConfig->ThermalT= hrottling.P1TDispFinit; + FspsUpd->FspsConfig.SataThermalSuggestedSetting =3D (UINT8)SataConfig->T= hermalThrottling.SuggestedSetting; + + // + // Update USB policies + // + FspsUpd->FspsConfig.PchEnableComplianceMode =3D (UINT8)UsbConf= ig->EnableComplianceMode; + FspsUpd->FspsConfig.UsbPdoProgramming =3D (UINT8)UsbConf= ig->PdoProgramming; + FspsUpd->FspsConfig.PchUsbOverCurrentEnable =3D (UINT8)UsbConf= ig->OverCurrentEnable; + FspsUpd->FspsConfig.PchUsb2PhySusPgEnable =3D (UINT8)UsbConf= ig->Usb2PhySusPgEnable; + FspsUpd->FspsTestConfig.PchXhciOcLock =3D (UINT8)UsbConf= ig->XhciOcLock; + for (Index =3D 0; Index < PCH_MAX_USB2_PORTS; Index++) { + FspsUpd->FspsConfig.PortUsb20Enable[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Enable; + FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] =3D (UINT8)UsbConfig->Po= rtUsb20[Index].OverCurrentPin; + FspsUpd->FspsConfig.Usb2AfePetxiset[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Petxiset; + FspsUpd->FspsConfig.Usb2AfeTxiset[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Txiset; + FspsUpd->FspsConfig.Usb2AfePredeemp[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Predeemp; + FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Pehalfbit; + } + for (Index =3D 0; Index < PCH_MAX_USB3_PORTS; Index++) { + FspsUpd->FspsConfig.PortUsb30Enable[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].Enable; + FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].OverCurrentPin; + FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDeEmphEnable; + FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDeEmph; + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDownscaleAmpEnable; + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDownscaleAmp; + + Data8 =3D 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfgEna= ble ? B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN : 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnable ? B_= XHCI_HSIO_FILTER_SELECT_N_EN : 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnable ? B_= XHCI_HSIO_FILTER_SELECT_P_EN : 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnResE= nable ? B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN : 0; + FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] =3D Data8; + + Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfg &= 0x1F) << N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG) | + ((UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnRes &= 0x7) << N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES); + FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] =3D Data8; + + Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN & 0x7) <<= N_XHCI_UPD_HSIO_FILTER_SELECT_N) | + ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP & 0x7) << N= _XHCI_UPD_HSIO_FILTER_SELECT_P); + FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] =3D Data8; + } + + FspsUpd->FspsConfig.XdciEnable =3D (UINT8)UsbConfig->XdciConfig.Enab= le; + + // + // Update SerialIo policies + // + for (Index =3D 0; Index < GetPchMaxSerialIoControllersNum (); Index++) { + FspsUpd->FspsConfig.SerialIoDevMode[Index] =3D SerialIoConfig->DevMode= [Index]; + } + for (Index =3D 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++= ) { + FspsUpd->FspsConfig.SerialIoSpiCsPolarity[Index] =3D SerialIoConfig->S= piCsPolarity[Index]; + } + for (Index =3D 0; Index < GetPchMaxSerialIoUartControllersNum (); Index+= +) { + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[Index] =3D SerialIoConfig->= UartHwFlowCtrl[Index]; + } + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++= ) { + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index] =3D SerialIoC= onfig->I2cPadsTermination[Index]; + } + + FspsUpd->FspsConfig.SerialIoDebugUartNumber =3D (UINT8)SerialIo= Config->DebugUartNumber; + FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost =3D (UINT8)SerialIo= Config->EnableDebugUartAfterPost; + FspsUpd->FspsConfig.SerialIoUart0PinMuxing =3D (UINT8)SerialIo= Config->Uart0PinMuxing; + + // + // Update Interrupt policies + // + FspsUpd->FspsConfig.DevIntConfigPtr =3D (UINT32)InterruptConfig->DevIntC= onfig; + FspsUpd->FspsConfig.NumOfDevIntConfig =3D InterruptConfig->NumOfDevIntCo= nfig; + for (Index =3D 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) { + FspsUpd->FspsConfig.PxRcConfig[Index] =3D (UINT8)InterruptConfig->PxRc= Config[Index]; + } + FspsUpd->FspsConfig.GpioIrqRoute =3D (UINT8)InterruptConfig->GpioIrqRout= e; + FspsUpd->FspsConfig.SciIrqSelect =3D (UINT8)InterruptConfig->SciIrqSelec= t; + FspsUpd->FspsConfig.TcoIrqSelect =3D (UINT8)InterruptConfig->TcoIrqSelec= t; + FspsUpd->FspsConfig.TcoIrqEnable =3D (UINT8)InterruptConfig->TcoIrqEnabl= e; + + // + // Update LockDown policies + // + FspsUpd->FspsTestConfig.PchLockDownGlobalSmi =3D (UINT8)LockDownConf= ig->GlobalSmi; + FspsUpd->FspsTestConfig.PchLockDownBiosInterface =3D (UINT8)LockDownConf= ig->BiosInterface; + FspsUpd->FspsConfig.PchLockDownBiosLock =3D (UINT8)LockDownConf= ig->BiosLock; + FspsUpd->FspsConfig.PchLockDownRtcMemoryLock =3D (UINT8)LockDownConf= ig->RtcMemoryLock; + FspsUpd->FspsTestConfig.PchUnlockGpioPads =3D (UINT8)LockDownConf= ig->UnlockGpioPads; + + // + // Update Dmi policies + // + FspsUpd->FspsConfig.PchPwrOptEnable =3D (UINT8)DmiConfig->PwrOptEnable; + FspsUpd->FspsConfig.PchDmiAspmCtrl =3D (UINT8)DmiConfig->DmiAspmCtrl; + + // + // Update Flash Protection policies + // + for (Index =3D 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) { + FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] =3D (UINT8)FlashPr= otectionConfig->ProtectRange[Index].WriteProtectionEnable; + FspsUpd->FspsConfig.PchReadProtectionEnable[Index] =3D (UINT8)FlashPr= otectionConfig->ProtectRange[Index].ReadProtectionEnable; + FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] =3D (UINT16)FlashPr= otectionConfig->ProtectRange[Index].ProtectedRangeLimit; + FspsUpd->FspsConfig.PchProtectedRangeBase[Index] =3D (UINT16)FlashPr= otectionConfig->ProtectRange[Index].ProtectedRangeBase; + } + + // + // Update IO Apic policies + // + FspsUpd->FspsConfig.PchIoApicEntry24_119 =3D (UINT8)IoApicConfig->= IoApicEntry24_119; + FspsUpd->FspsConfig.Enable8254ClockGating =3D (UINT8)IoApicConfig->= Enable8254ClockGating; + FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 =3D (UINT8)IoApicConfig->= Enable8254ClockGatingOnS3; + FspsUpd->FspsConfig.PchIoApicId =3D (UINT8)IoApicConfig->= IoApicId; + + // + // Update P2sb policies + // + FspsUpd->FspsTestConfig.PchSbAccessUnlock =3D (UINT8)P2sbConfig->SbAcce= ssUnlock; + + // + // Update Pch General policies + // + FspsUpd->FspsConfig.PchCrid =3D (UINT8)PchGeneralConfig->C= rid; + FspsUpd->FspsConfig.PchLegacyIoLowLatency =3D (UINT8)PchGeneralConfig->L= egacyIoLowLatency; + + // + // Update Pm policies + // + FspsUpd->FspsConfig.PchPmPmeB0S5Dis =3D (UINT8)PmConfig->WakeCon= fig.PmeB0S5Dis; + FspsUpd->FspsConfig.PchPmWolEnableOverride =3D (UINT8)PmConfig->WakeCon= fig.WolEnableOverride; + FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx =3D (UINT8)PmConfig->WakeCon= fig.PcieWakeFromDeepSx; + FspsUpd->FspsConfig.PchPmWoWlanEnable =3D (UINT8)PmConfig->WakeCon= fig.WoWlanEnable; + FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable =3D (UINT8)PmConfig->WakeCon= fig.WoWlanDeepSxEnable; + FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx =3D (UINT8)PmConfig->WakeCon= fig.LanWakeFromDeepSx; + + FspsUpd->FspsConfig.PchPmDeepSxPol =3D (UINT8)PmConfig->PchDeep= SxPol; + FspsUpd->FspsConfig.PchPmSlpS3MinAssert =3D (UINT8)PmConfig->PchSlpS= 3MinAssert; + FspsUpd->FspsConfig.PchPmSlpS4MinAssert =3D (UINT8)PmConfig->PchSlpS= 4MinAssert; + FspsUpd->FspsConfig.PchPmSlpSusMinAssert =3D (UINT8)PmConfig->PchSlpS= usMinAssert; + FspsUpd->FspsConfig.PchPmSlpAMinAssert =3D (UINT8)PmConfig->PchSlpA= MinAssert; + FspsUpd->FspsConfig.PchPmLpcClockRun =3D (UINT8)PmConfig->LpcCloc= kRun; + FspsUpd->FspsConfig.PchPmSlpStrchSusUp =3D (UINT8)PmConfig->SlpStrc= hSusUp; + FspsUpd->FspsConfig.PchPmSlpLanLowDc =3D (UINT8)PmConfig->SlpLanL= owDc; + FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod =3D (UINT8)PmConfig->PwrBt= nOverridePeriod; + FspsUpd->FspsTestConfig.PchPmDisableEnergyReport =3D (UINT8)PmConfig->D= isableEnergyReport; + FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown =3D (UINT8)PmConfig= ->DisableDsxAcPresentPulldown; + FspsUpd->FspsConfig.PchPmDisableNativePowerButton =3D (UINT8)PmConfig= ->DisableNativePowerButton; + FspsUpd->FspsConfig.PmcPowerButtonDebounce =3D PmConfig->PowerButtonDeb= ounce; + FspsUpd->FspsConfig.PchPmSlpS0Enable =3D (UINT8)PmConfig->SlpS0En= able; + FspsUpd->FspsConfig.PchPmMeWakeSts =3D (UINT8)PmConfig->MeWakeS= ts; + FspsUpd->FspsConfig.PchPmWolOvrWkSts =3D (UINT8)PmConfig->WolOvrW= kSts; + FspsUpd->FspsConfig.EnableTcoTimer =3D (UINT8)PmConfig->EnableT= coTimer; + FspsUpd->FspsConfig.PchPmVrAlert =3D (UINT8)PmConfig->VrAlert= ; + FspsUpd->FspsConfig.PchPmPwrCycDur =3D (UINT8)PmConfig->PchPwrC= ycDur; + FspsUpd->FspsConfig.PchPmPciePllSsc =3D (UINT8)PmConfig->PciePll= Ssc; + FspsUpd->FspsConfig.PchPmSlpS0VmRuntimeControl =3D (UINT8)PmConfig->SlpS= 0VmRuntimeControl; + FspsUpd->FspsConfig.PchPmSlpS0Vm070VSupport =3D (UINT8)PmConfig->SlpS0= Vm070VSupport; + FspsUpd->FspsConfig.PchPmSlpS0Vm075VSupport =3D (UINT8)PmConfig->SlpS0= Vm075VSupport; + FspsUpd->FspsConfig.SlpS0Override =3D (UINT8)PmConfig->SlpS0= Override; + FspsUpd->FspsConfig.SlpS0DisQForDebug =3D (UINT8)PmConfig->SlpS0= DisQForDebug; + FspsUpd->FspsConfig.PmcDbgMsgEn =3D (UINT8)PmConfig->PmcDb= gMsgEn; + FspsUpd->FspsConfig.PsOnEnable =3D (UINT8)PmConfig->PsOnE= nable; + FspsUpd->FspsConfig.PmcCpuC10GatePinEnable =3D (UINT8)PmConfig->CpuC1= 0GatePinEnable; + FspsUpd->FspsConfig.PmcModPhySusPgEnable =3D (UINT8)PmConfig->ModPh= ySusPgEnable; + FspsUpd->FspsConfig.SlpS0WithGbeSupport =3D (UINT8)PmConfig->SlpS0= WithGbeSupport; + // + // Update Pch Serial IRQ policies + // + FspsUpd->FspsConfig.PchSirqEnable =3D (UINT8)PchSerialIrqConfig->S= irqEnable; + FspsUpd->FspsConfig.PchSirqMode =3D (UINT8)PchSerialIrqConfig->S= irqMode; + FspsUpd->FspsConfig.PchStartFramePulse =3D (UINT8)PchSerialIrqConfig->S= tartFramePulse; + // + // Update Pch Thermal policies + // + FspsUpd->FspsConfig.PchTsmicLock =3D (UINT8)PchThermalConfig->Tsm= icLock; + FspsUpd->FspsConfig.PchHotEnable =3D (UINT8)PchThermalConfig->Pch= HotEnable; + + FspsUpd->FspsConfig.PchT0Level =3D (UINT16)PchThermalConfig->TT= Levels.T0Level; + FspsUpd->FspsConfig.PchT1Level =3D (UINT16)PchThermalConfig->TT= Levels.T1Level; + FspsUpd->FspsConfig.PchT2Level =3D (UINT16)PchThermalConfig->TT= Levels.T2Level; + FspsUpd->FspsConfig.PchTTEnable =3D (UINT8)PchThermalConfig->TTL= evels.TTEnable; + FspsUpd->FspsConfig.PchTTState13Enable =3D (UINT8)PchThermalConfig->TTL= evels.TTState13Enable; + FspsUpd->FspsConfig.PchTTLock =3D (UINT8)PchThermalConfig->TTL= evels.TTLock; + FspsUpd->FspsConfig.TTSuggestedSetting =3D (UINT8)PchThermalConfig->TTL= evels.SuggestedSetting; + FspsUpd->FspsConfig.TTCrossThrottling =3D (UINT8)PchThermalConfig->TTL= evels.PchCrossThrottling; + + FspsUpd->FspsConfig.PchDmiTsawEn =3D (UINT8)PchThermalConfig->Dmi= HaAWC.DmiTsawEn; + FspsUpd->FspsConfig.DmiSuggestedSetting =3D (UINT8)PchThermalConfig->Dmi= HaAWC.SuggestedSetting; + FspsUpd->FspsConfig.DmiTS0TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS0TW; + FspsUpd->FspsConfig.DmiTS1TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS1TW; + FspsUpd->FspsConfig.DmiTS2TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS2TW; + FspsUpd->FspsConfig.DmiTS3TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS3TW; + + FspsUpd->FspsConfig.PchMemoryThrottlingEnable =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.Enable; + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable; + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable; + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable; + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable; + FspsUpd->FspsConfig.PchMemoryPinSelection[0] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection; + FspsUpd->FspsConfig.PchMemoryPinSelection[1] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection; + + FspsUpd->FspsConfig.PchTemperatureHotLevel =3D (UINT16)PchThermalConfig-= >PchHotLevel; + + // + // Update Pch CNVi policies + // + FspsUpd->FspsConfig.PchCnviMode =3D (UINT8)CnviConfig->Mode; + FspsUpd->FspsConfig.PchCnviMfUart1Type =3D (UINT8)CnviConfig->MfUart1Typ= e; + + // + // Update Pch HSIO policies + // + FspsUpd->FspsConfig.ChipsetInitBinPtr =3D HsioConfig->ChipsetInitBinPtr; + FspsUpd->FspsConfig.ChipsetInitBinLen =3D HsioConfig->ChipsetInitBinLen; + + // + // Update Pch Espi policies + // + FspsUpd->FspsConfig.PchEspiLgmrEnable =3D (UINT8)EspiConfig->LgmrEnable; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c new file mode 100644 index 0000000000..ce34325781 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.c @@ -0,0 +1,223 @@ +/** @file + Instance of Fsp Policy Initialization Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +VOID +EFIAPI +FspPolicyInitPreMem( + IN FSPM_UPD *FspmUpdDataPtr +); + +VOID * +EFIAPI +SiliconPolicyInitPreMem( + IN OUT VOID *FspmUpd +) +{ + FspPolicyInitPreMem((FSPM_UPD *)FspmUpd); + return FspmUpd; +} + +RETURN_STATUS +EFIAPI +SiliconPolicyDonePreMem( + IN VOID *FspmUpd +) +{ + EFI_STATUS Status; + + Status =3D SpiServiceInit(); + ASSERT_EFI_ERROR(Status); + + return RETURN_SUCCESS; +} + +/** + Performs FSP PEI Policy Pre-memory initialization. + + @param[in] FspmUpdDataPtr Pointer to FSPM UPD data. +**/ +VOID +EFIAPI +FspPolicyInitPreMem ( + IN FSPM_UPD *FspmUpdDataPtr + ) +{ + EFI_STATUS Status; + + // + // SI Pei Fsp Policy Initialization + // + Status =3D PeiFspSiPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy in Pre-Memory Initiali= zation fail, Status =3D %r\n", Status)); + } + + // + // PCH Pei Fsp Policy Initialization + // + Status =3D PeiFspPchPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initial= ization fail, Status =3D %r\n", Status)); + } + + // + // Cpu Pei Fsp Policy Initialization + // + Status =3D PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initial= ization fail, Status =3D %r\n", Status)); + } + + // + // Security Pei Fsp Policy Initialization + // + Status =3D PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory In= itialization fail, Status =3D %r\n", Status)); + } + + // + // ME Pei Fsp Policy Initialization + // + Status =3D PeiFspMePolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory Initiali= zation fail, Status =3D %r\n", Status)); + } + + // + // SystemAgent Pei Fsp Policy Initialization + // + Status =3D PeiFspSaPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory= Initialization fail, Status =3D %r\n", Status)); + } + + // + // Other Upd Initialization + // + Status =3D PeiFspMiscUpdInitPreMem (FspmUpdDataPtr); + +} + +/** + Performs FSP PEI Policy initialization. + + @param[in][out] FspsUpd Pointer UPD data region + +**/ +VOID +EFIAPI +FspPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + + // + // SI Pei Fsp Policy Initialization + // + Status =3D PeiFspSiPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy iInitialization fail, = Status =3D %r\n", Status)); + } + + // + // PCH Pei Fsp Policy Initialization + // + Status =3D PeiFspPchPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fail,= Status =3D %r\n", Status)); + } + + // + // ME Pei Fsp Policy Initialization + // + Status =3D PeiFspMePolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail, S= tatus =3D %r\n", Status)); + } + + // + // SystemAgent Pei Fsp Policy Initialization + // + Status =3D PeiFspSaPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy Initializatio= n fail, Status =3D %r\n", Status)); + } + + // + // Cpu Pei Fsp Policy Initialization + // + Status =3D PeiFspCpuPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy Initialization fail, = Status =3D %r\n", Status)); + } + + // + // Security Pei Fsp Policy Initialization + // + Status =3D PeiFspSecurityPolicyInit(FspsUpd); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization fa= il, Status =3D %r\n", Status)); + } + +} + +/** +Performs silicon post-mem policy initialization. + +The meaning of Policy is defined by silicon code. +It could be the raw data, a handle, a PPI, etc. + +The returned data must be used as input data for SiliconPolicyDonePostMem(= ), +and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). + +1) In FSP path, the input Policy should be FspsUpd. +Value of FspsUpd has been initialized by FSP binary default value. +Only a subset of FspsUpd needs to be updated for different silicon sku. +The return data is same FspsUpd. + +2) In non-FSP path, the input policy could be NULL. +The return data is the initialized policy. + +@param[in, out] Policy Pointer to policy. + +@return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPostMem( + IN OUT VOID *FspsUpd +) +{ + FspPolicyInit((FSPS_UPD *)FspsUpd); + return FspsUpd; +} + +/* +The silicon post-mem policy is finalized. +Silicon code can do initialization based upon the policy data. + +The input Policy must be returned by SiliconPolicyInitPostMem(). + +@param[in] Policy Pointer to policy. + +@retval EFI_SUCCESS The policy is handled consumed by silicon code. +*/ +EFI_STATUS +EFIAPI +SiliconPolicyDonePostMem( + IN OUT VOID *FspsUpd +) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspSaPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c new file mode 100644 index 0000000000..0bfc379386 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspSaPolicyInitLib.c @@ -0,0 +1,848 @@ +/** @file + Implementation of Fsp SA Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define MAX_SPD_PAGE_COUNT (2) +#define MAX_SPD_PAGE_SIZE (256) +#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COU= NT) +#define SPD_PAGE_ADDRESS_0 (0x6C) +#define SPD_PAGE_ADDRESS_1 (0x6E) +#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02) +#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B) +#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C) +#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1) +#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F) +#define XMP_ID_STRING (0x4A0C) +#define SPD3_MANUF_START (117) +#define SPD3_MANUF_END (127) +#define SPD4_MANUF_START (320) +#define SPD4_MANUF_END (328) +#define SPDLP_MANUF_START (320) +#define SPDLP_MANUF_END (328) + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] =3D { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 41, (1 << SpdCold),}, + { 60, 63, (1 << SpdCold),}, + { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 128, 145, (1 << SpdCold),}, + { 39, 59, (1 << SpdCold),}, + { 64, 125, (1 << SpdCold),}, + { 176, 179, (1 << SpdCold),}, + { 180, 184, (1 << SpdCold),}, + { 185, 215, (1 << SpdCold),}, + { 220, 250, (1 << SpdCold),}, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] =3D { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 40, (1 << SpdCold),}, + { 117, 131, (1 << SpdCold),}, + { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 329, 348, (1 << SpdCold),}, + { 32, 119, (1 << SpdCold),}, + { 126, 255, (1 << SpdCold),}, + { 349, 383, (1 << SpdCold),}, + { 384, 387, (1 << SpdCold),}, + { 388, 389, (1 << SpdCold),}, + { 393, 431, (1 << SpdCold),}, + { 440, 478, (1 << SpdCold),}, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] =3D = { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 32, (1 << SpdCold),}, + { 120, 130, (1 << SpdCold),}, + { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 329, 348, (1 << SpdCold),}, + { 31, 121, (1 << SpdCold),}, + { 126, 255, (1 << SpdCold),}, + { 349, 383, (1 << SpdCold),}, + { 384, 387, (1 << SpdCold),}, + { 388, 389, (1 << SpdCold),}, + { 393, 431, (1 << SpdCold),}, + { 440, 478, (1 << SpdCold),}, +}; + + +/** + Update Spd Data + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + @param[in] MemConfigNoCrc Pointer to Mem Config No Crc. + @param[in] MiscPeiPreMemConfig Pointer to Misc Config. + + @retval EFI_SUCCESS The function completes successfully + @retval Other The function fail +**/ +VOID +EFIAPI +InternalUpdateSpdInfo ( + IN OUT FSPM_UPD *FspmUpd, + IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc, + IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig + ) +{ + + DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n")); + if ((FspmUpd =3D=3D NULL) || (MemConfigNoCrc =3D=3D NULL) || (MiscPeiPre= MemConfig =3D=3D NULL)) { + DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n")); + DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n")); + return; + } + + // + // Update MemorySpdPtrXX if SpdAddressTable is zero + // + if (MiscPeiPreMemConfig->SpdAddressTable[0] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr00 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData; + } else { + FspmUpd->FspmConfig.SpdAddressTable[0] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[0]; + } + + if (MiscPeiPreMemConfig->SpdAddressTable[1] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr01 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData + (1 * SA_MC_MAX_SPD_SIZE); + } else { + FspmUpd->FspmConfig.SpdAddressTable[1] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[1]; + } + + if (MiscPeiPreMemConfig->SpdAddressTable[2] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr10 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData + (2 * SA_MC_MAX_SPD_SIZE); + } else { + FspmUpd->FspmConfig.SpdAddressTable[2] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[2]; + } + + if (MiscPeiPreMemConfig->SpdAddressTable[3] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr11 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData + (3 * SA_MC_MAX_SPD_SIZE); + } else { + FspmUpd->FspmConfig.SpdAddressTable[3] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[3]; + } + + DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n")); +} + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ) +{ + EFI_STATUS Status; + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; + EFI_FV_FILE_INFO FvFileInfo; + PEI_CORE_INSTANCE *PrivateData; + UINTN CurrentFv; + PEI_CORE_FV_HANDLE *CoreFvHandle; + EFI_PEI_FILE_HANDLE VbtFileHandle; + EFI_GUID *VbtGuid; + EFI_COMMON_SECTION_HEADER *Section; + CONST EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D GetPeiServicesTablePointer (); + + PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices); + + Status =3D PeiServicesLocatePpi ( + &gEfiFirmwareFileSystem2Guid, + 0, + NULL, + (VOID **) &FvPpi + ); + ASSERT_EFI_ERROR (Status); + + CurrentFv =3D PrivateData->CurrentPeimFvCount; + CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]); + + Status =3D FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHan= dle, &VbtFileHandle); + if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) { + + DEBUG ((DEBUG_INFO, "Find SectionByType \n")); + + Status =3D FvPpi->FindSectionByType (FvPpi, EFI_SECTION_RAW, VbtFileHa= ndle, (VOID **) &VbtGuid); + if (!EFI_ERROR (Status)) { + + DEBUG ((DEBUG_INFO, "GetFileInfo \n")); + + Status =3D FvPpi->GetFileInfo (FvPpi, VbtFileHandle, &FvFileInfo); + Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; + + if (IS_SECTION2 (Section)) { + ASSERT (SECTION2_SIZE (Section) > 0x00FFFFFF); + *Size =3D SECTION2_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEA= DER2); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= 2)); + } else { + *Size =3D SECTION_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEAD= ER); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= )); + } + } + } + + return EFI_SUCCESS; +} + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIGURATION *MemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig; + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData; + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig; + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig; + VTD_CONFIG *Vtd; + IPU_PREMEM_CONFIG *IpuPreMemPolicy; + UINT8 Index; + VOID *Buffer; + + SiPreMemPolicyPpi =3D NULL; + MiscPeiPreMemConfig =3D NULL; + MemConfig =3D NULL; + MemConfigNoCrc =3D NULL; + PciePeiPreMemConfig =3D NULL; + SgGpioData =3D NULL; + GtPreMemConfig =3D NULL; + OcPreMemConfig =3D NULL; + Vtd =3D NULL; + IpuPreMemPolicy =3D NULL; + + + + // + // Locate SiPreMemPolicyPpi + // + Status =3D PeiServicesLocatePpi( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + if ((Status =3D=3D EFI_SUCCESS) && (SiPreMemPolicyPpi !=3D NULL)) { + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreM= emConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigN= oCrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigG= uid, (VOID *) &MemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPr= eMemConfigGuid, (VOID *) &GtPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreM= emConfigGuid, (VOID *) &PciePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSwitchableGra= phicsConfigGuid, (VOID *) &SgGpioData); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid= , (VOID *) &Vtd); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConf= igGuid, (VOID *) &IpuPreMemPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaOverclockin= gPreMemConfigGuid, (VOID *) &OcPreMemConfig); + ASSERT_EFI_ERROR (Status); + + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings= ...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1= 2, 12); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe= r + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp = Target Settings...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); + } + + // + // Update UPD:MemorySpdPtrXX and SpdAddressTable + // + InternalUpdateSpdInfo (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig); + + // + // Update UPD:MemorySpdDataLen + // + FspmUpd->FspmConfig.MemorySpdDataLen =3D SA_MC_MAX_SPD_SIZE; + + if (MemConfigNoCrc !=3D NULL) { + // + // Update UPD:PlatformMemorySize + // + // + // @todo: This value is used since #183932. Revisit. + // + FspmUpd->FspmConfig.PlatformMemorySize =3D MemConfigNoCrc->PlatformMe= morySize; + FspmUpd->FspmConfig.CleanMemory =3D (UINT8) MemConfigNoCrc->Cl= eanMemory; + FspmUpd->FspmConfig.MemTestOnWarmBoot =3D (UINT8) MemConfigNoCrc->Me= mTestOnWarmBoot; + } + + if (MemConfig !=3D NULL) { + // + // Update UPD:DqPinsInterleaved + // + FspmUpd->FspmConfig.DqPinsInterleaved =3D (UINT8) MemConfig->DqPin= sInterleaved; + + FspmUpd->FspmConfig.ProbelessTrace =3D MemConfig->ProbelessTrac= e; + FspmUpd->FspmConfig.GdxcIotSize =3D MemConfig->GdxcIotSize; + FspmUpd->FspmConfig.GdxcMotSize =3D MemConfig->GdxcMotSize; + FspmUpd->FspmConfig.DualDimmPerChannelBoardType =3D(UINT8) MemConfig->= DualDimmPerChannelBoardType; + FspmUpd->FspmConfig.Ddr4MixedUDimm2DpcLimit =3D(UINT8) MemConfig->= Ddr4MixedUDimm2DpcLimit; + // + // Update UPD:CaVrefConfig + // + FspmUpd->FspmConfig.CaVrefConfig =3D MemConfig->CaVrefConfig; + FspmUpd->FspmConfig.SaGv =3D MemConfig->SaGv; + FspmUpd->FspmConfig.FreqSaGvLow =3D MemConfig->FreqSaGvLow; + FspmUpd->FspmConfig.FreqSaGvMid =3D MemConfig->FreqSaGvMid; + FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->RMT; + FspmUpd->FspmConfig.DdrFreqLimit =3D MemConfig->DdrFreqLimit; + + FspmUpd->FspmConfig.SpdProfileSelected =3D MemConfig->SpdProfileSel= ected; + FspmUpd->FspmConfig.VddVoltage =3D MemConfig->VddVoltage; + FspmUpd->FspmConfig.RefClk =3D MemConfig->RefClk; + FspmUpd->FspmConfig.Ratio =3D MemConfig->Ratio; + FspmUpd->FspmConfig.OddRatioMode =3D (UINT8) MemConfig->OddRa= tioMode; + FspmUpd->FspmConfig.tCL =3D (UINT8) MemConfig->tCL; + FspmUpd->FspmConfig.tCWL =3D (UINT8) MemConfig->tCWL; + FspmUpd->FspmConfig.tFAW =3D MemConfig->tFAW; + FspmUpd->FspmConfig.tRAS =3D MemConfig->tRAS; + FspmUpd->FspmConfig.tRCDtRP =3D (UINT8) MemConfig->tRCDt= RP; + FspmUpd->FspmConfig.tREFI =3D MemConfig->tREFI; + FspmUpd->FspmConfig.tRFC =3D MemConfig->tRFC; + FspmUpd->FspmConfig.tRRD =3D (UINT8) MemConfig->tRRD; + FspmUpd->FspmConfig.tRTP =3D (UINT8) MemConfig->tRTP; + FspmUpd->FspmConfig.tWR =3D (UINT8) MemConfig->tWR; + FspmUpd->FspmConfig.tWTR =3D (UINT8) MemConfig->tWTR; + FspmUpd->FspmConfig.NModeSupport =3D MemConfig->NModeSupport; + FspmUpd->FspmConfig.DllBwEn0 =3D MemConfig->DllBwEn0; + FspmUpd->FspmConfig.DllBwEn1 =3D MemConfig->DllBwEn1; + FspmUpd->FspmConfig.DllBwEn2 =3D MemConfig->DllBwEn2; + FspmUpd->FspmConfig.DllBwEn3 =3D MemConfig->DllBwEn3; + FspmUpd->FspmConfig.MrcSafeConfig =3D (UINT8) MemConfig->MrcSa= feConfig; // Typecasting as MrcSafeConfig is of UINT32 in MEMORY_CONFIGURAT= ION + FspmUpd->FspmConfig.LpDdrDqDqsReTraining =3D (UINT8) MemConfig->Lp4Dq= sOscEn; + FspmUpd->FspmConfig.RmtPerTask =3D (UINT8) MemConfig->RmtPe= rTask; + FspmUpd->FspmConfig.TrainTrace =3D (UINT8) MemConfig->Train= Trace; + FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) MemConfig->Scram= blerSupport; + FspmUpd->FspmConfig.SafeMode =3D (UINT8) MemConfig->SafeM= ode; + + // + // Update UPD:SmramMask and DisableDimmChannel + // + FspmUpd->FspmConfig.SmramMask =3D MemConfig->SmramMask; + FspmUpd->FspmConfig.DisableDimmChannel0 =3D MemConfig->DisableDimm= Channel[0]; + FspmUpd->FspmConfig.DisableDimmChannel1 =3D MemConfig->DisableDimm= Channel[1]; + FspmUpd->FspmConfig.HobBufferSize =3D MemConfig->HobBufferSi= ze; + + FspmUpd->FspmConfig.ECT =3D (UINT8) MemConfig->ECT= ; + FspmUpd->FspmConfig.SOT =3D (UINT8) MemConfig->SOT= ; + FspmUpd->FspmConfig.ERDMPRTC2D =3D (UINT8) MemConfig->ERD= MPRTC2D; + FspmUpd->FspmConfig.RDMPRT =3D (UINT8) MemConfig->RDM= PRT; + FspmUpd->FspmConfig.RCVET =3D (UINT8) MemConfig->RCV= ET; + FspmUpd->FspmConfig.JWRL =3D (UINT8) MemConfig->JWR= L; + FspmUpd->FspmConfig.EWRTC2D =3D (UINT8) MemConfig->EWR= TC2D; + FspmUpd->FspmConfig.ERDTC2D =3D (UINT8) MemConfig->ERD= TC2D; + FspmUpd->FspmConfig.WRTC1D =3D (UINT8) MemConfig->WRT= C1D; + FspmUpd->FspmConfig.WRVC1D =3D (UINT8) MemConfig->WRV= C1D; + FspmUpd->FspmConfig.RDTC1D =3D (UINT8) MemConfig->RDT= C1D; + FspmUpd->FspmConfig.DIMMODTT =3D (UINT8) MemConfig->DIM= MODTT; + FspmUpd->FspmConfig.DIMMRONT =3D (UINT8) MemConfig->DIM= MRONT; + FspmUpd->FspmConfig.WRSRT =3D (UINT8) MemConfig->WRS= RT; + FspmUpd->FspmConfig.RDODTT =3D (UINT8) MemConfig->RDO= DTT; + FspmUpd->FspmConfig.RDEQT =3D (UINT8) MemConfig->RDE= QT; + FspmUpd->FspmConfig.RDAPT =3D (UINT8) MemConfig->RDA= PT; + FspmUpd->FspmConfig.WRTC2D =3D (UINT8) MemConfig->WRT= C2D; + FspmUpd->FspmConfig.RDTC2D =3D (UINT8) MemConfig->RDT= C2D; + FspmUpd->FspmConfig.WRVC2D =3D (UINT8) MemConfig->WRV= C2D; + FspmUpd->FspmConfig.RDVC2D =3D (UINT8) MemConfig->RDV= C2D; + FspmUpd->FspmConfig.CMDVC =3D (UINT8) MemConfig->CMD= VC; + FspmUpd->FspmConfig.LCT =3D (UINT8) MemConfig->LCT= ; + FspmUpd->FspmConfig.RTL =3D (UINT8) MemConfig->RTL= ; + FspmUpd->FspmConfig.TAT =3D (UINT8) MemConfig->TAT= ; + FspmUpd->FspmConfig.RCVENC1D =3D (UINT8) MemConfig->RCV= ENC1D; + FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->RMT= ; + FspmUpd->FspmConfig.MEMTST =3D (UINT8) MemConfig->MEM= TST; + FspmUpd->FspmConfig.ALIASCHK =3D (UINT8) MemConfig->ALI= ASCHK; + FspmUpd->FspmConfig.RMC =3D (UINT8) MemConfig->RMC= ; + FspmUpd->FspmConfig.WRDSUDT =3D (UINT8) MemConfig->WRD= SUDT; + FspmUpd->FspmConfig.EnBER =3D (UINT8) MemConfig->EnB= ER; + FspmUpd->FspmConfig.EccSupport =3D (UINT8) MemConfig->Ecc= Support; + FspmUpd->FspmConfig.RemapEnable =3D (UINT8) MemConfig->Rem= apEnable; + FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) MemConfig->Scr= amblerSupport; + FspmUpd->FspmConfig.MrcFastBoot =3D (UINT8) MemConfig->Mrc= FastBoot; + FspmUpd->FspmConfig.RankInterleave =3D (UINT8) MemConfig->Ran= kInterleave; + FspmUpd->FspmConfig.EnhancedInterleave =3D (UINT8) MemConfig->Enh= ancedInterleave; + FspmUpd->FspmConfig.MemoryTrace =3D (UINT8) MemConfig->Mem= oryTrace; + FspmUpd->FspmConfig.ChHashEnable =3D (UINT8) MemConfig->ChH= ashEnable; + FspmUpd->FspmConfig.EnableExtts =3D (UINT8) MemConfig->Ena= bleExtts; + FspmUpd->FspmConfig.EnableCltm =3D (UINT8) MemConfig->Ena= bleCltm; + FspmUpd->FspmConfig.EnableOltm =3D (UINT8) MemConfig->Ena= bleOltm; + FspmUpd->FspmConfig.EnablePwrDn =3D (UINT8) MemConfig->Ena= blePwrDn; + FspmUpd->FspmConfig.EnablePwrDnLpddr =3D (UINT8) MemConfig->Ena= blePwrDnLpddr; + FspmUpd->FspmConfig.UserPowerWeightsEn =3D (UINT8) MemConfig->Use= rPowerWeightsEn; + FspmUpd->FspmConfig.RaplLim2Lock =3D (UINT8) MemConfig->Rap= lLim2Lock; + FspmUpd->FspmConfig.RaplLim2Ena =3D (UINT8) MemConfig->Rap= lLim2Ena; + FspmUpd->FspmConfig.RaplLim1Ena =3D (UINT8) MemConfig->Rap= lLim1Ena; + FspmUpd->FspmConfig.SrefCfgEna =3D (UINT8) MemConfig->Sre= fCfgEna; + FspmUpd->FspmConfig.ThrtCkeMinDefeatLpddr =3D (UINT8) MemConfig->Thr= tCkeMinDefeatLpddr; + FspmUpd->FspmConfig.ThrtCkeMinDefeat =3D (UINT8) MemConfig->Thr= tCkeMinDefeat; + FspmUpd->FspmConfig.RhPrevention =3D (UINT8) MemConfig->RhP= revention; + FspmUpd->FspmConfig.ExitOnFailure =3D (UINT8) MemConfig->Exi= tOnFailure; + FspmUpd->FspmConfig.DdrThermalSensor =3D (UINT8) MemConfig->Ddr= ThermalSensor; + FspmUpd->FspmConfig.Ddr4DdpSharedClock =3D (UINT8) MemConfig->Ddr= 4DdpSharedClock; + FspmUpd->FspmConfig.Ddr4DdpSharedZq =3D (UINT8) MemConfig->Sha= redZqPin; + FspmUpd->FspmConfig.BClkFrequency =3D MemConfig->BClkFrequen= cy; + FspmUpd->FspmConfig.ChHashInterleaveBit =3D MemConfig->ChHashInter= leaveBit; + FspmUpd->FspmConfig.ChHashMask =3D MemConfig->ChHashMask; + FspmUpd->FspmConfig.EnergyScaleFact =3D MemConfig->EnergyScale= Fact; + FspmUpd->FspmConfig.Idd3n =3D MemConfig->Idd3n; + FspmUpd->FspmConfig.Idd3p =3D MemConfig->Idd3p; + FspmUpd->FspmConfig.CMDSR =3D (UINT8) MemConfig->CMD= SR; + FspmUpd->FspmConfig.CMDDSEQ =3D (UINT8) MemConfig->CMD= DSEQ; + FspmUpd->FspmConfig.CMDNORM =3D (UINT8) MemConfig->CMD= NORM; + FspmUpd->FspmConfig.EWRDSEQ =3D (UINT8) MemConfig->EWR= DSEQ; + FspmUpd->FspmConfig.FreqSaGvLow =3D MemConfig->FreqSaGvLow= ; + FspmUpd->FspmConfig.RhActProbability =3D MemConfig->RhActProbab= ility; + FspmUpd->FspmConfig.RaplLim2WindX =3D MemConfig->RaplLim2Win= dX; + FspmUpd->FspmConfig.RaplLim2WindY =3D MemConfig->RaplLim2Win= dY; + FspmUpd->FspmConfig.RaplLim1WindX =3D MemConfig->RaplLim1Win= dX; + FspmUpd->FspmConfig.RaplLim1WindY =3D MemConfig->RaplLim1Win= dY; + FspmUpd->FspmConfig.RaplLim2Pwr =3D MemConfig->RaplLim2Pwr= ; + FspmUpd->FspmConfig.RaplLim1Pwr =3D MemConfig->RaplLim1Pwr= ; + FspmUpd->FspmConfig.WarmThresholdCh0Dimm0 =3D MemConfig->WarmThresho= ldCh0Dimm0; + FspmUpd->FspmConfig.WarmThresholdCh0Dimm1 =3D MemConfig->WarmThresho= ldCh0Dimm1; + FspmUpd->FspmConfig.WarmThresholdCh1Dimm0 =3D MemConfig->WarmThresho= ldCh1Dimm0; + FspmUpd->FspmConfig.WarmThresholdCh1Dimm1 =3D MemConfig->WarmThresho= ldCh1Dimm1; + FspmUpd->FspmConfig.HotThresholdCh0Dimm0 =3D MemConfig->HotThreshol= dCh0Dimm0; + FspmUpd->FspmConfig.HotThresholdCh0Dimm1 =3D MemConfig->HotThreshol= dCh0Dimm1; + FspmUpd->FspmConfig.HotThresholdCh1Dimm0 =3D MemConfig->HotThreshol= dCh1Dimm0; + FspmUpd->FspmConfig.HotThresholdCh1Dimm1 =3D MemConfig->HotThreshol= dCh1Dimm1; + FspmUpd->FspmConfig.WarmBudgetCh0Dimm0 =3D MemConfig->WarmBudgetC= h0Dimm0; + FspmUpd->FspmConfig.WarmBudgetCh0Dimm1 =3D MemConfig->WarmBudgetC= h0Dimm1; + FspmUpd->FspmConfig.WarmBudgetCh1Dimm0 =3D MemConfig->WarmBudgetC= h1Dimm0; + FspmUpd->FspmConfig.WarmBudgetCh1Dimm1 =3D MemConfig->WarmBudgetC= h1Dimm1; + FspmUpd->FspmConfig.HotBudgetCh0Dimm0 =3D MemConfig->HotBudgetCh= 0Dimm0; + FspmUpd->FspmConfig.HotBudgetCh0Dimm1 =3D MemConfig->HotBudgetCh= 0Dimm1; + FspmUpd->FspmConfig.HotBudgetCh1Dimm0 =3D MemConfig->HotBudgetCh= 1Dimm0; + FspmUpd->FspmConfig.HotBudgetCh1Dimm1 =3D MemConfig->HotBudgetCh= 1Dimm1; + FspmUpd->FspmConfig.IdleEnergyCh0Dimm0 =3D MemConfig->IdleEnergyC= h0Dimm0; + FspmUpd->FspmConfig.IdleEnergyCh0Dimm1 =3D MemConfig->IdleEnergyC= h0Dimm1; + FspmUpd->FspmConfig.IdleEnergyCh1Dimm0 =3D MemConfig->IdleEnergyC= h1Dimm0; + FspmUpd->FspmConfig.IdleEnergyCh1Dimm1 =3D MemConfig->IdleEnergyC= h1Dimm1; + FspmUpd->FspmConfig.PdEnergyCh0Dimm0 =3D MemConfig->PdEnergyCh0= Dimm0; + FspmUpd->FspmConfig.PdEnergyCh0Dimm1 =3D MemConfig->PdEnergyCh0= Dimm1; + FspmUpd->FspmConfig.PdEnergyCh1Dimm0 =3D MemConfig->PdEnergyCh1= Dimm0; + FspmUpd->FspmConfig.PdEnergyCh1Dimm1 =3D MemConfig->PdEnergyCh1= Dimm1; + FspmUpd->FspmConfig.ActEnergyCh0Dimm0 =3D MemConfig->ActEnergyCh= 0Dimm0; + FspmUpd->FspmConfig.ActEnergyCh0Dimm1 =3D MemConfig->ActEnergyCh= 0Dimm1; + FspmUpd->FspmConfig.ActEnergyCh1Dimm0 =3D MemConfig->ActEnergyCh= 1Dimm0; + FspmUpd->FspmConfig.ActEnergyCh1Dimm1 =3D MemConfig->ActEnergyCh= 1Dimm1; + FspmUpd->FspmConfig.RdEnergyCh0Dimm0 =3D MemConfig->RdEnergyCh0= Dimm0; + FspmUpd->FspmConfig.RdEnergyCh0Dimm1 =3D MemConfig->RdEnergyCh0= Dimm1; + FspmUpd->FspmConfig.RdEnergyCh1Dimm0 =3D MemConfig->RdEnergyCh1= Dimm0; + FspmUpd->FspmConfig.RdEnergyCh1Dimm1 =3D MemConfig->RdEnergyCh1= Dimm1; + FspmUpd->FspmConfig.WrEnergyCh0Dimm0 =3D MemConfig->WrEnergyCh0= Dimm0; + FspmUpd->FspmConfig.WrEnergyCh0Dimm1 =3D MemConfig->WrEnergyCh0= Dimm1; + FspmUpd->FspmConfig.WrEnergyCh1Dimm0 =3D MemConfig->WrEnergyCh1= Dimm0; + FspmUpd->FspmConfig.WrEnergyCh1Dimm1 =3D MemConfig->WrEnergyCh1= Dimm1; + FspmUpd->FspmConfig.ThrtCkeMinTmr =3D MemConfig->ThrtCkeMinT= mr; + FspmUpd->FspmConfig.CkeRankMapping =3D MemConfig->CkeRankMapp= ing; + FspmUpd->FspmConfig.CaVrefConfig =3D MemConfig->CaVrefConfi= g; + FspmUpd->FspmConfig.RaplPwrFlCh1 =3D MemConfig->RaplPwrFlCh= 1; + FspmUpd->FspmConfig.RaplPwrFlCh0 =3D MemConfig->RaplPwrFlCh= 0; + FspmUpd->FspmConfig.EnCmdRate =3D MemConfig->EnCmdRate; + FspmUpd->FspmConfig.Refresh2X =3D MemConfig->Refresh2X; + FspmUpd->FspmConfig.EpgEnable =3D MemConfig->EpgEnable; + FspmUpd->FspmConfig.RhSolution =3D MemConfig->RhSolution; + FspmUpd->FspmConfig.UserThresholdEnable =3D MemConfig->UserThresho= ldEnable; + FspmUpd->FspmConfig.UserBudgetEnable =3D MemConfig->UserBudgetE= nable; + FspmUpd->FspmConfig.TsodTcritMax =3D MemConfig->TsodTcritMa= x; + FspmUpd->FspmConfig.TsodEventMode =3D MemConfig->TsodEventMo= de; + FspmUpd->FspmConfig.TsodEventPolarity =3D MemConfig->TsodEventPo= larity; + FspmUpd->FspmConfig.TsodCriticalEventOnly =3D MemConfig->TsodCritica= lEventOnly; + FspmUpd->FspmConfig.TsodEventOutputControl =3D MemConfig->TsodEventOu= tputControl; + FspmUpd->FspmConfig.TsodAlarmwindowLockBit =3D MemConfig->TsodAlarmwi= ndowLockBit; + FspmUpd->FspmConfig.TsodCriticaltripLockBit =3D MemConfig->TsodCritica= ltripLockBit; + FspmUpd->FspmConfig.TsodShutdownMode =3D MemConfig->TsodShutdow= nMode; + FspmUpd->FspmConfig.TsodThigMax =3D MemConfig->TsodThigMax= ; + FspmUpd->FspmConfig.TsodManualEnable =3D MemConfig->TsodManualE= nable; + FspmUpd->FspmConfig.IsvtIoPort =3D MemConfig->IsvtIoPort; + FspmUpd->FspmConfig.ForceOltmOrRefresh2x =3D MemConfig->ForceOltmOr= Refresh2x; + FspmUpd->FspmConfig.PwdwnIdleCounter =3D MemConfig->PwdwnIdleCo= unter; + FspmUpd->FspmConfig.CmdRanksTerminated =3D MemConfig->CmdRanksTer= minated; + FspmUpd->FspmConfig.GdxcEnable =3D MemConfig->GdxcEnable; + FspmUpd->FspmConfig.RMTLoopCount =3D MemConfig->RMTLoopCoun= t; + + // DDR4 Memory Timings + FspmUpd->FspmTestConfig.tRRD_L =3D (UINT8) MemConfig->tRRD_L; + FspmUpd->FspmTestConfig.tRRD_S =3D (UINT8) MemConfig->tRRD_S; + FspmUpd->FspmTestConfig.tWTR_L =3D (UINT8) MemConfig->tWTR_L; + FspmUpd->FspmTestConfig.tWTR_S =3D (UINT8) MemConfig->tWTR_S; + + // TurnAround Timing + // Read-to-Read + FspmUpd->FspmTestConfig.tRd2RdSG =3D MemConfig->tRd2RdSG; + FspmUpd->FspmTestConfig.tRd2RdDG =3D MemConfig->tRd2RdDG; + FspmUpd->FspmTestConfig.tRd2RdDR =3D MemConfig->tRd2RdDR; + FspmUpd->FspmTestConfig.tRd2RdDD =3D MemConfig->tRd2RdDD; + // Write-to-Read + FspmUpd->FspmTestConfig.tWr2RdSG =3D MemConfig->tWr2RdSG; + FspmUpd->FspmTestConfig.tWr2RdDG =3D MemConfig->tWr2RdDG; + FspmUpd->FspmTestConfig.tWr2RdDR =3D MemConfig->tWr2RdDR; + FspmUpd->FspmTestConfig.tWr2RdDD =3D MemConfig->tWr2RdDD; + // Write-to-Write + FspmUpd->FspmTestConfig.tWr2WrSG =3D MemConfig->tWr2WrSG; + FspmUpd->FspmTestConfig.tWr2WrDG =3D MemConfig->tWr2WrDG; + FspmUpd->FspmTestConfig.tWr2WrDR =3D MemConfig->tWr2WrDR; + FspmUpd->FspmTestConfig.tWr2WrDD =3D MemConfig->tWr2WrDD; + // Read-to-Write + FspmUpd->FspmTestConfig.tRd2WrSG =3D MemConfig->tRd2WrSG; + FspmUpd->FspmTestConfig.tRd2WrDG =3D MemConfig->tRd2WrDG; + FspmUpd->FspmTestConfig.tRd2WrDR =3D MemConfig->tRd2WrDR; + FspmUpd->FspmTestConfig.tRd2WrDD =3D MemConfig->tRd2WrDD; + } + + if (MiscPeiPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.IedSize =3D MiscPeiPreMemConfig->Ied= Size; + FspmUpd->FspmConfig.UserBd =3D MiscPeiPreMemConfig->Use= rBd; + FspmUpd->FspmConfig.SgDelayAfterPwrEn =3D MiscPeiPreMemConfig->SgD= elayAfterPwrEn; + FspmUpd->FspmConfig.SgDelayAfterHoldReset =3D MiscPeiPreMemConfig->SgD= elayAfterHoldReset; + FspmUpd->FspmConfig.MmioSize =3D MiscPeiPreMemConfig->Mmi= oSize; + FspmUpd->FspmConfig.MmioSizeAdjustment =3D MiscPeiPreMemConfig->Mmi= oSizeAdjustment; + FspmUpd->FspmConfig.TsegSize =3D MiscPeiPreMemConfig->Tse= gSize; + + FspmUpd->FspmTestConfig.SkipExtGfxScan =3D (UINT8) MiscPeiPr= eMemConfig->SkipExtGfxScan; + FspmUpd->FspmTestConfig.BdatEnable =3D (UINT8) MiscPeiPr= eMemConfig->BdatEnable; + FspmUpd->FspmTestConfig.BdatTestType =3D (UINT8) MiscPeiPr= eMemConfig->BdatTestType; + FspmUpd->FspmTestConfig.ScanExtGfxForLegacyOpRom =3D (UINT8) MiscPeiPr= eMemConfig->ScanExtGfxForLegacyOpRom; + FspmUpd->FspmTestConfig.LockPTMregs =3D (UINT8) MiscPeiPr= eMemConfig->LockPTMregs; + } + + if (Vtd !=3D NULL) { + FspmUpd->FspmConfig.X2ApicOptOut =3D (UINT8) Vtd->X2ApicOptOut; + FspmUpd->FspmConfig.VtdBaseAddress[0] =3D Vtd->BaseAddress[0]; + FspmUpd->FspmConfig.VtdBaseAddress[1] =3D Vtd->BaseAddress[1]; + FspmUpd->FspmConfig.VtdBaseAddress[2] =3D Vtd->BaseAddress[2]; + FspmUpd->FspmTestConfig.VtdDisable =3D (UINT8) Vtd->VtdDisable; + } + + if (PciePeiPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.DmiGen3ProgramStaticEq =3D (UINT8) PciePeiPreMemCo= nfig->DmiGen3ProgramStaticEq; + FspmUpd->FspmConfig.Peg0Enable =3D (UINT8) PciePeiPreMemConfig->Peg0En= able; + FspmUpd->FspmConfig.Peg1Enable =3D (UINT8) PciePeiPreMemConfig->Peg1En= able; + FspmUpd->FspmConfig.Peg2Enable =3D (UINT8) PciePeiPreMemConfig->Peg2En= able; + FspmUpd->FspmConfig.Peg3Enable =3D (UINT8) PciePeiPreMemConfig->Peg3En= able; + FspmUpd->FspmConfig.Peg0MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg0MaxLinkSpeed; + FspmUpd->FspmConfig.Peg1MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg1MaxLinkSpeed; + FspmUpd->FspmConfig.Peg2MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg2MaxLinkSpeed; + FspmUpd->FspmConfig.Peg3MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg3MaxLinkSpeed; + FspmUpd->FspmConfig.Peg0MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg0MaxLinkWidth; + FspmUpd->FspmConfig.Peg1MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg1MaxLinkWidth; + FspmUpd->FspmConfig.Peg2MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg2MaxLinkWidth; + FspmUpd->FspmConfig.Peg3MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg3MaxLinkWidth; + FspmUpd->FspmConfig.Peg0PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg0PowerDownUnusedLanes; + FspmUpd->FspmConfig.Peg1PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg1PowerDownUnusedLanes; + FspmUpd->FspmConfig.Peg2PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg2PowerDownUnusedLanes; + FspmUpd->FspmConfig.Peg3PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg3PowerDownUnusedLanes; + FspmUpd->FspmConfig.InitPcieAspmAfterOprom =3D (UINT8) PciePeiPreMemCo= nfig->InitPcieAspmAfterOprom; + FspmUpd->FspmConfig.PegDisableSpreadSpectrumClocking =3D (UINT8) PcieP= eiPreMemConfig->PegDisableSpreadSpectrumClocking; + for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) { + FspmUpd->FspmConfig.DmiGen3RootPortPreset[Index] =3D PciePeiPreMemCo= nfig->DmiGen3RootPortPreset[Index]; + FspmUpd->FspmConfig.DmiGen3EndPointPreset[Index] =3D PciePeiPreMemCo= nfig->DmiGen3EndPointPreset[Index]; + FspmUpd->FspmConfig.DmiGen3EndPointHint[Index] =3D PciePeiPreMemConf= ig->DmiGen3EndPointHint[Index]; + } + for (Index =3D 0; Index < SA_DMI_MAX_BUNDLE; Index++) { + FspmUpd->FspmConfig.DmiGen3RxCtlePeaking[Index] =3D PciePeiPreMemCon= fig->DmiGen3RxCtlePeaking[Index]; + } + for (Index =3D 0; Index < SA_PEG_MAX_BUNDLE ; Index++) { + FspmUpd->FspmConfig.PegGen3RxCtlePeaking[Index] =3D PciePeiPreMemCon= fig->PegGen3RxCtlePeaking[Index]; + } + FspmUpd->FspmConfig.PegDataPtr =3D (UINT32) PciePeiPreMemConfig->PegDa= taPtr; + CopyMem((VOID *)FspmUpd->FspmConfig.PegGpioData, &PciePeiPreMemConfig-= >PegGpioData, sizeof (PEG_GPIO_DATA)); + FspmUpd->FspmConfig.DmiDeEmphasis =3D PciePeiPreMemConfig->DmiDeEmphas= is; + + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + FspmUpd->FspmConfig.PegRootPortHPE[Index] =3D PciePeiPreMemConfig->P= egRootPortHPE[Index]; + } + FspmUpd->FspmTestConfig.DmiMaxLinkSpeed =3D (UINT8) PciePeiPreMemC= onfig->DmiMaxLinkSpeed; + FspmUpd->FspmTestConfig.DmiGen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->DmiGen3EqPh2Enable; + FspmUpd->FspmTestConfig.DmiGen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->DmiGen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg0Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg0Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg1Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg1Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg2Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg2Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg3Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg3Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg0Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg0Gen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg1Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg1Gen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg2Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg2Gen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg3Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg3Gen3EqPh3Method; + FspmUpd->FspmTestConfig.PegGen3ProgramStaticEq =3D (UINT8) PciePeiPreM= emConfig->PegGen3ProgramStaticEq; + FspmUpd->FspmTestConfig.Gen3SwEqAlwaysAttempt =3D (UINT8) PciePeiPreMe= mConfig->Gen3SwEqAlwaysAttempt; + FspmUpd->FspmTestConfig.Gen3SwEqNumberOfPresets =3D (UINT8) PciePeiPre= MemConfig->Gen3SwEqNumberOfPresets; + FspmUpd->FspmTestConfig.Gen3SwEqEnableVocTest =3D (UINT8) PciePeiPreMe= mConfig->Gen3SwEqEnableVocTest; + FspmUpd->FspmTestConfig.PegRxCemTestingMode =3D (UINT8) PciePeiPreMemC= onfig->PegRxCemTestingMode; + FspmUpd->FspmTestConfig.PegRxCemLoopbackLane =3D (UINT8) PciePeiPreMem= Config->PegRxCemLoopbackLane; + FspmUpd->FspmTestConfig.PegGenerateBdatMarginTable =3D (UINT8) PciePei= PreMemConfig->PegGenerateBdatMarginTable; + FspmUpd->FspmTestConfig.PegRxCemNonProtocolAwareness =3D (UINT8) PcieP= eiPreMemConfig->PegRxCemNonProtocolAwareness; + FspmUpd->FspmTestConfig.PegGen3RxCtleOverride =3D (UINT8) PciePeiPreMe= mConfig->PegGen3RxCtleOverride; + for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) { + FspmUpd->FspmTestConfig.PegGen3RootPortPreset[Index] =3D PciePeiPreM= emConfig->PegGen3RootPortPreset[Index]; + FspmUpd->FspmTestConfig.PegGen3EndPointPreset[Index] =3D PciePeiPreM= emConfig->PegGen3EndPointPreset[Index]; + FspmUpd->FspmTestConfig.PegGen3EndPointHint[Index] =3D PciePeiPreMem= Config->PegGen3EndPointHint[Index]; + } + FspmUpd->FspmTestConfig.Gen3SwEqJitterDwellTime =3D PciePeiPreMemConfi= g->Gen3SwEqJitterDwellTime; + FspmUpd->FspmTestConfig.Gen3SwEqJitterErrorTarget =3D PciePeiPreMemCon= fig->Gen3SwEqJitterErrorTarget; + FspmUpd->FspmTestConfig.Gen3SwEqVocDwellTime =3D PciePeiPreMemConfig->= Gen3SwEqVocDwellTime; + FspmUpd->FspmTestConfig.Gen3SwEqVocErrorTarget =3D PciePeiPreMemConfig= ->Gen3SwEqVocErrorTarget; + } + + if (GtPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.PrimaryDisplay =3D (UINT8) GtPreMemConfig->Primary= Display; + FspmUpd->FspmConfig.InternalGfx =3D (UINT8) GtPreMemConfig->InternalGr= aphics; + FspmUpd->FspmConfig.IgdDvmt50PreAlloc =3D (UINT8) GtPreMemConfig->IgdD= vmt50PreAlloc; + FspmUpd->FspmConfig.ApertureSize =3D (UINT8) GtPreMemConfig->ApertureS= ize; + FspmUpd->FspmConfig.GttMmAdr =3D GtPreMemConfig->GttMmAdr; + FspmUpd->FspmConfig.GmAdr =3D GtPreMemConfig->GmAdr; + FspmUpd->FspmConfig.GttSize =3D GtPreMemConfig->GttSize; + FspmUpd->FspmConfig.PsmiRegionSize =3D (UINT8) GtPreMemConfig->PsmiReg= ionSize; + FspmUpd->FspmConfig.GtPsmiSupport =3D (UINT8)GtPreMemConfig->GtPsmiSup= port; + FspmUpd->FspmTestConfig.PanelPowerEnable =3D (UINT8) GtPreMemConfig->P= anelPowerEnable; + FspmUpd->FspmTestConfig.DeltaT12PowerCycleDelayPreMem =3D (UINT16) GtP= reMemConfig->DeltaT12PowerCycleDelayPreMem; + } + + if (SgGpioData !=3D NULL) { + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie0Gpio, &SgGpioData->SaR= td3Pcie0Gpio, sizeof (SA_PCIE_RTD3_GPIO)); + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie1Gpio, &SgGpioData->SaR= td3Pcie1Gpio, sizeof (SA_PCIE_RTD3_GPIO)); + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie2Gpio, &SgGpioData->SaR= td3Pcie2Gpio, sizeof (SA_PCIE_RTD3_GPIO)); + FspmUpd->FspmConfig.RootPortIndex =3D SgGpioData->RootPortIndex; + } + + if (IpuPreMemPolicy !=3D NULL) { + FspmUpd->FspmConfig.SaIpuEnable =3D (UINT8) IpuPreMemPolicy->SaIpuEnab= le; + FspmUpd->FspmConfig.SaIpuImrConfiguration =3D (UINT8) IpuPreMemPolicy-= >SaIpuImrConfiguration; + } + + if (OcPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.SaOcSupport =3D (UINT8) OcPreMemConfig->OcSupport; + FspmUpd->FspmConfig.RealtimeMemoryTiming =3D (UINT8) OcPreMemConfig->R= ealtimeMemoryTiming; + FspmUpd->FspmConfig.GtVoltageMode =3D (UINT8) OcPreMemConfig->GtVoltag= eMode; + FspmUpd->FspmConfig.GtMaxOcRatio =3D OcPreMemConfig->GtMaxOcRatio; + FspmUpd->FspmConfig.GtVoltageOffset =3D OcPreMemConfig->GtVoltageOffse= t; + FspmUpd->FspmConfig.GtVoltageOverride =3D OcPreMemConfig->GtVoltageOve= rride; + FspmUpd->FspmConfig.GtExtraTurboVoltage =3D OcPreMemConfig->GtExtraTur= boVoltage; + FspmUpd->FspmConfig.SaVoltageOffset =3D OcPreMemConfig->SaVoltageOffse= t; + FspmUpd->FspmConfig.GtusMaxOcRatio =3D OcPreMemConfig->GtusMaxOcRatio; + FspmUpd->FspmConfig.GtusVoltageMode =3D (UINT8) OcPreMemConfig->GtusVo= ltageMode; + FspmUpd->FspmConfig.GtusVoltageOffset =3D OcPreMemConfig->GtusVoltageO= ffset; + FspmUpd->FspmConfig.GtusVoltageOverride =3D OcPreMemConfig->GtusVoltag= eOverride; + FspmUpd->FspmConfig.GtusExtraTurboVoltage =3D OcPreMemConfig->GtusExtr= aTurboVoltage; + } + + + + + return EFI_SUCCESS; +} + + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + SA_MISC_PEI_CONFIG *MiscPeiConfig; + GRAPHICS_PEI_CONFIG *GtConfig; + PCIE_PEI_CONFIG *PciePeiConfig; + GNA_CONFIG *GnaConfig; + UINT8 Index; + EFI_BOOT_MODE BootMode; + + MiscPeiConfig =3D NULL; + GtConfig =3D NULL; + PciePeiConfig =3D NULL; + GnaConfig =3D NULL; + + // + // @todo This could be cleared up after FSP provides ExitBootServices No= tifyPhase. + // + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Locate SiPolicyPpi + // + SiPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPpi + ); + if ((Status =3D=3D EFI_SUCCESS) && (SiPolicyPpi !=3D NULL)) { + MiscPeiConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid= , (VOID *) &MiscPeiConfig); + ASSERT_EFI_ERROR (Status); + + GtConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGu= id, (VOID *) &GtConfig); + ASSERT_EFI_ERROR (Status); + + GnaConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOI= D *) &GnaConfig); + ASSERT_EFI_ERROR (Status); + + PciePeiConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid= , (VOID *) &PciePeiConfig); + ASSERT_EFI_ERROR (Status); + + } + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n")); + + + if (MiscPeiConfig !=3D NULL) { + FspsUpd->FspsConfig.Device4Enable =3D (UINT8) MiscPeiConfig->Device4En= able; + FspsUpd->FspsConfig.CridEnable =3D (UINT8) MiscPeiConfig->CridEnable; + FspsUpd->FspsTestConfig.ChapDeviceEnable =3D (UINT8) MiscPeiConfig->Ch= apDeviceEnable; + FspsUpd->FspsTestConfig.SkipPamLock =3D (UINT8) MiscPeiConfig->SkipPam= Lock; + FspsUpd->FspsTestConfig.EdramTestMode =3D (UINT8) MiscPeiConfig->Edram= TestMode; + } + + if (PciePeiConfig !=3D NULL) { + FspsUpd->FspsConfig.DmiAspm =3D (UINT8) PciePeiConfig->DmiAspm; + FspsUpd->FspsTestConfig.DmiExtSync =3D (UINT8) PciePeiConfig->DmiExtSy= nc; + FspsUpd->FspsTestConfig.DmiIot =3D (UINT8) PciePeiConfig->DmiIot; + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + FspsUpd->FspsConfig.PegDeEmphasis[Index] =3D PciePeiConfig->PegDeEmp= hasis[Index]; + FspsUpd->FspsConfig.PegSlotPowerLimitValue[Index] =3D PciePeiConfig-= >PegSlotPowerLimitValue[Index]; + FspsUpd->FspsConfig.PegSlotPowerLimitScale[Index] =3D PciePeiConfig-= >PegSlotPowerLimitScale[Index]; + FspsUpd->FspsConfig.PegPhysicalSlotNumber[Index] =3D PciePeiConfig->= PegPhysicalSlotNumber[Index]; + FspsUpd->FspsTestConfig.PegMaxPayload[Index] =3D PciePeiConfig->PegM= axPayload[Index]; + } + } + + if (GtConfig !=3D NULL) { + FspsUpd->FspsConfig.PavpEnable =3D (UINT8) GtConfig->PavpEnable; + FspsUpd->FspsConfig.CdClock =3D (UINT8) GtConfig->CdClock; + FspsUpd->FspsTestConfig.RenderStandby =3D (UINT8) GtConfig->RenderStan= dby; + FspsUpd->FspsTestConfig.PmSupport =3D (UINT8) GtConfig->PmSupport; + FspsUpd->FspsTestConfig.CdynmaxClampEnable =3D (UINT8) GtConfig->Cdynm= axClampEnable; + FspsUpd->FspsTestConfig.GtFreqMax =3D (UINT8) GtConfig->GtFreqMax; + FspsUpd->FspsTestConfig.DisableTurboGt =3D (UINT8) GtConfig->DisableTu= rboGt; + FspsUpd->FspsConfig.SkipS3CdClockInit =3D (UINT8)GtConfig->SkipS3CdClo= ckInit; + + // + // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled = as default. + // + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D (UINT8) GtConfig->PeiGraph= icsPeimInit; // SA: InternalOnly: For Internal validation we still need to = enable both Enable/Disable Cases + + // + // Update UPD: VBT & LogoPtr + // + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) NULL; + } else { + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) GtConfig->Graphic= sConfigPtr; + } + DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd= ->FspsConfig.GraphicsConfigPtr)); + + FspsUpd->FspsConfig.LogoPtr =3D (UINT32) GtConfig->LogoPtr; + FspsUpd->FspsConfig.LogoSize =3D GtConfig->LogoSize; + DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig= is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); + DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfi= g is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); + + FspsUpd->FspsConfig.BltBufferAddress =3D (UINT32) GtConfig->BltBuffer= Address; + FspsUpd->FspsConfig.BltBufferSize =3D (UINT32) GtConfig->BltBuffer= Size; + + // + // Update DDI/DDC configuration + // + FspsUpd->FspsConfig.DdiPortEdp =3D GtConfig->DdiConfiguration.DdiPortE= dp; + FspsUpd->FspsConfig.DdiPortBHpd =3D GtConfig->DdiConfiguration.DdiPort= BHpd; + FspsUpd->FspsConfig.DdiPortCHpd =3D GtConfig->DdiConfiguration.DdiPort= CHpd; + FspsUpd->FspsConfig.DdiPortDHpd =3D GtConfig->DdiConfiguration.DdiPort= DHpd; + FspsUpd->FspsConfig.DdiPortFHpd =3D GtConfig->DdiConfiguration.DdiPort= FHpd; + FspsUpd->FspsConfig.DdiPortBDdc =3D GtConfig->DdiConfiguration.DdiPort= BDdc; + FspsUpd->FspsConfig.DdiPortCDdc =3D GtConfig->DdiConfiguration.DdiPort= CDdc; + FspsUpd->FspsConfig.DdiPortDDdc =3D GtConfig->DdiConfiguration.DdiPort= DDdc; + FspsUpd->FspsConfig.DdiPortFDdc =3D GtConfig->DdiConfiguration.DdiPort= FDdc; + + } + + if (GnaConfig !=3D NULL) { + FspsUpd->FspsConfig.GnaEnable =3D (UINT8) GnaConfig->GnaEnable; +#ifdef TESTMENU_FLAG +#endif // TESTMENU_FLAG + } + + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspSecurityPolicyInitLib.c b/Platform/Intel/WhiskeylakeO= penBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInit= Lib.c new file mode 100644 index 0000000000..80d20d74a9 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspSecurityPolicyInitLib.c @@ -0,0 +1,70 @@ +/** @file + Implementation of Fsp Security Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Performs FSP Security PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem Star= t\n")); + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem End\= n")); + + return EFI_SUCCESS; +} + +/** + Performs FSP Security PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspSiPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c new file mode 100644 index 0000000000..98658782aa --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspSiPolicyInitLib.c @@ -0,0 +1,95 @@ +/** @file + Implementation of Fsp SI Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + Performs FSP SI PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Performs FSP SI PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicy; + SI_CONFIG *SiConfig; + + // + // Locate SiPolicyPpi + // + SiPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &= SiConfig); + ASSERT_EFI_ERROR (Status); + + // + // Update SiConfig policies + // + FspsUpd->FspsConfig.SiCsmFlag =3D (UINT8)SiConfig->CsmFla= g; + FspsUpd->FspsConfig.SiSsidTablePtr =3D (UINT32)(UINTN)SiConfig= ->SsidTablePtr; + FspsUpd->FspsConfig.SiNumberOfSsidTableEntry =3D (UINT16)SiConfig->Numbe= rOfSsidTableEntry; + FspsUpd->FspsConfig.TraceHubMemBase =3D SiConfig->TraceHubMemB= ase; + + return EFI_SUCCESS; +} + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscU= pdUpdateLib.c new file mode 100644 index 0000000000..a341a58930 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -0,0 +1,100 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "PeiMiscPolicyUpdate.h" + +/** + Performs FSP Misc UPD initialization. + + @param[in,out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND An instance of gEfiPeiReadOnly= Variable2PpiGuid + could not be located. + @retval EFI_OUT_OF_RESOURCES Insufficent resources to alloc= ate a memory buffer. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + UINTN VariableSize; + VOID *MemorySavedData; + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **) &VariableServices + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + VariableSize =3D 0; + MemorySavedData =3D NULL; + Status =3D VariableServices->GetVariable ( + VariableServices, + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + NULL, + &VariableSize, + MemorySavedData + ); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + MemorySavedData =3D AllocatePool (VariableSize); + if (MemorySavedData =3D=3D NULL) { + ASSERT (MemorySavedData !=3D NULL); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize)); + Status =3D VariableServices->GetVariable ( + VariableServices, + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + NULL, + &VariableSize, + MemorySavedData + ); + if (Status =3D=3D EFI_SUCCESS) { + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; + } else { + DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMe= moryConfigVariableGuid, Status =3D %r\n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/Whiskeyla= keOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicy= UpdateLib.c new file mode 100644 index 0000000000..5119e934a2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiFspPolicyUpdateLib.c @@ -0,0 +1,124 @@ +/** @file + Provide FSP wrapper platform related function. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "PeiMiscPolicyUpdate.h" + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +VOID +InternalPrintVariableData ( + IN UINT8 *Data8, + IN UINTN DataSize + ) +{ + UINTN Index; + + for (Index =3D 0; Index < DataSize; Index++) { + if (Index % 0x10 =3D=3D 0) { + DEBUG ((DEBUG_INFO, "\n%08X:", Index)); + } + DEBUG ((DEBUG_INFO, " %02X", *Data8++)); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *FspmUpd + ) +{ + FSPM_UPD *FspmUpdDataPtr; + + FspmUpdDataPtr =3D FspmUpd; + + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); + InternalPrintVariableData ((VOID *) FspmUpdDataPtr, sizeof (FSPM_UPD)); + + return FspmUpd; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *FspsUpd + ) +{ + FSPS_UPD *FspsUpdDataPtr; + + FspsUpdDataPtr =3D FspsUpd; + + PeiFspPchPolicyUpdate (FspsUpd); + InternalPrintVariableData ((VOID * )FspsUpdDataPtr, sizeof (FSPS_UPD)); + + return FspsUpd; +} diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/WhiskeylakeO= penBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpd= ate.c new file mode 100644 index 0000000000..455467dc25 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiPchPolicyUpdate.c @@ -0,0 +1,60 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) mPcieDevi= ceTable; + + AddPlatformVerbTables ( + PchHdaCodecPlatformOnboard, + &(FspsUpd->FspsConfig.PchHdaVerbTableEntryNum), + &(FspsUpd->FspsConfig.PchHdaVerbTablePtr) + ); + +DEBUG_CODE_BEGIN(); +if ((PcdGet8 (PcdSerialIoUartDebugEnable) =3D=3D 1) && + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 = (PcdSerialIoUartNumber)] =3D=3D PchSerialIoDisabled ) { + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (P= cdSerialIoUartNumber)] =3D PchSerialIoHidden; + } +DEBUG_CODE_END(); + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/Whiske= ylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPol= icyUpdatePreMem.c new file mode 100644 index 0000000000..cbb818c875 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,39 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/WhiskeylakeOp= enBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdat= e.c new file mode 100644 index 0000000000..2114479030 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -0,0 +1,85 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; + + Size =3D 0; + Buffer =3D NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32)(UINTN)MemBuffer= ; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + FspsUpd->FspsConfig.GraphicsConfigPtr =3D 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", F= spsUpd->FspsConfig.GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= )); + + Size =3D 0; + Buffer =3D NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, = &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.LogoPtr =3D (UINT32)(UINTN)MemBuffer; + FspsUpd->FspsConfig.LogoSize =3D Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + FspsUpd->FspsConfig.LogoPtr =3D 0; + FspsUpd->FspsConfig.LogoSize =3D 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsU= pd->FspsConfig.LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", Fsps= Upd->FspsConfig.LogoSize)); + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/Whiskey= lakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolic= yUpdatePreMem.c new file mode 100644 index 0000000000..946182864e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,87 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + VOID *Buffer; + + // + // If SpdAddressTable are not all 0, it means DIMM slots implemented and + // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPoli= cyInitPreMem. + // + // If SpdAddressTable all 0, this is memory down design and hardcoded Sp= dData + // should be applied to MemorySpdPtr*. + // + if ((PcdGet8 (PcdMrcSpdAddressTable0) =3D=3D 0) && (PcdGet8 (PcdMrcSpdAd= dressTable1) =3D=3D 0) + && (PcdGet8 (PcdMrcSpdAddressTable2) =3D=3D 0) && (PcdGet8 (PcdMrcSp= dAddressTable3) =3D=3D 0)) { + DEBUG ((DEBUG_INFO, "Overriding SPD data for down memory.\n")); + CopyMem ( + (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00, + (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), + PcdGet16 (PcdMrcSpdDataSize) + ); + CopyMem ( + (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10, + (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), + PcdGet16 (PcdMrcSpdDataSize) + ); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings= ...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1= 2, 12); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe= r + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp = Target Settings...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); + } + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/Whiskey= lakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperP= latformSecLib.c new file mode 100644 index 0000000000..a767289bc5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/FspWrapperPlatformSecLib.c @@ -0,0 +1,163 @@ +/** @file + Provide FSP wrapper platform sec related function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param[in] PeiServices Pointer to the PEI Services Tab= le. + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer. + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ); + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. + +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ); + +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D { + SecGetPerformance +}; + +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gTopOfTemporaryRamPpiGuid, + NULL // To be patched later. + }, + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gPeiSecPerformancePpiGuid, + &mSecPerformancePpi + }, +}; + +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21 +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1 +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0 +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1 + +/** + Write to mask and edge/level triggered registers of master and slave 825= 9 PICs. + + @param[in] Mask low byte for master PIC mask register, + high byte for slave PIC mask register. + @param[in] EdgeLevel low byte for master PIC edge/level triggered regi= ster, + high byte for slave PIC edge/level triggered regi= ster. + +**/ +VOID +Interrupt8259WriteMask ( + IN UINT16 Mask, + IN UINT16 EdgeLevel + ) +{ + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8)); + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) Edge= Level); + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (Edge= Level >> 8)); +} + +/** + A developer supplied function to perform platform specific operations. + + It's a developer supplied function to perform any operations appropriate= to a + given platform. It's invoked just before passing control to PEI core by = SEC + core. Platform developer may modify the SecCoreData passed to PEI Core. + It returns a platform specific PPI list that platform wishes to pass to = PEI core. + The Generic SEC core module will merge this list to join the final list = passed to + PEI core. + + @param[in,out] SecCoreData The same parameter as passing to PE= I core. It + could be overridden by this functio= n. + + @return The platform specific PPI list to be passed to PEI core or + NULL if there is no need of such platform specific PPI list. + +**/ +EFI_PEI_PPI_DESCRIPTOR * +EFIAPI +SecPlatformMain ( + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData + ) +{ + EFI_PEI_PPI_DESCRIPTOR *PpiList; + + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCo= reData->BootFirmwareVolumeBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCo= reData->BootFirmwareVolumeSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCo= reData->TemporaryRamBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCo= reData->TemporaryRamSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCo= reData->PeiTemporaryRamBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCo= reData->PeiTemporaryRamSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCo= reData->StackBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCo= reData->StackSize)); + + InitializeApicTimer (0, (UINT32) -1, TRUE, 5); + + // + // Set all 8259 interrupts to edge triggered and disabled + // + Interrupt8259WriteMask (0xFFFF, 0x0000); + + // + // Use middle of Heap as temp buffer, it will be copied by caller. + // Do not use Stack, because it will cause wrong calculation on stack by= PeiCore + // + PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)Se= cCoreData->PeiTemporaryRamSize/2); + CopyMem (PpiList, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi)); + + // + // Patch TopOfTemporaryRamPpi + // + PpiList[0].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCo= reData->TemporaryRamSize); + + return PpiList; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/WhiskeylakeOpenBoar= dPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c new file mode 100644 index 0000000000..06ca63c19a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/PlatformInit.c @@ -0,0 +1,54 @@ +/** @file + Provide platform init function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Platform initialization. + + @param[in] FspHobList HobList produced by FSP. + @param[in] StartOfRange Start of temporary RAM. + @param[in] EndOfRange End of temporary RAM. +**/ +VOID +EFIAPI +PlatformInit ( + IN VOID *FspHobList, + IN VOID *StartOfRange, + IN VOID *EndOfRange + ) +{ + /// + /// Halt the TCO timer as early as possible + /// + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, B_TCO_IO_TC= O1_CNT_TMR_HLT); + + // + // Platform initialization + // Enable Serial port here + // + if (PcdGetBool(PcdSecSerialPortDebugEnable)) { + SerialPortInitialize (); + } + + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n")); + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList)); + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange)); + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange)); + + BoardAfterTempRamInit (); + + TestPointTempMemoryFunction (StartOfRange, EndOfRange); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/WhiskeylakeOpe= nBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.= c new file mode 100644 index 0000000000..67bdd232bb --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecGetPerformance.c @@ -0,0 +1,90 @@ +/** @file + Sample to provide SecGetPerformance function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include +#include + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. + +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ) +{ + UINT32 Size; + UINT32 Count; + UINT32 TopOfTemporaryRam; + UINT64 Ticker; + VOID *TopOfTemporaryRamPpi; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SecGetPerformance\n")); + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gTopOfTemporaryRamPpiGuid, + 0, + NULL, + (VOID **) &TopOfTemporaryRamPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + // + // |--------------| <- TopOfTemporaryRam - BL + // | List Ptr | + // |--------------| + // | BL RAM Start | + // |--------------| + // | BL RAM End | + // |--------------| + // |Number of BSPs| + // |--------------| + // | BIST | + // |--------------| + // | .... | + // |--------------| + // | TSC[63:32] | + // |--------------| + // | TSC[31:00] | + // |--------------| + // + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT3= 2); + TopOfTemporaryRam -=3D sizeof(UINT32) * 2; + Count =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (U= INT32)); + Size =3D Count * sizeof (UINT32); + + Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze - sizeof (UINT32) * 2); + Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/Whiskeyla= keOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformIn= formation.c new file mode 100644 index 0000000000..e05daa8784 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecPlatformInformation.c @@ -0,0 +1,79 @@ +/** @file + Provide SecPlatformInformation function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param[in] PeiServices Pointer to the PEI Services Tab= le. + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer. + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ) +{ + UINT32 *Bist; + UINT32 Size; + UINT32 Count; + UINT32 TopOfTemporaryRam; + VOID *TopOfTemporaryRamPpi; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n")); + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gTopOfTemporaryRamPpiGuid, + 0, + NULL, + (VOID **) &TopOfTemporaryRamPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + // + // The entries of BIST information, together with the number of them, + // reside in the bottom of stack, left untouched by normal stack operati= on. + // This routine copies the BIST information to the buffer pointed by + // PlatformInformationRecord for output. + // + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT= 32); + TopOfTemporaryRam -=3D sizeof(UINT32) * 2; + Count =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (U= INT32))); + Size =3D Count * sizeof (IA32_HANDOFF_STATUS); + + if ((*StructureSize) < (UINT64) Size) { + *StructureSize =3D Size; + return EFI_BUFFER_TOO_SMALL; + } + + *StructureSize =3D Size; + Bist =3D (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze); + + CopyMem (PlatformInformationRecord, Bist, Size); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c new file mode 100644 index 0000000000..04f12a9438 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecRamInitData.c @@ -0,0 +1,37 @@ +/** @file + Provide TempRamInitParams data. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include "FsptCoreUpd.h" + +typedef struct { + FSP_UPD_HEADER FspUpdHeader; + FSPT_CORE_UPD FsptCoreUpd; +} FSPT_UPD_CORE_DATA; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr =3D = { + { + 0x4450555F54505346, + 0x00, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }, + { + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (= PcdFlashMicrocodeOffset)), + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3= 2 (PcdFlashMicrocodeOffset)), + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. + FixedPcdGet32 (PcdFlashCodeCacheSize), + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + } +}; + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c new file mode 100644 index 0000000000..6d65d7d23f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecTempRamDone.c @@ -0,0 +1,48 @@ +/** @file + Provide SecTemporaryRamDone function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +/** +This interface disables temporary memory in SEC Phase. +**/ +VOID +EFIAPI +SecPlatformDisableTemporaryMemory ( + VOID + ) +{ + EFI_STATUS Status; + VOID *TempRamExitParam; + + DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); + + Status =3D BoardInitBeforeTempRamExit (); + ASSERT_EFI_ERROR (Status); + + TempRamExitParam =3D UpdateTempRamExitParam (); + Status =3D CallTempRamExit (TempRamExitParam); + DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status)); + ASSERT_EFI_ERROR(Status); + + Status =3D BoardInitAfterTempRamExit (); + ASSERT_EFI_ERROR (Status); + + return ; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/Ba= seAcpiTimerLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimer= Lib/BaseAcpiTimerLib.c new file mode 100644 index 0000000000..7bdb3943e5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiT= imerLib.c @@ -0,0 +1,48 @@ +/** @file + ACPI Timer implements one instance of Timer Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Calculate TSC frequency. + + The TSC counting frequency is determined by comparing how far it counts + during a 101.4 us period as determined by the ACPI timer. + The ACPI timer is used because it counts at a known frequency. + The TSC is sampled, followed by waiting 363 counts of the ACPI timer, + or 101.4 us. The TSC is then sampled again. The difference multiplied by + 9861 is the TSC frequency. There will be a small error because of the + overhead of reading the ACPI timer. An attempt is made to determine and + compensate for this error. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalCalculateTscFrequency ( + VOID + ); + +/** + Internal function to retrieves the 64-bit frequency in Hz. + + Internal function to retrieves the 64-bit frequency in Hz. + + @return The frequency in Hz. + +**/ +UINT64 +InternalGetPerformanceCounterFrequency ( + VOID + ) +{ + return InternalCalculateTscFrequency (); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpande= rLib/BaseGpioExpanderLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library= /BaseGpioExpanderLib/BaseGpioExpanderLib.c new file mode 100644 index 0000000000..8498952888 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.c @@ -0,0 +1,310 @@ +/** @file + Support for IO expander TCA6424. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +// +// Addresses of registers inside expander +// +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mInputRegister[3] =3D {0x0,0x1,0x2= }; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mOutputRegister[3] =3D {0x4,0x5,0x6= }; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mConfigRegister[3] =3D {0xC,0xD,0xE= }; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPolarityRegister[3] =3D {0x8,0x9,0xA= }; + +#define PCH_SERIAL_IO_I2C4 4 +#define TCA6424_I2C_ADDRESS 0x22 +#define PINS_PER_REGISTER 8 +#define GPIO_EXP_PIN_DIRECTION_OUT 1 +#define GPIO_EXP_PIN_DIRECTION_IN 0 +#define GPIO_EXP_PIN_POLARITY_NORMAL 0 +#define GPIO_EXP_PIN_POLARITY_INVERTED 1 +#define GPIO_EXP_SET_OUTPUT 0 +#define GPIO_EXP_SET_DIR 1 +#define GPIO_EXP_GET_INPUT 2 +#define GPIO_EXP_SET_POLARITY 3 +#define AUTO_INCREMENT 0x80 + +/** + Returns the Controller on which GPIO expander is present. + + This function returns the Controller value + + @param[out] Controller Pointer to a Controller value on + which I2C expander is configured. + + @retval EFI_SUCCESS non. +**/ +EFI_STATUS +GpioExpGetController ( + OUT UINT8 *Controller + ) +{ + *Controller =3D PCH_SERIAL_IO_I2C4; + return EFI_SUCCESS; +} + +/** + Returns the data from register value giving in the input. + + This function is to get the data from the Expander + Registers by following the I2C Protocol communication + + + @param[in] Bar0 Bar address of the SerialIo Controller + @param[in] Address Expander Value with in the Contoller + @param[in] Register Address of Input/Output/Configure/Polarity + registers with in the Expander + + @retval UINT8 Value returned from the register +**/ +UINT8 +GpioExpGetRegister ( + IN UINTN Bar0, + IN UINT8 Address, + IN UINT8 Register + ) +{ + EFI_STATUS Status; + UINT8 WriBuf[1]; + UINT8 ReBuf[1] =3D {0}; + + WriBuf[0] =3D Register; + Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 1, WriBuf, 1= , ReBuf, WAIT_1_SECOND); + + return ReBuf[0]; +} +/** + Set the input register to a give value mentioned in the function. + + This function is to Programm the data value to the Expander + Register by following the I2C Protocol communication. + + @param[in] Bar0 Bar address of the SerialIo Controller + @param[in] Address Expander Value with in the Contoller + @param[in] Register Address of Input/Output/Configure/Polarity + registers with in the Expander + @param[in] Value Value to set in the mentioned the register +**/ +VOID +GpioExpSetRegister ( + IN UINTN Bar0, + IN UINT8 Address, + IN UINT8 Register, + IN UINT8 Value + ) +{ + EFI_STATUS Status; + UINT8 WriBuf[2]; + + WriBuf[0] =3D Register; + WriBuf[1] =3D Value; + Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 2, WriBuf, 0= , NULL, WAIT_1_SECOND); + +} +/** + Set the input register to a give value mentioned in the function. + + This function is to update the status of the Gpio Expander + pin based on the input Operation value of the caller.This + function calculates the exact address of the register with + the help of the Register Bank + + @param[in] Controller SerialIo Controller value + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none + @param[in] Operation Type of operation (Setoutput/Setdirection + /Getinput/Setpolarity) + @retval UINT8 Final Value returned from the register +**/ +UINT8 +GpioExpDecodeRegAccess ( + IN UINT8 Controller, + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Value, + IN UINT8 Operation + ) +{ + UINT8* RegisterBank; + UINT8 OldValue; + UINT8 NewValue; + UINT8 RegisterAddress; + UINT8 PinNumber; + UINT8 ReturnValue =3D 0; + + DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n", Control= ler, Expander, Pin, Value, Operation)); + ASSERT(Controller<6); + ASSERT(Expander<2); + ASSERT(Pin<24); + ASSERT(Value<2); + ASSERT(Operation<4); + // + // Find the register Address value based on the OPeration + // + switch(Operation) { + case GPIO_EXP_SET_OUTPUT: + RegisterBank =3D mOutputRegister; + break; + case GPIO_EXP_SET_DIR: + RegisterBank =3D mConfigRegister; + break; + case GPIO_EXP_GET_INPUT: + RegisterBank =3D mInputRegister; + break; + case GPIO_EXP_SET_POLARITY: + RegisterBank =3D mPolarityRegister; + break; + default: + ASSERT(FALSE); + return 0; + } + // + // Each bit of register represents each Pin + // calaulate the register address and Pinnumber(offset with in register) + // + if (Pin >=3D 24) { + // + // Avoid out-of-bound usage of RegisterBank + // + return 0; + } + + RegisterAddress =3D RegisterBank[(Pin/PINS_PER_REGISTER)]; + PinNumber =3D Pin%PINS_PER_REGISTER; + + OldValue =3D GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expander= , RegisterAddress); + // + // If it to get the data ,just returned otherwise mark the input value a= nd write the register + // + if (Operation =3D=3D GPIO_EXP_GET_INPUT) { + ReturnValue =3D 0x1 & (OldValue>>PinNumber); + } else { + NewValue =3D OldValue; + NewValue &=3D ~(BIT0<>8) & 0xFF; + WriteBuf[3] =3D (Output>>16) & 0xFF; + I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); + WriteBuf[0] =3D mPolarityRegister[0] + AUTO_INCREMENT; + WriteBuf[1] =3D Polarity & 0xFF; + WriteBuf[2] =3D (Polarity>>8) & 0xFF; + WriteBuf[3] =3D (Polarity>>16) & 0xFF; + I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); + WriteBuf[0] =3D mConfigRegister[0] + AUTO_INCREMENT; + WriteBuf[1] =3D Direction & 0xFF; + WriteBuf[2] =3D (Direction>>8) & 0xFF; + WriteBuf[3] =3D (Direction>>16) & 0xFF; + I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); + +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PeiHdaVerbTableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/P= eiHdaVerbTableLib/PeiHdaVerbTableLib.c new file mode 100644 index 0000000000..b8afd791f0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.c @@ -0,0 +1,132 @@ +/** @file + This file is SampleCode of the library for Intel HD Audio Verb Table con= figuration. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include "PchHdaVerbTables.h" + +/** + Add verb table helper function. + This function calculates verbtable number and shows verb table informati= on. + + @param[in,out] VerbTableEntryNum Input current VerbTable number and= output the number after adding new table + @param[in,out] VerbTableArray Pointer to array of VerbTable + @param[in] VerbTable VerbTable which is going to add in= to array +**/ +STATIC +VOID +InternalAddVerbTable ( + IN OUT UINT8 *VerbTableEntryNum, + IN OUT UINT32 *VerbTableArray, + IN HDAUDIO_VERB_TABLE *VerbTable + ) +{ + if (VerbTable =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "InternalAddVerbTable wrong input: VerbTable =3D= =3D NULL\n")); + return; + } + + VerbTableArray[*VerbTableEntryNum] =3D (UINT32) VerbTable; + *VerbTableEntryNum +=3D 1; + + DEBUG ((DEBUG_INFO, + "HDA: Add verb table for vendor =3D 0x%04X devId =3D 0x%04X (size =3D = %d DWords)\n", + VerbTable->Header.VendorId, + VerbTable->Header.DeviceId, + VerbTable->Header.DataDwords) + ); +} + +/** + Add verb table function. + This function update the verb table number and verb table ptr of policy. + + @param[in] HdAudioConfig HD Audio config block + @param[out] VerbTableEntryNum Number of verb table entries + @param[out] HdaVerbTablePtr Pointer to the verb table +**/ +VOID +AddPlatformVerbTables ( + IN UINT8 CodecType, + OUT UINT8 *VerbTableEntryNum, + OUT UINT32 *HdaVerbTablePtr + ) +{ + UINT8 VerbTableEntries; + UINT32 VerbTableArray[6]; + UINT32 *VerbTablePtr; + + VerbTableEntries =3D 0; + + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN= ) PcdGet32 (PcdDisplayAudioHdaVerbTable)); + + if (CodecType =3D=3D PchHdaCodecPlatformOnboard) { + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdHdaVerbTable2)); + } else { + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdCommonHdaVerbTable1)); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdCommonHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdCommonHdaVerbTable3)); + } + + *VerbTableEntryNum =3D VerbTableEntries; + + VerbTablePtr =3D (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTabl= eEntries); + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntrie= s); + *HdaVerbTablePtr =3D (UINT32) VerbTablePtr; +} + +/** + HDA VerbTable init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +HdaVerbTableInit ( + IN UINT16 BoardId + ) +{ + HDAUDIO_VERB_TABLE *VerbTable; + HDAUDIO_VERB_TABLE *VerbTable2; + + VerbTable =3D NULL; + VerbTable2 =3D NULL; + + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + VerbTable =3D &WhlHdaVerbTableAlc700; + break; + + default: + DEBUG ((DEBUG_INFO, "HDA: Init default verb tables (Realtek ALC700 a= nd ALC701)\n")); + VerbTable =3D &HdaVerbTableAlc700; + VerbTable2 =3D &HdaVerbTableAlc701; + break; + } + + PcdSet32S (PcdHdaVerbTable, (UINT32) VerbTable); + PcdSet32S (PcdHdaVerbTable2, (UINT32) VerbTable2); + PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINT32) &HdaVerbTableDisplayAud= io); + + // Codecs - Realtek ALC700, ALC701, ALC274 (external - connected via HDA= header) + PcdSet32S (PcdCommonHdaVerbTable1, (UINT32) &HdaVerbTableAlc700); + PcdSet32S (PcdCommonHdaVerbTable2, (UINT32) &HdaVerbTableAlc701); + PcdSet32S (PcdCommonHdaVerbTable3, (UINT32) &HdaVerbTableAlc274); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib= /PeiI2cAccessLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cA= ccessLib/PeiI2cAccessLib.c new file mode 100644 index 0000000000..70f531daca --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2c= AccessLib.c @@ -0,0 +1,115 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +EFI_STATUS +I2cWriteRead ( + IN UINTN MmioBase, + IN UINT8 SlaveAddress, + IN UINT8 WriteLength, + IN UINT8 *WriteBuffer, + IN UINT8 ReadLength, + IN UINT8 *ReadBuffer, + IN UINT64 TimeBudget + //TODO: add Speed parameter + ) +{ + UINT8 ReadsNeeded =3D ReadLength; + UINT64 CutOffTime; + + if ((WriteLength =3D=3D 0 && ReadLength =3D=3D 0) || + (WriteLength !=3D 0 && WriteBuffer =3D=3D NULL) || + (ReadLength !=3D 0 && ReadBuffer =3D=3D NULL) ) { + DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n")); + return EFI_INVALID_PARAMETER; + } + + // + // Sanity checks to verify the I2C controller is alive + // Conveniently, ICON register's values of 0 or FFFFFFFF indicate + // I2c controller is out-of-order: either disabled, in D3 or in reset. + // + if (MmioRead32(MmioBase+R_IC_CON) =3D=3D 0xFFFFFFFF || MmioRead32(MmioBa= se+R_IC_CON) =3D=3D 0x0) { + DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n")); + return EFI_DEVICE_ERROR; + } + + MmioWrite32(MmioBase+R_IC_ENABLE, 0x0); + MmioRead32(MmioBase+0x40); + MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); + MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C); + // + // Set I2C Bus Speed at 400 kHz for GPIO Expander + // + MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128); + MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160); + MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress); + MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE | V_IC_SPEED_FAST | B_= IC_RESTART_EN | B_IC_SLAVE_DISABLE ); + MmioWrite32(MmioBase+R_IC_ENABLE, 0x1); + CutOffTime =3D AsmReadTsc() + TimeBudget; + + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D0 ) { + if (AsmReadTsc() > CutOffTime) { + DEBUG ((DEBUG_ERROR, "I2cWR timeout\n")); + return EFI_TIMEOUT; + } + } + + while(1) { + if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) { + DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason =3D 0x%08x\n",M= mioRead32(MmioBase+R_IC_TX_ABRT_SOURCE))); + MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} + return EFI_DEVICE_ERROR; + } + if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) { + if (WriteLength > 1) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); + WriteBuffer++; + WriteLength--; + } else if (WriteLength=3D=3D1 && ReadLength !=3D 0) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); + WriteBuffer++; + WriteLength--; + } else if (WriteLength=3D=3D1 && ReadLength =3D=3D 0) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer | B_IC_CMD_STOP); + WriteBuffer++; + WriteLength--; + } else if (ReadLength > 1) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ); + ReadLength--; + } else if (ReadLength =3D=3D 1) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ|B_IC_CMD_STOP); + ReadLength--; + } + } + + if (ReadsNeeded) { + if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) { + *ReadBuffer =3D (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD); + ReadBuffer++; + ReadsNeeded--; + } + } + if (WriteLength=3D=3D0 && ReadsNeeded=3D=3D0 && !(MmioRead32(MmioBase+= R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) { + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} + DEBUG ((DEBUG_INFO, "I2cWR success\n")); + return EFI_SUCCESS; + } + if (AsmReadTsc() > CutOffTime) { + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} + DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n")); + return EFI_TIMEOUT; + } + + } +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeCpuPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/DxePolicyUpdateLib/DxeCpuPolicyUpdate.c new file mode 100644 index 0000000000..7b9a32b3f5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeCpuPolicyUpdate.c @@ -0,0 +1,88 @@ +/** @file + This file is the library for CPU DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + This function prints the CPU DXE phase policy. + + @param[in] DxeCpuPolicy - CPU DXE Policy protocol +**/ +VOID +CpuDxePrintPolicyProtocol ( + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ) +{ + DEBUG_CODE_BEGIN (); + DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print B= EGIN -----------------\n")); + DEBUG ((DEBUG_INFO, "Revision : %x\n", DxeCpuPolicy->Revision)); + ASSERT (DxeCpuPolicy->Revision =3D=3D DXE_CPU_POLICY_PROTOCOL_REVISION); + DEBUG ((DEBUG_INFO, "\n------------------------ CPU_DXE_CONFIG ---------= --------\n")); + DEBUG ((DEBUG_INFO, "EnableDts : %x\n", DxeCpuPolicy->EnableDts)); + DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print E= ND -----------------\n")); + DEBUG_CODE_END (); +} + +/** + Get data for CPU policy from setup options. + + @param[in] DxeCpuPolicy The pointer to get CPU Policy proto= col instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSiCpuPolicy ( + IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ) +{ + return EFI_SUCCESS; +} + +/** + CpuInstallPolicyProtocol installs CPU Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol= instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +CpuInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ) +{ + EFI_STATUS Status; + + /// + /// Print CPU DXE Policy + /// + CpuDxePrintPolicyProtocol(DxeCpuPolicy); + + /// + /// Install the DXE_CPU_POLICY_PROTOCOL interface + /// + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gDxeCpuPolicyProtocolGuid, + DxeCpuPolicy, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeMePolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.c new file mode 100644 index 0000000000..863df3328c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeMePolicyUpdate.c @@ -0,0 +1,105 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "DxeMePolicyUpdate.h" + +// +// Record version +// +#define RECORD_REVISION_1 0x01 +#define MAX_FW_UPDATE_BIOS_SELECTIONS 2 + +// +// Function implementations executed during policy initialization phase +// + +/** + Update the ME Policy Library + + @param[in, out] DxeMePolicy The pointer to get ME Policy proto= col instance + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this= driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to in= itialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnorma= lly. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeMePolicy ( + IN OUT ME_POLICY_PROTOCOL *DxeMePolicy + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + DEBUG ((DEBUG_INFO, "UpdateDxeMePolicy\n")); + UpdateMePolicyFromSetup (DxeMePolicy); + UpdateMePolicyFromMeSetup (DxeMePolicy); + + // + // Register End of DXE event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + UpdateMeSetupCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + Update ME Policy while MePlatformProtocol is installed. + + @param[in] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromMeSetup ( + IN ME_POLICY_PROTOCOL *MePolicyInstance + ) +{ + +} + +/** + Update ME Policy if Setup variable exists. + + @param[in, out] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromSetup ( + IN OUT ME_POLICY_PROTOCOL *MePolicyInstance + ) +{ + +} + +/** + Functions performs HECI exchange with FW to update MePolicy settings. + + @param[in] Event A pointer to the Event that triggered the callb= ack. + @param[in] Context A pointer to private data registered with the c= allback function. + +**/ +VOID +EFIAPI +UpdateMeSetupCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gBS->CloseEvent (Event); + + return; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxePchPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/DxePolicyUpdateLib/DxePchPolicyUpdate.c new file mode 100644 index 0000000000..7945986aaa --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxePchPolicyUpdate.c @@ -0,0 +1,39 @@ +/** @file + This file is the library for PCH DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Get data for PCH policy from setup options. + + @param[in] PchPolicy The pointer to get PCH Policy proto= col instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxePchPolicy ( + IN OUT PCH_POLICY_PROTOCOL *PchPolicy + ) +{ + EFI_STATUS Status; + PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig; + + Status =3D GetConfigBlock ((VOID *)PchPolicy, &gHdAudioDxeConfigGuid, (V= OID *)&HdAudioDxeConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.c new file mode 100644 index 0000000000..af4c76bcd0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeSaPolicyUpdate.c @@ -0,0 +1,57 @@ +/** @file + This file is the library for SA DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protoc= ol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + PCIE_DXE_CONFIG *PcieDxeConfig; + MISC_DXE_CONFIG *MiscDxeConfig; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + GraphicsDxeConfig =3D NULL; + PcieDxeConfig =3D NULL; + MiscDxeConfig =3D NULL; + MemoryDxeConfig =3D NULL; + // + // Get requisite IP Config Blocks which needs to be used here + // + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (V= OID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID = *)&MiscDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOID = *)&PcieDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMemoryDxeConfigGuid, (VOI= D *)&MemoryDxeConfig); + ASSERT_EFI_ERROR (Status); + + PcieDxeConfig->PegAspmL0s[0] =3D 3; + PcieDxeConfig->PegAspmL0s[1] =3D 3; + PcieDxeConfig->PegAspmL0s[2] =3D 3; + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Li= brary/PeiPolicyInitLib/PeiPolicyInit.c new file mode 100644 index 0000000000..93be38a832 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInit.c @@ -0,0 +1,65 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyInit.h" + +/** + Initialize Intel PEI Platform Policy + + @param[in] PeiServices General purpose services available to = every PEIM. + @param[in] FirmwareConfiguration It uses to skip specific policy init t= hat depends + on the 'FirmwareConfiguration' varaibl= e. +**/ +VOID +EFIAPI +PeiPolicyInit ( + IN UINT8 FirmwareConfiguration + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + + // + // Call SiCreateConfigBlocks to initialize Silicon Policy structure + // and get all Intel default policy settings. + // + Status =3D SiCreateConfigBlocks (&SiPolicyPpi); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return; + } + + if (PcdGetBool (PcdDumpDefaultSiliconPolicy)) { + DEBUG ((DEBUG_INFO, "Dump Default Silicon Policy...\n")); + DumpSiPolicy (SiPolicyPpi); + } + + // + // Update policy by board configuration + // + UpdatePeiSiPolicyBoardConfig (SiPolicyPpi); + UpdatePeiPchPolicyBoardConfig (SiPolicyPpi); + UpdatePeiSaPolicyBoardConfig (SiPolicyPpi); + UpdatePeiCpuPolicyBoardConfig (SiPolicyPpi); + UpdatePeiMePolicyBoardConfig (SiPolicyPpi); + + UpdatePeiSiPolicy(SiPolicyPpi); + UpdatePeiPchPolicy(SiPolicyPpi); + UpdatePeiSaPolicy(SiPolicyPpi); + UpdatePeiCpuPolicy(SiPolicyPpi); + UpdatePeiMePolicy(SiPolicyPpi); + + // + // Install SiPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D SiInstallPolicyPpi (SiPolicyPpi); + ASSERT_EFI_ERROR (Status); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInitPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyInitLib/PeiPolicyInitPreMem.c new file mode 100644 index 0000000000..9f8014b72a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInitPreMem.c @@ -0,0 +1,60 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyInit.h" + +/** + Initialize Intel PEI Platform Policy + + @param[in] FirmwareConfiguration It uses to skip specific policy init = that depends + on the 'FirmwareConfiguration' varaib= le. +**/ +VOID +EFIAPI +PeiPolicyInitPreMem ( + IN UINT8 FirmwareConfiguration + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memo= ry...\n")); + // + // Call SiCreatePreMemConfigBlocks to initialize platform policy structu= re + // and get all intel default policy settings. + // + Status =3D SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + // + // Update policy by board configuration + // + UpdatePeiPchPolicyBoardConfigPreMem (SiPreMemPolicyPpi); + UpdatePeiMePolicyBoardConfigPreMem (SiPreMemPolicyPpi); + UpdatePeiSaPolicyBoardConfigPreMem (SiPreMemPolicyPpi); + UpdatePeiCpuPolicyBoardConfigPreMem (SiPreMemPolicyPpi); + + // + // Update and override all platform related and customized settings belo= w. + // + UpdatePeiPchPolicyPreMem (SiPreMemPolicyPpi); + UpdatePeiMePolicyPreMem (SiPreMemPolicyPpi); + UpdatePeiSaPolicyPreMem (SiPreMemPolicyPpi); + UpdatePeiCpuPolicyPreMem (SiPreMemPolicyPpi); + + // + // Install SiPreMemPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memor= y\n")); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiSaPolicyInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiSaPolicyInit.c new file mode 100644 index 0000000000..922bcd135f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiSaPolicyInit.c @@ -0,0 +1,114 @@ +/** @file + This file is SampleCode for Intel SA PEI Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyInit.h" + + +/** + PcieCardResetWorkAround performs PCIe Card reset on root port + + @param[in out] SiPreMemPolicyPpi SI_PREMEM_POLICY_PPI + + @retval EFI_SUCCESS The policy is installed and initialized= . +**/ +EFI_STATUS + PcieCardResetWorkAround ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData; + + Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSaMiscPeiPreMemCo= nfigGuid, (VOID *)&MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSwitchableGraphic= sConfigGuid, (VOID *)&SgGpioData); + ASSERT_EFI_ERROR(Status); + + if (SgGpioData->SaRtd3Pcie0Gpio.GpioSupport !=3D NotSupported) { + /// + /// dGPU is present. + /// If PCIe Mode or SG Muxless + /// Power on MXM + /// Configure GPIOs to drive MXM in PCIe mode or SG Muxle= ss + /// else + /// Do Nothing + /// + if ((MiscPeiPreMemConfig->SgMode =3D=3D SgModeMuxless) || + (MiscPeiPreMemConfig->SgMode =3D=3D SgModeDgpu)) { + DEBUG((DEBUG_INFO, "Configure GPIOs for driving the dGPU.\n")); + /// + /// Drive DGPU HOLD RST Enable to make sure we hold reset + /// + PcieGpioWrite ( + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo, + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active, + GP_ENABLE + ); + /// + /// wait 100ms + /// + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STAL= L_ONE_MILLI_SECOND); + + /// + /// Drive DGPU PWR EN to Power On MXM + /// + PcieGpioWrite ( + SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.GpioNo, + SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.Active, + GP_ENABLE + ); + /// + /// wait 300ms + /// + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterPwrEn) * STALL_ON= E_MILLI_SECOND); + + /// + /// Drive DGPU HOLD RST Disabled to remove reset + /// + PcieGpioWrite ( + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo, + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active, + GP_DISABLE + ); + /// + /// wait 100ms + /// + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STAL= L_ONE_MILLI_SECOND); + } + } + return EFI_SUCCESS; +} + +/** + PCIe GPIO Write + + @param[in] Gpio - GPIO Number + @param[in] Active - GPIO Active Information; High/Low + @param[in] Level - Write GPIO value (0/1) + +**/ +VOID +PcieGpioWrite ( + IN UINT32 Gpio, + IN BOOLEAN Active, + IN BOOLEAN Level + ) +{ + EFI_STATUS Status; + + if (Active =3D=3D 0) { + Level =3D (~Level) & 0x1; + } + Status =3D GpioSetOutputValue(Gpio, (UINT32)Level); + if (Status !=3D EFI_SUCCESS) { + return; + } +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c new file mode 100644 index 0000000000..144480a83d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiCpuPolicyUpdate.c @@ -0,0 +1,80 @@ +/** @file + CPU PEI Policy Update & initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyUpdate.h" +#include +#include +#include +#include + +/** + This function performs CPU PEI Policy initialization. + + @param[in] SiPolicyPpi The SI Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial= ize the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + CPU_CONFIG *CpuConfig; + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + CPU_TEST_CONFIG *CpuTestConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf= igGuid, (VOID *) &CpuPowerMgmtBasicConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtCustomConfi= gGuid, (VOID *)&CpuPowerMgmtCustomConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuTestConfigGuid, (VOI= D *)&CpuTestConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtTestConfigG= uid, (VOID *)&CpuPowerMgmtTestConfig); + ASSERT_EFI_ERROR(Status); + + // + // Init Power Management Policy Variables + // + CpuPowerMgmtBasicConfig->HwpInterruptControl =3D 1; + CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio =3D 0x4; + CpuPowerMgmtBasicConfig->OneCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->TwoCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->FourCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->FiveCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->SixCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->SevenCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->EightCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->Hwp =3D 0x1; + CpuTestConfig->CpuWakeUpTimer =3D 1; + CpuPowerMgmtTestConfig->AutoThermalReporting =3D 0; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c new file mode 100644 index 0000000000..bce02a9c5a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiCpuPolicyUpdatePreMem.c @@ -0,0 +1,108 @@ +/** @file + This file is SampleCode of the library for Intel CPU PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyUpdate.h" +#include +#include +#include +#include +#include + +/** + Check on the processor if SGX is supported. + + @retval True if SGX supported or FALSE if not +**/ +BOOLEAN +IsSgxCapSupported ( + VOID + ) +{ + EFI_CPUID_REGISTER CpuidRegs; + + /// + /// Processor support SGX feature by reading CPUID.(EAX=3D7,ECX=3D0):EBX= [2] + /// + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, &CpuidRegs.RegEa= x,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.RegEdx); + + /// + /// SGX feature is supported only on WHL and later, + /// with CPUID.(EAX=3D7,ECX=3D0):EBX[2]=3D1 + /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] =3D=3D 1 + /// + if ((CpuidRegs.RegEbx & BIT2) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & BIT1= 2)) { + return TRUE; + } + + return FALSE; +} + +/** + This function performs CPU PEI Policy initialization in Pre-memory. + + @param[in] SiPreMemPolicyPpi The SI Pre-Mem Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial= ize the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig; + UINT32 PchSpiBar0; + UINT32 MaxLogicProcessors; + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking= PreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "UpdatePeiCpuPolicyPreMem Start\n")); + + // + // Get current boot mode + // + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + SpiServiceInit (); + + PchSpiBar0 =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + R_SPI_CFG_BAR0 + )); + PchSpiBar0 &=3D ~(B_SPI_CFG_BAR0_MASK); + + if (PchSpiBar0 =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n")); + ASSERT (FALSE); + } + + CpuConfigLibPreMemConfig->PeciC10Reset =3D 0; + CpuConfigLibPreMemConfig->CpuRatio =3D 0; + /// + /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical process= ors enabled + /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads + /// + MaxLogicProcessors =3D (UINT32) (AsmReadMsr64 (MSR_CORE_THREAD_COUNT) & = B_THREAD_COUNT_MASK); + DEBUG ((DEBUG_INFO, "MaxLogicProcessors =3D %d\n", MaxLogicProcessors)); + PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiMePolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c new file mode 100644 index 0000000000..e557f04971 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiMePolicyUpdate.c @@ -0,0 +1,49 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiMePolicyUpdate.h" +#include +#include +#include +#include +#include + +/** + Update the ME Policy Library + + @param[in, out] SiPolicyPpi The pointer to SiPolicyPpi + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +UpdatePeiMePolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG ((DEBUG_INFO, "UpdatePeiMePolicy\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI= D *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + if (!PmcIsRtcBatteryGood ()) { + // + // For non coin battery design, this can be skipped. + // + MePeiConfig->MeUnconfigOnRtcClear =3D 2; + } + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiMePolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c new file mode 100644 index 0000000000..de9849b807 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiMePolicyUpdatePreMem.c @@ -0,0 +1,32 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiMePolicyUpdate.h" +#include +#include +#include + +/** + Update the ME Policy Library + + @param[in] SiPreMemPolicyPpi The pointer to SiPreMemPolicyPpi + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +UpdatePeiMePolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "UpdatePeiMePolicyPreMem\n")); + + Status =3D EFI_SUCCESS; + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c new file mode 100644 index 0000000000..3e44c6cc29 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdate.c @@ -0,0 +1,523 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +UpdatePcieClockInfo ( + PCH_PCIE_CONFIG *PcieRpConfig, + UINTN Index, + UINT64 Data + ) +{ + PCD64_BLOB Pcd64; + + Pcd64.Blob =3D Data; + DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Suppor= ted %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupport= ed)); + + PcieRpConfig->PcieClock[Index].Usage =3D (UINT8)Pcd64.PcieClock.ClockUsa= ge; + if (Pcd64.PcieClock.ClkReqSupported) { + PcieRpConfig->PcieClock[Index].ClkReq =3D (UINT8)Index; + } else { + PcieRpConfig->PcieClock[Index].ClkReq =3D 0xFF; + } +} + +/** + This is helper function for getting I2C Pads Internal Termination settin= gs from Pcd + + @param[in] Index I2C Controller Index +**/ +UINT8 +GetSerialIoI2cPadsTerminationFromPcd ( + IN UINT8 Index +) +{ + switch (Index) { + case 0: + return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm); + case 1: + return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm); + case 2: + return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm); + case 3: + return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm); + case 4: + return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm); + case 5: + return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm); + default: + ASSERT (FALSE); // Invalid I2C Controller Index + } + return 0; +} +/** + This is a helper function for updating USB Policy according to Blob data + + @param[in] UsbConfig Pointer to USB_CONFIG data buffer + @param[in] PortIndex USB Port index + @param[in] Data32 Blob containing USB2 Afe (PCD32_BLOB) data +**/ +VOID +UpdateUsb20AfePolicy ( + IN USB_CONFIG *UsbConfig, + IN UINT8 PortIndex, + UINT32 Data32 +) +{ + PCD32_BLOB Pcd32; + Pcd32.Blob =3D Data32; + + if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset !=3D 0) { + UsbConfig->PortUsb20[PortIndex].Afe.Petxiset =3D Pcd32.Info.Petxis= et; + UsbConfig->PortUsb20[PortIndex].Afe.Txiset =3D Pcd32.Info.Txiset= ; + UsbConfig->PortUsb20[PortIndex].Afe.Predeemp =3D Pcd32.Info.Predee= mp; + UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit =3D Pcd32.Info.Pehalf= bit; + } +} + +/** + This function updates USB Policy per port OC Pin number + + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer + @param[in] PortIndex USB Port index + @param[in] Pin OverCurrent pin number +**/ +VOID +UpdateUsb20OverCurrentPolicy ( + IN USB_CONFIG *UsbConfig, + IN UINT8 PortIndex, + UINT8 Pin +) +{ + if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin = =3D=3D UsbOverCurrentPinSkip))) { + UsbConfig->PortUsb20[PortIndex].OverCurrentPin =3D Pin; + } else { + if (PortIndex >=3D MAX_USB2_PORTS) { + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number= %d is not a valid USB2 port number\n", PortIndex)); + } else { + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurr= ent pin specified USB2 port %d\n", PortIndex)); + } + } +} + +/** + This function updates USB Policy per port OC Pin number + + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer + @param[in] PortIndex USB Port index + @param[in] Pin OverCurrent pin number +**/ +VOID +UpdateUsb30OverCurrentPolicy ( + IN USB_CONFIG *UsbConfig, + IN UINT8 PortIndex, + UINT8 Pin +) +{ + if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin = =3D=3D UsbOverCurrentPinSkip))) { + UsbConfig->PortUsb30[PortIndex].OverCurrentPin =3D Pin; + } else { + if (PortIndex >=3D MAX_USB2_PORTS) { + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number= %d is not a valid USB3 port number\n", PortIndex)); + } else { + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurr= ent pin specified USB3 port %d\n", PortIndex)); + } + } +} + +/** + This function performs PCH USB Platform Policy initialization + + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer + @param[in] PchSetup Pointer to PCH_SETUP data buffer +**/ +VOID +UpdatePchUsbConfig ( + IN USB_CONFIG *UsbConfig + ) +{ + UINTN PortIndex; + + UsbConfig->OverCurrentEnable =3D TRUE; + + for (PortIndex =3D 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortI= ndex++) { + UsbConfig->PortUsb20[PortIndex].Enable =3D TRUE; + } + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex= ++) { + UsbConfig->PortUsb30[PortIndex].Enable =3D TRUE; + } + + UsbConfig->XdciConfig.Enable =3D FALSE; + + + // + // USB2 AFE settings. + // + UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe)); + UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe)); + UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe)); + UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe)); + UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe)); + UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe)); + UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe)); + UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe)); + UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe)); + UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe)); + UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe)); + UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe)); + UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe)); + UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe)); + UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe)); + UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe)); + + // + // Platform Board programming per the layout of each port. + // + UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrent= PinPort0)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrent= PinPort1)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrent= PinPort2)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrent= PinPort3)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrent= PinPort4)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrent= PinPort5)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrent= PinPort6)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrent= PinPort7)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrent= PinPort8)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrent= PinPort9)); + UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 (PcdUsb20OverCurrent= PinPort10)); + UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 (PcdUsb20OverCurrent= PinPort11)); + UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 (PcdUsb20OverCurrent= PinPort12)); + UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 (PcdUsb20OverCurrent= PinPort13)); + UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 (PcdUsb20OverCurrent= PinPort14)); + UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 (PcdUsb20OverCurrent= PinPort15)); + + UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrent= PinPort0)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrent= PinPort1)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrent= PinPort2)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrent= PinPort3)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrent= PinPort4)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrent= PinPort5)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrent= PinPort6)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrent= PinPort7)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrent= PinPort8)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrent= PinPort9)); + +} + +/** + Return if input ImageGuid belongs to system FMP GUID list. + + @param[in] ImageGuid A pointer to GUID + + @retval TRUE ImageGuid is in the list of PcdSystemFmpCapsuleImageTypeId= Guid + @retval FALSE ImageGuid is not in the list of PcdSystemFmpCapsuleImageTy= peIdGuid +**/ +BOOLEAN +IsSystemFmpGuid ( + IN GUID *ImageGuid + ) +{ + GUID *Guid; + UINTN Count; + UINTN Index; + + Guid =3D PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid); + Count =3D PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof (GUID= ); + + for (Index =3D 0; Index < Count; Index++, Guid++) { + if (CompareGuid (ImageGuid, Guid)) { + return TRUE; + } + } + + return FALSE; +} + +/** + This function performs PCH PEI Policy initialization. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT SI_POLICY_PPI *SiPolicy + ) +{ + EFI_STATUS Status; + UINT8 Index; + DMI_HW_WIDTH_CONTROL *DmiHaAWC; + UINT16 LpcDid; + PCH_GENERAL_CONFIG *PchGeneralConfig; + PCH_PCIE_CONFIG *PcieRpConfig; + PCH_SATA_CONFIG *SataConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_DMI_CONFIG *DmiConfig; + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + PCH_HDAUDIO_CONFIG *HdAudioConfig; + PCH_INTERRUPT_CONFIG *InterruptConfig; + PCH_ISH_CONFIG *IshConfig; + PCH_LAN_CONFIG *LanConfig; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_PM_CONFIG *PmConfig; + PCH_SCS_CONFIG *ScsConfig; + PCH_SERIAL_IO_CONFIG *SerialIoConfig; + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; + PCH_THERMAL_CONFIG *ThermalConfig; + USB_CONFIG *UsbConfig; + PCH_ESPI_CONFIG *EspiConfig; + PCH_CNVI_CONFIG *CnviConfig; + PEI_TBT_POLICY *PeiTbtPolicy; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (V= OID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID = *) &PcieRpConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)= &SataConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID = *) &IoApicConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) = &DmiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGui= d, (VOID *) &FlashProtectionConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID= *) &HdAudioConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VO= ID *) &InterruptConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) = &IshConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) = &LanConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOI= D *) &LockDownConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &= PmConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) = &ScsConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI= D *) &SerialIoConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VO= ID *) &SerialIrqConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID= *) &ThermalConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) = &UsbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *)= &EspiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *)= &CnviConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + + PeiTbtPolicy =3D NULL; + LpcDid =3D PchGetLpcDid (); + + DmiConfig->PwrOptEnable =3D TRUE; + PmConfig->PchSlpS3MinAssert =3D 0; + PmConfig->PchSlpS4MinAssert =3D 0; + PmConfig->PchSlpSusMinAssert =3D 0; + PmConfig->PchSlpAMinAssert =3D 0; + + SataConfig->ThermalThrottling.P1T3M =3D 3; + SataConfig->ThermalThrottling.P1T2M =3D 2; + SataConfig->ThermalThrottling.P1T1M =3D 1; + SataConfig->ThermalThrottling.P0T3M =3D 3; + SataConfig->ThermalThrottling.P0T2M =3D 2; + SataConfig->ThermalThrottling.P0T1M =3D 1; + + UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64 (PcdPcieClock0)); + UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64 (PcdPcieClock1)); + UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64 (PcdPcieClock2)); + UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64 (PcdPcieClock3)); + UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64 (PcdPcieClock4)); + UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64 (PcdPcieClock5)); + UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64 (PcdPcieClock6)); + UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64 (PcdPcieClock7)); + UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64 (PcdPcieClock8)); + UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64 (PcdPcieClock9)); + UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10)); + UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11)); + UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12)); + UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13)); + UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14)); + UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15)); + + PcieRpConfig->PcieDeviceOverrideTablePtr =3D (UINT32) mPcieDeviceTable; + PcieRpConfig->RootPort[0].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[1].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[2].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[3].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[4].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[5].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[6].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[7].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[8].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[9].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[10].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[11].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[12].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[13].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[14].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[15].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[0].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[1].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[2].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[3].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[4].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[5].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[6].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[7].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[8].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[9].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[10].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[11].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[12].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[13].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[14].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[15].AdvancedErrorReporting =3D TRUE; + + // + // Install HDA Link/iDisplay Codec Verb Table + // + AddPlatformVerbTables ( + PchHdaCodecPlatformOnboard, + &(HdAudioConfig->VerbTableEntryNum), + &(HdAudioConfig->VerbTablePtr) + ); + + LockDownConfig->BiosLock =3D FALSE; + LockDownConfig->BiosInterface =3D FALSE; + + // + // IOAPIC Config + // +// IoApicConfig->IoApicEntry24_119 =3D PchSetup.PchIoApic24119Entries= ; + // + // To support SLP_S0, it's required to disable 8254 timer. + // Note that CSM may require this option to be disabled for correct oper= ation. + // Once 8254 timer disabled, some legacy OPROM and legacy OS will fail w= hile using 8254 timer. + // For some OS environment that it needs to set 8254CGE in late state it= should + // set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in S= MM later. + // This is also required during S3 resume. + // + // The Enable8254ClockGatingOnS3 is only applicable when Enable8254Clock= Gating is disabled. + // If Enable8254ClockGating is enabled, RC will do 8254 CGE programming = on S3 as well. + // else, RC will do the programming on S3 when Enable8254ClockGatingOnS3= is enabled. + // This avoids the SMI requirement for the programming. + // + // If S0ix is not enabled, then disable 8254CGE for leagcy boot case. + // + IoApicConfig->Enable8254ClockGating =3D FALSE; + IoApicConfig->Enable8254ClockGatingOnS3 =3D FALSE; + + // + // SerialIo Config + // + SerialIoConfig->DevMode[0] =3D 1; + SerialIoConfig->DevMode[1] =3D 1; + SerialIoConfig->DevMode[2] =3D 0; + SerialIoConfig->DevMode[3] =3D 0; + SerialIoConfig->DevMode[4] =3D 1; + SerialIoConfig->DevMode[5] =3D 0; + SerialIoConfig->DevMode[6] =3D 0; + SerialIoConfig->DevMode[7] =3D 0; + SerialIoConfig->DevMode[8] =3D 0; + SerialIoConfig->DevMode[9] =3D 0; + SerialIoConfig->DevMode[10] =3D 0; + SerialIoConfig->DevMode[11] =3D 3; + + SerialIoConfig->Uart0PinMuxing =3D 1; + SerialIoConfig->SpiCsPolarity[0] =3D 1; + SerialIoConfig->SpiCsPolarity[1] =3D 0; + SerialIoConfig->SpiCsPolarity[2] =3D 0; + + SerialIoConfig->UartHwFlowCtrl[0] =3D 1; + SerialIoConfig->UartHwFlowCtrl[1] =3D 1; + SerialIoConfig->UartHwFlowCtrl[2] =3D 1; + // + // I2C4 and I2C5 don't exist in SPT-H chipset + // + if (IsPchH ()) { + SerialIoConfig->DevMode[PchSerialIoIndexI2C4] =3D PchSerialIoDisabled; + SerialIoConfig->DevMode[PchSerialIoIndexI2C5] =3D PchSerialIoDisabled; + } + + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++= ) { + SerialIoConfig->I2cPadsTermination[Index] =3D GetSerialIoI2cPadsTermin= ationFromPcd (Index); + } + + PmConfig->SlpS0Override =3D 2; //PchSetup.SlpS0O= verride; + PmConfig->SlpS0DisQForDebug =3D 3; //PchSetup.SlpS0= DisQForDebug; + PmConfig->SlpS0Vm075VSupport =3D 1; // PcdGetBool(Pcd= SlpS0Vm075VSupport); + PmConfig->CpuC10GatePinEnable =3D 1; + + // + // Thermal Config + // + ThermalConfig->TsmicLock =3D TRUE; + ThermalConfig->PchHotEnable =3D PcdGetBool (PcdPchThermalHotEnabl= e); + + DmiHaAWC =3D &ThermalConfig->DmiHaAWC; + DmiHaAWC->TS3TW =3D 0; + DmiHaAWC->TS2TW =3D 1; + DmiHaAWC->TS1TW =3D 2; + DmiHaAWC->TS0TW =3D 3; + // + // Update Pch Usb Config + // + UpdatePchUsbConfig ( + UsbConfig + ); + + ScsConfig->ScsUfsEnabled =3D 0; + ScsConfig->ScsEmmcHs400Enabled =3D 1; + ScsConfig->ScsEmmcHs400TuningRequired =3D TRUE; + + IshConfig->I2c0GpioAssign =3D 1; + IshConfig->I2c1GpioAssign =3D 1; + IshConfig->Gp0GpioAssign =3D 1; + IshConfig->Gp1GpioAssign =3D 1; + IshConfig->Gp2GpioAssign =3D 1; + IshConfig->Gp3GpioAssign =3D 1; + IshConfig->Gp4GpioAssign =3D 1; + IshConfig->Gp5GpioAssign =3D 1; + IshConfig->Gp6GpioAssign =3D 1; + + return Status; +} diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c new file mode 100644 index 0000000000..968df0f55c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,113 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only= ) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + + +/** + This function performs PCH PEI Policy initialization. + + @param[in, out] SiPreMemPolicy The SI PREMEM Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy + ) +{ + EFI_STATUS Status; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; + PCH_WDT_PREMEM_CONFIG *WatchDogPreMemConfig; + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemCo= nfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemC= onfigGuid, (VOID *) &PchTraceHubPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigG= uid, (VOID *) &SmbusPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGui= d, (VOID *) &LpcPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConf= igGuid, (VOID *) &WatchDogPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGui= d, (VOID *) &DciPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig= Guid, (VOID *) &PcieRpPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfi= gGuid, (VOID *) &HdaPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGui= d, (VOID *) &IshPreMemConfig); + ASSERT_EFI_ERROR (Status); + + DciPreMemConfig->DciUsb3TypecUfpDbg =3D 2; + PchTraceHubPreMemConfig->MemReg0Size =3D 3; + PchTraceHubPreMemConfig->MemReg1Size =3D 3; + // + // SMBUS + // + SmbusPreMemConfig->Enable =3D TRUE; + SmbusPreMemConfig->SmbAlertEnable =3D PcdGetBool (PcdSmbusAlertEnable); + // + // SMBUS reserved addresses + // + SmBusReservedTable =3D NULL; + SmBusReservedNum =3D 0; + SmbusPreMemConfig->SmbusIoBase =3D PcdGet16 (PcdSmbusBaseAddress); + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable !=3D NULL) { + SmbusPreMemConfig->NumRsvdSmbusAddresses =3D SmBusReservedNum; + CopyMem ( + SmbusPreMemConfig->RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c new file mode 100644 index 0000000000..c1ac7d890f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdate.c @@ -0,0 +1,242 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + UpdatePeiSaPolicy performs SA PEI Policy initialization + + @param[in out] SiPolicyPpi - SI_POLICY PPI + + @retval EFI_SUCCESS The policy is installed and initialized= . +**/ +EFI_STATUS +UpdatePeiSaPolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_GUID FileGuid; + VOID *Buffer; + UINT8 SaDisplayConfigTable[9] =3D {0}; + VOID *MemBuffer; + BMP_IMAGE_HEADER *BmpHeader; + UINT64 BltBufferSize; + UINT32 Size; + GRAPHICS_PEI_CONFIG *GtConfig; + GNA_CONFIG *GnaConfig; + WDT_PPI *gWdtPei; + PCIE_PEI_CONFIG *PciePeiConfig; + SA_MISC_PEI_CONFIG *MiscPeiConfig; + EFI_BOOT_MODE BootMode; + + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + + Size =3D 0; + MemBuffer =3D NULL; + BmpHeader =3D NULL; + BltBufferSize =3D 0; + GtConfig =3D NULL; + GnaConfig =3D NULL; + + Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid,= (VOID *)&GtConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOID *= )&GnaConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid, = (VOID *)&PciePeiConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, = (VOID *)&MiscPeiConfig); + ASSERT_EFI_ERROR (Status); + + + // + // Locate WDT_PPI (ICC WDT PPI) + // + gWdtPei =3D NULL; + Status =3D PeiServicesLocatePpi( + &gWdtPpiGuid, + 0, + NULL, + (VOID **) &gWdtPei + ); + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + if (!EFI_ERROR (Status)) { + Buffer =3D NULL; + + CopyMem(&FileGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(File= Guid)); + PeiGetSectionFromFv(FileGuid, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); + } + + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->GraphicsConfigPtr =3D MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + GtConfig->GraphicsConfigPtr =3D NULL; + } + + GtConfig->PeiGraphicsPeimInit =3D 1; + + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", G= tConfig->GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= )); + + PeiGetSectionFromFv (gTianoLogoGuid, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } + + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->LogoPtr =3D MemBuffer; + GtConfig->LogoSize =3D Size; + + // + // Calculate the BltBuffer needed size. + // + BmpHeader =3D (BMP_IMAGE_HEADER *) GtConfig->LogoPtr; + + if (BmpHeader->CharB =3D=3D 'B' && BmpHeader->CharM =3D=3D 'M') { + BltBufferSize =3D MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpH= eader->PixelHeight); + if (BltBufferSize < DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OU= TPUT_BLT_PIXEL))) { + BltBufferSize =3D MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHIC= S_OUTPUT_BLT_PIXEL)); + GtConfig->BltBufferSize =3D (UINT32) BltBufferSize; + GtConfig->BltBufferAddress =3D (VOID *) AllocatePages (EFI_SIZE_= TO_PAGES ((UINTN)GtConfig->BltBufferSize)); + } else { + DEBUG ((DEBUG_ERROR, "Blt Buffer Size overflow.\n")); + ASSERT (FALSE); + } + } else { + DEBUG ((DEBUG_ERROR, "Wrong Bmp Image Header.\n")); + ASSERT (FALSE); + } + + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + GtConfig->LogoPtr =3D NULL; + GtConfig->LogoSize =3D 0; + } + + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtCon= fig->LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtCo= nfig->LogoSize)); + + // + // Display DDI Initialization ( default Native GPIO as per board durin= g AUTO case) + // + if (PcdGet32 (PcdSaDisplayConfigTable) !=3D 0) { + CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDispl= ayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize)); + GtConfig->DdiConfiguration.DdiPortEdp =3D SaDisplayConfigTable[0= ]; + GtConfig->DdiConfiguration.DdiPortBHpd =3D SaDisplayConfigTable[1= ]; + GtConfig->DdiConfiguration.DdiPortCHpd =3D SaDisplayConfigTable[2= ]; + GtConfig->DdiConfiguration.DdiPortDHpd =3D SaDisplayConfigTable[3= ]; + GtConfig->DdiConfiguration.DdiPortFHpd =3D SaDisplayConfigTable[4= ]; + GtConfig->DdiConfiguration.DdiPortBDdc =3D SaDisplayConfigTable[5= ]; + GtConfig->DdiConfiguration.DdiPortCDdc =3D SaDisplayConfigTable[6= ]; + GtConfig->DdiConfiguration.DdiPortDDdc =3D SaDisplayConfigTable[7= ]; + GtConfig->DdiConfiguration.DdiPortFDdc =3D SaDisplayConfigTable[8= ]; + } + } + + PciePeiConfig->DmiAspm =3D 0x3; + + return EFI_SUCCESS; +} + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ) +{ + EFI_STATUS Status; + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; + EFI_FV_FILE_INFO FvFileInfo; + PEI_CORE_INSTANCE *PrivateData; + UINTN CurrentFv; + PEI_CORE_FV_HANDLE *CoreFvHandle; + EFI_PEI_FILE_HANDLE VbtFileHandle; + EFI_GUID *VbtGuid; + EFI_COMMON_SECTION_HEADER *Section; + CONST EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D GetPeiServicesTablePointer(); + + PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices); + + Status =3D PeiServicesLocatePpi( + &gEfiFirmwareFileSystem2Guid, + 0, + NULL, + (VOID **)&FvPpi + ); + ASSERT_EFI_ERROR(Status); + + CurrentFv =3D PrivateData->CurrentPeimFvCount; + CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]); + + Status =3D FvPpi->FindFileByName(FvPpi, &NameGuid, &CoreFvHandle->FvHand= le, &VbtFileHandle); + if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) { + + DEBUG((DEBUG_INFO, "Find SectionByType \n")); + + Status =3D FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, VbtFileHan= dle, (VOID **)&VbtGuid); + if (!EFI_ERROR(Status)) { + + DEBUG((DEBUG_INFO, "GetFileInfo \n")); + + Status =3D FvPpi->GetFileInfo(FvPpi, VbtFileHandle, &FvFileInfo); + Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; + + if (IS_SECTION2(Section)) { + ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF); + *Size =3D SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEAD= ER2); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= 2)); + } else { + *Size =3D SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADE= R); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= )); + } + } + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c new file mode 100644 index 0000000000..3dc455ab29 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,221 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/// +/// Memory Reserved should be between 125% to 150% of the Current required= memory +/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum= e issues. +/// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { + { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL + { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) + { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) + { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)= }, // Runtime Service Data + { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)= }, // Runtime Service Code + { EfiMaxMemoryType, 0 } +}; + + +/** + UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization + + @param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY PPI + + @retval EFI_SUCCESS The policy is installed and initialized= . +**/ +EFI_STATUS +UpdatePeiSaPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig =3D NULL; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc =3D NULL; + SA_MEMORY_RCOMP *RcompData; + WDT_PPI *gWdtPei; + UINT8 Index; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; + EFI_BOOT_MODE BootMode; + UINT8 MorControl; + UINT32 TraceHubTotalMemSize; + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig =3D NULL; + MEMORY_CONFIGURATION *MemConfig =3D NULL; + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig =3D NULL; + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData =3D NULL; + IPU_PREMEM_CONFIG *IpuPreMemPolicy =3D NULL; + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig =3D NULL; + VTD_CONFIG *Vtd =3D NULL; + UINT32 ProcessorTraceTotalMemSize; + UINT16 AdjustedMmioSize; + CPU_FAMILY CpuFamilyId; + CPU_STEPPING CpuStepping; + + TraceHubTotalMemSize =3D 0; + ProcessorTraceTotalMemSize =3D 0; + AdjustedMmioSize =3D PcdGet16 (PcdSaMiscMmioSizeAdjustment); + CpuFamilyId =3D GetCpuFamily(); + CpuStepping =3D GetCpuStepping(); + + DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdateP= eiSaPolicyPreMem\n")); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMe= mConfigGuid, (VOID *) &GtPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid= , (VOID *) &MemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemC= onfigGuid, (VOID *) &PciePeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphi= csConfigGuid, (VOID *) &SgGpioData); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigG= uid, (VOID *) &IpuPreMemPolicy); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCr= cGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPr= eMemConfigGuid, (VOID *) &OcPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (= VOID *)&Vtd); + ASSERT_EFI_ERROR(Status); + + + RcompData =3D MemConfigNoCrc->RcompData; + + // + // Locate WDT_PPI (ICC WDT PPI) + // + gWdtPei =3D NULL; + Status =3D PeiServicesLocatePpi( + &gWdtPpiGuid, + 0, + NULL, + (VOID **) &gWdtPei + ); + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + MiscPeiPreMemConfig->S3DataPtr =3D NULL; + MorControl =3D 0; + MiscPeiPreMemConfig->UserBd =3D 0; // It's a CRB mobile board by default= (btCRBMB) + + PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform)= ); + MiscPeiPreMemConfig->SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddressTab= le0); + MiscPeiPreMemConfig->SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddressTab= le1); + MiscPeiPreMemConfig->SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddressTab= le2); + MiscPeiPreMemConfig->SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddressTab= le3); + MemConfig->CaVrefConfig =3D PcdGet8 (PcdMrcCaVrefConfig)= ; + MemConfig->DualDimmPerChannelBoardType =3D PcdGetBool (PcdDualDimmPerCh= annelBoardType); + if (PcdGet32 (PcdMrcRcompResistor)) { + CopyMem((VOID *)RcompData->RcompResistor, (VOID *) (UINTN) PcdGet32 (P= cdMrcRcompResistor), sizeof (RcompData->RcompResistor)); + } + if (PcdGet32 (PcdMrcRcompTarget)) { + CopyMem((VOID *)RcompData->RcompTarget, (VOID *) (UINTN) PcdGet32 (Pcd= MrcRcompTarget), sizeof (RcompData->RcompTarget)); + } + if (PcdGet32 (PcdMrcDqByteMap)) { + CopyMem((VOID *)MemConfigNoCrc->DqByteMap, (VOID *) (UINTN) PcdGet32 (= PcdMrcDqByteMap), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX= * 2); + } + if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) { + CopyMem((VOID *)MemConfigNoCrc->DqsMap, (VOID *) (UINTN) PcdGet32 (Pcd= MrcDqsMapCpu2Dram), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO= _ECC); + } + if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) { + MemConfig->DqPinsInterleaved =3D PcdGetBool (PcdMrcDqPinsInterleaved); + } + if (PcdGet32 (PcdMrcSpdData)) { + CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *) (UINT= N) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE); + CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *) (UINT= N) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE); + } + + MiscPeiPreMemConfig->MchBar =3D (UINTN) PcdGet64 (PcdMchBaseAddress); + MiscPeiPreMemConfig->DmiBar =3D (UINTN) PcdGet64 (PcdDmiBaseAddress); + MiscPeiPreMemConfig->EpBar =3D (UINTN) PcdGet64 (PcdEpBaseAddress); + MiscPeiPreMemConfig->EdramBar =3D (UINTN) PcdGet64 (PcdEdramBaseAddress)= ; + MiscPeiPreMemConfig->SmbusBar =3D PcdGet16(PcdSmbusBaseAddress); + MiscPeiPreMemConfig->TsegSize =3D PcdGet32(PcdTsegSize); + MiscPeiPreMemConfig->UserBd =3D PcdGet8 (PcdSaMiscUserBd); + MiscPeiPreMemConfig->MmioSizeAdjustment =3D PcdGet16 (PcdSaMiscMmioSizeA= djustment); + if (PcdGetBool (PcdPegGpioResetControl)) { + PciePeiPreMemConfig->PegGpioData.GpioSupport =3D PcdGetBool (PcdPegGpi= oResetSupoort); + } else { + + } + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad =3D PcdGet32 (P= cdPeg0ResetGpioPad); + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active =3D PcdGetBool = (PcdPeg0ResetGpioActive); + + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad =3D PcdGet32 (P= cdPeg3ResetGpioPad); + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active =3D PcdGetBool = (PcdPeg3ResetGpioActive); + + MemConfig->CkeRankMapping =3D 0xAA; + /// + /// Initialize the VTD Configuration + /// + Vtd->VtdDisable =3D 0; + + MemConfig->RMT =3D 1; + MemConfig->UserPowerWeightsEn =3D 0; + MemConfig->RaplLim2WindY =3D 0x0A; + MemConfig->ExitOnFailure =3D 1; + + MemConfigNoCrc->PlatformMemorySize =3D PEI_MIN_MEMORY_SIZE + TraceHubTot= alMemSize + ProcessorTraceTotalMemSize; + DataSize =3D sizeof (mDefaultMemoryTypeInformation); + CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize); + + if (BootMode !=3D BOOT_IN_RECOVERY_MODE) { + for (Index =3D 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATI= ON); Index++) { + MemConfigNoCrc->PlatformMemorySize +=3D MemoryData[Index].NumberOfPa= ges * EFI_PAGE_SIZE; + } + + OcPreMemConfig->GtMaxOcRatio =3D 0; + OcPreMemConfig->GtVoltageMode =3D 0; + OcPreMemConfig->GtVoltageOverride =3D 0; + OcPreMemConfig->GtExtraTurboVoltage =3D 0; + OcPreMemConfig->GtVoltageOffset =3D 0; + OcPreMemConfig->SaVoltageOffset =3D 0; + OcPreMemConfig->GtusMaxOcRatio =3D 0; + OcPreMemConfig->GtusVoltageMode =3D 0; + OcPreMemConfig->GtusVoltageOverride =3D 0; + OcPreMemConfig->GtusExtraTurboVoltage =3D 0; + OcPreMemConfig->GtusVoltageOffset =3D 0; + + /// + /// Build the GUID'd HOB for DXE + /// + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + MemoryData, + DataSize + ); + } + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSiPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c new file mode 100644 index 0000000000..3efbe2ccbd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSiPolicyUpdate.c @@ -0,0 +1,168 @@ +/** @file + This file is SampleCode of the library for Intel Silicon PEI + Platform Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSiPolicyUpdate.h" +#include +#include +#include +#include +#include + +STATIC SVID_SID_INIT_ENTRY mCdfSsidTablePtr[] =3D { + // + // SA Device(s) + // + {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + // + // PCH Device(s) + // + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DE= VICE_NUMBER_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DE= VICE_NUMBER_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DE= VICE_NUMBER_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DE= VICE_NUMBER_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1, PCI_DE= VICE_NUMBER_CDF_PCH_SATA_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2, PCI_DE= VICE_NUMBER_CDF_PCH_SATA_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3, PCI_DE= VICE_NUMBER_CDF_PCH_SATA_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DE= VICE_NUMBER_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DE= VICE_NUMBER_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DE= VICE_NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DE= VICE_NUMBER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DE= VICE_NUMBER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DE= VICE_NUMBER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, +}; + +STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[] =3D { + // + // SA Device(s) + // + {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + // + // PCH Device(s) + // + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DEVICE_NUMBE= R_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DEVICE_NUMBE= R_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DEVICE_NUMBE= R_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DEVICE_NUMBE= R_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SATA, PCI_DEVICE_NUMBE= R_PCH_SATA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DEVICE_NUMBE= R_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DEVICE_NUMBE= R_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + // + // Skip PCH LAN controller + // PCH LAN SVID/SID may be loaded automatically from the NVM Word 0Ch/0B= h upon power up or reset + // depending on the "Load Subsystem ID" bit field in NVM word 0Ah + // + //{{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LAN, PCI_DEVICE_NUM= BER_PCH_LAN, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_P= CH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DEVICE= _NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_UART0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_UART1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_SPI0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_SPI1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD, PCI_DEVICE_= NUMBER_PCH_CNL_SCS_SDCARD, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGME= NT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DEVICE_NUMB= ER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE= R_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DEVICE_NUMB= ER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE= R_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DEVICE_NUMB= ER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE= R_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_ISH, PCI_DEVI= CE_NUMBER_PCH_ISH, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_UART2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C5, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C4, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + // + // ME Device(s) + // + {{{PCI_SVID_OFFSET, HECI_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, HECI2_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, IDER_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SOL_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, HECI3_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, HECI4_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0} +}; + +/** + This function performs Silicon PEI Policy initialization. + + @param[in] SiPolicy The Silicon Policy PPI instance + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicy ( + IN OUT SI_POLICY_PPI *SiPolicy + ) +{ + EFI_STATUS Status; + SI_CONFIG *SiConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &= SiConfig); + ASSERT_EFI_ERROR (Status); + + SiConfig->CsmFlag =3D 0; + + if (IsCdfPch ()) { + SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mCdfSsidTablePtr; + SiConfig->NumberOfSsidTableEntry =3D (sizeof (mCdfSsidTablePtr) / size= of (SVID_SID_INIT_ENTRY)); + } else { + SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mSsidTablePtr; + SiConfig->NumberOfSsidTableEntry =3D (sizeof (mSsidTablePtr) / sizeof = (SVID_SID_INIT_ENTRY)); + } + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/Whiskeylake= OpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEnt= ry.nasm new file mode 100644 index 0000000000..5c5b788085 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/PeiCoreEntry.nasm @@ -0,0 +1,130 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; PeiCoreEntry.nasm +; +; Abstract: +; +; Find and call SecStartup +; +;-------------------------------------------------------------------------= ----- + +SECTION .text + +extern ASM_PFX(SecStartup) +extern ASM_PFX(PlatformInit) + +global ASM_PFX(CallPeiCoreEntryPoint) +ASM_PFX(CallPeiCoreEntryPoint): + ; + ; Obtain the hob list pointer + ; + mov eax, [esp+4] + ; + ; Obtain the stack information + ; ECX: start of range + ; EDX: end of range + ; + mov ecx, [esp+8] + mov edx, [esp+0xC] + + ; + ; Platform init + ; + pushad + push edx + push ecx + push eax + call ASM_PFX(PlatformInit) + pop eax + pop eax + pop eax + popad + + ; + ; Set stack top pointer + ; + mov esp, edx + + ; + ; Push the hob list pointer + ; + push eax + + ; + ; Save the value + ; ECX: start of range + ; EDX: end of range + ; + mov ebp, esp + push ecx + push edx + + ; + ; Push processor count to stack first, then BIST status (AP then BSP) + ; + mov eax, 1 + cpuid + shr ebx, 16 + and ebx, 0xFF + cmp bl, 1 + jae PushProcessorCount + + ; + ; Some processors report 0 logical processors. Effectively 0 =3D 1. + ; So we fix up the processor count + ; + inc ebx + +PushProcessorCount: + push ebx + + ; + ; We need to implement a long-term solution for BIST capture. For now, = we just copy BSP BIST + ; for all processor threads + ; + xor ecx, ecx + mov cl, bl +PushBist: + movd eax, mm0 + push eax + loop PushBist + + ; Save Time-Stamp Counter + movd eax, mm5 + push eax + + movd eax, mm6 + push eax + + ; + ; Pass entry point of the PEI core + ; + mov edi, 0xFFFFFFE0 + push DWORD [edi] + + ; + ; Pass BFV into the PEI Core + ; + mov edi, 0xFFFFFFFC + push DWORD [edi] + + ; + ; Pass stack size into the PEI Core + ; + mov ecx, [ebp - 4] + mov edx, [ebp - 8] + push ecx ; RamBase + + sub edx, ecx + push edx ; RamSize + + ; + ; Pass Control into the PEI Core + ; + call ASM_PFX(SecStartup) + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/WhiskeylakeOpen= BoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm new file mode 100644 index 0000000000..7f6d771e41 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/SecEntry.nasm @@ -0,0 +1,361 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; Module Name: +; +; SecEntry.nasm +; +; Abstract: +; +; This is the code that goes from real-mode to protected mode. +; It consumes the reset vector, calls TempRamInit API from FSP binary. +; +;-------------------------------------------------------------------------= ----- + +#include "Fsp.h" + +SECTION .text + +extern ASM_PFX(CallPeiCoreEntryPoint) +extern ASM_PFX(FsptUpdDataPtr) +extern ASM_PFX(BoardBeforeTempRamInit) +; Pcds +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress)) + +;-------------------------------------------------------------------------= --- +; +; Procedure: _ModuleEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; Transition to non-paged flat-model protected mode from a +; hard-coded GDT that provides exactly two descriptors. +; This is a bare bones transition to protected mode only +; used for a while in PEI and possibly DXE. +; +; After enabling protected mode, a far jump is executed to +; transfer to PEI using the newly loaded GDT. +; +; Return: None +; +; MMX Usage: +; MM0 =3D BIST State +; MM5 =3D Save time-stamp counter value high32bit +; MM6 =3D Save time-stamp counter value low32bit. +; +;-------------------------------------------------------------------------= --- + +BITS 16 +align 4 +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + fninit ; clear any pending Floating point= exceptions + ; + ; Store the BIST value in mm0 + ; + movd mm0, eax + cli + + ; + ; Check INIT# is asserted by port 0xCF9 + ; + mov dx, 0CF9h + in al, dx + cmp al, 04h + jnz NotWarmStart + + + ; + ; @note Issue warm reset, since if CPU only reset is issued not all MSRs= are restored to their defaults + ; + mov dx, 0CF9h + mov al, 06h + out dx, al + +NotWarmStart: + ; + ; Save time-stamp counter value + ; rdtsc load 64bit time-stamp counter to EDX:EAX + ; + rdtsc + movd mm5, edx + movd mm6, eax + + ; + ; Load the GDT table in GdtDesc + ; + mov esi, GdtDesc + DB 66h + lgdt [cs:si] + + ; + ; Transition to 16 bit protected mode + ; + mov eax, cr0 ; Get control register 0 + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #= 1) + mov cr0, eax ; Activate protected mode + + mov eax, cr4 ; Get control register 4 + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCP= T bit (bit #10) + mov cr4, eax + + ; + ; Now we're in 16 bit protected mode + ; Set up the selectors for 32 bit protected mode entry + ; + mov ax, SYS_DATA_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + ; + ; Transition to Flat 32 bit protected mode + ; The jump to a far pointer causes the transition to 32 bit mode + ; + mov esi, ProtectedModeEntryLinearAddress + jmp dword far [cs:si] + +;-------------------------------------------------------------------------= --- +; +; Procedure: ProtectedModeEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; This function handles: +; Call two basic APIs from FSP binary +; Initializes stack with some early data (BIST, PEI entry, etc) +; +; Return: None +; +;-------------------------------------------------------------------------= --- + +BITS 32 +align 4 +ProtectedModeEntryPoint: + ; + ; Early board hooks + ; + mov esp, BoardBeforeTempRamInitRet + jmp ASM_PFX(BoardBeforeTempRamInit) + +BoardBeforeTempRamInitRet: + + ; Find the fsp info header + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))] + + mov eax, dword [edi + FVH_SIGINATURE_OFFSET] + cmp eax, FVH_SIGINATURE_VALID_VALUE + jnz FspHeaderNotFound + + xor eax, eax + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET] + cmp ax, 0 + jnz FspFvExtHeaderExist + + xor eax, eax + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header + add edi, eax + jmp FspCheckFfsHeader + +FspFvExtHeaderExist: + add edi, eax + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Heade= r + add edi, eax + + ; Round up to 8 byte alignment + mov eax, edi + and al, 07h + jz FspCheckFfsHeader + + and edi, 0FFFFFFF8h + add edi, 08h + +FspCheckFfsHeader: + ; Check the ffs guid + mov eax, dword [edi] + cmp eax, FSP_HEADER_GUID_DWORD1 + jnz FspHeaderNotFound + + mov eax, dword [edi + 4] + cmp eax, FSP_HEADER_GUID_DWORD2 + jnz FspHeaderNotFound + + mov eax, dword [edi + 8] + cmp eax, FSP_HEADER_GUID_DWORD3 + jnz FspHeaderNotFound + + mov eax, dword [edi + 0Ch] + cmp eax, FSP_HEADER_GUID_DWORD4 + jnz FspHeaderNotFound + + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header + + ; Check the section type as raw section + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET] + cmp al, 019h + jnz FspHeaderNotFound + + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header + jmp FspHeaderFound + +FspHeaderNotFound: + jmp $ + +FspHeaderFound: + ; Get the fsp TempRamInit Api address + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] + + ; Setup the hardcode stack + mov esp, TempRamInitStack + + ; Call the fsp TempRamInit Api + jmp eax + +TempRamInitDone: + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for= Microcode Update not found. + je CallSecFspInit ;If microcode not found, don't hang, but continu= e. + + cmp eax, 0 ;Check if EFI_SUCCESS retuned. + jnz FspApiFailed + + ; ECX: start of range + ; EDX: end of range +CallSecFspInit: + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam= for FSP + xor eax, eax + mov esp, edx + + ; Align the stack at DWORD + add esp, 3 + and esp, 0FFFFFFFCh + + push edx + push ecx + push eax ; zero - no hob list yet + call ASM_PFX(CallPeiCoreEntryPoint) + +FspApiFailed: + jmp $ + +align 10h +TempRamInitStack: + DD TempRamInitDone + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams + +; +; ROM-based Global-Descriptor Table for the Tiano PEI Phase +; +align 16 +global ASM_PFX(BootGdtTable) + +; +; GDT[0]: 0x00: Null entry, never used. +; +NULL_SEL EQU $ - GDT_BASE ; Selector [0] +GDT_BASE: +ASM_PFX(BootGdtTable): + DD 0 + DD 0 +; +; Linear data segment descriptor +; +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 092h ; present, ring 0, data, expand-up= , writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Linear code segment descriptor +; +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 09Bh ; present, ring 0, data, expand-up= , not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; System data segment descriptor +; +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up= , not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 + +; +; System code segment descriptor +; +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 09Ah ; present, ring 0, data, expand-up= , writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0Eh ; Changed from F000 to E000. + DB 09Bh ; present, ring 0, code, expand-up= , writable + DB 00h ; byte-granular, 16-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up= , not-writable + DB 00h ; byte-granular, 16-bit + DB 0 + +; +; Spare segment descriptor +; +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38] + DW 0 ; limit 0 + DW 0 ; base 0 + DB 0 + DB 0 ; present, ring 0, data, expand-up= , writable + DB 0 ; page-granular, 32-bit + DB 0 +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes + +; +; GDT Descriptor +; +GdtDesc: ; GDT descriptor + DW GDT_SIZE - 1 ; GDT limit + DD GDT_BASE ; GDT base address + + +ProtectedModeEntryLinearAddress: +ProtectedModeEntryLinear: + DD ProtectedModeEntryPoint ; Offset of our 32 bit code + DW LINEAR_CODE_SEL diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm new file mode 100644 index 0000000000..47db32d64c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/Stack.nasm @@ -0,0 +1,72 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; Abstract: +; +; Switch the stack from temporary memory to permanent memory. +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; SecSwitchStack ( +; UINT32 TemporaryMemoryBase, +; UINT32 PermanentMemoryBase +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(SecSwitchStack) +ASM_PFX(SecSwitchStack): + ; + ; Save three register: eax, ebx, ecx + ; + push eax + push ebx + push ecx + push edx + + ; + ; !!CAUTION!! this function address's is pushed into stack after + ; migration of whole temporary memory, so need save it to permanent + ; memory at first! + ; + + mov ebx, [esp + 20] ; Save the first parameter + mov ecx, [esp + 24] ; Save the second parameter + + ; + ; Save this function's return address into permanent memory at first. + ; Then, Fixup the esp point to permanent memory + ; + mov eax, esp + sub eax, ebx + add eax, ecx + mov edx, dword [esp] ; copy pushed register's value to perma= nent memory + mov dword [eax], edx + mov edx, dword [esp + 4] + mov dword [eax + 4], edx + mov edx, dword [esp + 8] + mov dword [eax + 8], edx + mov edx, dword [esp + 12] + mov dword [eax + 12], edx + mov edx, dword [esp + 16] ; Update this function's return address= into permanent memory + mov dword [eax + 16], edx + mov esp, eax ; From now, esp is pointed to perma= nent memory + + ; + ; Fixup the ebp point to permanent memory + ; + mov eax, ebp + sub eax, ebx + add eax, ecx + mov ebp, eax ; From now, ebp is pointed to permanent = memory + + pop edx + pop ecx + pop ebx + pop eax + ret + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/Ba= seAcpiTimerLib.uni b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTim= erLib/BaseAcpiTimerLib.uni new file mode 100644 index 0000000000..33b4be68db --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiT= imerLib.uni @@ -0,0 +1,15 @@ +/** @file + Base ACPI Timer Library + Provides basic timer support using the ACPI timer hardware. The perform= ance + counter features are provided by the processors time stamp counter. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#string STR_MODULE_ABSTRACT #language en-US "ACPI Timer Librar= y" + +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti= mer support using the ACPI timer hardware." + + --=20 2.16.2.windows.1