From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by groups.io with SMTP; Fri, 30 Aug 2019 11:39:49 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Aug 2019 11:39:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,447,1559545200"; d="scan'208";a="193417091" Received: from orsmsx101.amr.corp.intel.com ([10.22.225.128]) by orsmga002.jf.intel.com with ESMTP; 30 Aug 2019 11:39:40 -0700 Received: from orsmsx116.amr.corp.intel.com (10.22.240.14) by ORSMSX101.amr.corp.intel.com (10.22.225.128) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 30 Aug 2019 11:39:39 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.225]) by ORSMSX116.amr.corp.intel.com ([169.254.7.63]) with mapi id 14.03.0439.000; Fri, 30 Aug 2019 11:39:39 -0700 From: "Nate DeSimone" To: "devel@edk2.groups.io" , "Agyeman, Prince" CC: "Gao, Liming" , "Wei, David Y" , "Kubacki, Michael A" , "Chiu, Chasel" Subject: Re: [edk2-devel] [edk2-platforms] ClevoOpenBoardPkg: Update board gpios Thread-Topic: [edk2-devel] [edk2-platforms] ClevoOpenBoardPkg: Update board gpios Thread-Index: AQHVXtAD13b+3K+hKU6u+i3hFUNGKacUBtlw Date: Fri, 30 Aug 2019 18:39:38 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE7BCAA@ORSMSX114.amr.corp.intel.com> References: <1b3a0b39093f7736b8f0b965f27bfbf4631224fb.1567127470.git.prince.agyeman@intel.com> In-Reply-To: <1b3a0b39093f7736b8f0b965f27bfbf4631224fb.1567127470.git.prince.agyeman@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTE1ODBmOGUtMDk0Mi00MmMzLTlmMjMtMzE3Njk0NDcwOWVlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoid281QjZtM25TSzg4WHFQU0R0TmRaQnpjUEtacEJHNjUrSm5tRkU3eWZWbVJvSFRpM00waE5HbHAxSTJ4WXFtOCJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: devel@edk2.groups.io On Behalf Of Agyeman, Pr= ince Sent: Thursday, August 29, 2019 6:12 PM To: devel@edk2.groups.io Cc: Gao, Liming ; Wei, David Y ; Kubacki, Michael A ; Desimone, Nathaniel L= ; Chiu, Chasel Subject: [edk2-devel] [edk2-platforms] ClevoOpenBoardPkg: Update board gpi= os Updated board GPIOS Cc: Liming Gao Cc: David Y Wei Cc: Michael Kubacki Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Agyeman --- .../Library/BoardInitLib/N1xxWUGpioTable.c | 329 +++++++++--------- 1 file changed, 165 insertions(+), 164 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/= N1xxWUGpioTable.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardIn= itLib/N1xxWUGpioTable.c index d055fda8c3..c99b83753f 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUG= pioTable.c +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUG= pioTable.c @@ -20,170 +20,171 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 GPIO_INIT_CONFIG mGpioTableN1xxWU[] =3D { -//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermNone}},//H_RCIN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermWpd20K}},//LPC_AD0_ESPI_IO0 -//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermWpd20K}},//LPC_AD1_ESPI_IO1 -//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermWpd20K}},//LPC_AD2_ESPI_IO2 -//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermWpd20K}},//LPC_AD3_ESPI_IO3 -//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, Gpio= HostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermNone}},//LPC_FRAME_ESPI_CS_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, Gpio= HostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermNone}},//INT_SERIRQ - {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_= S0ix_R_N -// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermNone}},//PM_CLKRUN_N -//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, Gp= ioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,= GpioTermWpd20K}},//LPC_CLK_ESPI_CLK -// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, Gp= ioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,= GpioTermWpd20K}},//PCH_CLK_PCI_TPM - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTerm= None}},//EC_HID_INTR - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_G= NSS_UART_RST_N -//skip for SUS_PWR_ACK_R {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, Gpio= HostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermNone}},//SUS_PWR_ACK_R -//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, Gp= ioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,= GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N -//skip for SUSACK_R_N {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHos= tOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gpi= oTermWpd20K}},//SUSACK_R_N - {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_= SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_= EN_N - {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_= 0_SENSOR - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_= 1_SENSOR - {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_= 2_SENSOR - {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CH= UB_IRQ - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP= _N - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTerm= None}},//FPS_DRDY - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_= VID0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_= VID1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRAL= ERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTerm= None}},//TCH_PAD_INTR_R_N - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_K= ILL_N - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTerm= None}},//M.2_BT_UART_WAKE_N - // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_= REQ_SLOT1_N - // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_= REQ_SLOT2_LAN_N - // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_= REQ_M.2_SSD_SLOT3_N - // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_= REQ_M.2_WIGIG_N - // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_= REQ_M.2_WLAN_N - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EX= T_PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP= _S0_N - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST= _N - {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_P= NL_PWREN - // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_= NFC_DFU, NOT OWNED BY BIOS - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermN= one}},//M.2_WLAN_WIFI_WAKE_N - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWp= u20K}},//TBT_CIO_PLUG_EVENT_N - {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermW= pu20K}},//PCH_SLOT1_WAKE_N - {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GS= PI1_CS_R1_N - {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_G= SPI1_CLK_R1 - {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_G= SPI1_MISO_R1 - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_G= SPI1_MOSI_R1 - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCR= ETE_GNSS_RESET_N - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_D= ATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_= THRM_SNSR_ALERT_N - {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CL= K - {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DA= TA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermW= pd20K}},//M.2_WIGIG_WAKE_N - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CL= K, OWNED BY ME - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_= DATA, OWNED BY ME - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART0_RTS_N - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART0_CTS_N - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART1_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART1_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART1_ISH_UART1_RTS_N - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART1_ISH_UART1_CTS_N - {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_I2C0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_I2C0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_I2C1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART2_RTS_N - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALI= O_UART2_CTS_N - {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TC= HPNL_CS_N - {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TC= HPNL_CLK - {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TC= HPNL_MISO - {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TC= HPNL_MOSI - {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FL= ASH_STROBE - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C= 0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C= 0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C= 1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C= 1_SCL/SB_BLON - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermN= one}},//HOME_BTN - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermN= one}},//SCREEN_LOCK_PCH - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermN= one}},//VOL_UP_PCH - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermN= one}},//VOL_DOWN_PCH - {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UAR= T0_RXD_SML0B_DATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UAR= T0_TXD_SML0B_CLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UAR= T0_RTS_N - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UAR= T0_CTS_SML0B_ALERT_N - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CL= K_1 - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_= DATA_1 - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CL= K_0 - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_= DATA_0 - {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TC= HPNL_IO2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TC= HPNL_IO3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCL= K - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//SPI_TPM_HDR_IRQ_N - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_OD= D_PRSNT_N - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, Gpio= TermNone}},//M.2_SSD_SATA2_PCIE3_DET_N - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_= DFU_N - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC= _RESET - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_P= HYSLP1_DIRECT_R - // {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA= 2_PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SAT= A_LED_N - {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_= 0_WP1_OTG_N - {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_= 1_WP4_N - {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_= 2_WP2_WP3_WP5_R_N - // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTe= rmNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HP= D_Q - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HP= D_Q - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNo= ne}},//SMC_EXTSMI_R_N - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermN= one}},//SMC_RUNTIME_SCI_R_N - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CT= RL_CLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_= CTRL_DATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CT= RL_CLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_= CTRL_DATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTerm= None}},//PCH_CODEC_IRQ - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_P= NL_RST_N - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SC= LK - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SF= RM - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TX= D - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RX= D - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C2_SDA - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C2_SCL - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C3_SDA - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C3_SCL - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C4_SDA - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C4_SCL - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C5_ISH_12C2_SDA - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTe= rmNone}},//SERIALIO_I2C5_ISH_12C2_SCL - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CM= D - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA0 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA1 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA2 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA3 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA4 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA5 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA6 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DA= TA7 - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RC= LK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CL= K - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTerm= None}},//PCH_M.2_WWAN_UIM_SIM_DET - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA= 0 - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA= 1 - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA= 2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA= 3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},= //LANWAKE_SMC_WAKE_SCI_N - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R= _N - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N - {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_I= NTRUDET_N - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_= N - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENA= BLE - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End o= f Table + {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= n, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //RC= INB_TIME_SYNC_1 + {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= nOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNative}}, //= LAD_0_ESPI_IO_0 + {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= nOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LA= D_1_ESPI_IO_1 + {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= nOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNative}}, //= LAD_2_ESPI_IO_2 + {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= nOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LA= D_3_ESPI_IO_3 + {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LF= RAMEB_ESPI_CSB + {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= nOut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SE= RIRQ + {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //PI= RQAB_GSPI0_CS1B + {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CL= KRUNB + {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //= CLKOUT_LPC_0_ESPI_CLK + {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //= CLKOUT_LPC_1 + {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //= PMEB_GSPI1_CS1B + {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //BM= _BUSYB_ISH_GP_6 + {GPIO_SKL_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SU= SWARNB_SUSPWRDNACK + {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SU= S_STATB_ESPI_RESETB + {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= n, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //= SUSACKB + {GPIO_SKL_LP_GPP_A16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SD= _1P8_SEL + {GPIO_SKL_LP_GPP_A17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SD= _VDD1_PWR_EN_B_ISH_GP_7 + {GPIO_SKL_LP_GPP_A18, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_GP_0 + {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirO= ut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_GP_1 + {GPIO_SKL_LP_GPP_A20, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_GP_2 + {GPIO_SKL_LP_GPP_A21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //IS= H_GP_3 + {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //IS= H_GP_4 + {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //IS= H_GP_5 + {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CO= RE_VID_0 + {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CO= RE_VID_1 + {GPIO_SKL_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //VR= ALERTB + {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CP= U_GP_2 + {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CP= U_GP_3 + {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SR= CCLKREQB_0 + {GPIO_SKL_LP_GPP_B6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SR= CCLKREQB_1 + {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SR= CCLKREQB_2 + {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SR= CCLKREQB_3 + {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SR= CCLKREQB_4 + {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SR= CCLKREQB_5 + {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EX= T_PWR_GATEB + {GPIO_SKL_LP_GPP_B12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SL= P_S0B + {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //PL= TRSTB + {GPIO_SKL_LP_GPP_B14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //= SPKR + {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GS= PI0_CS0B + {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GS= PI0_CLK + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GS= PI0_MISO + {GPIO_SKL_LP_GPP_B18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //= GSPI0_MOSI + {GPIO_SKL_LP_GPP_B19, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GS= PI1_CS0B + {GPIO_SKL_LP_GPP_B20, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GS= PI1_CLK_NFC_CLK + {GPIO_SKL_LP_GPP_B21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GS= PI1_MISO_NFC_CLKREQ + {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //= GSPI1_MOSI + {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= L1ALERTB_PCHHOTB + {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_0_SD3_CMD + {GPIO_SKL_LP_GPP_G1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_1_SD3_D0_SD4_RCLK_P + {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_2_SD3_D1_SD4_RCLK_N + {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_3_SD3_D2 + {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_4_SD3_D3 + {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_5_SD3_CDB + {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_6_SD3_CLK + {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GP= PC_G_7_SD3_WP + {GPIO_SKL_LP_GPP_D0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SP= I1_CSB_BK_0 + {GPIO_SKL_LP_GPP_D1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SP= I1_CLK_BK_1 + {GPIO_SKL_LP_GPP_D2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SP= I1_MISO_IO_1_BK_2 + {GPIO_SKL_LP_GPP_D3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SP= I1_MOSI_IO_0_BK_3 + {GPIO_SKL_LP_GPP_D4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IM= GCLKOUT_0_BK_4 + {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_I2C0_SDA + {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_I2C0_SCL + {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_I2C1_SDA + {GPIO_SKL_LP_GPP_D8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_I2C1_SCL + {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_SPI_CSB + {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_SPI_CLK + {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_SPI_MISO_GP_BSSB_CLK + {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_SPI_MOSI_GP_BSSB_DI + {GPIO_SKL_LP_GPP_D13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_UART0_RXD_SML0BDATA + {GPIO_SKL_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_UART0_TXD_SML0BCLK + {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_UART0_RTSB_GSPI2_CS1B + {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IS= H_UART0_CTSB_SML0BALERTB + {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DM= IC_CLK_1_SNDW3_CLK + {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DM= IC_DATA_1_SNDW3_DATA + {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DM= IC_CLK_0_SNDW4_CLK + {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DM= IC_DATA_0_SNDW4_DATA + {GPIO_SKL_LP_GPP_D21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SP= I1_IO_2 + {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SP= I1_IO_3 + {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SS= P_MCLK + {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_GNSS_PA_BLANKING + {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_GNSS_FTA + {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_GNSS_SYSCK + {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, // + {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_BRI_DT_UART0_RTSB + {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_BRI_RSP_UART0_RXD + {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_RGI_DT_UART0_TXD + {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_RGI_RSP_UART0_CTSB + {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_MFUART2_RXD + {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CN= V_MFUART2_TXD + {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnDefault, GpioDirD= efault, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, // + {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_CMD + {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA0 + {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA1 + {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA2 + {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA3 + {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA4 + {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA5 + {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA6 + {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_DATA7 + {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_RCLK + {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_CLK + {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EM= MC_RESETB + {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirI= n, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, Gpio= TermNone}}, //A4WP_PRESENT + {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //BAT= LOWB + {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNative}}, //A= CPRESENT + {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirI= nInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetDefault, GpioTe= rmNone}}, //LAN_WAKEB + {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermWpu20K}}, //P= WRBTNB + {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP= _S3B + {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP= _S4B + {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP= _AB + {GPIO_SKL_LP_GPD7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, // + {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SUS= CLK + {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP= _WLANB + {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP= _S5B + {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirI= n, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //LAN= PHYPC + {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= BCLK + {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= BDATA + {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //= SMBALERTB + {GPIO_SKL_LP_GPP_C3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= L0CLK + {GPIO_SKL_LP_GPP_C4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= L0DATA + {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= L0ALERTB + {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= L1CLK + {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SM= L1DATA + {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT0_RXD + {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT0_TXD + {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT0_RTSB + {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT0_CTSB + {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT1_RXD_ISH_UART1_RXD + {GPIO_SKL_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirI= nInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTe= rmNone}}, //UART1_TXD_ISH_UART1_TXD + {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT1_RTSB_ISH_UART1_RTSB + {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT1_CTSB_ISH_UART1_CTSB + {GPIO_SKL_LP_GPP_C16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2= C0_SDA + {GPIO_SKL_LP_GPP_C17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2= C0_SCL + {GPIO_SKL_LP_GPP_C18, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2= C1_SDA + {GPIO_SKL_LP_GPP_C19, GpioPadModeGpio, GpioHostOwnAcpi, GpioDirI= nInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioT= ermNone}, //I2C1_SCL + {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT2_RXD + {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT2_TXD + {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT2_RTSB + {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UA= RT2_CTSB + {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioT= ermWpd20K}}, //SATAXPCIE_0_SATAGP_0 + {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SA= TAXPCIE_1_SATAGP_1 + {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SA= TAXPCIE_2_SATAGP_2 + {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= nOut, GpioOutLow, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioT= ermNone}}, //CPU_GP_0 + {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //SATA= _DEVSLP_0 + {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //SATA= _DEVSLP_1 + {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SA= TA_DEVSLP_2 + {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CP= U_GP_1 + {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SA= TA_LEDB + {GPIO_SKL_LP_GPP_E9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //US= B2_OCB_0_GP_BSSB_CLk + {GPIO_SKL_LP_GPP_E10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //US= B2_OCB_1_GP_BSSB_DI + {GPIO_SKL_LP_GPP_E11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //US= B2_OCB_2 + {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //US= B2_OCB_3 + {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DD= SP_HPD_0_DISP_MISC_0 + {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DD= SP_HPD_1_DISP_MISC_1 + {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirI= nInv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTe= rmNone}}, //DDSP_HPD_2_DISP_MISC_2 + {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirI= nInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioT= ermNone}}, //DDSP_HPD_3_DISP_MISC_3 + {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ED= P_HPD_DISP_MISC_4 + {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirD= efault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DD= PB_CTRLCLK + {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DD= PB_CTRLDATA + {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DD= PC_CTRLCLK + {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DD= PC_CTRLDATA + {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= nOut, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, Gpio= TermNone}}, //DDPD_CTRLCLK + {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirO= ut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DD= PD_CTRLDATA + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirN= one, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking= End of Table }; =20 UINT16 mGpioTableN1xxWUSize =3D sizeof (mGpioTableN1xxWU) / sizeof (GPIO_= INIT_CONFIG) - 1; --=20 2.19.1.windows.1