From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by groups.io with SMTP; Mon, 02 Sep 2019 21:56:03 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Sep 2019 21:56:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,461,1559545200"; d="scan'208";a="194227962" Received: from orsmsx108.amr.corp.intel.com ([10.22.240.6]) by orsmga002.jf.intel.com with ESMTP; 02 Sep 2019 21:56:03 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.225]) by ORSMSX108.amr.corp.intel.com ([169.254.2.9]) with mapi id 14.03.0439.000; Mon, 2 Sep 2019 21:56:03 -0700 From: "Nate DeSimone" To: "Wei, David Y" , "devel@edk2.groups.io" CC: "Wu, Hao A" , "Gao, Liming" , "Sinha, Ankit" , "Agyeman, Prince" , "Kubacki, Michael A" , "Kinney, Michael D" Subject: Re: [edk2-platforms PATCH v4 7/7] SimicsOpenBoardPkg/BoardX58Ich10: Add board modules for QSP Build tip Thread-Topic: [edk2-platforms PATCH v4 7/7] SimicsOpenBoardPkg/BoardX58Ich10: Add board modules for QSP Build tip Thread-Index: AQHVX3igARA0mfroCk2hffEdQdXfB6cZaM9w Date: Tue, 3 Sep 2019 04:56:02 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEE88D12@ORSMSX114.amr.corp.intel.com> References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODEzNWNjMzItMDFlNy00ZTZkLThjOTktYTJjOWU5NjZiOTUxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiV1FRQ3l1YUVneTNVdk9ZTkZlUFRHNitkTGJ4NmdjT0Q3akxjdkhRM3hGRFFQMXdUOWEra0N5Q0tlN1Y3UUpCVCJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Wei, David Y=20 Sent: Friday, August 30, 2019 2:19 PM To: devel@edk2.groups.io Cc: Wu, Hao A ; Gao, Liming ; Sin= ha, Ankit ; Agyeman, Prince ; Kubacki, Michael A ; Desimone, Nathaniel L= ; Kinney, Michael D Subject: [edk2-platforms PATCH v4 7/7] SimicsOpenBoardPkg/BoardX58Ich10: Ad= d board modules for QSP Build tip Add BoardX58ICH10 modules for QSP Build tip Cc: Hao Wu Cc: Liming Gao Cc: Ankit Sinha Cc: Agyeman Prince Cc: Kubacki Michael A Cc: Nate DeSimone Cc: Michael D Kinney Signed-off-by: David Wei --- .../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 44 +++ .../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 110 ++++++++ .../Library/BoardInitLib/PeiX58Ich10Detect.c | 26 ++ .../BoardInitLib/PeiX58Ich10InitPostMemLib.c | 34 +++ .../BoardInitLib/PeiX58Ich10InitPreMemLib.c | 111 ++++++++ .../BoardX58Ich10/DecomprScratchEnd.fdf.inc | 67 +++++ .../BoardInitLib/PeiBoardInitPostMemLib.inf | 36 +++ .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 39 +++ .../Library/BoardInitLib/PeiX58Ich10InitLib.h | 16 ++ .../BoardX58Ich10/OpenBoardPkg.dsc | 233 ++++++++++++++++ .../BoardX58Ich10/OpenBoardPkg.fdf | 304 +++++++++++++++++= ++++ .../BoardX58Ich10/OpenBoardPkg.fdf.inc | 54 ++++ .../BoardX58Ich10/OpenBoardPkgBuildOption.dsc | 78 ++++++ .../BoardX58Ich10/OpenBoardPkgConfig.dsc | 56 ++++ .../BoardX58Ich10/OpenBoardPkgPcd.dsc | 281 +++++++++++++++++= ++ .../BoardX58Ich10/VarStore.fdf.inc | 53 ++++ .../BoardX58Ich10/build_config.cfg | 31 +++ 17 files changed, 1573 insertions(+) create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiBoardInitPostMemLib.c create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiBoardInitPreMemLib.c create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiX58Ich10Detect.c create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiX58Ich10InitPostMemLib.c create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiX58Ich10InitPreMemLib.c create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Decompr= ScratchEnd.fdf.inc create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiBoardInitPreMemLib.inf create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library= /BoardInitLib/PeiX58Ich10InitLib.h create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoa= rdPkg.dsc create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoa= rdPkg.fdf create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoa= rdPkg.fdf.inc create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoa= rdPkgBuildOption.dsc create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoa= rdPkgConfig.dsc create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoa= rdPkgPcd.dsc create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStor= e.fdf.inc create mode 100644 Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_c= onfig.cfg diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/SimicsOpenBoardPkg/BoardX5= 8Ich10/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 0000000000..5ece8c6e34 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiBoardInitPostMemLib.c @@ -0,0 +1,44 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +X58Ich10BoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +X58Ich10BoardInitAfterSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + X58Ich10BoardInitBeforeSiliconInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + X58Ich10BoardInitAfterSiliconInit (); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/SimicsOpenBoardPkg/BoardX58= Ich10/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..d16e649d34 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiBoardInitPreMemLib.c @@ -0,0 +1,110 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +X58Ich10BoardDetect( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +X58Ich10BoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +X58Ich10BoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +X58Ich10BoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +X58Ich10BoardInitAfterMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + X58Ich10BoardDetect (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + X58Ich10BoardDebugInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return X58Ich10BoardBootModeDetect (); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + X58Ich10BoardInitBeforeMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + X58Ich10BoardInitAfterMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiX58Ich10Detect.c b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich1= 0/Library/BoardInitLib/PeiX58Ich10Detect.c new file mode 100644 index 0000000000..03488ef1f4 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiX58Ich10Detect.c @@ -0,0 +1,26 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +X58Ich10BoardDetect ( + VOID + ) +{ + DEBUG ((EFI_D_INFO, "X58Ich10BoardDetect\n")); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiX58Ich10InitPostMemLib.c b/Platform/Intel/SimicsOpenBoardPkg/Boar= dX58Ich10/Library/BoardInitLib/PeiX58Ich10InitPostMemLib.c new file mode 100644 index 0000000000..bd6924e269 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiX58Ich10InitPostMemLib.c @@ -0,0 +1,34 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "PeiX58Ich10InitLib.h" +EFI_STATUS +EFIAPI +X58Ich10BoardInitBeforeSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +X58Ich10BoardInitAfterSiliconInit ( + VOID + ) +{ + + DEBUG((EFI_D_ERROR, "X58Ich10BoardInitAfterSiliconInit\n")); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiX58Ich10InitPreMemLib.c b/Platform/Intel/SimicsOpenBoardPkg/Board= X58Ich10/Library/BoardInitLib/PeiX58Ich10InitPreMemLib.c new file mode 100644 index 0000000000..c3a31ed426 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiX58Ich10InitPreMemLib.c @@ -0,0 +1,111 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiX58Ich10InitLib.h" +#include +/** + Reads 8-bits of CMOS data. + + Reads the 8-bits of CMOS data at the location specified by Index. + The 8-bit read value is returned. + + @param Index The CMOS location to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +CmosRead8( + IN UINTN Index + ) +{ + IoWrite8 (0x70, (UINT8)Index); + return IoRead8(0x71); +} + + +/** + Writes 8-bits of CMOS data. + + Writes 8-bits of CMOS data to the location specified by Index + with the value specified by Value and returns Value. + + @param Index The CMOS location to write. + @param Value The value to write to CMOS. + + @return The value written to CMOS. + +**/ +UINT8 +EFIAPI +CmosWrite8( + IN UINTN Index, + IN UINT8 Value + ) +{ + IoWrite8 (0x70, (UINT8)Index); + IoWrite8 (0x71, Value); + return Value; +} + + +EFI_STATUS +EFIAPI +X58Ich10BoardInitBeforeMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +X58Ich10BoardInitAfterMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +X58Ich10BoardDebugInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +X58Ich10BoardBootModeDetect ( + VOID + ) +{ + EFI_BOOT_MODE BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + + DEBUG((EFI_D_INFO, "modeValue =3D %x\n", IoBitFieldRead16(ICH10_PMBASE_I= O + 4, 10, 12))); + if (IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12) =3D=3D 0x5) { + BootMode =3D BOOT_ON_S3_RESUME; + } + + return BootMode; +} diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratch= End.fdf.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratc= hEnd.fdf.inc new file mode 100644 index 0000000000..ae9a625da9 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf= .inc @@ -0,0 +1,67 @@ +## @file +# This FDF include file computes the end of the scratch buffer used in +# DecompressMemFvs() [SimicsX58Pkg/Sec/SecMain.c]. It is based on the dec= ompressed +# (ie. original) size of the LZMA-compressed section of the one FFS file = in +# the FVMAIN_COMPACT firmware volume. +# +# Copyright (C) 2015, Red Hat, Inc. +# Copyright (c) 2006 - 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# The GUID EE4E5898-3914-4259-9D6E-DC7BD79403CF means "LzmaCustomDecompres= s". +# The decompressed output will have the following structure (see the file +# "9E21FD93-9C72-4c15-8C4B-E77F1DB2D792SEC1.guided.dummy" in the +# Build/SimicsX58*/*/FV/Ffs/9E21FD93-9C72-4c15-8C4B-E77F1DB2D792/ director= y): +# +# Size Contents +# ------------------- ---------------------------------------------------= ----- +# 4 EFI_COMMON_SECTION_HEADER, stating size 124 (0x7C) = and +# type 0x19 (EFI_SECTION_RAW). The purpose of this se= ction +# is to pad the start of PEIFV to 128 bytes. +# 120 Zero bytes (padding). +# +# 4 EFI_COMMON_SECTION_HEADER, stating size +# (PcdSimicsPeiMemFvSize + 4), and type 0x17 +# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE). +# PcdSimicsPeiMemFvSize PEIFV. Note that the above sizes pad the offset o= f this +# object to 128 bytes. See also the "guided.dummy.txt= " +# file in the same directory. +# +# 4 EFI_COMMON_SECTION_HEADER, stating size 12 (0xC) an= d +# type 0x19 (EFI_SECTION_RAW). The purpose of this se= ction +# is to pad the start of DXEFV to 16 bytes. +# 8 Zero bytes (padding). +# +# 4 EFI_COMMON_SECTION_HEADER, stating size +# (PcdSimicsDxeMemFvSize + 4), and type 0x17 +# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE). +# PcdSimicsDxeMemFvSize DXEFV. Note that the above sizes pad the offset o= f this +# object to 16 bytes. See also the "guided.dummy.txt"= file +# in the same directory. +# +# The total size after decompression is (128 + PcdSimicsPeiMemFvSize + 16 = + +# PcdSimicsDxeMemFvSize). + +DEFINE OUTPUT_SIZE =3D (128 + gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFv= Size + 16 + gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize) + +# LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; see +# SCRATCH_BUFFER_REQUEST_SIZE in +# "MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaDecompress.c". + +DEFINE DECOMP_SCRATCH_SIZE =3D 0x00010000 + +# Note: when we use PcdSimicsDxeMemFvBase in this context, BaseTools have = not yet +# offset it with MEMFD's base address. For that reason we have to do it ma= nually. +# +# The calculation below mirrors DecompressMemFvs() [SimicsX58Pkg/Sec/SecMa= in.c]. + +DEFINE OUTPUT_BASE =3D ($(MEMFD_BASE_ADDRESS) + gBoardMo= duleTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000) +DEFINE DECOMP_SCRATCH_BASE_UNALIGNED =3D ($(OUTPUT_BASE) + $(OUTPUT_SIZE)) +DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT =3D 0x000FFFFF +DEFINE DECOMP_SCRATCH_BASE_MASK =3D 0xFFF00000 +DEFINE DECOMP_SCRATCH_BASE =3D (($(DECOMP_SCRATCH_BASE_UNALIGNED= ) + $(DECOMP_SCRATCH_BASE_ALIGNMENT)) & $(DECOMP_SCRATCH_BASE_MASK)) + +SET gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =3D $(DECO= MP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Board= X58Ich10/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..a035eb0e50 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiBoardInitPostMemLib.inf @@ -0,0 +1,36 @@ +## @file +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardPostMemInitLib + FILE_GUID =3D 30F407D6-6B92-412A-B2DA-8E73E2B386E6 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Sources] + PeiX58Ich10InitPostMemLib.c + PeiBoardInitPostMemLib.c + +[FixedPcd] + +[Pcd] + diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/SimicsOpenBoardPkg/BoardX= 58Ich10/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..08a6eb159a --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiBoardInitPreMemLib.inf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardInitPreMemLib + FILE_GUID =3D 73AA24AE-FB20-43F9-A3BA-448953A03A78 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SimicsOpenBoardPkg/OpenBoardPkg.dec + SimicsIch10Pkg/Ich10Pkg.dec + +[Sources] + PeiX58Ich10Detect.c + PeiX58Ich10InitPreMemLib.c + PeiBoardInitPreMemLib.c + +[Pcd] + +[FixedPcd] + diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardI= nitLib/PeiX58Ich10InitLib.h b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich= 10/Library/BoardInitLib/PeiX58Ich10InitLib.h new file mode 100644 index 0000000000..93544a838b --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/= PeiX58Ich10InitLib.h @@ -0,0 +1,16 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_X58Ich10_BOARD_INIT_LIB_H_ +#define _PEI_X58Ich10_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include + +#endif diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.d= sc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc new file mode 100644 index 0000000000..59e13154a7 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc @@ -0,0 +1,233 @@ +## @file +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg + DEFINE BOARD_NAME =3D BoardX58Ich10 + DEFINE BOARD_PKG =3D SimicsOpenBoardPkg + DEFINE SKT_PKG =3D SimicsX58SktPkg + DEFINE PCH_PKG =3D SimicsIch10Pkg + DEFINE DXE_ARCH =3D X64 + DEFINE PEI_ARCH =3D IA32 + + PLATFORM_NAME =3D SimicsX58 + PLATFORM_GUID =3D EE8EBB5A-CC95-412f-9987-2AF70F88B69A + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/SimicsX58Ia32X64 + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardP= kg.fdf + + DEFINE SMM_REQUIRE =3D TRUE + + # + #PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64 platf= orm + # + DEFINE PLATFORMX64_ENABLE =3D TRUE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + !include NetworkPkg/NetworkDefines.dsc.inc +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this Platf= orm. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + +[PcdsFeatureFlag] + # + # Platform On/Off features are defined here + # + !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc + !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc + !include $(PCH_PKG)/IchCommonLib.dsc + +[LibraryClasses] + ReportFvLib|$(BOARD_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf + NvVarsFileLib|$(BOARD_PKG)/Library/NvVarsFileLib/NvVarsFileLib.inf + SerializeVariablesLib|$(BOARD_PKG)/Library/SerializeVariablesLib/Seriali= zeVariablesLib.inf + DxeLoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/DxeLoadLinuxLib.inf + CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/C= puExceptionHandlerLibNull.inf + + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Test= PointCheckLibNull.inf + BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardI= nitLibNull.inf + SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/Si= liconPolicyInitLib.inf + SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLi= b/SiliconPolicyUpdateLib.inf + PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/Pci= SegmentInfoLibSimple.inf + + !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc + + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf + AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib= .inf + LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf +[LibraryClasses.common.SEC] + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + +[LibraryClasses.common.PEI_CORE] + +[LibraryClasses.common.PEIM] + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf + +[LibraryClasses.IA32] +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestP= ointCheckLib.inf +!endif + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.in= f + + !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc + +[LibraryClasses.common.DXE_DRIVER] + PlatformBootManagerLib|$(BOARD_PKG)/Library/PlatformBootManagerLib/Platf= ormBootManagerLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER] + SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCom= monLib.inf + + !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc + +[Components.IA32] + $(BOARD_PKG)/SecCore/SecMain.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + !include $(SKT_PKG)/SktPkgPei.dsc + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc + + $(BOARD_PKG)/SimicsPei/SimicsPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } +# S3 SMM driver +# UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf { + + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf + } + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(SKT_PKG)/Smm/Access/SmmAccessPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } +!endif + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoar= dInitPreMemLib.inf + } + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + + BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoar= dInitPostMemLib.inf + } + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf + +[Components.X64] + !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc + !include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc + + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + # + # ISA Support + # + $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf + + $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + $(BOARD_PKG)/AcpiTables/AcpiTables.inf + # + # Video support + # + $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf + + MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf + + SimicsIch10BinPkg/UndiBinary/UndiDxe.inf + + # + # Shell + # + ShellPkg/Application/Shell/Shell.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com= mandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C= ommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C= ommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C= ommandsLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand= Lib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars= ingLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg= CommandLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib= .inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + } + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf + $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf + $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf + MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf { + + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf + } +!endif + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + PciHostBridgeLib|$(BOARD_PKG)/Library/PciHostBridgeLib/PciHostBridge= Lib.inf + } + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable =3D=3D TRUE + AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf +!endif + + !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgBuildOption.dsc diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.f= df b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf new file mode 100644 index 0000000000..6c1579bef7 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf @@ -0,0 +1,304 @@ +## @file +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +!include OpenBoardPkg.fdf.inc + +# +# Build the variable store and the firmware code as one unified flash devi= ce +# image. +# +[FD.SIMICSX58IA32X64] +BaseAddress =3D $(FW_BASE_ADDRESS) +Size =3D $(FW_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(FW_BLOCKS) + +!include VarStore.fdf.inc + +$(VARS_SIZE)|0x00002000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x00040000|0x00040000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + +0x00080000|0x0016C000 +FV =3D FVMAIN_COMPACT + +$(SECFV_OFFSET)|$(SECFV_SIZE) +FV =3D FvTempMemorySilicon + +# +# Build the variable store and the firmware code as separate flash device +# images. +# +[FD.SIMICS_VARS] +BaseAddress =3D $(FW_BASE_ADDRESS) +Size =3D 0x80000 +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D 0x80 + +!include VarStore.fdf.inc + +[FD.SIMICS_CODE] +BaseAddress =3D $(CODE_BASE_ADDRESS) +Size =3D $(CODE_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(CODE_BLOCKS) + +0x00000000|0x0016C000 +FV =3D FVMAIN_COMPACT + +0x0016C000|$(SECFV_SIZE) +FV =3D FvTempMemorySilicon + +[FD.MEMFD] +BaseAddress =3D $(MEMFD_BASE_ADDRESS) +Size =3D 0xB00000 +ErasePolarity =3D 1 +BlockSize =3D 0x10000 +NumBlocks =3D 0xB0 + +0x000000|0x006000 +gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|gBoardModuleTokenSpa= ceGuid.PcdSimicsSecPageTablesSize + +0x006000|0x001000 +gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gBoardModuleTokenSp= aceGuid.PcdSimicsLockBoxStorageSize + +0x007000|0x001000 +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gBoardModuleT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize + +0x010000|0x008000 +gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gBoardModuleTokenSpa= ceGuid.PcdSimicsSecPeiTempRamSize + +0x020000|0x0E0000 +gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|gBoardModuleTokenSpaceGui= d.PcdSimicsPeiMemFvSize +FV =3D FvPreMemory + +0x100000|0xA00000 +gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|gBoardModuleTokenSpaceGui= d.PcdSimicsDxeMemFvSize +FV =3D DXEFV + +##########################################################################= ###### + +[FV.FvTempMemorySilicon] +FvAlignment =3D 16 +FvForceRebase =3D TRUE +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 229EEDCE-8E76-4809-B233-EC36BFBF6989 + +INF RuleOverride=3DRESET_SECMAIN USE =3D IA32 $(BOARD_PKG)/SecCore/SecMai= n.inf +!include $(SKT_PKG)/SktSecInclude.fdf + +[FV.FvPreMemory] +FvAlignment =3D 16 +FvForceRebase =3D TRUE +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 + +## +# PEI Apriori file example, more PEIM module added later. +## +INF MdeModulePkg/Core/Pei/PeiMain.inf +!include $(SKT_PKG)/SktPreMemoryInclude.fdf +!include $(PCH_PKG)/IchPreMemoryInclude.fdf +!include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf +INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf +INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.i= nf +!include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPreMemoryInclude.fdf +INF $(BOARD_PKG)/SimicsPei/SimicsPei.inf +!include $(SKT_PKG)/SktPostMemoryInclude.fdf +!include $(PCH_PKG)/IchPostMemoryInclude.fdf +!include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf +INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf +INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.= inf +!include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPostMemoryInclude.fdf + +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf +INF $(SKT_PKG)/Smm/Access/SmmAccessPei.inf +# S3 SMM PEI driver +#INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + +[FV.DXEFV] +FvNameGuid =3D EACAB9EA-C3C6-4438-8FD7-2270826DC0BB +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +!include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf +!include $(SKT_PKG)/SktUefiBootInclude.fdf +!include $(PCH_PKG)/IchUefiBootInclude.fdf + +INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf +INF UefiCpuPkg/CpuDxe/CpuDxe.inf + +!include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf +INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorD= xe.inf +INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +INF MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + +INF $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf +INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf + +INF $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf + +INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf +INF $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf +INF RuleOverride=3DACPITABLE $(BOARD_PKG)/AcpiTables/AcpiTables.inf + +INF $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf +INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf +INF MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf +INF $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf + +FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D { + SECTION RAW =3D $(BOARD_PKG)/Logo/Logo.bmp +} + +INF ShellPkg/Application/Shell/Shell.inf + +# +# Network modules +# +INF SimicsIch10BinPkg/UndiBinary/UndiDxe.inf + +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedLateInclude.fdf + +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable =3D=3D TRUE + INF AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf +!endif + +!include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + +[FV.FVMAIN_COMPACT] +FvNameGuid =3D 6189987A-DDA6-4060-B313-49168DA9BD46 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = =3D TRUE { + # + # These firmware volumes will have files placed in them uncompressed, + # and then both firmware volumes will be compressed in a single + # compression operation in order to achieve better overall compression= . + # + SECTION FV_IMAGE =3D FvPreMemory + SECTION FV_IMAGE =3D DXEFV + } +} + +!include DecomprScratchEnd.fdf.inc + + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf + +[Rule.Common.SEC.RESET_VECTOR] + FILE RAW =3D $(NAMED_GUID) { + RAW RAW |.raw + } + +[Rule.Common.SEC.RESET_SECMAIN] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER= ) + PE32 PE32 Align =3D 16 $(INF_OUTPUT)/$(MODULE_NAME).efi + } diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.f= df.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.i= nc new file mode 100644 index 0000000000..044129c941 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc @@ -0,0 +1,54 @@ +## @file +# FDF include file that defines the main macros and sets the dependent PC= Ds. +# +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Default flash size is 2MB. +# +# Defining FD_SIZE_2MB on the build command line can override this. +# + +DEFINE BLOCK_SIZE =3D 0x1000 +DEFINE VARS_SIZE =3D 0x3e000 +DEFINE VARS_BLOCKS =3D 0x3e + +DEFINE FW_BASE_ADDRESS =3D 0xFFE00000 +DEFINE FW_SIZE =3D 0x00200000 +DEFINE FW_BLOCKS =3D 0x200 +DEFINE CODE_BASE_ADDRESS =3D 0xFFE80000 +DEFINE CODE_SIZE =3D 0x00180000 +DEFINE CODE_BLOCKS =3D 0x180 +DEFINE FVMAIN_SIZE =3D 0x0016C000 +DEFINE SECFV_OFFSET =3D 0x001EC000 +DEFINE SECFV_SIZE =3D 0x14000 + + +SET gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress =3D $(FW_BASE_AD= DRESS) +SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize =3D $(FW_SIZE) +SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize =3D $(BLOCK_SIZE= ) + +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =3D $(F= W_BASE_ADDRESS) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0xE00= 0 + +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =3D gBo= ardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase + gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =3D $(B= LOCK_SIZE) + +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase =3D g= BoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase + gBoardModul= eTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D $(B= LOCK_SIZE) + +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =3D gBo= ardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x100= 00 + +SET gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFFE00000 +SET gEfiPchTokenSpaceGuid.PcdFlashAreaSize =3D 0x00200000 + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gEfiPchToken= SpaceGuid.PcdFlashAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gEfiPchTokenSpaceGu= id.PcdFlashAreaSize + +DEFINE MEMFD_BASE_ADDRESS =3D 0x800000 diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBu= ildOption.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPk= gBuildOption.dsc new file mode 100644 index 0000000000..25998b83e7 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOpti= on.dsc @@ -0,0 +1,78 @@ +## @file +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions.Common.EDKII] +# Append build options for EDK and EDKII drivers (=3D is Append, =3D=3D is= Replace) + + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D + +!if $(TARGET) =3D=3D "DEBUG" + DEFINE DEBUG_BUILD_FLAG =3D -D SERIAL_DBG_MSG=3D1 +!else + DEFINE DEBUG_BUILD_FLAG =3D -D MDEPKG_NDEBUG -D SILENT_MODE +!endif + + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD= _OPTIONS) $(DEBUG_BUILD_FLAG) +# +# PC_BUILD_END +# + + + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D $(EDKII_DSC_FEATURE_BUILD= _OPTIONS) + + + *_*_IA32_CC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + *_*_X64_CC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) + + + +# +# Enable source level debugging for RELEASE build +# +!if $(TARGET) =3D=3D "RELEASE" + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =3D /Zi + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =3D /Zi /Gm + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =3D /DEBUG + + MSFT:*_*_*_ASM_FLAGS =3D $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) + MSFT:*_*_*_CC_FLAGS =3D $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) + MSFT:*_*_*_DLINK_FLAGS =3D $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) +!endif + + +# +# Override the existing iasl path in tools_def.template +# +# MSFT:*_*_*_ASL_PATH =3D=3D c:/Iasl/iasl.exe + +# +# Override the VFR compile flags to speed the build time +# + +*_*_*_VFR_FLAGS =3D=3D -n + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection +#[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_= CORE] +# MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 +# GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support Memory= Attribute table +#[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] +# MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 +# GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgCo= nfig.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConf= ig.dsc new file mode 100644 index 0000000000..75de60e5bc --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.ds= c @@ -0,0 +1,56 @@ +## @file +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# TRUE is ENABLE. FALSE is DISABLE. +# + +[PcdsFixedAtBuild] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + +[PcdsFeatureFlag] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + + gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPc= d.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc new file mode 100644 index 0000000000..3bf10ee524 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc @@ -0,0 +1,281 @@ +## @file +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFeatureFlag.common] +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!endif + # Server doesn't support capsle update on Reset. + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + + +#S3 add + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE +#S3 add + + ## This PCD specified whether ACPI SDT protocol is installed. + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFeatureFlag.X64] + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE + +[PcdsDynamicExDefault] + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRU= E +!if $(TARGET) =3D=3D "RELEASE" + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 +!else + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 +#S3 modified + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE +#S3 modified + + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000 + + ## Specifies delay value in microseconds after sending out an INIT IPI. + # @Prompt Configure delay value after send an INIT IPI + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processorss + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + ## Defines the ACPI register set base address. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Timer IO Port Address + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0400 + + ## Defines the PCI Bus Number of the PCI device that contains the BAR an= d Enable for ACPI hardware registers. + # @Prompt ACPI Hardware PCI Bus Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x20091013 + + ## Defines the PCI Device Number of the PCI device that contains the BAR= and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Device Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F + + ## Defines the PCI Function Number of the PCI device that contains the B= AR and Enable for ACPI hardware registers. + # The invalid 0xFF is as its default value. It must be configured to th= e real value. + # @Prompt ACPI Hardware PCI Function Number + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x00 + + ## Defines the PCI Register Offset of the PCI device that contains the E= nable for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 + + ## Defines the bit mask that must be set to enable the APIC hardware reg= ister BAR. + # @Prompt ACPI Hardware PCI Bar Enable BitMask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 + + ## Defines the PCI Register Offset of the PCI device that contains the B= AR for ACPI hardware registers. + # The invalid 0xFFFF is as its default value. It must be configured to = the real value. + # @Prompt ACPI Hardware PCI Bar Register Offset + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 + + ## Defines the offset to the 32-bit Timer Value register that resides wi= thin the ACPI BAR. + # @Prompt Offset to 32-bit Timer register in ACPI BAR + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 + + ## Defines the bit mask to retrieve ACPI IO Port Base Address + # @Prompt ACPI IO Port Base Address Mask + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4 + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + +[PcdsFixedAtBuild.X64] + gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8 + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 + # Change PcdBootManagerMenuFile to UiApp +## + + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + + [PcdsPatchableInModule.common] + +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0 + +[PcdsDynamicExDefault.common.DEFAULT] + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0 + +[PcdsDynamicExHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|50 # Variable: L"Timeout" + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + + +[PcdsDynamicExDefault] + + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F + + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x= 45, 0x4C, 0x20} + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20465730303632= 53 + +[PcdsDynamicExDefault.X64] + + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 + + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + #gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE + #gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE +!endif + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xc000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + + # + # PCI feature overrides. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + +##########################################################################= ###### +# +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform +# +##########################################################################= ###### + +[PcdsDynamicDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + + gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 + gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0 + gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0 + gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0 + gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0 + gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0 + gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x800000000 + + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"Ver.1= .0.0" + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|"QSP U= EFI BIOS" + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|"QSP U= EFI BIOS" + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"2= 019-08-09" + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.i= nc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.inc new file mode 100644 index 0000000000..ea5b86228f --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.inc @@ -0,0 +1,53 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +0x00000000|0x0003e000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x80000 + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + #Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0= xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + #Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x03DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.c= fg b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg new file mode 100644 index 0000000000..72512837f5 --- /dev/null +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg @@ -0,0 +1,31 @@ +# @ build_config.cfg +# This is the BoardX58Ich10 board specific build settings +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D edk2-non-osi/Platform/Intel +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D SimicsOpenBoardPkg +PROJECT =3D SimicsOpenBoardPkg/BoardX58Ich10 +BOARD =3D BoardX58Ich10 +FLASH_MAP_FDF =3D SimicsOpenBoardPkg/BoardX58Ich10/Include/Fdf/FlashMapInc= lude.fdf +PROJECT_DSC =3D SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc +BOARD_PKG_PCD_DSC =3D SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D FALSE +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE --=20 2.16.2.windows.1