From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Tue, 10 Sep 2019 19:32:39 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Sep 2019 19:32:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,491,1559545200"; d="scan'208";a="175508086" Received: from orsmsx102.amr.corp.intel.com ([10.22.225.129]) by orsmga007.jf.intel.com with ESMTP; 10 Sep 2019 19:32:38 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.225]) by ORSMSX102.amr.corp.intel.com ([169.254.3.129]) with mapi id 14.03.0439.000; Tue, 10 Sep 2019 19:32:38 -0700 From: "Nate DeSimone" To: "Agyeman, Prince" , "devel@edk2.groups.io" CC: "Wei, David Y" , "Gao, Liming" , "Sinha, Ankit" , "Kubacki, Michael A" Subject: Re: [edk2-platforms] [PATCH 3/3] SimicsIch10Pkg: Fix GCC build issues Thread-Topic: [edk2-platforms] [PATCH 3/3] SimicsIch10Pkg: Fix GCC build issues Thread-Index: AQHVZ2RyYUiMAWjQdUWbBudPDL6bK6clw2Jw Date: Wed, 11 Sep 2019 02:32:37 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEEAB18E@ORSMSX114.amr.corp.intel.com> References: <53c8ae3dc3621bf64abfe21ceff0d04831df787e.1568070575.git.prince.agyeman@intel.com> In-Reply-To: <53c8ae3dc3621bf64abfe21ceff0d04831df787e.1568070575.git.prince.agyeman@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTdlMTVjODctMGMyNi00M2QyLTkyZGUtYTEzYTZhZmUxM2U5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZ0NzRXpZMFVLTHNpZWR0Q0U4WnVDYjVKZzhTM0lyOHFJRnpESlczUW9ubVZmaytXK3h0dDRHSnBkblFjYnlpUCJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Agyeman, Prince=20 Sent: Monday, September 9, 2019 4:15 PM To: devel@edk2.groups.io Cc: Wei, David Y ; Gao, Liming ; Sinha, Ankit ; Agyeman, Prince ; Kubacki, Michael A ; Desimone, Natha= niel L Subject: [edk2-platforms] [PATCH 3/3] SimicsIch10Pkg: Fix GCC build issues Cc: David Wei Cc: Liming Gao Cc: Ankit Sinha Cc: Agyeman Prince Cc: Kubacki Michael A Cc: Nate DeSimone Signed-off-by: Prince Agyeman --- .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 3 --- .../SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c | 7 ++----- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLi= b/SpiCommon.c b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommo= nLib/SpiCommon.c index bd08b2453b..3e7dffedfb 100644 --- a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCo= mmon.c +++ b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/Sp +++ iCommon.c @@ -637,7 +637,6 @@ SendSpiCmd ( EFI_STATUS Status; UINT32 Index; SPI_INSTANCE *SpiInstance; - UINTN SpiBaseAddress; UINTN PchSpiBar0; UINT32 HardwareSpiAddr; UINT32 FlashRegionSize; @@ -648,9 +647,7 @@ SendSpiCmd ( =20 Status =3D EFI_SUCCESS; SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); - SpiBaseAddress =3D SpiInstance->PchSpiBase; PchSpiBar0 =3D AcquireSpiBar0 (SpiInstance); - SpiBaseAddress =3D SpiInstance->PchSpiBase; ABase =3D SpiInstance->PchAcpiBase; =20 // diff --git a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2= Dxe.c b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c index 268b04d25a..cc2d00b785 100644 --- a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c +++ b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe. +++ c @@ -131,7 +131,6 @@ SmmControl2DxeTrigger ( IN UINTN ActivationInterval OPTIONAL ) { - EFI_STATUS Status; // // No support for queued or periodic activation. // @@ -141,7 +140,7 @@ SmmControl2DxeTrigger ( /// /// Clear any pending the APM SMI /// - Status =3D SmmClear(); + SmmClear(); // // The so-called "Advanced Power Management Status Port Register" is in = fact // a generic data passing register, between the caller and the SMI @@ -1= 81,8 +180,6 @@ SmmControl2DxeClear ( IN BOOLEAN Periodic OPTIONAL ) { - EFI_STATUS Status; - if (Periodic) { return EFI_INVALID_PARAMETER; } @@ -201,7 +198,7 @@ SmmControl2DxeClear ( // // So, nothing to do here. // - Status =3D SmmClear(); + SmmClear(); =20 return EFI_SUCCESS; } -- 2.19.1.windows.1