From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by groups.io with SMTP; Mon, 23 Sep 2019 01:04:06 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 01:04:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="363554521" Received: from orsmsx108.amr.corp.intel.com ([10.22.240.6]) by orsmga005.jf.intel.com with ESMTP; 23 Sep 2019 01:04:04 -0700 Received: from orsmsx156.amr.corp.intel.com (10.22.240.22) by ORSMSX108.amr.corp.intel.com (10.22.240.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 23 Sep 2019 01:04:03 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.55]) by ORSMSX156.amr.corp.intel.com ([169.254.8.15]) with mapi id 14.03.0439.000; Mon, 23 Sep 2019 01:04:02 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chiu, Chasel" , "Sinha, Ankit" , Jeremy Soller Subject: Re: [edk2-platforms][PATCH V1 02/12] ClevoOpenBoardPkg: Remove package contents Thread-Topic: [edk2-platforms][PATCH V1 02/12] ClevoOpenBoardPkg: Remove package contents Thread-Index: AQHVb+MAeeSw1/SpDUSjHkAz9MYY96c46t0w Date: Mon, 23 Sep 2019 08:04:01 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEF0A5D5@ORSMSX114.amr.corp.intel.com> References: <20190920184030.6148-1-michael.a.kubacki@intel.com> <20190920184030.6148-3-michael.a.kubacki@intel.com> In-Reply-To: <20190920184030.6148-3-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTVhNGM2NjYtMDBlYS00MzljLTljZTQtMTg4Njg5MGFmMTk1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiNUNtWFVwcW1EbXBLVndPbWx4REl5TVdXRE9tM095NDQwMjlCZG1TbHVcLzJjK1wvVmNBT1pEd3g2WWh2MW10elhuIn0= x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable This patch is on the hairy edge of being too big, but I'll allow it this ti= me. Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A =20 Sent: Friday, September 20, 2019 11:40 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Sinha, Ankit ; Jeremy Soller = Subject: [edk2-platforms][PATCH V1 02/12] ClevoOpenBoardPkg: Remove package= contents REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2207 The N1xxWU board contents will be moved to KabylakeOpenBoardPkg to reduce code duplication between ClevoOpenBoardPkg and KabylakeOpenBoardPkg. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Ankit Sinha Cc: Jeremy Soller Signed-off-by: Michael Kubacki --- Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec = | 305 ---- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc = | 385 ---- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc = | 151 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc = | 132 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc = | 265 --- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf = | 48 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf = | 716 -------- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf = | 69 - Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf = | 59 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeT= btPolicyLib.inf | 67 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLi= b/TbtCommonLib.inf | 62 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiT= btPolicyLib.inf | 56 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitL= ib/PeiDTbtInitLib.inf | 41 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf = | 49 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf = | 44 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf = | 77 - Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpan= derLib.inf | 33 - Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.i= nf | 36 - Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeria= lPortLibSpiFlash.inf | 50 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf | 43 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 146 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePl= atformHookLib.inf | 51 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiT= ableLib.inf | 47 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoard= AcpiSupportLib.inf | 48 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiE= nableLib.inf | 47 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoard= AcpiSupportLib.inf | 48 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitP= ostMemLib.inf | 53 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitP= reMemLib.inf | 132 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoard= InitPostMemLib.inf | 55 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoard= InitPreMemLib.inf | 137 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatfor= mPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpd= ateLib/DxeSiliconPolicyUpdateLib.inf | 49 - Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h = | 130 -- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsAreaDef.h= | 62 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtPolicy= Lib.h | 46 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtPolicy= Lib.h | 41 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtCommonLib= .h | 241 --- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolicy.h = | 29 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiD= TbtInitLib.h | 108 -- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library/PeiT= btCommonInitLib.h | 41 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbtPolic= y.h | 110 -- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvsArea.= h | 42 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h = | 22 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommonDefin= ition.h | 77 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeT= btPolicyLibrary.h | 22 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiT= btPolicyLibrary.h | 17 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.h = | 179 -- Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h = | 116 -- Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h = | 67 - Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h = | 122 -- Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h = | 33 - Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h = | 51 - Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h = | 47 - Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h = | 157 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiPchPolicyUpdate.h | 28 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.h | 30 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h = | 13 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInit= Lib.h | 42 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpd= ateLib/DxeGopPolicyInit.h | 39 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpd= ateLib/DxeSaPolicyInit.h | 64 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c = | 95 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c = | 307 ---- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c = | 776 -------- Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c = | 351 ---- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/DxeT= btPolicyLib.c | 160 -- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommonLi= b/TbtCommonLib.c | 315 ---- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/PeiT= btPolicyLib.c | 204 --- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbtInitL= ib/PeiDTbtInitLib.c | 566 ------ Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c = | 228 --- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.c = | 193 -- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandler.c = | 1610 -----------= ------ Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c = | 1764 -----------= ------- Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpan= derLib.c | 306 ---- Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccessLib.c= | 115 -- Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSeria= lPortLibSpiFlash.c | 320 ---- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c | 103 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PcieDeviceTable.c | 115 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 87 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiFspPolicyUpdateLib.c | 186 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiPchPolicyUpdate.c | 153 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 248 --- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.c | 84 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 75 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/BasePl= atformHookLib.c | 662 ------- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoardAcpiT= ableLib.c | 36 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMultiBoard= AcpiSupportLib.c | 43 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1xxWUAcpi= TableLib.c | 74 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoardAcpiE= nableLib.c | 62 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMultiBoard= AcpiSupportLib.c | 81 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN1xxWUAcpi= EnableLib.c | 39 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSiliconAcp= iEnableLib.c | 168 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUGpioTab= le.c | 370 ---- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHdaVerb= Tables.c | 232 --- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHsioPts= sTables.c | 105 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUSpdTabl= e.c | 426 ----- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitP= ostMemLib.c | 39 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoardInitP= reMemLib.c | 105 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoard= InitPostMemLib.c | 40 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoard= InitPreMemLib.c | 82 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUDete= ct.c | 66 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInit= PostMemLib.c | 209 --- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInit= PreMemLib.c | 236 --- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatfor= mPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 ------- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpd= ateLib/DxeGopPolicyInit.c | 175 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpd= ateLib/DxeSaPolicyUpdate.c | 65 - Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpd= ateLib/DxeSiliconPolicyUpdateLib.c | 54 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL = | 37 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl = | 21 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl = | 246 --- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL = | 121 -- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl = | 850 --------- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl = | 33 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL = | 199 -- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl = | 88 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL = | 116 -- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl = | 306 ---- Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl = | 1129 -----------= - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl = | 8 - Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl = | 27 - Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3SptPcieTbt.as= l | 403 ----- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl = | 1894 -----------= --------- Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs.asl = | 56 - Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl = | 114 -- Platform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg = | 33 - 124 files changed, 23595 deletions(-) diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec b/Platform/I= ntel/ClevoOpenBoardPkg/OpenBoardPkg.dec deleted file mode 100644 index 28aedfef59..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec +++ /dev/null @@ -1,305 +0,0 @@ -## @file -# Clevo board declaration file. -# -# The DEC files are used by the utilities that parse DSC and -# INF files to generate AutoGen.c and AutoGen.h files -# for the build infrastructure. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## -[Defines] -DEC_SPECIFICATION =3D 0x00010017 -PACKAGE_NAME =3D OpenBoardPkg -PACKAGE_VERSION =3D 0.1 -PACKAGE_GUID =3D D04CCA80-5F71-478D-9A26-72BC751D0106 - -[Includes] -Include -N1xxWU/Include -Features/Tbt/Include - -[Guids] -gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, {0= xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} -gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} -gSpiFlashDebugHobGuid =3D {0xcaaaf418, 0x38a5, 0x4d49, {0= xbe, 0x74, 0xe6, 0x06, 0xe4, 0x02, 0x6d, 0x25}} -gTbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0= xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} -gPlatformModuleTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0= xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} - -[Protocols] -gTbtNvsAreaProtocolGuid =3D {0x4d6a54d1, 0xcd56, 0x47f3, {0= x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}} -gDxeTbtPolicyProtocolGuid =3D {0x196bf9e3, 0x20d7, 0x4b7b, {0= x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}} - -[Ppis] -gPeiTbtPolicyPpiGuid =3D {0xd7e7e1e6, 0xcbec, 0x4f5f, {0= xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}} -gPeiTbtPolicyBoardInitDonePpiGuid =3D {0x970f9c60, 0x8547, 0x49d7, { = 0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}} - -[LibraryClasses] - -[PcdsFixedAtBuild, PcdsPatchableInModule] - -[PcdsFixedAtBuild] - -gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004 -gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005 - -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018 -gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F - -gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000= 001C -gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D - -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000= 021 -gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x900000= 22 - -## Tbt SW_SMI_DTBT_ENUMERATEgSetupVariableGuid -gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x000000110 - -gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 - -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000|UINT32|0x= 90000030 -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000|UINT32|0x= 90000031 -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x00000000|UINT32|= 0x90000032 - -[PcdsDynamic] - -# Board GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x00000011= 4 - -# Board Expander GPIO Table -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047 - -# TouchPanel & SDHC CD GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048 - -# PCH-LP HSIO PTSS Table -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x000000= 4C -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x000000= 4D -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x0000= 0050 -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x0000= 0051 - -# PCH-H HSIO PTSS Table -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x0000005= 4 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x0000005= 5 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000= 058 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000= 059 - -# HDA Verb Table -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B -gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F -gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060 - -# SA Misc Configuration -gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 -gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067 -gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101 - -# DRAM Configuration -gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068 -gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069 -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x= 0000006E -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006= F -gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070 -gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071 - -# PEG RESET GPIO -gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072 -gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073 -gBoardModuleTokenSpaceGuid.PcdPegResetGpioPad|0|UINT32|0x00000074 -gBoardModuleTokenSpaceGuid.PcdPegResetGpioActive|FALSE|BOOLEAN|0x00000075 -gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079 -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007= F - -# SPD Address Table -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099 -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C - -# CA Vref Configuration -gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D - -# Root Port Clock Info -gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo|0|UINT64|0x0000009E -gBoardModuleTokenSpaceGuid.PcdRootPort1ClkInfo|0|UINT64|0x0000009F -gBoardModuleTokenSpaceGuid.PcdRootPort2ClkInfo|0|UINT64|0x000000A0 -gBoardModuleTokenSpaceGuid.PcdRootPort3ClkInfo|0|UINT64|0x000000A1 -gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo|0|UINT64|0x000000A2 -gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo|0|UINT64|0x000000A3 -gBoardModuleTokenSpaceGuid.PcdRootPort6ClkInfo|0|UINT64|0x000000A4 -gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo|0|UINT64|0x000000A5 -gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo|0|UINT64|0x000000A6 -gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo|0|UINT64|0x000000A7 -gBoardModuleTokenSpaceGuid.PcdRootPort10ClkInfo|0|UINT64|0x000000A8 -gBoardModuleTokenSpaceGuid.PcdRootPort11ClkInfo|0|UINT64|0x000000A9 -gBoardModuleTokenSpaceGuid.PcdRootPort12ClkInfo|0|UINT64|0x000000AA -gBoardModuleTokenSpaceGuid.PcdRootPort13ClkInfo|0|UINT64|0x000000AB -gBoardModuleTokenSpaceGuid.PcdRootPort14ClkInfo|0|UINT64|0x000000AC -gBoardModuleTokenSpaceGuid.PcdRootPort15ClkInfo|0|UINT64|0x000000AD -gBoardModuleTokenSpaceGuid.PcdRootPort16ClkInfo|0|UINT64|0x000000AE -gBoardModuleTokenSpaceGuid.PcdRootPort17ClkInfo|0|UINT64|0x000000AF -gBoardModuleTokenSpaceGuid.PcdRootPort18ClkInfo|0|UINT64|0x000000B0 -gBoardModuleTokenSpaceGuid.PcdRootPort19ClkInfo|0|UINT64|0x000000B1 -gBoardModuleTokenSpaceGuid.PcdRootPort20ClkInfo|0|UINT64|0x000000B2 -gBoardModuleTokenSpaceGuid.PcdRootPort21ClkInfo|0|UINT64|0x000000B3 -gBoardModuleTokenSpaceGuid.PcdRootPort22ClkInfo|0|UINT64|0x000000B4 -gBoardModuleTokenSpaceGuid.PcdRootPort23ClkInfo|0|UINT64|0x000000B5 -gBoardModuleTokenSpaceGuid.PcdRootPort24ClkInfo|0|UINT64|0x000000B6 -gBoardModuleTokenSpaceGuid.PcdRootPort25ClkInfo|0|UINT64|0x000000B7 -gBoardModuleTokenSpaceGuid.PcdRootPort26ClkInfo|0|UINT64|0x000000B8 -gBoardModuleTokenSpaceGuid.PcdRootPort27ClkInfo|0|UINT64|0x000000B9 -gBoardModuleTokenSpaceGuid.PcdRootPort28ClkInfo|0|UINT64|0x000000BA -gBoardModuleTokenSpaceGuid.PcdRootPort29ClkInfo|0|UINT64|0x000000BB -gBoardModuleTokenSpaceGuid.PcdRootPort30ClkInfo|0|UINT64|0x000000BC -gBoardModuleTokenSpaceGuid.PcdRootPort31ClkInfo|0|UINT64|0x000000BD -gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo|0|UINT64|0x000000BE - -# USB 2.0 Port AFE -gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF -gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0 -gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1 -gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2 -gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3 -gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4 -gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5 -gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6 -gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7 -gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8 -gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9 -gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA -gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB -gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC -gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD -gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE - -# USB 2.0 Port Over Current Pin -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE - -# USB 3.0 Port Over Current Pin -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8 - -# TBT -gBoardModuleTokenSpaceGuid.PcdDTbtBootOn |0|UINT8|0x000000E9 -gBoardModuleTokenSpaceGuid.PcdDTbtUsbOn |0|UINT8|0x000000EA -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwr |0|UINT8|0x000000EB -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly |0|UINT16|0x000000ED -gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn |0|UINT8|0x000000EE -gBoardModuleTokenSpaceGuid.PcdDTbtControllerType |0|UINT8|0x000000EF -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber |0|UINT8|0x000000F0 -gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType |0|UINT8|0x000000F1 -gBoardModuleTokenSpaceGuid.PcdExpander |0|UINT8|0x000000F2 -gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3 -gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4 -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5 -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature |0|UINT32|0x000000F6 -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting |0|BOOLEAN|0x000= 000F7 -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode |0|UINT8|0x000000F8 -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter |0|UINT8|0x000000F9 -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD -gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE -gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116 -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support |0|UINT8|0x000000102 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay |0|UINT16|0x00000103 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay |0|UINT16|0x00000104 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd |0|UINT8|0x00000105 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd |0|UINT16|0x00000106 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109 -gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0|UINT32|0x00000117 - -# UCMC GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111 -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112 - -# Misc -gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC - -gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000009 -gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002 -gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003 -gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004 -gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005 -gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006 -gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A -gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B -gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C -# 0: Type-C -# 1: Stacked-Jack -gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012 -gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013 -gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xe= b, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|= 0x40000014 - -[PcdsDynamicEx] - -[PcdsDynamic, PcdsDynamicEx] - -[PcdsPatchableInModule] - -[PcdsFeatureFlag] - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF00000= 62 - - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|0xF00000= 00 - - gBoardModuleTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN|0x00000= 0115 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc deleted file mode 100644 index 516685c514..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ /dev/null @@ -1,385 +0,0 @@ -## @file -# Clevo N1xxWU board description file. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## -[Defines] - # - # Set platform specific package/folder name, same as passed from PREBUIL= D script. - # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package= build folder - # DEFINE only takes effect at R9 DSC and FDF. - # - DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg - DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg - DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE =3D KabylakeFspBinPkg - DEFINE PLATFORM_BOARD_PACKAGE =3D ClevoOpenBoardPkg - DEFINE BOARD =3D N1xxWU - DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD) - - # - # Platform On/Off features are defined here - # - !include OpenBoardPkgConfig.dsc - -##########################################################################= ###### -# -# Defines Section - statements that will be processed to create a Makefile= . -# -##########################################################################= ###### -[Defines] - PLATFORM_NAME =3D $(PLATFORM_PACKAGE) - PLATFORM_GUID =3D 7324F33D-4E96-4F8B-A550-544DE616= 2AB7 - PLATFORM_VERSION =3D 0.1 - DSC_SPECIFICATION =3D 0x00010005 - OUTPUT_DIRECTORY =3D Build/$(PROJECT) - SUPPORTED_ARCHITECTURES =3D IA32|X64 - BUILD_TARGETS =3D DEBUG|RELEASE - SKUID_IDENTIFIER =3D ALL - - - FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf - - FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 - DEFINE TOP_MEMORY_ADDRESS =3D 0x0 - - # - # Default value for OpenBoardPkg.fdf use - # - DEFINE BIOS_SIZE_OPTION =3D SIZE_60 - -##########################################################################= ###### -# -# SKU Identification section - list of all SKU IDs supported by this -# Platform. -# -##########################################################################= ###### -[SkuIds] - 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. - 0x60|N1xxWU - -##########################################################################= ###### -# -# Library Class section - list of all Library Classes needed by this Platf= orm. -# -##########################################################################= ###### - -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc -!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc - -[LibraryClasses.common] - - PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf - - PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf - PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf - PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf - I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf - GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf - - PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf - - FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf - PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf= ormSecLib/SecFspWrapperPlatformSecLib.inf - - FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf - FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf - - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf - SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf - - ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf - SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInit= Lib.inf - - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf - -# Tbt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf - DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf -!endif -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc - -[LibraryClasses.IA32.SEC] - SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf - SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf - -[LibraryClasses.IA32] - # - # PEI phase common - # - SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf - DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf - -# Tbt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf - PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf -!endif -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc - -[LibraryClasses.X64] - # - # DXE phase common - # - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/DxeMultiBoardInitSupportLib.inf - MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/DxeMultiBoardAcpiSupportLib.inf - BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf - - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInit= Lib/DxeSiliconPolicyInitLib.inf - SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateL= ib/DxeSiliconPolicyUpdateLib.inf - -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc - -[LibraryClasses.X64.DXE_SMM_DRIVER] - SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf - MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf - BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf - -[LibraryClasses.X64.DXE_RUNTIME_DRIVER] - ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf - -!include OpenBoardPkgPcd.dsc - -[Components.IA32] - -# -# Common -# -!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc - - # - # Core - # - MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { - - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - } - - # - # FSP wrapper SEC Core - # - UefiCpuPkg/SecCore/SecCore.inf { - - #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } - -# -# Silicon -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc - -# -# Platform -# - $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf - $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPreMem.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.i= nf -!else - NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf -!endif - } - IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { - - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf - } - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf{ - - # # - # Hook a library constructor to update some policy fields when policy = installed. - # - NULL|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMem= SiliconPolicyNotifyLib.inf - } - - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.= inf -!else - NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf -!endif - } - - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { - - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf - } - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf - -# -# Security -# - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf -!endif - - IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf - IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf - -# Tbt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf -!endif - -[Components.X64] - -# -# Common -# -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc - - UefiCpuPkg/CpuDxe/CpuDxe.inf - MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf - MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - - # - # Shell - # - ShellPkg/Application/Shell/Shell.inf { - - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com= mandsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C= ommandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C= ommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C= ommandsLib.inf - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand= Lib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars= ingLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg= CommandLib.inf - ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib= .inf - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf - } - -# -# Silicon -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc - -# Tbt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf - $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf -!endif - -# -# Platform -# - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf - IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf - - $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - - $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf - $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf - -# -# OS Boot -# -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableL= ib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf -!endif - } - $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableL= ib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf -!endif - } - $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnabl= eLib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf -!endif - } - - $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf - - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 - -!if $(TARGET) =3D=3D DEBUG - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf -!endif - } - -!endif - -# -# Security -# - $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf -!endif - - IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf - -# -# Other -# - $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf - -!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc -!include OpenBoardPkgBuildOption.dsc diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOptio= n.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc deleted file mode 100644 index 31e7f41c65..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc +++ /dev/null @@ -1,151 +0,0 @@ -## @file -# Clevo N1xxWU board build option configuration. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[BuildOptions] -# Define Build Options both for EDK and EDKII drivers. - - - DEFINE DSC_S3_BUILD_OPTIONS =3D - - DEFINE DSC_CSM_BUILD_OPTIONS =3D - -!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE - DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1 -!else - DEFINE DSC_ACPI_BUILD_OPTIONS =3D -!endif - - DEFINE BIOS_GUARD_BUILD_OPTIONS =3D - - DEFINE OVERCLOCKING_BUILD_OPTION =3D - - DEFINE FSP_BINARY_BUILD_OPTIONS =3D - - DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG - - DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D - - DEFINE RESTRICTED_OPTION =3D - - - DEFINE SV_BUILD_OPTIONS =3D - - DEFINE TEST_MENU_BUILD_OPTION =3D - -!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE - DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- -!else - DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -!endif - - DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D - - - DEFINE TPM_BUILD_OPTION =3D - - DEFINE TPM2_BUILD_OPTION =3D - - DEFINE DSC_TBT_BUILD_OPTIONS =3D - - DEFINE DSC_DCTT_BUILD_OPTIONS =3D - - DEFINE EMB_BUILD_OPTIONS =3D - - DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D -DMEM_DOWN_FLAG=3D1 - - DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D - - DEFINE BOOT_GUARD_BUILD_OPTIONS =3D - - DEFINE SECURE_BOOT_BUILD_OPTIONS =3D - - DEFINE USBTYPEC_BUILD_OPTION =3D - - DEFINE CAPSULE_BUILD_OPTIONS =3D - - DEFINE PERFORMANCE_BUILD_OPTION =3D - - DEFINE DEBUGUSEUSB_BUILD_OPTION =3D - - DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D -DDISABLE_NEW_= DEPRECATED_INTERFACES=3D1 - - DEFINE SINITBIN_BUILD_OPTION =3D - - DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1 - -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTI= ONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_= OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS) -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGU= SEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS) -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_T= EMPRAM_INIT_AND_EXIT_OPTIONS) -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_B= UILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_= BUILD_OPTION) -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS) -DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYP= EC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION) - -[BuildOptions.Common.EDKII] - -# -# For IA32 Global Build Flag -# - *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI - *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_IA32_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - -# -# For IA32 Specific Build Flag -# -GCC: *_*_IA32_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -GCC: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D = PI_SPECIFICATION_VERSION=3D0x00010015 -Wno-unused -Wl,--allow-multiple-defi= nition -MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI -MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) - -# -# For X64 Global Build Flag -# - *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 - *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - *_*_X64_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - - -# -# For X64 Specific Build Flag -# -GCC: *_*_X64_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -GCC: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 -Wno-unused -Wl,--allow-multiple-defin= ition -MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -MSFT: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -MSFT: *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) - - -# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection -[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_C= ORE] - MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 - GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 - -# Force PE/COFF sections to be aligned at 4KB boundaries to support Memory= Attribute table -[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] - MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 - GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 - -# Force PE/COFF sections to be aligned at 4KB boundaries to support NX pro= tection -[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE,= BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPL= ICATION] - #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 - #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc= b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc deleted file mode 100644 index ea759776fb..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgConfig.dsc +++ /dev/null @@ -1,132 +0,0 @@ -## @file -# Clevo N1xxWU board configuration. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[PcdsFixedAtBuild] - # - # Please select BootStage here. - # Stage 1 - enable debug (system deadloop after debug init) - # Stage 2 - mem init (system deadloop after mem init) - # Stage 3 - boot to shell only - # Stage 4 - boot to OS - # Stage 5 - boot to OS with security boot enabled - # - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 - -[PcdsFeatureFlag] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE -!endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - -# -# TRUE is ENABLE. FALSE is DISABLE. -# - -# -# BIOS build switches configuration -# - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - -# CPU - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @tod= o Convert TXT ASM to NASM - gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE - -# SA - gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE - gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE - gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE - -# ME - gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE - gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE - - gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE - gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE - gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE - gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE - -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # - - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif - - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/= Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc deleted file mode 100644 index 83cbd18557..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc +++ /dev/null @@ -1,265 +0,0 @@ -## @file -# Clevo N1xxWU board PCD configuration. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -##########################################################################= ###### -# -# Pcd Section - list of all EDK II PCD Entries defined by this Platform -# -##########################################################################= ###### -[PcdsFeatureFlag.common] - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE -!if $(TARGET) =3D=3D RELEASE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE -!else - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE -!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE - -[PcdsFixedAtBuild.common] - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 -!endif - - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 - - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 - - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 -!if $(TARGET) =3D=3D RELEASE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 -!endif - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 - - gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE - - # - # 8MB Default - # - gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 - - # - # 16MB TSEG in Debug build only. - # - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 - !endif - - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC - - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 - !endif - - # - # FSP Base address PCD will be updated in FDF basing on flash map. - # - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 - - ## Specifies the size of the microcode Region. - # @Prompt Microcode Region size. - gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 - - ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - - ## Specifies the AP wait loop state during POST phase. - # The value is defined as below. - # 1: Place AP in the Hlt-Loop state. - # 2: Place AP in the Mwait-Loop state. - # 3: Place AP in the Run-Loop state. - # @Prompt The AP wait loop state. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 - - # - # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags - # - # BIT0: If set, expresses that for all synchronous SMM entries,SMM will = validate that input and output buffers lie entirely within the expected fix= ed memory regions. - # BIT1: If set, expresses that for all synchronous SMM entries, SMM will= validate that input and output pointers embedded within the fixed communic= ation buffer only refer to address ranges \ - # that lie entirely within the expected fixed memory regions. - # BIT2: Firmware setting this bit is an indication that it will not allo= w reconfiguration of system resources via non-architectural mechanisms. - # BIT3-31: Reserved - # - gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 - - # - # See HstiFeatureBit.h for the definition - # - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6 - gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} -!endif - -[PcdsFixedAtBuild.IA32] - gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 - gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 - -[PcdsFixedAtBuild.X64] - # Default platform supported RFC 4646 languages: (American) English - gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" - -[PcdsPatchableInModule.common] - gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 - -!if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 -!endif - -[PcdsDynamicHii.X64.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" -!endif - -[PcdsDynamicDefault] - # - # FSP Base address PCD will be updated in FDF basing on flash map. - # - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 - # Platform will pre-allocate UPD buffer and pass it to FspWrapper - # Those dummy address will be patched before FspWrapper executing - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF - -[PcdsDynamicDefault.common.DEFAULT] - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE - # - # Set video to native resolution as Windows 8 WHCK requirement. - # - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 - - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 - -[PcdsDynamicDefault.common.DEFAULT] - # gEfiTpmDeviceInstanceTpm20DtpmGuid - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} - gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 - gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 - - # Tbt - gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType | 0x2 - gBoardModuleTokenSpaceGuid.PcdExpander | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature | 0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting | 0 - gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode | 0x1 - #gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support | 0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay | 0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay | 5000 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd | 56 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd | 100 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapIn= clude.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInc= lude.fdf deleted file mode 100644 index d48f8c7a2a..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.f= df +++ /dev/null @@ -1,48 +0,0 @@ -## @file -# Flash map layout file for the Clevo N1xxWU board. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# -# 6 M BIOS - for FSP wrapper -#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# -DEFINE FLASH_BASE =3D 0x= FFA20000 # -DEFINE FLASH_SIZE =3D 0x= 005E0000 # -DEFINE FLASH_BLOCK_SIZE =3D 0x= 00010000 # -DEFINE FLASH_NUM_BLOCKS =3D 0x= 0000005E # -#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# - -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFFA20000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D 0x= 00040000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFFA20000) -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x= 0001E000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D 0x= 0001E000 # Flash addr (0xFFA3E000) -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x= 00002000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFFA40000) -SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x= 00020000 # -SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset =3D 0x= 00040000 # Flash addr (0xFFA60000) -SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize =3D 0x= 00010000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00050000 # Flash addr (0xFFA70000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 000B0000 # Flash addr (0xFFAD0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00070000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00120000 # Flash addr (0xFFB40000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 00090000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 001B0000 # Flash addr (0xFFBD0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00140000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 002F0000 # Flash addr (0xFFD10000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 000B0000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 003A0000 # Flash addr (0xFFDC0000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00440000 # Flash addr (0xFFE60000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00060000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 004A0000 # Flash addr (0xFFEC0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000BC000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 0055C000 # Flash addr (0xFFF7C000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00004000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 00560000 # Flash addr (0xFFF80000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00080000 # diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf deleted file mode 100644 index c21ffbc4ca..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf +++ /dev/null @@ -1,716 +0,0 @@ -## @file -# Clevo N1xxWU board flash file. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf - -##########################################################################= ###### -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -##########################################################################= ###### -[FD.N1xxWU] -# -# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, c= annot be -# assigned with PCD values. Instead, it uses the definitions for its varie= ty, which -# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. -# -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAdd= ress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device -ErasePolarity =3D 1 -BlockSize =3D $(FLASH_BLOCK_SIZE) -NumBlocks =3D $(FLASH_NUM_BLOCKS) - -DEFINE SIPKG_DXE_SMM_BIN =3D INF -DEFINE SIPKG_PEI_BIN =3D INF - -# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr= o expression is not supported. -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to= get the real CodeCache base address. -SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffs= et) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize -##########################################################################= ###### -# -# Following are lists of FD Region layout which correspond to the location= s of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by -# the pipe "|" character, followed by the size of the region, also in hex = with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# Fv Size can be adjusted -# -##########################################################################= ###### -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -#NV_VARIABLE_STORE -DATA =3D { - ## This is the EFI_FIRMWARE_VOLUME_HEADER - # ZeroVector [] - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - # FileSystemGuid - 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, - 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, - # FvLength: 0x40000 - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, - #Signature "_FVH" #Attributes - 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00, - #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision - # - # Be careful on CheckSum field. - # - 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02, - #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, - #Blockmap[1]: End - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - ## This is the VARIABLE_STORE_HEADER -!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE - # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0x= 439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} - 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, - 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, -!else - # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98,= 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} - 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, - 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, -!endif - #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x1DFB8 - # This can speed up the Variable Dispatch a bit. - 0xB8, 0xDF, 0x01, 0x00, - #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 - 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -#NV_FTW_WORKING -DATA =3D { - # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D - # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} - 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, - 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, - # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved - 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, - # WriteQueueSize: UINT64 - 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -} - -gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize -#NV_FTW_SPARE - -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardModuleTokenS= paceGuid.PcdFlashNvDebugMessageSize -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardModuleTokenSpa= ceGuid.PcdFlashNvDebugMessageSize -#DEBUG_MESSAGE_AREA - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvAdvancedSize -FV =3D FvAdvanced - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvSecuritySize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvSecuritySize -FV =3D FvSecurity - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvOsBootSize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize -FV =3D FvOsBoot - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvUefiBootSize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvUefiBootSize -FV =3D FvUefiBoot - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize -FV =3D FvPostMemory - -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvSize -#Microcode -FV =3D FvMicrocode - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSSize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspSSize -# FSP_S Section -FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspMSize -# FSP_M Section -FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTSize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspTSize -# FSP_T Section -FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd - -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTok= enSpaceGuid.PcdFlashFvPreMemorySize -gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgToken= SpaceGuid.PcdFlashFvPreMemorySize -FV =3D FvPreMemory - -##########################################################################= ###### -# -# FV Section -# -# [FV] section is used to define what components or modules are placed wit= hin a flash -# device file. This section also defines order the components and modules= are positioned -# within the image. The [FV] section consists of define statements, set s= tatements and -# module statements. -# -##########################################################################= ###### -[FV.FvMicrocode] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D FALSE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D FALSE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE - -INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microc= odeUpdates.inf - -[FV.FvPreMemory] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D - -INF UefiCpuPkg/SecCore/SecCore.inf -INF MdeModulePkg/Core/Pei/PeiMain.inf -!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf - -INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf -INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/Platfor= mInitPei/PlatformInitPreMem.inf -INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf -INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM= em.inf - -[FV.FvPostMemoryUncompact] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 - -!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf - -# Init Board Config PCD -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i= nf -INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf -INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPost= Mem.inf - -!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE -FILE FREEFORM =3D 4ad46122-ffeb-4a52-bfb0-518cfca02db0 { - SECTION RAW =3D N1xxWU/Gop/Vbt.bin - SECTION UI =3D "Vbt" -} -FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D { - SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp -} -!endif # PcdPeiDisplayEnable - -[FV.FvPostMemory] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917 - -FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE { - SECTION FV_IMAGE =3D FvPostMemoryUncompact - } -} - -[FV.FvUefiBootUncompact] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5 - -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf - -INF UefiCpuPkg/CpuDxe/CpuDxe.inf -INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - -INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf -INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf -INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf -INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.in= f -INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - -INF ShellPkg/Application/Shell/Shell.inf - -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf -INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf - -INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf - -[FV.FvUefiBoot] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B - -FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { - SECTION FV_IMAGE =3D FvUefiBootUncompact - } - } - -[FV.FvOsBootUncompact] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC - -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf - -INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE -INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.in= f -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf -INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf - -INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf -INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf - -INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/Boar= dAcpiDxe/BoardAcpiDxe.inf - -INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - -!endif - -[FV.FvLateSilicon] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitD= xe.inf - -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmA= ccess.inf - -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSm= iDispatcher.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmC= ontrol.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf -$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf - -INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab= les/SaAcpiTables.inf -INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab= les/SaSsdt/SaSsdt.inf - -!endif - -[FV.FvOsBoot] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A - -FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { - SECTION FV_IMAGE =3D FvOsBootUncompact - } - } - -FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { - SECTION FV_IMAGE =3D FvLateSilicon - } - } - -[FV.FvSecurityPreMemory] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 #FV alignment and FV attributes setting. -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B - -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf - -INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS= amplePei.inf - -INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf - -[FV.FvSecurityPostMemory] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 #FV alignment and FV attributes setting. -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A - -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE -INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf -!endif - -[FV.FvSecurityLate] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C - -!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf - -INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - -INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf - -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - -INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE -INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf -!endif - -!endif - -[FV.FvSecurity] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF - -FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 { - SECTION FV_IMAGE =3D FvSecurityPreMemory - } - -FILE FV_IMAGE =3D 80BB8482-44D5-4BEC-82B5-8D87A933830B { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { - SECTION FV_IMAGE =3D FvSecurityPostMemory - } - } - -FILE FV_IMAGE =3D C83522D9-80A1-4D95-8C25-3F1370497406 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { - SECTION FV_IMAGE =3D FvSecurityLate - } - } - -[FV.FvAdvancedPreMem] -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 - -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE -INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf -!endif - -[FV.FvAdvancedPostMem] -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27 - -[FV.FvAdvancedLate] -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D - -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE -INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf -INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf -INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf -!endif - -[FV.FvAdvanced] -BlockSize =3D $(FLASH_BLOCK_SIZE) -FvAlignment =3D 16 -ERASE_POLARITY =3D 1 -MEMORY_MAPPED =3D TRUE -STICKY_WRITE =3D TRUE -LOCK_CAP =3D TRUE -LOCK_STATUS =3D TRUE -WRITE_DISABLED_CAP =3D TRUE -WRITE_ENABLED_CAP =3D TRUE -WRITE_STATUS =3D TRUE -WRITE_LOCK_CAP =3D TRUE -WRITE_LOCK_STATUS =3D TRUE -READ_DISABLED_CAP =3D TRUE -READ_ENABLED_CAP =3D TRUE -READ_STATUS =3D TRUE -READ_LOCK_CAP =3D TRUE -READ_LOCK_STATUS =3D TRUE -FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A - -FILE FV_IMAGE =3D 35E7406A-5842-4F2B-BC62-19022C12AF74 { - SECTION FV_IMAGE =3D FvAdvancedPreMem - } - -FILE FV_IMAGE =3D F5DCB34F-27EA-48AC-9406-C894F6D587CA { - SECTION FV_IMAGE =3D FvAdvancedPostMem - } - -FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { - SECTION FV_IMAGE =3D FvAdvancedLate - } - } - -##########################################################################= ###### -# -# Rules are use with the [FV] section's module INF type to define -# how an FFS file is created for a given INF file. The following Rule are = the default -# rules for the different module type. User can add the customized rules t= o define the -# content of the FFS file. -# -##########################################################################= ###### - -!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDx= e.inf b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf deleted file mode 100644 index f7f4bd2e3d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf +++ /dev/null @@ -1,69 +0,0 @@ -### @file -# Component information file for board ACPI initialization. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D BoardAcpiDxe - FILE_GUID =3D E269E77D-6163-4F5D-8E59-21EAF114D307 - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - ENTRY_POINT =3D InstallAcpiBoard - -[Sources.common] - BoardAcpiDxe.c - AcpiGnvsInit.c - UpdateDsdt.c - Dsdt/DSDT.ASL - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - UefiCpuPkg/UefiCpuPkg.dec - MinPlatformPkg/MinPlatformPkg.dec - PcAtChipsetPkg/PcAtChipsetPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - BaseLib - DebugLib - IoLib - PcdLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - BaseMemoryLib - HobLib - AslUpdateLib - BoardAcpiTableLib - -[Protocols] - gEfiAcpiTableProtocolGuid ## CONSUMES - gEfiFirmwareVolume2ProtocolGuid ## CONSUMES - gEfiMpServiceProtocolGuid ## CONSUMES - gEfiGlobalNvsAreaProtocolGuid - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress - - gBoardModuleTokenSpaceGuid.PcdAcpiSleepState - gBoardModuleTokenSpaceGuid.PcdAcpiHibernate - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints - gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints - gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints - -[Depex] - gEfiAcpiTableProtocolGuid AND - gEfiFirmwareVolume2ProtocolGuid AND - gEfiPciRootBridgeIoProtocolGuid AND - gEfiVariableArchProtocolGuid AND - gEfiVariableWriteArchProtocolGuid - - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlu= g.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf deleted file mode 100644 index e50763336b..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf +++ /dev/null @@ -1,59 +0,0 @@ -### @file -# Performs specific PCI-EXPRESS device resource configuration. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D PciHotPlug - FILE_GUID =3D 3022E512-B94A-4F12-806D-7EF1177899D8 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D DXE_DRIVER - ENTRY_POINT =3D PciHotPlug -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 EBC -# - -[LibraryClasses] - UefiDriverEntryPoint - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - BaseMemoryLib - MemoryAllocationLib - DevicePathLib - DebugLib - UefiLib - HobLib - PchPcieRpLib - ConfigBlockLib - TbtCommonLib - -[Packages] - MdePkg/MdePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PciHotPlug.c - PciHotPlug.h - -[Protocols] - gEfiPciHotPlugInitProtocolGuid ## PRODUCES - gSaPolicyProtocolGuid ## CONSUMES - -[Guids] - gEfiHobListGuid ## CONSUMES - gPcieRpConfigGuid ## CONSUMES - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe - -[Depex] - gDxeTbtPolicyProtocolGuid diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPo= licyLib/DxeTbtPolicyLib.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt= /Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf deleted file mode 100644 index ceeca81a50..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib= /DxeTbtPolicyLib.inf +++ /dev/null @@ -1,67 +0,0 @@ -## @file -# Component description file for Tbt functionality -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - - -[Defines] -INF_VERSION =3D 0x00010017 -BASE_NAME =3D DxeTbtPolicyLib -FILE_GUID =3D 28ABF346-4E52-4BD3-b1FF-63BA7563C9D4 -VERSION_STRING =3D 1.0 -MODULE_TYPE =3D BASE -LIBRARY_CLASS =3D DxeTbtPolicyLib - - -[LibraryClasses] -BaseMemoryLib -UefiRuntimeServicesTableLib -UefiBootServicesTableLib -DebugLib -PostCodeLib -HobLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber ## CONSUMES - - -[Sources] -DxeTbtPolicyLib.c - - -[Guids] -gEfiEndOfDxeEventGroupGuid -#gSetupVariableGuid -gTbtInfoHobGuid - -[Protocols] -gDxeTbtPolicyProtocolGuid diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSm= mTbtCommonLib/TbtCommonLib.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/= Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf deleted file mode 100644 index b7277c1c57..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCom= monLib/TbtCommonLib.inf +++ /dev/null @@ -1,62 +0,0 @@ -### @file -# Component information file for Thunderbolt common library -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D TbtCommonLib - FILE_GUID =3D 5F03614E-CB56-40B1-9989-A09E25BBA294 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D TbtCommonLib -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 EBC -# - -[LibraryClasses] - DebugLib - PchPcieRpLib - PciSegmentLib - TimerLib - BaseLib - GpioLib - GpioExpanderLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber - -[Sources] - TbtCommonLib.c - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPo= licyLib/PeiTbtPolicyLib.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt= /Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf deleted file mode 100644 index 8f554c8aa7..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib= /PeiTbtPolicyLib.inf +++ /dev/null @@ -1,56 +0,0 @@ -## @file -# Component description file for Tbt policy -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - - -[Defines] -INF_VERSION =3D 0x00010017 -BASE_NAME =3D PeiTbtPolicyLib -FILE_GUID =3D 4A95FDBB-2535-49eb-9A79-D56D24257106 -VERSION_STRING =3D 1.0 -MODULE_TYPE =3D PEIM -LIBRARY_CLASS =3D PeiTbtPolicyLib - - -[LibraryClasses] -BaseMemoryLib -PeiServicesLib -PeiServicesTablePointerLib -MemoryAllocationLib -DebugLib -PostCodeLib -HobLib -GpioLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - IntelSiliconPkg/IntelSiliconPkg.dec - -[Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtControllerType ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtBootOn ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtUsbOn ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwr ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSUMES - -[Sources] -PeiTbtPolicyLib.c - -[Guids] -gTbtInfoHobGuid - -[Ppis] -gEfiPeiReadOnlyVariable2PpiGuid -gPeiTbtPolicyPpiGuid diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/= PeiDTbtInitLib/PeiDTbtInitLib.inf b/Platform/Intel/ClevoOpenBoardPkg/Featur= es/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf deleted file mode 100644 index e33601618a..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbt= InitLib/PeiDTbtInitLib.inf +++ /dev/null @@ -1,41 +0,0 @@ -### @file -# Component description file for PEI DTBT Init library. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D PeiDTbtInitLib - FILE_GUID =3D 06768A8D-8152-403f-83C1-59584FD2B438 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D PEIM - LIBRARY_CLASS =3D PeiDTbtInitLib - -[LibraryClasses] - PeiServicesLib - DebugLib - PcdLib - TbtCommonLib - PciSegmentLib - PeiTbtPolicyLib - PchPmcLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Ppis] - gPeiTbtPolicyPpiGuid ## CONSUMES - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES - -[Sources] - PeiDTbtInitLib.c diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtD= xe.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.i= nf deleted file mode 100644 index 6ec93bf03a..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf +++ /dev/null @@ -1,49 +0,0 @@ -### @file -# Thunderbolt initialization in DXE. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D TbtDxe - FILE_GUID =3D 19C9762C-3A88-41B0-906F-8C4C2895A887 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D DXE_DRIVER - ENTRY_POINT =3D TbtDxeEntryPoint - -[LibraryClasses] - DebugLib - BaseMemoryLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - UefiDriverEntryPoint - HobLib - UefiLib - TbtCommonLib - DxeTbtPolicyLib - AslUpdateLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - TbtDxe.c - -[Protocols] - gTbtNvsAreaProtocolGuid ## CONSUMES - gDxeTbtPolicyProtocolGuid - -[Guids] - gTbtInfoHobGuid ## CONSUMES - -[Depex] - gEfiVariableWriteArchProtocolGuid AND - gEfiVariableArchProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiT= btInit.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiT= btInit.inf deleted file mode 100644 index d15c571784..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.= inf +++ /dev/null @@ -1,44 +0,0 @@ -### @file -# Thunderbolt initialization in PEI. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D PeiTbtInit - FILE_GUID =3D 90BF2BFB-F998-4cbc-AD72-008D4D047A4B - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D PEIM - ENTRY_POINT =3D TbtInitEntryPoint - -[LibraryClasses] - PeimEntryPoint - DebugLib - HobLib - PeiServicesLib - PeiTbtPolicyLib - PeiDTbtInitLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PeiTbtInit.c - -[Guids] - gTbtInfoHobGuid ## CONSUMES - -[Ppis] - gEfiEndOfPeiSignalPpiGuid ## CONSUMES - gPeiTbtPolicyBoardInitDonePpiGuid ## CONSUMES - -[Depex] - gEfiPeiMemoryDiscoveredPpiGuid \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS= mm.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.i= nf deleted file mode 100644 index c08608ae76..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ /dev/null @@ -1,77 +0,0 @@ -### @file -# Thunderbolt SMM initialization module. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D TbtSmm - FILE_GUID =3D 5BDCD685-D80A-42E6-9867-A84CCE7F828E - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D DXE_SMM_DRIVER - PI_SPECIFICATION_VERSION =3D 1.10 - ENTRY_POINT =3D TbtSmmEntryPoint - -[LibraryClasses] - UefiDriverEntryPoint - BaseLib - BaseMemoryLib - DebugLib - UefiRuntimeServicesTableLib - UefiBootServicesTableLib - IoLib - PciExpressLib - HobLib - ReportStatusCodeLib - PciSegmentLib - UefiLib - SmmServicesTableLib - GpioLib - PchInfoLib - TbtCommonLib - PchPmcLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength ## CONSUMES - -[FixedPcd] - gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES - -[Sources] - TbtSmiHandler.h - TbtSmiHandler.c - TbtSmm.c - -[Protocols] - gTbtNvsAreaProtocolGuid ## CONSUMES - gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES - gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES - gEfiSmmVariableProtocolGuid ## CONSUMES - gDxeTbtPolicyProtocolGuid - -[Guids] - gTbtInfoHobGuid ## CONSUMES - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES - -[Depex] - gEfiSmmBase2ProtocolGuid AND - gEfiSmmSxDispatch2ProtocolGuid AND - gEfiSmmSwDispatch2ProtocolGuid AND - gEfiGlobalNvsAreaProtocolGuid AND - gEfiVariableWriteArchProtocolGuid AND - gEfiVariableArchProtocolGuid AND - gEfiSmmVariableProtocolGuid diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/B= aseGpioExpanderLib.inf b/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioE= xpanderLib/BaseGpioExpanderLib.inf deleted file mode 100644 index 4c2478155e..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpio= ExpanderLib.inf +++ /dev/null @@ -1,33 +0,0 @@ -### @file -# Library producing Gpio Expander functionality. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D BaseGpioExpanderLib - FILE_GUID =3D D10AE2A4-782E-427E-92FB-BB74505ED329 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D GpioExpanderLib - -[LibraryClasses] - BaseLib - IoLib - DebugLib - TimerLib - PchSerialIoLib - I2cAccessLib - -[Packages] - MdePkg/MdePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - BaseGpioExpanderLib.c diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2= cAccessLib.inf b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/P= eiI2cAccessLib.inf deleted file mode 100644 index bbbc74cf90..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccess= Lib.inf +++ /dev/null @@ -1,36 +0,0 @@ -### @file -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D PeiI2cAccessLib - FILE_GUID =3D 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D PeiI2cAccessLib -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# - -[LibraryClasses] - BaseLib - BaseMemoryLib - DebugLib - TimerLib - -[Packages] - MdePkg/MdePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - SecurityPkg/SecurityPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PeiI2cAccessLib.c diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFl= ash/PeiSerialPortLibSpiFlash.inf b/Platform/Intel/ClevoOpenBoardPkg/Library= /PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf deleted file mode 100644 index b81ce9dd7a..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/Pei= SerialPortLibSpiFlash.inf +++ /dev/null @@ -1,50 +0,0 @@ -### @file -# Component description file for Serial I/O Port library to write to SPI f= lash. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PeiSerialPortLibFlash - FILE_GUID =3D 35A3BA89-04BE-409C-A3CA-DEF6B510F80F - VERSION_STRING =3D 1.1 - MODULE_TYPE =3D PEIM - LIBRARY_CLASS =3D SerialPortLib|PEIM PEI_CORE -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF -# - -[LibraryClasses] - BaseLib - BaseMemoryLib - HobLib - PcdLib - PeiServicesLib - SpiLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - KabylakeSiliconPkg/SiPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - -[Sources] - PeiSerialPortLibSpiFlash.c - -[Ppis] - gPchSpiPpiGuid - -[Guids] - gSpiFlashDebugHobGuid - -[Pcd] - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize ## CONSU= MES diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf b/Platform/Intel= /ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiP= reMemSiliconPolicyNotifyLib.inf deleted file mode 100644 index 13c12655f6..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf +++ /dev/null @@ -1,43 +0,0 @@ -## @file -# Component information file for Silicon Policy Notify Library. -# This library implements constructor function to register notify call bac= k -# when policy PPI installed. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PeiPreMemSiliconPolicyNotifyLib - FILE_GUID =3D 6D231E12-C088-47C8-8B16-61F07293EEF8 - MODULE_TYPE =3D PEIM - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D NULL - CONSTRUCTOR =3D PeiPreMemSiliconPolicyNotifyLibConstr= uctor - -[LibraryClasses] - BaseLib - -[Packages] - MdePkg/MdePkg.dec - KabylakeOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PeiPreMemSiliconPolicyNotifyLib.c - -[Guids] - gSaMiscPeiPreMemConfigGuid - -[Ppis] - gSiPreMemPolicyPpiGuid - -[Pcd] - # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel= /ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/P= eiSiliconPolicyUpdateLibFsp.inf deleted file mode 100644 index b9b9232692..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +++ /dev/null @@ -1,146 +0,0 @@ -## @file -# FSP wrapper silicon policy update library. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -##########################################################################= ###### -# -# Defines Section - statements that will be processed to create a Makefile= . -# -##########################################################################= ###### -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D SiliconPolicyUpdateLibFsp - FILE_GUID =3D 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2 - MODULE_TYPE =3D PEIM - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D SiliconPolicyUpdateLib - - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 -# - -##########################################################################= ###### -# -# Sources Section - list of files that are required for the build to succe= ed. -# -##########################################################################= ###### - -[Sources] - PeiFspPolicyUpdateLib.c - PeiPchPolicyUpdatePreMem.c - PeiPchPolicyUpdate.c - PeiSaPolicyUpdatePreMem.c - PeiSaPolicyUpdate.c - PeiFspMiscUpdUpdateLib.c - PcieDeviceTable.c - -##########################################################################= ###### -# -# Package Dependency Section - list of Package files that are required for -# this module. -# -##########################################################################= ###### - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - IntelFsp2Pkg/IntelFsp2Pkg.dec - IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec - IntelSiliconPkg/IntelSiliconPkg.dec - KabylakeSiliconPkg/SiPkg.dec - KabylakeFspBinPkg/KabylakeFspBinPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - MinPlatformPkg/MinPlatformPkg.dec - -[LibraryClasses.IA32] - FspWrapperApiLib - OcWdtLib - PchResetLib - FspWrapperPlatformLib - BaseMemoryLib - CpuPlatformLib - DebugLib - HobLib - IoLib - PcdLib - PostCodeLib - SmbusLib - MmPciLib - ConfigBlockLib - PeiSaPolicyLib - PchGbeLib - PchInfoLib - PchHsioLib - PchPcieRpLib - MemoryAllocationLib - CpuMailboxLib - DebugPrintErrorLevelLib - SiPolicyLib - PchGbeLib - TimerLib - GpioLib - PeiLib - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES - - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size - - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size - - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 - gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable - - gBoardModuleTokenSpaceGuid.PcdAudioConnector - - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid - -[Guids] - gFspNonVolatileStorageHobGuid ## CONSUMES - gTianoLogoGuid ## CONSUMES - gEfiMemoryOverwriteControlDataGuid - -[Depex] - gEdkiiVTdInfoPpiGuid - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHo= okLib/BasePlatformHookLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Lib= rary/BasePlatformHookLib/BasePlatformHookLib.inf deleted file mode 100644 index c4ea31bff2..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/B= asePlatformHookLib.inf +++ /dev/null @@ -1,51 +0,0 @@ -### @file -# Platform Hook Library instance for Clevo N1xxWU board. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D BasePlatformHookLib - FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D PlatformHookLib -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# - -[LibraryClasses] - BaseLib - IoLib - MmPciLib - PciLib - PchCycleDecodingLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] - gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES - -[FixedPcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES - gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES - -[Sources] - BasePlatformHookLib.c diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/D= xeBoardAcpiTableLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/B= oardAcpiLib/DxeBoardAcpiTableLib.inf deleted file mode 100644 index 06e703e12d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoard= AcpiTableLib.inf +++ /dev/null @@ -1,47 +0,0 @@ -### @file -# Clevo N1xxWU board DXE ACPI table functionality. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D DxeBoardAcpiTableLib - FILE_GUID =3D 6562E0AE-90D8-4D41-8C97-81286B4BE7D2 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D BoardAcpiTableLib - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# - -[LibraryClasses] - BaseLib - IoLib - PciLib - AslUpdateLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable - gMinPlatformPkgTokenSpaceGuid.PcdPciExpNative - gMinPlatformPkgTokenSpaceGuid.PcdNativeAspmEnable - gMinPlatformPkgTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress - -[Sources] - DxeN1xxWUAcpiTableLib.c - DxeBoardAcpiTableLib.c - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/D= xeMultiBoardAcpiSupportLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Li= brary/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf deleted file mode 100644 index c505909ad3..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMulti= BoardAcpiSupportLib.inf +++ /dev/null @@ -1,48 +0,0 @@ -### @file -# Clevo N1xxWU multi-board DXE ACPI table support functionality. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D DxeN1xxWUMultiBoardAcpiTableLib - FILE_GUID =3D 8E6A3B38-53E0-48C0-970F-058F380FCB80 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D NULL - CONSTRUCTOR =3D DxeN1xxWUMultiBoardAcpiSupportLibCons= tructor - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# - -[LibraryClasses] - BaseLib - IoLib - PciLib - AslUpdateLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable - gBoardModuleTokenSpaceGuid.PcdPciExpNative - gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress - -[Sources] - DxeN1xxWUAcpiTableLib.c - DxeMultiBoardAcpiSupportLib.c - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/S= mmBoardAcpiEnableLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/= BoardAcpiLib/SmmBoardAcpiEnableLib.inf deleted file mode 100644 index 8752fbb43f..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoard= AcpiEnableLib.inf +++ /dev/null @@ -1,47 +0,0 @@ -### @file -# Clevo N1xxWU board SMM ACPI table enable/disable functionality. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D SmmBoardAcpiEnableLib - FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D BoardAcpiEnableLib - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# - -[LibraryClasses] - BaseLib - IoLib - PciLib - MmPciLib - PchCycleDecodingLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES - -[Protocols] - -[Sources] - SmmN1xxWUAcpiEnableLib.c - SmmSiliconAcpiEnableLib.c - SmmBoardAcpiEnableLib.c - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/S= mmMultiBoardAcpiSupportLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Li= brary/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf deleted file mode 100644 index 3c4cfaccd3..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMulti= BoardAcpiSupportLib.inf +++ /dev/null @@ -1,48 +0,0 @@ -### @file -# SMM multi-board ACPI support functionality. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D SmmN1xxWUMultiBoardAcpiSupportLib - FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D BASE - LIBRARY_CLASS =3D NULL - CONSTRUCTOR =3D SmmN1xxWUMultiBoardAcpiSupportLibCons= tructor - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# - -[LibraryClasses] - BaseLib - IoLib - PciLib - MmPciLib - PchCycleDecodingLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES - -[Protocols] - -[Sources] - SmmN1xxWUAcpiEnableLib.c - SmmSiliconAcpiEnableLib.c - SmmMultiBoardAcpiSupportLib.c - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiBoardInitPostMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library= /BoardInitLib/PeiBoardInitPostMemLib.inf deleted file mode 100644 index 01225c9114..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoard= InitPostMemLib.inf +++ /dev/null @@ -1,53 +0,0 @@ -## @file -# Component information file for N1xxWUInitLib in PEI post memory phase. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PeiBoardPostMemInitLib - FILE_GUID =3D 7fcc3900-d38d-419f-826b-72481e8b5509 - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D BoardInitLib - -[LibraryClasses] - BaseLib - DebugLib - BaseMemoryLib - MemoryAllocationLib - GpioExpanderLib - PcdLib - SiliconInitLib - -[Packages] - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PeiN1xxWUInitPostMemLib.c - N1xxWUGpioTable.c - N1xxWUHdaVerbTables.c - PeiBoardInitPostMemLib.c - -[FixedPcd] - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel - - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize - - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable - - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/= BoardInitLib/PeiBoardInitPreMemLib.inf deleted file mode 100644 index 22797cd80f..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoard= InitPreMemLib.inf +++ /dev/null @@ -1,132 +0,0 @@ -## @file -# Component information file for PEI N1xxWU Board Init Pre-Mem Library -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PeiBoardInitPreMemLib - FILE_GUID =3D ec3675bc-1470-417d-826e-37378140213d - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D BoardInitLib - -[LibraryClasses] - BaseLib - DebugLib - BaseMemoryLib - MemoryAllocationLib - PcdLib - SiliconInitLib - -[Packages] - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PeiN1xxWUDetect.c - PeiN1xxWUInitPreMemLib.c - N1xxWUHsioPtssTables.c - N1xxWUSpdTable.c - PeiBoardInitPreMemLib.c - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort - - # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size - - # PCH-H HSIO PTSS Table - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - - # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize - - # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive - - - # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 - - # CA Vref Configuration - - # Root Port Clock Info - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo - - # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe - - # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 - - # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 - - # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent - - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiMultiBoardInitPostMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Li= brary/BoardInitLib/PeiMultiBoardInitPostMemLib.inf deleted file mode 100644 index 47efb21a79..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMulti= BoardInitPostMemLib.inf +++ /dev/null @@ -1,55 +0,0 @@ -## @file -# Component information file for N1xxWUInitLib in PEI post memory phase. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PeiN1xxWUMultiBoardInitLib - FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280 - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D NULL - CONSTRUCTOR =3D PeiN1xxWUMultiBoardInitLibConstructor - -[LibraryClasses] - BaseLib - DebugLib - BaseMemoryLib - MemoryAllocationLib - GpioExpanderLib - PcdLib - SiliconInitLib - MultiBoardInitSupportLib - -[Packages] - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PeiN1xxWUInitPostMemLib.c - N1xxWUGpioTable.c - N1xxWUHdaVerbTables.c - PeiMultiBoardInitPostMemLib.c - -[FixedPcd] - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel - - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize - - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable - - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Lib= rary/BoardInitLib/PeiMultiBoardInitPreMemLib.inf deleted file mode 100644 index 0f6be110c0..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMulti= BoardInitPreMemLib.inf +++ /dev/null @@ -1,137 +0,0 @@ -## @file -# Component information file for PEI N1xxWU Board Init Pre-Mem Library -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PeiN1xxWUMultiBoardInitPreMemLib - FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D NULL - CONSTRUCTOR =3D PeiN1xxWUMultiBoardInitPreMemLibConst= ructor - -[LibraryClasses] - BaseLib - DebugLib - BaseMemoryLib - MemoryAllocationLib - PcdLib - SiliconInitLib - MultiBoardInitSupportLib - -[Packages] - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - KabylakeSiliconPkg/SiPkg.dec - -[Sources] - PeiN1xxWUInitPreMemLib.c - N1xxWUHsioPtssTables.c - N1xxWUSpdTable.c - PeiMultiBoardInitPreMemLib.c - PeiN1xxWUDetect.c - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort - - # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size - - # PCH-H HSIO PTSS Table - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - - # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved - - # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive - - - # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 - - # CA Vref Configuration - - # Root Port Clock Info - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo - - # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe - - # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 - - # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 - - # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent - - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Inte= l/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Plat= form/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/= PlatformInit/PlatformInitPei/PlatformInitPreMem.inf deleted file mode 100644 index 76dd67d1a8..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPl= atformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +++ /dev/null @@ -1,67 +0,0 @@ -### @file -# Component information file for the Platform Init Pre-Memory PEI module. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D PlatformInitPreMem - FILE_GUID =3D EEEE611D-F78F-4FB9-B868-55907F169280 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D PEIM - ENTRY_POINT =3D PlatformInitPreMemEntryPoint - -[LibraryClasses] - BaseMemoryLib - BoardInitLib - DebugLib - HobLib - IoLib - MemoryAllocationLib - MtrrLib - PeimEntryPoint - PeiServicesLib - ReportFvLib - TestPointCheckLib - TimerLib - -[Packages] - MinPlatformPkg/MinPlatformPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec - -[Pcd] - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES - -[FixedPcd] - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CO= NSUMES - -[Sources] - PlatformInitPreMem.c - -[Ppis] - gEfiPeiMemoryDiscoveredPpiGuid - gEfiPeiMasterBootModePpiGuid ## PRODUCES - gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES - gEfiPeiReadOnlyVariable2PpiGuid - gPeiBaseMemoryTestPpiGuid - gPeiPlatformMemorySizePpiGuid - -[Guids] - gEfiMemoryTypeInformationGuid - -[Depex] - gEfiPeiReadOnlyVariable2PpiGuid diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSili= conPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/ClevoOpen= BoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUp= dateLib.inf deleted file mode 100644 index dd7047b9cf..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli= cyUpdateLib/DxeSiliconPolicyUpdateLib.inf +++ /dev/null @@ -1,49 +0,0 @@ -## @file -# Component information file for DXE silicon policy update library -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D DxeSiliconUpdateLib - FILE_GUID =3D C523609D-E354-416B-B24F-33468D4BD21D - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D SiliconUpdateLib - -[LibraryClasses] - BaseLib - PcdLib - DebugLib - -[Packages] - MdePkg/MdePkg.dec - KabylakeSiliconPkg/SiPkg.dec - MinPlatformPkg/MinPlatformPkg.dec - ClevoOpenBoardPkg/OpenBoardPkg.dec - -[Sources] - DxeSiliconPolicyUpdateLib.c - DxeGopPolicyInit.c - DxeSaPolicyUpdate.c - -[Pcd] - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid - -[Protocols] - gEfiFirmwareVolume2ProtocolGuid ## CONSUMES - gSaPolicyProtocolGuid ## CONSUMES - gDxeSiPolicyProtocolGuid ## PRODUCES - gGopPolicyProtocolGuid ## PRODUCES - -[Guids] - gMiscDxeConfigGuid - -[Depex] - gEfiVariableArchProtocolGuid - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlu= g.h b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h deleted file mode 100644 index 53274c17c5..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h +++ /dev/null @@ -1,130 +0,0 @@ -/**@file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _PCI_HOT_PLUG_H_ -#define _PCI_HOT_PLUG_H_ - -// -// External include files do NOT need to be explicitly specified in real E= DKII -// environment -// -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('G', 'U', 'L',= 'P') - -#define ACPI \ - { \ - { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH))= , (UINT8) \ - ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (0x0A03), 0 = \ - } - -#define PCI(device, function) \ - { \ - { HARDWARE_DEVICE_PATH, HW_PCI_DP, { (UINT8) (sizeof (PCI_DEVICE_PATH)= ), (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) } }, \ - (UINTN) function, (UINTN) device \ - } - -#define END \ - { \ - END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PAT= H_LENGTH, 0 } \ - } - -#define LPC(eisaid, function) \ - { \ - { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH))= , (UINT8) \ - ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (eisaid), fu= nction \ - } - -typedef struct PCIE_HOT_PLUG_DEVICE_PATH { - ACPI_HID_DEVICE_PATH PciRootBridgeNode; - PCI_DEVICE_PATH PciRootPortNode; - EFI_DEVICE_PATH_PROTOCOL EndDeviceNode; -} PCIE_HOT_PLUG_DEVICE_PATH; - -typedef struct { - UINTN Signature; - EFI_HANDLE Handle; // Handle for protocol this driv= er installs on - EFI_PCI_HOT_PLUG_INIT_PROTOCOL HotPlugInitProtocol; -} PCI_HOT_PLUG_INSTANCE; - -/** - This procedure returns a list of Root Hot Plug controllers that require - initialization during boot process - - @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLU= G_INIT protocol. - @param[out] HpcCount The number of Root HPCs returned. - @param[out] HpcList The list of Root HPCs. HpcCount defines the number= of elements in this list. - - @retval EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -GetRootHpcList ( - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, - OUT UINTN *PhpcCount, - OUT EFI_HPC_LOCATION **PhpcList - ); - -/** - This procedure Initializes one Root Hot Plug Controller - This process may casue initialization of its subordinate buses - - @param[in] This The pointer to the instance of the EFI_PCI_H= OT_PLUG_INIT protocol. - @param[in] HpcDevicePath The Device Path to the HPC that is being ini= tialized. - @param[in] HpcPciAddress The address of the Hot Plug Controller funct= ion on the PCI bus. - @param[in] Event The event that should be signaled when the H= ot Plug Controller initialization is complete. Set to NULL if the caller wa= nts to wait until the entire initialization process is complete. The event = must be of the type EFI_EVT_SIGNAL. - @param[out] HpcState The state of the Hot Plug Controller hardwar= e. The type EFI_Hpc_STATE is defined in section 3.1. - - @retval EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -InitializeRootHpc ( - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, - IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath, - IN UINT64 PhpcPciAddress, - IN EFI_EVENT Event, OPTIONAL - OUT EFI_HPC_STATE *PhpcState - ); - -/** - Returns the resource padding required by the PCI bus that is controlled = by the specified Hot Plug Controller. - - @param[in] This The pointer to the instance of the EFI_PCI_HO= T_PLUG_INIT protocol. initialized. - @param[in] HpcDevicePath The Device Path to the Hot Plug Controller. - @param[in] HpcPciAddress The address of the Hot Plug Controller functi= on on the PCI bus. - @param[out] HpcState The state of the Hot Plug Controller hardware= . The type EFI_HPC_STATE is defined in section 3.1. - @param[out] Padding This is the amount of resource padding requir= ed by the PCI bus under the control of the specified Hpc. Since the caller = does not know the size of this buffer, this buffer is allocated by the call= ee and freed by the caller. - @param[out] Attribute Describes how padding is accounted for. - - @retval EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -GetResourcePadding ( - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, - IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath, - IN UINT64 PhpcPciAddress, - OUT EFI_HPC_STATE *PhpcState, - OUT VOID **Padding, - OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes - ); - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/Tbt= NvsAreaDef.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/T= btNvsAreaDef.h deleted file mode 100644 index e988bdd712..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvsArea= Def.h +++ /dev/null @@ -1,62 +0,0 @@ -/**@file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - // - // Define TBT NVS Area operation region. - // -#ifndef _TBT_NVS_AREA_DEF_H_ -#define _TBT_NVS_AREA_DEF_H_ - -#pragma pack (push,1) -typedef struct { - UINT8 ThunderboltSmiFunction; ///< Offset 0 Th= underbolt(TM) SMI Function Number - UINT8 ThunderboltHotSmi; ///< Offset 1 SM= I on Hot Plug for TBT devices - UINT8 TbtWin10Support; ///< Offset 2 Tb= tWin10Support - UINT8 TbtGpioFilter; ///< Offset 3 Gp= io filter to detect USB Hotplug event - UINT8 ThunderboltHotNotify; ///< Offset 4 No= tify on Hot Plug for TBT devices - UINT8 TbtSelector; ///< Offset 5 Th= underbolt(TM) Root port selector - UINT8 WAKFinished; ///< Offset 6 WA= K Finished - UINT8 DiscreteTbtSupport; ///< Offset 7 Th= underbolt(TM) support - UINT8 TbtAcpiRemovalSupport; ///< Offset 8 Tb= tAcpiRemovalSupport - UINT32 TbtFrcPwrEn; ///< Offset 9 Tb= tFrcPwrEn - UINT32 TbtFrcPwrGpioNo0; ///< Offset 13 Tb= tFrcPwrGpioNo - UINT8 TbtFrcPwrGpioLevel0; ///< Offset 17 Tb= tFrcPwrGpioLevel - UINT32 TbtCioPlugEventGpioNo0; ///< Offset 18 Tb= tCioPlugEventGpioNo - UINT32 TbtPcieRstGpioNo0; ///< Offset 22 Tb= tPcieRstGpioNo - UINT8 TbtPcieRstGpioLevel0; ///< Offset 26 Tb= tPcieRstGpioLevel - UINT8 CurrentDiscreteTbtRootPort; ///< Offset 27 Cu= rrent Port that has plug event - UINT8 RootportSelected0; ///< Offset 28 Ro= ot port Selected by the User - UINT8 RootportSelected0Type; ///< Offset 29 Ro= ot port Type - UINT8 RootportSelected1; ///< Offset 30 Ro= ot port Selected by the User - UINT8 RootportSelected1Type; ///< Offset 31 Ro= ot port Type - UINT8 RootportEnabled0; ///< Offset 32 Ro= ot port Enabled by the User - UINT8 RootportEnabled1; ///< Offset 33 Ro= ot port Enabled by the User - UINT32 TbtFrcPwrGpioNo1; ///< Offset 34 Tb= tFrcPwrGpioNo - UINT8 TbtFrcPwrGpioLevel1; ///< Offset 38 Tb= tFrcPwrGpioLevel - UINT32 TbtCioPlugEventGpioNo1; ///< Offset 39 Tb= tCioPlugEventGpioNo - UINT32 TbtPcieRstGpioNo1; ///< Offset 43 Tb= tPcieRstGpioNo - UINT8 TbtPcieRstGpioLevel1; ///< Offset 47 Tb= tPcieRstGpioLevel - UINT8 TBtCommonGpioSupport; ///< Offset 48 Se= t if Single GPIO is used for Multi/Different Controller Hot plug support - UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 49 Ro= ot Port type for which SCI Triggered - UINT8 TrOsup; ///< Offset 50 Ti= tan Ridge Osup command - UINT8 TbtAcDcSwitch; ///< Offset 51 TB= T Dynamic AcDc L1 - UINT8 DTbtControllerEn0; ///< Offset 52 DT= btController0 is enabled or not. - UINT8 DTbtControllerEn1; ///< Offset 53 DT= btController1 is enabled or not. - UINT8 TbtAspm; ///< Offset 54 AS= PM setting for all the PCIe device in TBT daisy chain. - UINT8 TbtL1SubStates; ///< Offset 55 L1= SubState for for all the PCIe device in TBT daisy chain. - UINT8 TbtSetClkReq; ///< Offset 56 CL= K REQ for all the PCIe device in TBT daisy chain. - UINT8 TbtLtr; ///< Offset 57 LT= R for for all the PCIe device in TBT daisy chain. - UINT8 TbtPtm; ///< Offset 58 PT= M for for all the PCIe device in TBT daisy chain. - UINT8 TbtWakeupSupport; ///< Offset 59 Se= nd Go2SxNoWake or GoSxWake according to TbtWakeupSupport - UINT16 Rtd3TbtOffDelay; ///< Offset 60 Rt= d3TbtOffDelay TBT RTD3 Off Delay - UINT8 TbtSxWakeSwitchLogicEnable; ///< Offset 62 Tb= tSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB= at Sx entry point. HW logic is required. - UINT8 Rtd3TbtSupport; ///< Offset 63 En= able Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup. - UINT8 Rtd3TbtClkReq; ///< Offset 64 En= able TBT RTD3 CLKREQ mask. - UINT16 Rtd3TbtClkReqDelay; ///< Offset 65 TB= T RTD3 CLKREQ mask delay. -} TBT_NVS_AREA; - -#pragma pack(pop) -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/= DxeTbtPolicyLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/L= ibrary/DxeTbtPolicyLib.h deleted file mode 100644 index 3ac3d88a33..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/DxeTbtP= olicyLib.h +++ /dev/null @@ -1,46 +0,0 @@ -/** @file - Prototype of the DxeTbtPolicyLib library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _DXE_TBT_POLICY_LIB_H_ -#define _DXE_TBT_POLICY_LIB_H_ - -/** - Install TBT Policy. - - @param[in] ImageHandle Image handle of this driver. - - @retval EFI_SUCCESS The policy is installed. - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer - -**/ -EFI_STATUS -EFIAPI -InstallTbtPolicy ( - IN EFI_HANDLE ImageHandle - ); - -/** - Update Tbt Policy Callback. - - @param[in] Event A pointer to the Event that triggered the callb= ack. - @param[in] Context A pointer to private data registered with the c= allback function. - -**/ -VOID -EFIAPI -UpdateTbtPolicyCallback ( - VOID - ); - -/** - Print DXE TBT Policy -**/ -VOID -TbtPrintDxePolicyConfig ( - VOID - ); -#endif // _DXE_TBT_POLICY_LIB_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/= PeiTbtPolicyLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/L= ibrary/PeiTbtPolicyLib.h deleted file mode 100644 index cf9ca8f0c8..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/PeiTbtP= olicyLib.h +++ /dev/null @@ -1,41 +0,0 @@ -/** @file - Prototype of the PeiTbtPolicyLib library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _PEI_TBT_POLICY_LIB_H_ -#define _PEI_TBT_POLICY_LIB_H_ - -/** - Install Tbt Policy - - @retval EFI_SUCCESS The policy is installed. - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer - -**/ -EFI_STATUS -EFIAPI -InstallPeiTbtPolicy ( - VOID - ); - -/** - Update PEI TBT Policy -**/ -VOID -EFIAPI -UpdatePeiTbtPolicy ( - VOID - ); - -/** - Print PEI TBT Policy -**/ -VOID -EFIAPI -TbtPrintPeiPolicyConfig ( - VOID - ); -#endif // _DXE_TBT_POLICY_LIB_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/= TbtCommonLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Libr= ary/TbtCommonLib.h deleted file mode 100644 index 90966fa4cc..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Library/TbtComm= onLib.h +++ /dev/null @@ -1,241 +0,0 @@ -/**@file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _TBT_COMMON_LIB_H_ -#define _TBT_COMMON_LIB_H_ - -#include -#include -#include - -#define DTBT_CONTROLLER 0x00 -#define DTBT_TYPE_PCH 0x01 -#define DTBT_TYPE_PEG 0x02 -#define TBT2PCIE_DTBT_R 0x548 -#define PCIE2TBT_DTBT_R 0x54C - -// -// Thunderbolt FW OS capability -// -#define NO_OS_NATIVE_SUPPORT 0 -#define OS_NATIVE_SUPPORT_ONLY 1 -#define OS_NATIVE_SUPPORT_RTD3 2 - -#define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 i= s in use) -/** -Get Tbt2Pcie Register Offset - -@retval Register Register Variable -**/ - -#define GET_TBT2PCIE_REGISTER_ADDRESS(Segment, Bus, Device, Function, Regi= sterAddress) \ -RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function= , TBT2PCIE_DTBT_R); \ - -/** -Get Pcie2Tbt Register Offset - -@retval Register Register Variable -**/ - -#define GET_PCIE2TBT_REGISTER_ADDRESS(Segment, Bus, Device, Function, Regi= sterAddress) \ -RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function= , PCIE2TBT_DTBT_R); \ - -#define PCIE2TBT_VLD_B BIT0 -#define TBT2PCIE_DON_R BIT0 -#define TBT_MAIL_BOX_DELAY (100*1000) -#define TBT_5S_TIMEOUT 50 -#define TBT_1S_TIMEOUT 10 -#define TBT_3S_TIMEOUT 30 - -#define PCIE2TBT_GO2SX (0x02 << 1) -#define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1) -#define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1) -#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1) -#define PCIE2TBT_OS_UP (0x06 << 1) -#define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1) -#define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1) -#define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1) -#define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1) -#define PCIE2TBT_BOOT_ON (0x18 << 1) -#define PCIE2TBT_BOOT_OFF (0x19 << 1) -#define PCIE2TBT_USB_ON (0x19 << 1) -#define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1) -#define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1) -#define PCIE2TBT_POWER_CYCLE (0x1C << 1) -#define PCIE2TBT_PREBOOTACL (0x1E << 1) -#define CONNECT_TOPOLOGY_COMMAND (0x1F << 1) - -#define RESET_HR_BIT BIT0 -#define ENUMERATE_HR_BIT BIT1 -#define AUTO 0x0 - -// -//Thunder Bolt Device IDs -// - -// -// Alpine Ridge HR device IDs -// -#define AR_HR_2C 0x1576 -#define AR_HR_4C 0x1578 -#define AR_XHC 0x15B5 -#define AR_XHC_4C 0x15B6 -#define AR_HR_LP 0x15C0 -// -// Alpine Ridge C0 HR device IDs -// -#define AR_HR_C0_2C 0x15DA -#define AR_HR_C0_4C 0x15D3 -// -// Titan Ridge HR device IDs -// -#define TR_HR_2C 0x15E7 -#define TR_HR_4C 0x15EA -// -//End of Thunderbolt(TM) Device IDs -// - -typedef struct _DEV_ID { - UINT8 Segment; - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; -} DEV_ID; - -//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf -//@todo should refactor this to only be present in that driver -//@todo also definitions like this should never be in a .h file anyway -//@todo this is a quick hack to get things compiling for now -#ifdef __GNUC__ -#pragma GCC diagnostic warning "-Wunused-variable" -#endif - -/** -Based on the Security Mode Selection, BIOS drives FORCE_PWR. - -@param[in] GpioNumber -@param[in] Value -**/ -VOID -ForceDtbtPower( - IN UINT8 GpioAccessType, - IN UINT8 Expander, - IN UINT32 GpioNumber, - IN BOOLEAN Value -); - -/** - Get Security Level. - @param[in] Bus Bus number for Host Router (DTBT) - @param[in] Device Device number for Host Router (DTBT) - @param[in] Function Function number for Host Router (DTBT) - @param[in] Timeout Time out with 100 ms garnularity -**/ -UINT8 -GetSecLevel ( - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 Command, - IN UINT32 Timeout - ); - -/** - Set Security Level. - @param[in] Data Security State - @param[in] Bus Bus number for Host Router (DTBT) - @param[in] Device Device number for Host Router (DTBT) - @param[in] Function Function number for Host Router (DTBT) - @param[in] Timeout Time out with 100 ms garnularity -**/ -BOOLEAN -SetSecLevel ( - IN UINT8 Data, - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 Command, - IN UINT32 Timeout - ); - -/** -Execute TBT Mail Box Command - -@param[in] Command TBT Command -@param[in] Bus Bus number for Host Router (DTBT) -@param[in] Device Device number for Host Router (DTBT) -@param[in] Function Function number for Host Router (DTBT) -@param[in] Timeout Time out with 100 ms garnularity -@Retval true if command executes succesfully -**/ -BOOLEAN -TbtSetPcie2TbtCommand( - IN UINT8 Command, - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT32 Timeout -); -/** - Check connected TBT controller is supported or not by DeviceID - - @param[in] DeviceID DeviceID of of TBT controller - - - @retval TRUE Valid DeviceID - @retval FALSE Invalid DeviceID -**/ - -BOOLEAN -IsTbtHostRouter ( - IN UINT16 DeviceID - ); - -/** - Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po= rt physical Number - - @param[in] RpNumber Root port physical number. (0-based) - @param[out] RpDev Return corresponding root port device = number. - @param[out] RpFun Return corresponding root port functio= n number. - - @retval EFI_SUCCESS Root port device and function is retri= eved -**/ -EFI_STATUS -EFIAPI -GetDTbtRpDevFun( - IN BOOLEAN Type, - IN UINTN RpNumber, - OUT UINTN *RpDev, - OUT UINTN *RpFunc - ); - -/** - Internal function to Wait for Tbt2PcieDone Bit.to Set or clear - @param[in] CommandOffsetAddress Tbt2Pcie Register Address - @param[in] TimeOut Time out with 100 ms garnularity - @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl= ear/Set) - @param[out] *Tbt2PcieValue Function Register value -**/ -BOOLEAN -InternalWaitforCommandCompletion ( - IN UINT64 CommandOffsetAddress, - IN UINT32 TimeOut, - IN BOOLEAN Tbt2PcieDone, - OUT UINT32 *Tbt2PcieValue - ); - -VOID -GetRootporttoSetResourcesforTbt ( - IN UINTN RpIndex, - OUT UINT8 *RsvdExtraBusNum, - OUT UINT16 *RsvdPcieMegaMem, - OUT UINT8 *PcieMemAddrRngMax, - OUT UINT16 *RsvdPciePMegaMem, - OUT UINT8 *PciePMemAddrRngMax, - OUT BOOLEAN *SetResourceforTbt - ); - -#endif \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiT= btPolicy.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiT= btPolicy.h deleted file mode 100644 index 09b74df889..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPolic= y.h +++ /dev/null @@ -1,29 +0,0 @@ -/** @file -TBT PEI Policy - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _PEI_TBT_POLICY_H_ -#define _PEI_TBT_POLICY_H_ - -#include - -#pragma pack(push, 1) - -#define PEI_TBT_POLICY_REVISION 1 - -/** - TBT PEI configuration\n - Revision 1: - - Initial version. -**/ -typedef struct _PEI_TBT_POLICY { - DTBT_COMMON_CONFIG DTbtCommonConfig; ///< dTbt Comm= on Configuration - DTBT_CONTROLLER_CONFIG DTbtControllerConfig; ///< dTbt Cont= roller Configuration -} PEI_TBT_POLICY; - -#pragma pack(pop) - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/= Library/PeiDTbtInitLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/In= clude/Private/Library/PeiDTbtInitLib.h deleted file mode 100644 index dd31099a7d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library= /PeiDTbtInitLib.h +++ /dev/null @@ -1,108 +0,0 @@ -/**@file - PEI DTBT Init Dispatch library Header file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef __PEI_DTBT_INIT_LIB_H__ -#define __PEI_DTBT_INIT_LIB_H__ - -#include - -/** - set tPCH25 Timing to 10 ms for DTBT. - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtSetTPch25Timing ( - IN PEI_TBT_POLICY *PeiTbtConfig -); - -/** - Do ForcePower for DTBT Controller - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtForcePower ( - IN PEI_TBT_POLICY *PeiTbtConfig -); - -/** - Clear VGA Registers for DTBT. - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtClearVgaRegisters ( - IN PEI_TBT_POLICY *PeiTbtConfig -); - -/** - Exectue Mail box command "Boot On". - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtBootOn ( - IN PEI_TBT_POLICY *PeiTbtConfig -); - -/** - Exectue Mail box command "USB On". - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtUsbOn ( - IN PEI_TBT_POLICY *PeiTbtConfig -); - -/** - Exectue Mail box command "Sx Exit". - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtSxExitFlow ( - IN PEI_TBT_POLICY *PeiTbtConfig -); -/** - Initialize Thunderbolt(TM) - - @retval EFI_SUCCESS The function completes successfully - @retval others -**/ -EFI_STATUS -EFIAPI -TbtInit ( - VOID -); - -#endif \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/= Library/PeiTbtCommonInitLib.h b/Platform/Intel/ClevoOpenBoardPkg/Features/T= bt/Include/Private/Library/PeiTbtCommonInitLib.h deleted file mode 100644 index 718e858b70..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Private/Library= /PeiTbtCommonInitLib.h +++ /dev/null @@ -1,41 +0,0 @@ -/**@file - PEI TBT Common Init Dispatch library Header file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef __PEI_TBT_COMMON_INIT_LIB_H__ -#define __PEI_TBT_COMMON_INIT_LIB_H__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -VOID -TbtSetSxMode( -IN BOOLEAN Type, -IN UINT8 Bus, -IN UINT8 Device, -IN UINT8 Function, -IN UINT8 TbtBootOn -); - -VOID -TbtClearVgaRegisters( -IN UINTN Segment, -IN UINTN Bus, -IN UINTN Device, -IN UINTN Function -); - -#endif \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol= /DxeTbtPolicy.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Pro= tocol/DxeTbtPolicy.h deleted file mode 100644 index 5167661c02..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTbt= Policy.h +++ /dev/null @@ -1,110 +0,0 @@ -/** @file -TBT DXE Policy - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _DXE_TBT_POLICY_H_ -#define _DXE_TBT_POLICY_H_ - -#include - -#pragma pack(push, 1) - -#define DXE_TBT_POLICY_REVISION 1 - -// -// TBT Common Data Structure -// -typedef struct _TBT_COMMON_CONFIG{ - /** - TBT Security Level - 0: SL0 No Security, 1: SL1 User Authorization, 2: SL2 Secure Co= nnect, 3: SL3 Display Port and USB - **/ - UINT32 SecurityMode : 3; - /** - BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH= GPIOs - 0: Disabled, 1: Enabled - **/ - UINT32 Gpio5Filter : 1; - /** - Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport - 0: Disabled, 1: Enabled - **/ - UINT32 TbtWakeupSupport : 1; - /** - SMI TBT enumeration - 0: Disabled, 1: Enabled - **/ - UINT32 TbtHotSMI : 1; - /** - Notify PCIe RP after Hot-Plug/Hot-Unplug occurred. - 0: Disabled, 1: Enabled - **/ - UINT32 TbtHotNotify : 1; - /** - CLK REQ for all the PCIe device in TBT daisy chain. - 0: Disabled, 1: Enabled - **/ - UINT32 TbtSetClkReq : 1; - /** - ASPM setting for all the PCIe device in TBT daisy chain. - 0: Disabled, 1: L0s, 2: L1, 3: L0sL1 - **/ - UINT32 TbtAspm : 2; - /** - LTR for for all the PCIe device in TBT daisy chain. - 0: Disabled, 1: Enabled - **/ - UINT32 TbtLtr : 1; - /** - TBT Dynamic AC/DC L1. - 0: Disabled, 1: Enabled - **/ - UINT32 TbtAcDcSwitch : 1; - /** - TBT RTD3 Support. - 0: Disabled, 1: Enabled - **/ - UINT32 Rtd3Tbt : 1; - /** - TBT ClkReq for RTD3 Flow. - 0: Disabled, 1: Enabled - **/ - UINT32 Rtd3TbtClkReq : 1; - /** - TBT Win10support for Tbt FW execution mode. - 0: Disabled, 1: Native, 2: Native + RTD3 - **/ - UINT32 Win10Support : 2; - UINT32 Rsvd0 : 17; ///< Reserved bits - UINT16 Rtd3TbtClkReqDelay; - UINT16 Rtd3TbtOffDelay; -} TBT_COMMON_CONFIG; - -// -// dTBT Resource Data Structure -// -typedef struct _DTBT_RESOURCE_CONFIG{ - UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe RP = that connect to dTBT Host Router - UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for PCIe RP = that connect to dTBT Host Router - UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM resource= for PCIe RP that connect to dTBT Host Router - UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for PCIe RP= that connect to dTBT Host Router - UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve PMEM resourc= e for PCIe RP that connect to dTBT Host Router - UINT8 Reserved[1]; ///< Reserved for DWORD alignment -} DTBT_RESOURCE_CONFIG; - -/** - TBT DXE configuration\n - Revision 1: - - Initial version. -**/ -typedef struct _DXE_TBT_POLICY_PROTOCOL { - TBT_COMMON_CONFIG TbtCommonConfig; = ///< Tbt Common Information - DTBT_RESOURCE_CONFIG DTbtResourceConfig; ///< dTbt Resource Configur= ation -} DXE_TBT_POLICY_PROTOCOL; - -#pragma pack(pop) - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol= /TbtNvsArea.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Proto= col/TbtNvsArea.h deleted file mode 100644 index e57381e12c..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNvs= Area.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @file - This file defines the TBT NVS Area Protocol. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _TBT_NVS_AREA_H_ -#define _TBT_NVS_AREA_H_ - -// -// Platform NVS Area definition -// -#include - -// -// Includes -// -#define TBT_NVS_DEVICE_ENABLE 1 -#define TBT_NVS_DEVICE_DISABLE 0 - -// -// Forward reference for pure ANSI compatibility -// -typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL; - -/// -/// Extern the GUID for protocol users. -/// -extern EFI_GUID gTbtNvsAreaProtocolGuid; - -#define TBT_NVS_AREA_REVISION_1 1 - -// -// Platform NVS Area Protocol -// -typedef struct _TBT_NVS_AREA_PROTOCOL { - TBT_NVS_AREA *Area; -} TBT_NVS_AREA_PROTOCOL; - -#endif // _TBT_NVS_AREA_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoard= Info.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo= .h deleted file mode 100644 index 13319a9cec..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _TBT_INFO_GUID_H_ -#define _TBT_INFO_GUID_H_ -#include - -#pragma pack(1) -// -// TBT Info HOB -// -typedef struct _TBT_INFO_HOB { - EFI_HOB_GUID_TYPE EfiHobGuidType; - DTBT_COMMON_CONFIG DTbtCommonConfig; = ///< dTbt Common Configuration - DTBT_CONTROLLER_CONFIG DTbtControllerConfig; = ///< dTbt Controller Configuration -} TBT_INFO_HOB; -#pragma pack() - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolic= yCommonDefinition.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /TbtPolicyCommonDefinition.h deleted file mode 100644 index eb4c79317d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommon= Definition.h +++ /dev/null @@ -1,77 +0,0 @@ -/** @file -TBT Policy Common definition. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _TBT_POLICY_COMMON_H_ -#define _TBT_POLICY_COMMON_H_ - -#include -#include - -#define TYPE_PCIE 0x01 -#define TYPE_PEG 0x02 - -#pragma pack(push, 1) - -// -// dTBT Force Power GPIO Data Structure -// -typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG { - UINT8 GpioAccessType; ///< Where the GPIO comes from [a.k.a= how to access the GPIO],Where the GPIO comes from. 0: Disabled; 1: PCH, 2:= I/O Expander - UINT8 Expander; ///< Applicable to GpioAccessType =3D= IoExpander {TCA6424A} type - GPIO_PAD GpioPad; ///< GPIO Pad Number - BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act= ive High - UINT8 Reserved[1]; ///< Reserved for DWORD alignmen= t -} DTBT_FORCE_POWER_GPIO_CONFIG; - -// -// dTBT CIO Plug Event GPIO Data Structure -// -typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG { - GPIO_PAD GpioPad; ///< GPIO Pad Number - UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will ch= ange the XTBT method to the _Lxx or _Exx that we assign in this item. - BOOLEAN AcpiGpeSignaturePorting; ///< 0 =3D No porting required(f= or 2-tier GPI GPE event architecture), 1 =3D Porting required(for 1-tier GP= I GPE event architecture) - UINT8 Reserved[3]; ///< Reserved for DWORD alignmen= t -} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG; - -// -// dTBT PCIE Reset GPIO Data Structure -// -typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG { - GPIO_PAD GpioPad; ///< GPIO Pad Number - BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act= ive High - UINT8 Reserved[3]; ///< Reserved for DWORD alignmen= t -} DTBT_PCIE_RESET_GPIO_CONFIG; - -// -// dTBT Controller Data Structure -// -typedef struct _DTBT_CONTROLLER_CONFIG{ - UINT8 DTbtControllerEn; ///< Enable/Disable DT= btController. - UINT8 Type; ///< 01-Pcie RP, 02- P= EG,Reserved. - UINT8 PcieRpNumber; ///< RP Number/ PEG Po= rt (0,1,2) that connecet to dTBT controller. - DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The GPIO pin that= can force dTBT Power On. - DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that= can generate Hot-Plug event. - DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO pin that= is use to perform Reset when platform enters to Sx, it is required for pla= tforms where PCI_RST pin connected to Tbt is controlled with GPIO - UINT8 Reserved[1]; ///< Reserved for DWOR= D alignment -} DTBT_CONTROLLER_CONFIG; - -// -// dTBT Controller Data Structure -// -typedef struct _DTBT_COMMON_CONFIG{ - UINT8 TbtBootOn; ///< Send BootOn Mailbox = command when TbtBootOn is enabled. - UINT8 TbtUsbOn; ///< Send UsbOn Mailbox c= ommand when TbtBootOn is enabled. - UINT8 Gpio3ForcePwr; ///< Force GPIO to power = on or not - UINT16 Gpio3ForcePwrDly; ///< The delay time after= do ForcePwr - BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT contro= llers share the same GPIO pin - BOOLEAN PcieRstSupport; ///< 0 =3D Not Support, 1= =3D Supported. it is required for platforms where PCI_RST pin connected to= Tbt is controlled with GPIO - UINT8 Reserved[1]; ///< Reserved for DWORD a= lignment -} DTBT_COMMON_CONFIG; - -#pragma pack(pop) - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPo= licyLib/DxeTbtPolicyLibrary.h b/Platform/Intel/ClevoOpenBoardPkg/Features/T= bt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h deleted file mode 100644 index 75bc01e29a..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib= /DxeTbtPolicyLibrary.h +++ /dev/null @@ -1,22 +0,0 @@ -/** @file - Header file for the DxeTBTPolicy library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _DXE_TBT_POLICY_LIBRARY_H_ -#define _DXE_TBT_POLICY_LIBRARY_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif // _DXE_TBT_POLICY_LIBRARY_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPo= licyLib/PeiTbtPolicyLibrary.h b/Platform/Intel/ClevoOpenBoardPkg/Features/T= bt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h deleted file mode 100644 index 38c5d60fab..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib= /PeiTbtPolicyLibrary.h +++ /dev/null @@ -1,17 +0,0 @@ -/** @file - Header file for the PeiTBTPolicy library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _PEI_TBT_POLICY_LIBRARY_H_ -#define _PEI_TBT_POLICY_LIBRARY_H_ - -#include -#include -#include -#include -#include - -#endif // _PEI_TBT_POLICY_LIBRARY_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS= miHandler.h b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tbt= SmiHandler.h deleted file mode 100644 index 7b06a037da..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandl= er.h +++ /dev/null @@ -1,179 +0,0 @@ -/**@file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _TBT_SMI_HANDLER_H_ -#define _TBT_SMI_HANDLER_H_ - -#include -#include -#include - -#ifdef PROGRESS_CODE -#undef PROGRESS_CODE -#endif - -#define MAX_TBT_DEPTH 6 - -#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRID= GE_P2P)) - -#define BAR_ALIGN(v, a) ((((v) - 1) | (a)) + 1) - -#define CMD_BUS_MASTER BIT2 -#define CMD_BM_IO (CMD_BUS_MASTER | BIT0) -#define CMD_BM_MEM (CMD_BUS_MASTER | BIT1) -#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0) - -#define DEF_CACHE_LINE_SIZE 0x20 -#define DEF_RES_IO_PER_DEV 4 -#define DEF_RES_MEM_PER_DEV 32 -#define DEF_RES_PMEM_PER_DEV 32 - -#define DOCK_BUSSES 8 - -#define DISBL_IO_REG1C 0x01F1 -#define DISBL_MEM32_REG20 0x0000FFF0 -#define DISBL_PMEM_REG24 0x0001FFF1 - -#define count(x) (sizeof (x) / sizeof ((x)[0])) - -#define PCIE_CAP_ID_SSID_SSVID 0x0D -#define INVALID_PCI_DEVICE 0xFFFFFFFF -#define PCI_TBT_VESC_REG2 0x510 - -typedef struct _PortInfo { - UINT8 IoBase; - UINT8 IoLimit; - UINT16 MemBase; - UINT16 MemLimit; - UINT64 PMemBase64; - UINT64 PMemLimit64; - UINT8 BusNumLimit; - UINT8 ConfedEP; -} PORT_INFO; - -typedef struct _MEM_REGS { - UINT32 Base; - UINT32 Limit; -} MEM_REGS; - -typedef struct _PMEM_REGS { - UINT64 Base64; - UINT64 Limit64; -} PMEM_REGS; - -typedef struct _IO_REGS { - UINT16 Base; - UINT16 Limit; -} IO_REGS; - -typedef struct _BRDG_RES_CONFIG { - UINT8 Cmd; - UINT8 Cls; - UINT8 IoBase; - UINT8 IoLimit; - UINT16 MemBase; - UINT16 MemLimit; - UINT64 PMemBase64; - UINT64 PMemLimit64; -} BRDG_RES_CONFIG; - -typedef struct _BRDG_CONFIG { - DEV_ID DevId; - UINT8 PBus; - UINT8 SBus; - UINT8 SubBus; - BOOLEAN IsDSBridge; - BRDG_RES_CONFIG Res; -} BRDG_CONFIG; - -enum { - HR_US_PORT, - HR_DS_PORT0, - HR_DS_PORT3, - HR_DS_PORT4, - HR_DS_PORT5, - HR_DS_PORT6, - MAX_CFG_PORTS -}; - -enum { - HR_DS_PORT1 =3D HR_DS_PORT3 -}; - -// -// Alpine Ridge -// -enum { - AR_DS_PORT1 =3D HR_DS_PORT3, - AR_DS_PORT2, - AR_DS_PORT3, - AR_DS_PORT4 -}; - -typedef struct _HR_CONFIG { - UINT16 DeviceId; - UINT8 HRBus; - UINT8 MinDSNumber; - UINT8 MaxDSNumber; - UINT8 BridgeLoops; -} HR_CONFIG; - -STATIC const BRDG_RES_CONFIG NOT_IN_USE_BRIDGE =3D { - CMD_BUS_MASTER, - 0, - DISBL_IO_REG1C & 0xFF, - DISBL_IO_REG1C >> 8, - DISBL_MEM32_REG20 & 0xFFFF, - DISBL_MEM32_REG20 >> 16, - DISBL_PMEM_REG24 & 0xFFFF, - DISBL_PMEM_REG24 >> 16 -}; - -typedef union _BRDG_CIO_MAP_REG { - UINT32 AB_REG; - struct { - UINT32 NumOfDSPorts : 5; - UINT32 CioPortMap : 27; - } Bits; -} BRDG_CIO_MAP_REG; - -// -// Functions -// -VOID -ThunderboltCallback ( - IN UINT8 Type - ); - -VOID -TbtDisablePCIDevicesAndBridges ( - IN UINT8 Type - ); - -VOID -EndOfThunderboltCallback( - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction -); - -VOID -ConfigureTbtAspm( - IN UINT8 Type, - IN UINT16 Aspm -); - -UINT8 -PcieFindCapId ( - IN UINT8 Segment, - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 CapId - ); - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef= .h b/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h deleted file mode 100644 index 5d096db346..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h +++ /dev/null @@ -1,116 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - // Define a Global region of ACPI NVS Region that may be used for any - // type of implementation. The starting offset and size will be fixed - // up by the System BIOS during POST. Note that the Size must be a word - // in size to be fixed up correctly. - -#ifndef _GLOBAL_NVS_AREA_DEF_H_ -#define _GLOBAL_NVS_AREA_DEF_H_ - -#pragma pack (push,1) -typedef struct { - // - // Miscellaneous Dynamic Registers: - // - UINT16 OperatingSystem; ///< Offset 0 Op= erating System - UINT8 SmiFunction; ///< Offset 2 SM= I Function Call (ASL to SMI via I/O Trap) - UINT32 Port80DebugValue; ///< Offset 3 Po= rt 80 Debug Port Value - UINT8 PowerState; ///< Offset 7 Po= wer State (AC Mode =3D 1) - // - // Thermal Policy Registers: - // - UINT8 EnableDigitalThermalSensor; ///< Offset 8 Di= gital Thermal Sensor Enable - UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9 DT= S SMI Function Call - // - // CPU Identification Registers: - // - UINT8 ApicEnable; ///< Offset 10 AP= IC Enabled by SBIOS (APIC Enabled =3D 1) - UINT8 ThreadCount; ///< Offset 11 Nu= mber of Enabled Threads - // - // PCIe Hot Plug - // - UINT8 PcieOSCControl; ///< Offset 12 PC= IE OSC Control - UINT8 NativePCIESupport; ///< Offset 13 Na= tive PCIE Setup Value - // - // Global Variables - // - UINT8 DisplaySupportFlag; ///< Offset 14 _D= OS Display Support Flag. - UINT8 InterruptModeFlag; ///< Offset 15 Gl= obal IOAPIC/8259 Interrupt Mode Flag. - UINT8 L01Counter; ///< Offset 16 Gl= obal L01 Counter. - UINT8 LtrEnable[24]; ///< Offset 17 La= tency Tolerance Reporting Enable - ///< Offset 18 La= tency Tolerance Reporting Enable - ///< Offset 19 La= tency Tolerance Reporting Enable - ///< Offset 20 La= tency Tolerance Reporting Enable - ///< Offset 21 La= tency Tolerance Reporting Enable - ///< Offset 22 La= tency Tolerance Reporting Enable - ///< Offset 23 La= tency Tolerance Reporting Enable - ///< Offset 24 La= tency Tolerance Reporting Enable - ///< Offset 25 La= tency Tolerance Reporting Enable - ///< Offset 26 La= tency Tolerance Reporting Enable - ///< Offset 27 La= tency Tolerance Reporting Enable - ///< Offset 28 La= tency Tolerance Reporting Enable - ///< Offset 29 La= tency Tolerance Reporting Enable - ///< Offset 30 La= tency Tolerance Reporting Enable - ///< Offset 31 La= tency Tolerance Reporting Enable - ///< Offset 32 La= tency Tolerance Reporting Enable - ///< Offset 33 La= tency Tolerance Reporting Enable - ///< Offset 34 La= tency Tolerance Reporting Enable - ///< Offset 35 La= tency Tolerance Reporting Enable - ///< Offset 36 La= tency Tolerance Reporting Enable - ///< Offset 37 La= tency Tolerance Reporting Enable - ///< Offset 38 La= tency Tolerance Reporting Enable - ///< Offset 39 La= tency Tolerance Reporting Enable - ///< Offset 40 La= tency Tolerance Reporting Enable - UINT8 ObffEnable[24]; ///< Offset 41 Op= timized Buffer Flush and Fill - ///< Offset 42 Op= timized Buffer Flush and Fill - ///< Offset 43 Op= timized Buffer Flush and Fill - ///< Offset 44 Op= timized Buffer Flush and Fill - ///< Offset 45 Op= timized Buffer Flush and Fill - ///< Offset 46 Op= timized Buffer Flush and Fill - ///< Offset 47 Op= timized Buffer Flush and Fill - ///< Offset 48 Op= timized Buffer Flush and Fill - ///< Offset 49 Op= timized Buffer Flush and Fill - ///< Offset 50 Op= timized Buffer Flush and Fill - ///< Offset 51 Op= timized Buffer Flush and Fill - ///< Offset 52 Op= timized Buffer Flush and Fill - ///< Offset 53 Op= timized Buffer Flush and Fill - ///< Offset 54 Op= timized Buffer Flush and Fill - ///< Offset 55 Op= timized Buffer Flush and Fill - ///< Offset 56 Op= timized Buffer Flush and Fill - ///< Offset 57 Op= timized Buffer Flush and Fill - ///< Offset 58 Op= timized Buffer Flush and Fill - ///< Offset 59 Op= timized Buffer Flush and Fill - ///< Offset 60 Op= timized Buffer Flush and Fill - ///< Offset 61 Op= timized Buffer Flush and Fill - ///< Offset 62 Op= timized Buffer Flush and Fill - ///< Offset 63 Op= timized Buffer Flush and Fill - ///< Offset 64 Op= timized Buffer Flush and Fill - UINT8 Rtd3Support; ///< Offset 65 Ru= ntime D3 support. - UINT8 LowPowerS0Idle; ///< Offset 66 Lo= w Power S0 Idle Enable - UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67 Vi= rtual GPIO button Notify Sleep State Change - UINT8 PstateCapping; ///< Offset 68 P-= state Capping - UINT8 Ps2MouseEnable; ///< Offset 69 Ps= 2 Mouse Enable - UINT8 Ps2KbMsEnable; ///< Offset 70 Ps= 2 Keyboard and Mouse Enable - // - // Driver Mode - // - UINT32 GpioIrqRoute; ///< Offset 71 GP= IO IRQ - UINT8 PL1LimitCS; ///< Offset 75 se= t PL1 limit when entering CS - UINT16 PL1LimitCSValue; ///< Offset 76 PL= 1 limit value - UINT8 TenSecondPowerButtonEnable; ///< Offset 78 10= sec Power button support - UINT8 PciDelayOptimizationEcr; ///< Offset 79 Pc= i Delay Optimization Ecr - UINT8 TbtSupport; ///< Offset 80 Th= underbolt(TM) support - UINT8 TbtNativeOsHotPlug; ///< Offset 81 Tb= tNativeOsHotPlug - UINT8 TbtSelector; ///< Offset 82 Th= underbolt(TM) Root port selector - UINT8 TbtSelector1; ///< Offset 83 Th= underbolt(TM) Root port selector -} EFI_GLOBAL_NVS_AREA; - -#pragma pack(pop) -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h b/Platfo= rm/Intel/ClevoOpenBoardPkg/Include/IoExpander.h deleted file mode 100644 index 0f313e429a..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @file - GPIO definition table for N1xxWU - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _IO_EXPANDER_H_ -#define _IO_EXPANDER_H_ - -typedef struct { - UINT32 IoExpanderNumber : 1; // IO Expander Number (0/1) - UINT32 GpioPinNumber : 5; // GPIO Pin Number (0 to 23) - UINT32 GpioDirection : 1; // GPIO Pin Direction (Input/Output) - UINT32 GpioLevel : 1; // GPIO Pin Output Level (High/Low) - UINT32 GpioInversion : 1; // GPIO Pin Inversion (Enabled/Disabled) - UINT32 Reserved : 23; // Reserved -} IO_EXPANDER_GPIO_CONFIG; - -//SKL PCH LP GPIO Expander Number -#define IO_EXPANDER_0 0 -#define IO_EXPANDER_1 1 - -//SKL PCH LP GPIO Pin Mapping -#define IO_EXPANDER_GPIO_0 0 // P00 -#define IO_EXPANDER_GPIO_1 1 // P01 -#define IO_EXPANDER_GPIO_2 2 // P02 -#define IO_EXPANDER_GPIO_3 3 // P03 -#define IO_EXPANDER_GPIO_4 4 // P04 -#define IO_EXPANDER_GPIO_5 5 // P05 -#define IO_EXPANDER_GPIO_6 6 // P06 -#define IO_EXPANDER_GPIO_7 7 // P07 -#define IO_EXPANDER_GPIO_8 8 // P10 -#define IO_EXPANDER_GPIO_9 9 // P11 -#define IO_EXPANDER_GPIO_10 10 // P12 -#define IO_EXPANDER_GPIO_11 11 // P13 -#define IO_EXPANDER_GPIO_12 12 // P14 -#define IO_EXPANDER_GPIO_13 13 // P15 -#define IO_EXPANDER_GPIO_14 14 // P16 -#define IO_EXPANDER_GPIO_15 15 // P17 -#define IO_EXPANDER_GPIO_16 16 // P20 -#define IO_EXPANDER_GPIO_17 17 // P21 -#define IO_EXPANDER_GPIO_18 18 // P22 -#define IO_EXPANDER_GPIO_19 19 // P23 -#define IO_EXPANDER_GPIO_20 20 // P24 -#define IO_EXPANDER_GPIO_21 21 // P25 -#define IO_EXPANDER_GPIO_22 22 // P26 -#define IO_EXPANDER_GPIO_23 23 // P27 - -//SKL PCH LP GPIO Expander GPIO Direction -#define IO_EXPANDER_GPIO_OUTPUT 0 -#define IO_EXPANDER_GPIO_INPUT 1 - -//SKL PCH LP GPIO Expaner GPIO Output Level -#define IO_EXPANDER_GPO_LEVEL_LOW 0 -#define IO_EXPANDER_GPO_LEVEL_HIGH 1 - -//SKL PCH LP GPIO Expaner GPIO Inversion Status -#define IO_EXPANDER_GPI_INV_DISABLED 0 -#define IO_EXPANDER_GPI_INV_ENABLED 1 -#define IO_EXPANDER_GPIO_RESERVED 0x00 - -//GPIO Table Terminator -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderL= ib.h b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h deleted file mode 100644 index dc75a7decb..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/GpioExpanderLib.h +++ /dev/null @@ -1,122 +0,0 @@ -/** @file - Support for IO expander TCA6424. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _GPIO_EXPANDER_LIB_H_ -#define _GPIO_EXPANDER_LIB_H_ - -#include -#include -#include -#include -#include -#include -#include - -/** - Set the Direction value for the given Expander Gpio pin. - - This function is to Set the direction value for the GPIO - Pin within the giving Expander. - - @param[in] Expander Expander Value with in the Contoller - @param[in] Pin Pin with in the Expnader Value - @param[in] Value none -**/ -VOID -GpioExpSetDirection ( - IN UINT8 Expander, - IN UINT8 Pin, - IN UINT8 Direction - ); -/** - Set the input value for the given Expander Gpio pin. - - This function is to get the input value for the GPIO - Pin within the giving Expander. - - @param[in] Expander Expander Value with in the Contoller - @param[in] Pin Pin with in the Expnader Value - @param[in] Value none - -**/ -VOID -GpioExpSetPolarity ( - IN UINT8 Expander, - IN UINT8 Pin, - IN UINT8 Polarity - ); -/** - Set the Output value for the given Expander Gpio pin. - - This function is to Set the Output value for the GPIO - Pin within the giving Expander. - - @param[in] Expander Expander Value with in the Contoller - @param[in] Pin Pin with in the Expnader Value - @param[in] Value none - -**/ -VOID -GpioExpSetOutput ( - IN UINT8 Expander, - IN UINT8 Pin, - IN UINT8 Value - ); -/** - Returns the data from register value giving in the input. - - This function is to get the data from the Expander - Registers by following the I2C Protocol communication - - - @param[in] Bar0 Bar address of the SerialIo Controller - @param[in] Address Expander Value with in the Contoller - @param[in] Register Address of Input/Output/Configure/Polarity - registers with in the Expander - - @retval UINT8 Value returned from the register -**/ -UINT8 -GpioExpGetInput ( - IN UINT8 Expander, - IN UINT8 Pin - ); - -/** - Configures all registers of a single IO Expander in one go. - - @param[in] Expander Expander number (0/1) - @param[in] Direction Bit-encoded direction values. BIT0 is for pin0, = etc. 0=3Doutput, 1=3Dinput - @param[in] Polarity Bit-encoded input inversion values. BIT0 is for = pin0, etc. 0=3Dnormal, 1=3Dinversion - @param[in] Output Bit-encoded output state, ignores polarity, only= applicable if direction=3DINPUT. BIT0 is for pin0, etc. 0=3Dlow, 1=3Dhigh - -**/ -VOID -GpioExpBulkConfig ( - IN UINT8 Expander, - IN UINT32 Direction, - IN UINT32 Polarity, - IN UINT32 Output - ); - -/** - Returns the Controller on which GPIO expander is present. - - This function returns the Controller value - - @param[out] Controller Pointer to a Controller value on - which I2C expander is configured. - - @retval EFI_SUCCESS non. -**/ -EFI_STATUS -GpioExpGetController ( - OUT UINT8 *Controller - ); - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.= h b/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h deleted file mode 100644 index e36699e8e9..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cAccessLib.h +++ /dev/null @@ -1,33 +0,0 @@ -/** @file - Support for IO expander TCA6424. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _I2C_ACCESS_LIB_H_ -#define _I2C_ACCESS_LIB_H_ - -#include -#include -#include -#include -#include -#include -#include - -#define WAIT_1_SECOND 1600000000 //1.6 * 10^9 - -EFI_STATUS -I2cWriteRead ( - IN UINTN MmioBase, - IN UINT8 SlaveAddress, - IN UINT8 WriteLength, - IN UINT8 *WriteBuffer, - IN UINT8 ReadLength, - IN UINT8 *ReadBuffer, - IN UINT64 TimeBudget - ); - -#endif \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h b= /Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h deleted file mode 100644 index a2003002cf..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssTables.h +++ /dev/null @@ -1,51 +0,0 @@ -/** @file* - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef PCH_HSIO_PTSSTABLES_H_ -#define PCH_HSIO_PTSSTABLES_H_ - -#include - -/// -/// SATA PTSS Topology Types -/// -typedef enum { - PchSataTopoUnknown =3D 0x00, - PchSataTopoIsata, - PchSataTopoDirectConnect, - PchSataTopoFlex, - PchSataTopoM2 -} PCH_SATA_TOPOLOGY; - -/// -/// PCIe PTSS Topology Types -/// -typedef enum { - PchPcieTopoUnknown =3D 0x00, - PchPcieTopox1, - PchPcieTopox4, - PchPcieTopoSataE, - PchPcieTopoM2 -} PCH_PCIE_TOPOLOGY; - -/// -/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH= . -/// -typedef struct { - UINT8 LaneNum; - UINT8 PhyMode; - UINT16 Offset; - UINT32 Value; - UINT32 BitMask; -} PCH_SBI_PTSS_HSIO_TABLE; - -typedef struct { - PCH_SBI_PTSS_HSIO_TABLE PtssTable; - UINT16 Topology; -} HSIO_PTSS_TABLES; - -#endif // PCH_HSIO_PTSSTABLES_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsAre= a.h b/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h deleted file mode 100644 index b10547b6b9..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/GlobalNvsArea.h +++ /dev/null @@ -1,47 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _GLOBAL_NVS_AREA_H_ -#define _GLOBAL_NVS_AREA_H_ - -// -// Includes -// -#define GLOBAL_NVS_DEVICE_ENABLE 1 -#define GLOBAL_NVS_DEVICE_DISABLE 0 - -// -// Forward reference for pure ANSI compatibility -// - -typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL; - -// -// Global NVS Area Protocol GUID -// -#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \ -{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xd= c } - -#define GLOBAL_NVS_AREA_REVISION 16 -// -// Extern the GUID for protocol users. -// -extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; - -// -// Global NVS Area definition -// -#include - -// -// Global NVS Area Protocol -// -typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { - EFI_GLOBAL_NVS_AREA *Area; -} EFI_GLOBAL_NVS_AREA_PROTOCOL; - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h b/Platform/= Intel/ClevoOpenBoardPkg/Include/SioRegs.h deleted file mode 100644 index cf636b798c..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h +++ /dev/null @@ -1,157 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _SIO_REG_H_ -#define _SIO_REG_H_ - -#define REG_LOGICAL_DEVICE 0x07 -#define ACTIVATE 0x30 - -#define BASE_ADDRESS_HIGH0 0x60 -#define BASE_ADDRESS_LOW0 0x61 -#define BASE_ADDRESS_HIGH1 0x62 -#define BASE_ADDRESS_LOW1 0x63 -#define BASE_ADDRESS_HIGH2 0x64 -#define BASE_ADDRESS_LOW2 0x65 -#define BASE_ADDRESS_HIGH3 0x66 -#define BASE_ADDRESS_LOW3 0x67 -#define PRIMARY_INTERRUPT_SELECT 0x70 -#define WAKEUP_ON_IRQ_EN 0x70 -#define INTERRUPT_TYPE 0x71 -#define DMA_CHANNEL_SELECT0 0x74 -#define DMA_CHANNEL_SELECT1 0x75 - - - -// -//Port address for PILOT - III -// -#define PILOTIII_CHIP_ID 0x03 -#define PILOTIII_SIO_INDEX_PORT 0x04E -#define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1) - -#define PILOTIII_UNLOCK 0x5A -#define PILOTIII_LOCK 0xA5 - -// -// logical device in PILOT-III -// -#define PILOTIII_SIO_PSR 0x00 -#define PILOTIII_SIO_COM2 0x01 -#define PILOTIII_SIO_COM1 0x02 -#define PILOTIII_SIO_SWCP 0x03 -#define PILOTIII_SIO_GPIO 0x04 -#define PILOTIII_SIO_WDT 0x05 -#define PILOTIII_SIO_KCS3 0x08 -#define PILOTIII_SIO_KCS4 0x09 -#define PILOTIII_SIO_KCS5 0x0A -#define PILOTIII_SIO_BT 0x0B -#define PILOTIII_SIO_SMIC 0x0C -#define PILOTIII_SIO_MAILBOX 0x0D -#define PILOTIII_SIO_RTC 0x0E -#define PILOTIII_SIO_SPI 0x0F -#define PILOTIII_SIO_TAP 0x10 -// -// Regisgers for Pilot-III -// -#define PILOTIII_CHIP_ID_REG 0x20 -#define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE -#define PILOTIII_ACTIVATE ACTIVATE -#define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 -#define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 -#define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1 -#define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1 -#define PILOTIII_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT - -// -// Port address for PC8374 -// -#define PC8374_SIO_INDEX_PORT 0x02E -#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1) - -// -// Logical device in PC8374 -// -#define PC8374_SIO_FLOPPY 0x00 -#define PC8374_SIO_PARA 0x01 -#define PC8374_SIO_COM2 0x02 -#define PC8374_SIO_COM1 0x03 -#define PC8374_SIO_MOUSE 0x05 -#define PC8374_SIO_KYBD 0x06 -#define PC8374_SIO_GPIO 0x07 - -// -// Registers specific for PC8374 -// -#define PC8374_CLOCK_SELECT 0x2D -#define PC8374_CLOCK_CONFIG 0x29 - -// -// Registers for PC8374 -// -#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE -#define PC8374_ACTIVATE ACTIVATE -#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 -#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 -#define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT -#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0 - -#define PC87427_SERVERIO_CNF2 0x22 - - -// -// Pilot III Mailbox Data Register definitions -// -#define MBDAT00_OFFSET 0x00 -#define MBDAT01_OFFSET 0x01 -#define MBDAT02_OFFSET 0x02 -#define MBDAT03_OFFSET 0x03 -#define MBDAT04_OFFSET 0x04 -#define MBDAT05_OFFSET 0x05 -#define MBDAT06_OFFSET 0x06 -#define MBDAT07_OFFSET 0x07 -#define MBDAT08_OFFSET 0x08 -#define MBDAT09_OFFSET 0x09 -#define MBDAT10_OFFSET 0x0A -#define MBDAT11_OFFSET 0x0B -#define MBDAT12_OFFSET 0x0C -#define MBDAT13_OFFSET 0x0D -#define MBDAT14_OFFSET 0x0E -#define MBDAT15_OFFSET 0x0F -#define MBST0_OFFSET 0x10 -#define MBST1_OFFSET 0x11 -#define MBBINT_OFFSET 0x12 - -// -// Mailbox Bit definitions... -// -#define MBBINT_MBBIST_BIT 0x80 -// If both are there, use the default one -// -#define W83527_EXIST BIT2 -#define PC8374_EXIST BIT1 -#define PILOTIII_EXIST BIT0 -#define DEFAULT_SIO PILOTIII_EXIST -#define DEFAULT_KDB PC8374_EXIST - -#define IPMI_DEFAULT_SMM_IO_BASE 0xca2 -// -// For Pilot III -// - -#define PILOTIII_SWC_BASE_ADDRESS 0xA00 -#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80 -#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84 -#define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86 -#define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4 -#define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5 -#define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2 -#define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3 -#define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600 -#define PILOTIII_MAILBOX_MASK 0xFFE0 -#define BMC_KCS_BASE_ADDRESS 0x0CA0 -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/ClevoOpenBo= ardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyU= pdate.h deleted file mode 100644 index 9f6b236e42..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiPchPolicyUpdate.h +++ /dev/null @@ -1,28 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _PEI_PCH_POLICY_UPDATE_H_ -#define _PEI_PCH_POLICY_UPDATE_H_ - -// -// External include files do NOT need to be explicitly specified in real E= DKII -// environment -// -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/ClevoOpenBoa= rdPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpd= ate.h deleted file mode 100644 index c006dbcd68..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSaPolicyUpdate.h +++ /dev/null @@ -1,30 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _PEI_SA_POLICY_UPDATE_H_ -#define _PEI_SA_POLICY_UPDATE_H_ - -// -// External include files do NOT need to be explicitly specified in real E= DKII -// environment -// -#include -#include -#include -#include -#include "PeiPchPolicyUpdate.h" -#include -#include - -#include -#include -#include - -extern EFI_GUID gTianoLogoGuid; - -#endif - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h b/P= latform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h deleted file mode 100644 index 684b31f051..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h +++ /dev/null @@ -1,13 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _N1_XX_WU_ID_H_ -#define _N1_XX_WU_ID_H_ - -#define BoardIdN1xxWU 0x60 - -#endif // _PEI_N1_XX_WU_BOARD_INIT_LIB_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiN1xxWUInitLib.h b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardIn= itLib/PeiN1xxWUInitLib.h deleted file mode 100644 index ddb873aaa2..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW= UInitLib.h +++ /dev/null @@ -1,42 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _PEI_N1_XX_WU_BOARD_INIT_LIB_H_ -#define _PEI_N1_XX_WU_BOARD_INIT_LIB_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -extern const UINT8 mDqByteMapSklRvp3[2][6][2]; -extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8]; -extern const UINT8 mSkylakeRvp3Spd110[]; -extern const UINT16 mSkylakeRvp3Spd110Size; -extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_N1xxWU[]; -extern UINT16 PchLpHsioPtss_Bx_N1xxWU_Size; -extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_N1xxWU[]; -extern UINT16 PchLpHsioPtss_Cx_N1xxWU_Size; - -extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3; -extern GPIO_INIT_CONFIG mGpioTableN1xxWUUcmcDevice[]; -extern UINT16 mGpioTableN1xxWUUcmcDeviceSize; - -extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[]; -extern UINT16 mGpioTableIoExpanderSize; -extern GPIO_INIT_CONFIG mGpioTableN1xxWUTouchpanel; -extern GPIO_INIT_CONFIG mGpioTableN1xxWU[]; -extern UINT16 mGpioTableN1xxWUSize; - -#endif // _PEI_N1_XX_WU_BOARD_INIT_LIB_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSili= conPolicyUpdateLib/DxeGopPolicyInit.h b/Platform/Intel/ClevoOpenBoardPkg/N1= xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h deleted file mode 100644 index f4ab1a5bca..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli= cyUpdateLib/DxeGopPolicyInit.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @file -Header file for the GopPolicyInitDxe Driver. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _GOP_POLICY_INIT_DXE_H_ -#define _GOP_POLICY_INIT_DXE_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/** -Initialize GOP DXE Policy - -@param[in] ImageHandle Image handle of this driver. - -@retval EFI_SUCCESS Initialization complete. -@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. -@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. -@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ -EFI_STATUS -EFIAPI -GopPolicyInitDxe( - IN EFI_HANDLE ImageHandle - ); - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSili= conPolicyUpdateLib/DxeSaPolicyInit.h b/Platform/Intel/ClevoOpenBoardPkg/N1x= xWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h deleted file mode 100644 index bb4b4369ad..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli= cyUpdateLib/DxeSaPolicyInit.h +++ /dev/null @@ -1,64 +0,0 @@ -/** @file - Header file for the SaPolicyInitDxe Driver. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#ifndef _SA_POLICY_INIT_DXE_H_ -#define _SA_POLICY_INIT_DXE_H_ - -#include -#include -#include -#include -#include -#include - -#include - - -/** - SA DXE Policy Driver Entry Point \n - - Introduction \n - System Agent DXE drivers behavior can be controlled by platform policy= without modifying reference code directly. - Platform policy Protocol is initialized with default settings in this = funciton. - This policy Protocol has to be initialized prior to System Agent initi= alization DXE drivers execution. - - - @pre - - Runtime variable service should be ready if policy initialization re= quired. - - - @result - SA_POLICY_PROTOCOL will be installed successfully and ready for System= Agent reference code use. - - - Porting Recommendations \n - Policy should be initialized basing on platform design or user selecti= on (like BIOS Setup Menu) - - @param[in] ImageHandle - Image handle of this driver. - - @retval EFI_SUCCESS Initialization complete. - @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. - @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. - @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ -EFI_STATUS -EFIAPI -SaPolicyInitDxe ( - IN EFI_HANDLE ImageHandle - ); - -/** - Get data for platform policy from setup options. - - @param[in] SaPolicy The pointer to get SA Policy protoc= ol instance - - @retval EFI_SUCCESS Operation success. - -**/ -EFI_STATUS -EFIAPI -UpdateDxeSaPolicy ( - IN OUT SA_POLICY_PROTOCOL *SaPolicy - ); - -#endif diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsIni= t.c b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c deleted file mode 100644 index 7c10cf8f73..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c +++ /dev/null @@ -1,95 +0,0 @@ -/** @file - Acpi Gnvs Init Library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/** -@brief - Global NVS initialize. - - @param[in] GlobalNvs - Pointer of Global NVS area - - @retval EFI_SUCCESS - Allocate Global NVS completed. - @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS= . -**/ -EFI_STATUS -EFIAPI -AcpiGnvsInit ( - IN OUT VOID **GlobalNvs - ) -{ - UINTN Pages; - EFI_PHYSICAL_ADDRESS Address; - EFI_STATUS Status; - EFI_GLOBAL_NVS_AREA_PROTOCOL *GNVS; - EFI_MP_SERVICES_PROTOCOL *MpService; - UINTN NumberOfCPUs; - UINTN NumberOfEnabledCPUs; - - Pages =3D EFI_SIZE_TO_PAGES (sizeof (EFI_GLOBAL_NVS_AREA)); - Address =3D 0xffffffff; // allocate address below 4G. - - Status =3D gBS->AllocatePages ( - AllocateMaxAddress, - EfiACPIMemoryNVS, - Pages, - &Address - ); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR(Status)) { - return Status; - } - - // - // Locate the MP services protocol - // Find the MP Protocol. This is an MP platform, so MP protocol must be = there. - // - Status =3D gBS->LocateProtocol ( - &gEfiMpServiceProtocolGuid, - NULL, - (VOID **) &MpService - ); - ASSERT_EFI_ERROR (Status); - - // - // Determine the number of processors - // - MpService->GetNumberOfProcessors ( - MpService, - &NumberOfCPUs, - &NumberOfEnabledCPUs - ); - - *GlobalNvs =3D (VOID *) (UINTN) Address; - SetMem (*GlobalNvs, sizeof (EFI_GLOBAL_NVS_AREA), 0); - - // - // GNVS default value init here... - // - GNVS =3D (EFI_GLOBAL_NVS_AREA_PROTOCOL *) &Address; - - GNVS->Area->ThreadCount =3D (UINT8)NumberOfEnabledCPUs; - - // - // Miscellaneous - // - GNVS->Area->PL1LimitCS =3D 0; - GNVS->Area->PL1LimitCSValue =3D 4500; - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDx= e.c b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c deleted file mode 100644 index 4f248006bf..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c +++ /dev/null @@ -1,307 +0,0 @@ -/** @file - Board ACPI DXE initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mG= lobalNvsArea; - -/** -@brief - Global NVS initialize. - - @param[in] GlobalNvs - Pointer of Global NVS area - - @retval EFI_SUCCESS - Allocate Global NVS completed. - @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS= . -**/ -EFI_STATUS -EFIAPI -AcpiGnvsInit ( - IN OUT VOID **GlobalNvs - ); - -VOID -UpdateDsdt ( - IN VOID *Table - ); - -// -// Function implementations -// - -/** - Locate the first instance of a protocol. If the protocol requested is a= n - FV protocol, then it will return the first FV that contains the ACPI tab= le - storage file. - - @param[in] Protocol The protocol to find. - @param[in] Instance Return pointer to the first instance of th= e protocol. - @param[in] Type TRUE if the desired protocol is a FV proto= col. - - @retval EFI_SUCCESS The function completed successfully. - @retval EFI_NOT_FOUND The protocol could not be located. - @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the= protocol. -**/ -EFI_STATUS -LocateSupportProtocol ( - IN EFI_GUID *Protocol, - IN EFI_GUID *gEfiAcpiMultiTableStorageGuid, - OUT VOID **Instance, - IN BOOLEAN Type - ) -{ - EFI_STATUS Status; - EFI_HANDLE *HandleBuffer; - UINTN NumberOfHandles; - EFI_FV_FILETYPE FileType; - UINT32 FvStatus; - EFI_FV_FILE_ATTRIBUTES Attributes; - UINTN Size; - UINTN Index; - - // - // Locate protocol. - // - Status =3D gBS->LocateHandleBuffer ( - ByProtocol, - Protocol, - NULL, - &NumberOfHandles, - &HandleBuffer - ); - if (EFI_ERROR (Status)) { - // - // Defined errors at this time are not found and out of resources. - // - return Status; - } - - // - // Looking for FV with ACPI storage file - // - for (Index =3D 0; Index < NumberOfHandles; Index++) { - - // - // Get the protocol on this handle - // This should not fail because of LocateHandleBuffer - // - Status =3D gBS->HandleProtocol ( - HandleBuffer[Index], - Protocol, - Instance - ); - ASSERT_EFI_ERROR (Status); - - if (!Type) { - - // - // Not looking for the FV protocol, so find the first instance of th= e - // protocol. There should not be any errors because our handle buff= er - // should always contain at least one or LocateHandleBuffer would ha= ve - // returned not found. - // - break; - } - - // - // See if it has the ACPI storage file - // - Size =3D 0; - FvStatus =3D 0; - Status =3D ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile ( - *Instance, - gEfiAcpiMult= iTableStorageGuid, - NULL, - &Size, - &FileType, - &Attributes, - &FvStatus - ); - - // - // If we found it, then we are done - // - if (Status =3D=3D EFI_SUCCESS) { - break; - } - } - - // - // Our exit status is determined by the success of the previous operatio= ns - // If the protocol was found, Instance already points to it. - // - // - // Free any allocated buffers - // - FreePool (HandleBuffer); - - return Status; -} - -EFI_STATUS -PublishAcpiTablesFromFv ( - IN EFI_GUID *gEfiAcpiMultiTableStorageGuid - ) -{ - EFI_STATUS Status; - EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; - EFI_ACPI_COMMON_HEADER *CurrentTable; - UINT32 FvStatus; - UINTN Size; - EFI_ACPI_TABLE_VERSION Version; - UINTN TableHandle; - INTN Instance; - EFI_ACPI_TABLE_PROTOCOL *AcpiTable; - - Instance =3D 0; - TableHandle =3D 0; - CurrentTable =3D NULL; - FwVol =3D NULL; - - // - // Find the AcpiSupport protocol - // - Status =3D LocateSupportProtocol ( - &gEfiAcpiTableProtocolGuid, - gEfiAcpiMultiTableStorageGuid, - (VOID **) &AcpiTable, - FALSE - ); - ASSERT_EFI_ERROR (Status); - - // - // Locate the firmware volume protocol - // - Status =3D LocateSupportProtocol ( - &gEfiFirmwareVolume2ProtocolGuid, - gEfiAcpiMultiTableStorageGuid, - (VOID **) &FwVol, - TRUE - ); - - // - // Read tables from the storage file. - // - - while (Status =3D=3D EFI_SUCCESS) { - Status =3D FwVol->ReadSection ( - FwVol, - gEfiAcpiMultiTableStorageGuid, - EFI_SECTION_RAW, - Instance, - (VOID **) &CurrentTable, - &Size, - &FvStatus - ); - - if (!EFI_ERROR (Status)) { - - // - // Perform any table specific updates. - // - if (CurrentTable->Signature =3D=3D EFI_ACPI_2_0_DIFFERENTIATED_SYSTE= M_DESCRIPTION_TABLE_SIGNATURE) { - UpdateDsdt (CurrentTable); - } - BoardUpdateAcpiTable (CurrentTable, &Version); - - // - // Add the table - // - TableHandle =3D 0; - - if (Version !=3D EFI_ACPI_TABLE_VERSION_NONE) { - Status =3D AcpiTable->InstallAcpiTable ( - AcpiTable, - CurrentTable, - CurrentTable->Length, - &TableHandle - ); - } - - ASSERT_EFI_ERROR (Status); - - // - // Increment the instance - // - Instance++; - CurrentTable =3D NULL; - } - } - - // - // Finished - // - return EFI_SUCCESS; -} - -/** - ACPI Platform driver installation function. - - @param[in] ImageHandle Handle for this drivers loaded image protocol= . - @param[in] SystemTable EFI system table. - - @retval EFI_SUCCESS The driver installed without error. - @retval EFI_ABORTED The driver encountered an error and could not= complete installation of - the ACPI tables. - -**/ -EFI_STATUS -EFIAPI -InstallAcpiBoard ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_HANDLE Handle; - - AcpiGnvsInit((VOID **) &mGlobalNvsArea.Area); - - // - // This PCD set must be done before PublishAcpiTablesFromFv. - // The PCD data will be used there. - // - PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mGlobalNvsArea.Area); - - // - // Platform ACPI Tables - // - PublishAcpiTablesFromFv (&gEfiCallerIdGuid); - - // - // This protocol publish must be done after PublishAcpiTablesFromFv. - // The NVS data is be updated there. - // - Handle =3D NULL; - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiGlobalNvsAreaProtocolGuid, - &mGlobalNvsArea, - NULL - ); - ASSERT_EFI_ERROR (Status); - - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.= c b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c deleted file mode 100644 index 41f0b8c113..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/UpdateDsdt.c +++ /dev/null @@ -1,776 +0,0 @@ -/** @file - Performs board DSDT ACPI table updates. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -#include -extern GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL = mGlobalNvsArea; - -VOID -UpdateDsdt ( - IN VOID *Table - ) -{ - UINT8 *CurrPtr; - UINT8 *TmpDsdtPointer; - UINT8 *DsdtPointer; - UINT32 *Signature; - UINT8 *Operation; - UINT32 *Address; - UINT8 *Value; - UINT16 *Size; - BOOLEAN EnterDock =3D FALSE; - - UINT8 MaximumDsdtPointLength; - - MaximumDsdtPointLength =3D 20; - - // - // Fix up the AML code in the DSDT affected by end user options. - // Fix up the following ASL Code: - // (1) ACPI Global NVS Memory Base and Size. - // (2) ACPI Graphics NVS Memory Base and Size. - // (3) SMBus I/O Base. - // (4) Thermal Management Methods. - // - // - // Loop through the ASL looking for values that we must fix up. - // - CurrPtr =3D (UINT8 *) Table; - for (DsdtPointer =3D CurrPtr; - DsdtPointer <=3D (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr= )->Length); - DsdtPointer++ - ) { - Signature =3D (UINT32 *) DsdtPointer; - switch (*Signature) { - // - // GNVS operation region - // - case (SIGNATURE_32 ('G', 'N', 'V', 'S')): - // - // Conditional match. For Region Objects, the Operator will alw= ays be the - // byte immediately before the specific name. Therefore, subtra= ct 1 to check - // the Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_EXT_REGION_OP) { - Address =3D (UINT32 *) (DsdtPointer + 6); - *Address =3D (UINT32) (UINTN) mGlobalNvsArea.Area; - Size =3D (UINT16 *) (DsdtPointer + 11); - *Size =3D sizeof (EFI_GLOBAL_NVS_AREA); - } - break; - - // - // _AC0 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '0')): - // - // Conditional match. _AC0 is >63 and <4095 bytes, so the packa= ge length is 2 bytes. - // Therefore, subtract 3 to check the Operator. - // - Operation =3D DsdtPointer - 3; - if (*Operation =3D=3D AML_METHOD_OP) { - // - // Check if we want _AC0 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '0'); - } - } - break; - - // - // _AL0 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '0')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL0 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '0'); - } - } - break; - - // - // _AC1 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '1')): - // - // Conditional match. _AC1 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC1 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '1'); - } - } - break; - - // - // _AL1 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '1')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL1 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '1'); - } - } - break; - - // - // _AC2 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '2')): - // - // Conditional match. _AC2 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC2 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '2'); - } - } - break; - - // - // _AL2 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '2')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL2 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '2'); - } - } - break; - - // - // _AC3 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '3')): - // - // Conditional match. _AC3 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC3 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '3'); - } - } - break; - - // - // _AL3 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '3')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL3 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '3'); - } - } - break; - - // - // _AC4 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '4')): - // - // Conditional match. _AC4 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC4 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '4'); - } - } - break; - - // - // _AL4 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '4')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL4 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '4'); - } - } - break; - - // - // _AC5 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '5')): - // - // Conditional match. _AC5 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC5 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '5'); - } - } - break; - - // - // _AL5 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '5')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL5 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '5'); - } - } - break; - - // - // _AC6 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '6')): - // - // Conditional match. _AC6 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC6 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '6'); - } - } - break; - - // - // _AL6 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '6')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL6 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '6'); - } - } - break; - - // - // _AC7 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '7')): - // - // Conditional match. _AC7 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC7 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '7'); - } - } - break; - - // - // _AL7 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '7')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL7 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '7'); - } - } - break; - - // - // _AC8 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '8')): - // - // Conditional match. _AC8 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC8 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '8'); - } - } - break; - - // - // _AL8 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '8')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL8 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '8'); - } - } - break; - - // - // _AC9 method - // - case (SIGNATURE_32 ('_', 'A', 'C', '9')): - // - // Conditional match. _AC9 is < 63 bytes, so the package length= is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _AC9 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'C', '9'); - } - } - break; - - // - // _AL9 method - // - case (SIGNATURE_32 ('_', 'A', 'L', '9')): - // - // Conditional match. For Name Objects, the Operator will alway= s be the byte - // immediately before the specific name. Therefore, subtract 1 t= o check the - // Operator. - // - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - - // - // Check if we want _AL9 enabled - // - if (PcdGet8 (PcdDisableActiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'A', 'L', '9'); - } - } - break; - - // - // _PSL method - // - case (SIGNATURE_32 ('_', 'P', 'S', 'L')): - // - // Conditional match. _PSL is < 256 bytes, so the package lengt= h is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 3; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _PSL enabled - // - if (PcdGet8 (PcdDisablePassiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'P', 'S', 'L'); - } - } - break; - - // - // _PSV method - // - case (SIGNATURE_32 ('_', 'P', 'S', 'V')): - // - // Conditional match. _PSV is < 256 bytes, so the package lengt= h is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 3; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _PSV enabled - // - if (PcdGet8 (PcdDisablePassiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'P', 'S', 'V'); - } - } - break; - - // - // _CRT method - // - case (SIGNATURE_32 ('_', 'C', 'R', 'T')): - // - // Conditional match. _CRT is < 256 bytes, so the package lengt= h is 1 byte. - // Subtract 3 to check the Operator for CRB, subract 2 for Harri= s Beach. - // - Operation =3D DsdtPointer - 3; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _CRT enabled - // - if (PcdGet8 (PcdDisableCriticalTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'C', 'R', 'T'); - } - } - break; - - // - // _TC1 method - // - case (SIGNATURE_32 ('_', 'T', 'C', '1')): - // - // Conditional match. _TC1 is < 256 bytes, so the package lengt= h is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _TC1 enabled - // - if (PcdGet8 (PcdDisablePassiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'T', 'C', '1'); - } - } - break; - - // - // _TC2 method - // - case (SIGNATURE_32 ('_', 'T', 'C', '2')): - // - // Conditional match. _TC2 is < 256 bytes, so the package lengt= h is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _TC2 enabled - // - if (PcdGet8 (PcdDisablePassiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'T', 'C', '2'); - } - } - break; - - // - // _TSP method - // - case (SIGNATURE_32 ('_', 'T', 'S', 'P')): - // - // Conditional match. _TSP is < 256 bytes, so the package lengt= h is 1 byte. - // Therefore, subtract 2 to check the Operator. - // - Operation =3D DsdtPointer - 2; - if (*Operation =3D=3D AML_METHOD_OP) { - - // - // Check if we want _TSP enabled - // - if (PcdGet8 (PcdDisablePassiveTripPoints) =3D=3D 0) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'T', 'S', 'P'); - } - } - break; - - // - // Update SS3 Name with Setup value - // - case (SIGNATURE_32 ('S', 'S', '3', '_')): - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - Value =3D (UINT8 *) DsdtPointer + 4; - *Value =3D PcdGet8 (PcdAcpiSleepState); - } - break; - // - // Update SS4 Name with Setup value - // - case (SIGNATURE_32 ('S', 'S', '4', '_')): - Operation =3D DsdtPointer - 1; - if (*Operation =3D=3D AML_NAME_OP) { - Value =3D (UINT8 *) DsdtPointer + 4; - *Value =3D PcdGet8 (PcdAcpiHibernate); - } - break; - // - // _EJ0 method - // - case (SIGNATURE_32 ('_', 'E', 'J', '0')): - if (PcdGet8 (PcdLowPowerS0Idle)) { - // - // Remove _EJ0 for SOC - // - if (*(DsdtPointer-3) =3D=3D AML_METHOD_OP) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'E', 'J', '0'); - EnterDock =3D TRUE; - } - } - break; - // - // _STA method for Device (\_SB.PCI0.DOCK) - // - case (SIGNATURE_32 ('_', 'S', 'T', 'A')): - if (PcdGet8 (PcdLowPowerS0Idle)) { - // - // Remove _STA in (\_SB.PCI0.DOCK) for SOC - // - if ((*(DsdtPointer-3) =3D=3D AML_METHOD_OP) && (EnterDock)) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'S', 'T', 'A'); - EnterDock =3D FALSE; - } - } - break; - // - // _UPC method for Device (\_SB.PCI0.XHC.RHUB) - // - case (SIGNATURE_32('H', 'S', '1', '3')): - for (TmpDsdtPointer =3D DsdtPointer; - TmpDsdtPointer <=3D DsdtPointer + MaximumDsdtPointLength; - TmpDsdtPointer++){ - Signature =3D (UINT32 *) TmpDsdtPointer; - switch (*Signature) { - case(SIGNATURE_32('U', 'P', 'C', 'P')): - Value =3D (UINT8 *)((UINT32 *)TmpDsdtPointer + 2); - break; - default: - // - // Do nothing. - // - break; - } - } - break; - - - // - // _DCK method - // - case (SIGNATURE_32 ('_', 'D', 'C', 'K')): - if (PcdGet8 (PcdLowPowerS0Idle)) { - // - // Remove _DCK for SOC - // - if (*(DsdtPointer-3) =3D=3D AML_METHOD_OP) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'D', 'C', 'K'); - } - } - break; - - // - // mask _DEP from CPU's scope if CS disabled. - // - case (SIGNATURE_32 ('P', 'R', '0', '0')): - case (SIGNATURE_32 ('P', 'R', '0', '1')): - case (SIGNATURE_32 ('P', 'R', '0', '2')): - case (SIGNATURE_32 ('P', 'R', '0', '3')): - case (SIGNATURE_32 ('P', 'R', '0', '4')): - case (SIGNATURE_32 ('P', 'R', '0', '5')): - case (SIGNATURE_32 ('P', 'R', '0', '6')): - case (SIGNATURE_32 ('P', 'R', '0', '7')): - case (SIGNATURE_32 ('P', 'R', '0', '8')): - case (SIGNATURE_32 ('P', 'R', '0', '9')): - case (SIGNATURE_32 ('P', 'R', '1', '0')): - case (SIGNATURE_32 ('P', 'R', '1', '1')): - case (SIGNATURE_32 ('P', 'R', '1', '2')): - case (SIGNATURE_32 ('P', 'R', '1', '3')): - case (SIGNATURE_32 ('P', 'R', '1', '4')): - case (SIGNATURE_32 ('P', 'R', '1', '5')): - - if (PcdGet8 (PcdLowPowerS0Idle) =3D=3D 0) { - for (TmpDsdtPointer =3D DsdtPointer; TmpDsdtPointer <=3D DsdtP= ointer + MaximumDsdtPointLength; TmpDsdtPointer++){ - Signature =3D (UINT32 *) TmpDsdtPointer; - switch (*Signature) { - case(SIGNATURE_32('_', 'D', 'E', 'P')): - *(UINT8 *) TmpDsdtPointer =3D 'X'; - break; - default: - // - // Do nothing. - // - break; - } - } - } - break; - - // - // _EDL name - // - case (SIGNATURE_32 ('_', 'E', 'D', 'L')): - if (PcdGet8 (PcdLowPowerS0Idle)) { - // - // Remove _EDL for SOC - // - if (*(DsdtPointer-1) =3D=3D AML_NAME_OP) { - Signature =3D (UINT32 *) DsdtPointer; - *Signature =3D SIGNATURE_32 ('X', 'E', 'D', 'L'); - } - } - break; - - default: - // - // Do nothing. - // - break; - } - } -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlu= g.c b/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c deleted file mode 100644 index 05f128d719..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c +++ /dev/null @@ -1,351 +0,0 @@ -/** @file - Performs specific PCI-EXPRESS device resource configuration. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -// -// Statements that include other files -// -#include "PciHotPlug.h" -#include -#include -#include -#include - -#define PCIE_NUM (20) -#define PEG_NUM (3) -#define PADDING_BUS (1) -#define PADDING_NONPREFETCH_MEM (1) -#define PADDING_PREFETCH_MEM (1) -#define PADDING_IO (1) -#define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFE= TCH_MEM + PADDING_IO) - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE= _NUM + PEG_NUM]; - -GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount =3D 0; - -GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevice= PathTemplate =3D { - ACPI, - PCI(0xFF, 0xFF), // Dummy Device no & Function no - END -}; - -/** - Entry point for the driver. - - This routine reads the PlatformType GPI on FWH and produces a protocol - to be consumed by the chipset driver to effect those settings. - - @param[in] ImageHandle An image handle. - @param[in] SystemTable A pointer to the system table. - - @retval EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -PciHotPlug ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - PCI_HOT_PLUG_INSTANCE *PciHotPlug; - UINTN Index; - UINTN RpDev; - UINTN RpFunc; - PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath; - UINT32 PcieRootPortHpeData =3D 0; - - DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n")); - - PcieRootPortHpeData =3D PcdGet32 (PcdPchPcieRootPortHpe); - // - // PCH Rootports Hotplug device path creation - // - for (Index =3D 0; Index < PCIE_NUM; Index++) { - if (((PcieRootPortHpeData >> Index) & BIT0) =3D=3D BIT0) { // Check th= e Rootport no's hotplug is set - Status =3D GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the a= ctual device/function no corresponding to the Rootport no provided - ASSERT_EFI_ERROR (Status); - - HotplugPcieDevicePath =3D NULL; - HotplugPcieDevicePath =3D AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE= _PATH)); - ASSERT (HotplugPcieDevicePath !=3D NULL); - if (HotplugPcieDevicePath =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, siz= eof (PCIE_HOT_PLUG_DEVICE_PATH)); - HotplugPcieDevicePath->PciRootPortNode.Device =3D (UINT8) RpDev; // = Update real Device no - HotplugPcieDevicePath->PciRootPortNode.Function =3D (UINT8) RpFunc; = // Update real Function no - - mPcieLocation[mHpcCount].HpcDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL= *)HotplugPcieDevicePath; - mPcieLocation[mHpcCount].HpbDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL= *)HotplugPcieDevicePath; - mHpcCount++; - - DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device = 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount= , RpDev, RpFunc)); - } - } - - - PciHotPlug =3D AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE)); - ASSERT (PciHotPlug !=3D NULL); - if (PciHotPlug =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - // - // Initialize driver private data. - // - ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE)); - - PciHotPlug->Signature =3D PCI_HOT_PLUG_DRI= VER_PRIVATE_SIGNATURE; - PciHotPlug->HotPlugInitProtocol.GetRootHpcList =3D GetRootHpcList; - PciHotPlug->HotPlugInitProtocol.InitializeRootHpc =3D InitializeRootHp= c; - PciHotPlug->HotPlugInitProtocol.GetResourcePadding =3D GetResourcePaddi= ng; - - Status =3D gBS->InstallProtocolInterface ( - &PciHotPlug->Handle, - &gEfiPciHotPlugInitProtocolGuid, - EFI_NATIVE_INTERFACE, - &PciHotPlug->HotPlugInitProtocol - ); - ASSERT_EFI_ERROR (Status); - - return EFI_SUCCESS; -} - - -/** - This procedure returns a list of Root Hot Plug controllers that require - initialization during boot process - - @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLU= G_INIT protocol. - @param[out] HpcCount The number of Root HPCs returned. - @param[out] HpcList The list of Root HPCs. HpcCount defines the number= of elements in this list. - - @retval EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -GetRootHpcList ( - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, - OUT UINTN *HpcCount, - OUT EFI_HPC_LOCATION **HpcList - ) -{ - *HpcCount =3D mHpcCount; - *HpcList =3D mPcieLocation; - - return EFI_SUCCESS; -} - - -/** - This procedure Initializes one Root Hot Plug Controller - This process may casue initialization of its subordinate buses - - @param[in] This The pointer to the instance of the EFI_PCI_H= OT_PLUG_INIT protocol. - @param[in] HpcDevicePath The Device Path to the HPC that is being ini= tialized. - @param[in] HpcPciAddress The address of the Hot Plug Controller funct= ion on the PCI bus. - @param[in] Event The event that should be signaled when the H= ot Plug Controller initialization is complete. Set to NULL if the caller wa= nts to wait until the entire initialization process is complete. The event = must be of the type EFI_EVT_SIGNAL. - @param[out] HpcState The state of the Hot Plug Controller hardwar= e. The type EFI_Hpc_STATE is defined in section 3.1. - - @retval EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -InitializeRootHpc ( - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, - IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, - IN UINT64 HpcPciAddress, - IN EFI_EVENT Event, OPTIONAL - OUT EFI_HPC_STATE *HpcState - ) -{ - if (Event) { - gBS->SignalEvent (Event); - } - - *HpcState =3D EFI_HPC_STATE_INITIALIZED; - - return EFI_SUCCESS; -} - - -/** - Returns the resource padding required by the PCI bus that is controlled = by the specified Hot Plug Controller. - - @param[in] This The pointer to the instance of the EFI_PCI_HO= T_PLUG_INIT protocol. initialized. - @param[in] HpcDevicePath The Device Path to the Hot Plug Controller. - @param[in] HpcPciAddress The address of the Hot Plug Controller functi= on on the PCI bus. - @param[out] HpcState The state of the Hot Plug Controller hardware= . The type EFI_HPC_STATE is defined in section 3.1. - @param[out] Padding This is the amount of resource padding requir= ed by the PCI bus under the control of the specified Hpc. Since the caller = does not know the size of this buffer, this buffer is allocated by the call= ee and freed by the caller. - @param[out] Attribute Describes how padding is accounted for. - - @retval EFI_SUCCESS. -**/ -EFI_STATUS -EFIAPI -GetResourcePadding ( - IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, - IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, - IN UINT64 HpcPciAddress, - OUT EFI_HPC_STATE *HpcState, - OUT VOID **Padding, - OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes - ) -{ - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; - EFI_STATUS Status; - UINT8 RsvdExtraBusNum =3D 0; - UINT16 RsvdPcieMegaMem =3D 10; - UINT8 PcieMemAddrRngMax =3D 0; - UINT16 RsvdPciePMegaMem =3D 10; - UINT8 PciePMemAddrRngMax =3D 0; - UINT8 RsvdTbtExtraBusNum =3D 0; - UINT16 RsvdTbtPcieMegaMem =3D 10; - UINT8 TbtPcieMemAddrRngMax =3D 0; - UINT16 RsvdTbtPciePMegaMem =3D 10; - UINT8 TbtPciePMemAddrRngMax =3D 0; - UINT8 RsvdPcieKiloIo =3D 4; - BOOLEAN SetResourceforTbt =3D FALSE; - UINTN RpIndex; - UINTN RpDev; - UINTN RpFunc; - -DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n")); - - PaddingResource =3D AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS= _SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); - ASSERT (PaddingResource !=3D NULL); - if (PaddingResource =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - *Padding =3D (VOID *) PaddingResource; - - RpDev =3D (UINTN) ((HpcPciAddress >> 16) & 0xFF); - RpFunc =3D (UINTN) ((HpcPciAddress >> 8) & 0xFF); - - // Get the actual Rootport no corresponding to the device/function no pr= ovided - if (RpDev =3D=3D SA_PEG_DEV_NUM) { - // PEG - RpIndex =3D PCIE_NUM + RpFunc; - DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d Bus 0x0= 0, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev, RpFunc)); - } else { - // PCH - Status =3D GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex); - DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d Bus 0x0= 0, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc)); - } - - GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum, &RsvdTbtPc= ieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaMem ,&TbtPciePMemAddrRng= Max, &SetResourceforTbt); - if (SetResourceforTbt) { - RsvdExtraBusNum =3D RsvdTbtExtraBusNum; - RsvdPcieMegaMem =3D RsvdTbtPcieMegaMem; - PcieMemAddrRngMax =3D TbtPcieMemAddrRngMax; - RsvdPciePMegaMem =3D RsvdTbtPciePMegaMem; - PciePMemAddrRngMax =3D TbtPciePMemAddrRngMax; - } - - // - // Padding for bus - // - ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_D= ESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); - *Attributes =3D EfiPaddingPciBus; - - PaddingResource->Desc =3D 0x8A; - PaddingResource->Len =3D 0x2B; - PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_BUS; - PaddingResource->GenFlag =3D 0x0; - PaddingResource->SpecificFlag =3D 0; - PaddingResource->AddrRangeMin =3D 0; - PaddingResource->AddrRangeMax =3D 0; - PaddingResource->AddrLen =3D RsvdExtraBusNum; - - // - // Padding for non-prefetchable memory - // - PaddingResource++; - PaddingResource->Desc =3D 0x8A; - PaddingResource->Len =3D 0x2B; - PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; - PaddingResource->GenFlag =3D 0x0; - if (SetResourceforTbt) { - PaddingResource->AddrSpaceGranularity =3D 32; - } else { - PaddingResource->AddrSpaceGranularity =3D 32; - } - PaddingResource->SpecificFlag =3D 0; - // - // Pad non-prefetchable - // - PaddingResource->AddrRangeMin =3D 0; - PaddingResource->AddrLen =3D RsvdPcieMegaMem * 0x100000; - if (SetResourceforTbt) { - PaddingResource->AddrRangeMax =3D (1 << PcieMemAddrRngMax) - 1; - } else { - PaddingResource->AddrRangeMax =3D 1; - } - - // - // Padding for prefetchable memory - // - PaddingResource++; - PaddingResource->Desc =3D 0x8A; - PaddingResource->Len =3D 0x2B; - PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; - PaddingResource->GenFlag =3D 0x0; - if (SetResourceforTbt) { - PaddingResource->AddrSpaceGranularity =3D 32; - } else { - PaddingResource->AddrSpaceGranularity =3D 32; - } - PaddingResource->SpecificFlag =3D 06; - // - // Padding for prefetchable memory - // - PaddingResource->AddrRangeMin =3D 0; - if (SetResourceforTbt) { - PaddingResource->AddrLen =3D RsvdPciePMegaMem * 0x100000; - } else { - PaddingResource->AddrLen =3D RsvdPcieMegaMem * 0x100000; - } - // - // Pad 16 MB of MEM - // - if (SetResourceforTbt) { - PaddingResource->AddrRangeMax =3D (1 << PciePMemAddrRngMax) - 1; - } else { - PaddingResource->AddrRangeMax =3D 1; - } - // - // Alignment - // - // Padding for I/O - // - PaddingResource++; - PaddingResource->Desc =3D 0x8A; - PaddingResource->Len =3D 0x2B; - PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; - PaddingResource->GenFlag =3D 0x0; - PaddingResource->SpecificFlag =3D 0; - PaddingResource->AddrRangeMin =3D 0; - PaddingResource->AddrLen =3D RsvdPcieKiloIo * 0x400; - // - // Pad 4K of IO - // - PaddingResource->AddrRangeMax =3D 1; - // - // Alignment - // - // Terminate the entries. - // - PaddingResource++; - ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc =3D ACPI_END= _TAG_DESCRIPTOR; - ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum =3D 0x0; - - *HpcState =3D EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; - - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPo= licyLib/DxeTbtPolicyLib.c b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/L= ibrary/DxeTbtPolicyLib/DxeTbtPolicyLib.c deleted file mode 100644 index b221e26d8e..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib= /DxeTbtPolicyLib.c +++ /dev/null @@ -1,160 +0,0 @@ -/** @file - This file is DxeTbtPolicyLib library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include - -/** -Update Tbt Policy Callback -Need to add PCDs for setup options -**/ - -VOID -EFIAPI -UpdateTbtPolicyCallback ( - VOID - ) -{ - - EFI_STATUS Status; - DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; - - DxeTbtConfig =3D NULL; - Status =3D EFI_NOT_FOUND; - DEBUG ((DEBUG_INFO, "UpdateTbtPolicyCallback\n")); - - Status =3D gBS->LocateProtocol ( - &gDxeTbtPolicyProtocolGuid, - NULL, - (VOID **) &DxeTbtConfig - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"))= ; - } else { - DxeTbtConfig->DTbtResourceConfig.DTbtPcieExtraBusRsvd =3D PcdGet8 (P= cdDTbtPcieExtraBusRsvd); - DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemRsvd =3D PcdGet16 (= PcdDTbtPcieMemRsvd); - DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemAddrRngMax =3D PcdGet8 (P= cdDTbtPcieMemAddrRngMax); - DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemRsvd =3D PcdGet16 (= PcdDTbtPciePMemRsvd); - DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemAddrRngMax =3D PcdGet8 (P= cdDTbtPciePMemAddrRngMax); - - DxeTbtConfig->TbtCommonConfig.TbtAspm =3D PcdGet8 (PcdDTbtAsp= m); - DxeTbtConfig->TbtCommonConfig.TbtHotNotify =3D PcdGet8 (PcdDTbtHot= Notify); - DxeTbtConfig->TbtCommonConfig.TbtHotSMI =3D PcdGet8 (PcdDTbtHot= SMI); - DxeTbtConfig->TbtCommonConfig.TbtSetClkReq =3D PcdGet8 (PcdDTbtSet= ClkReq); - DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport =3D PcdGet8 (PcdDTbtWak= eupSupport); - DxeTbtConfig->TbtCommonConfig.SecurityMode =3D PcdGet8 (PcdDTbtSec= urityMode); - - DxeTbtConfig->TbtCommonConfig.Gpio5Filter =3D PcdGet8 (PcdDTbtGpi= o5Filter); - DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch =3D PcdGet8 (PcdDTbtAcD= cSwitch); - - DxeTbtConfig->TbtCommonConfig.Rtd3Tbt =3D PcdGet8 (PcdRtd3Tbt= ); - DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay =3D PcdGet16 (PcdRtd3Tb= tOffDelay); - DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq =3D PcdGet8 (PcdRtd3Tbt= ClkReq); - DxeTbtConfig->TbtCommonConfig.Win10Support =3D PcdGet8 (PcdDTbtWin1= 0Support); - } - - return; -} - -/** - Print DXE TBT Policy -**/ -VOID -TbtPrintDxePolicyConfig ( - VOID - ) -{ - EFI_STATUS Status; - DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; - - DEBUG ((DEBUG_INFO, "TbtPrintDxePolicyConfig Start\n")); - - DxeTbtConfig =3D NULL; - Status =3D EFI_NOT_FOUND; - Status =3D gBS->LocateProtocol ( - &gDxeTbtPolicyProtocolGuid, - NULL, - (VOID **) &DxeTbtConfig - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n"))= ; - } - ASSERT_EFI_ERROR (Status); - // - // Print DTBT Policy - // - DEBUG ((DEBUG_ERROR, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D DXE TBT POLICY =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D \n")); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig.DTbtPcieExtraBusRs= vd =3D %x\n", DxeTbtConfig->DTbtResourceConfig.DTbtPcieExtraBusRsvd)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemRsvd = =3D %x\n", DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemRsvd)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemAddrRng= Max =3D %x\n", DxeTbtConfig->DTbtResourceConfig.DTbtPcieMemAddrRngMax)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemRsvd = =3D %x\n", DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemRsvd)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemAddrRn= gMax =3D %x\n", DxeTbtConfig->DTbtResourceConfig.DTbtPciePMemAddrRngMax)); - - - // - // Print TBT Common Policy - // - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAspm =3D %x\n", Dx= eTbtConfig->TbtCommonConfig.TbtAspm)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotNotify =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.TbtHotNotify)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotSMI =3D %x\n", = DxeTbtConfig->TbtCommonConfig.TbtHotSMI)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtLtr =3D %x\n", Dxe= TbtConfig->TbtCommonConfig.TbtLtr)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtSetClkReq =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.TbtSetClkReq)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport =3D = %x\n", DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.SecurityMode =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.SecurityMode)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Gpio5Filter =3D %x\n"= , DxeTbtConfig->TbtCommonConfig.Gpio5Filter)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch =3D %x\= n", DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3Tbt =3D %x\n", Dx= eTbtConfig->TbtCommonConfig.Rtd3Tbt)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay =3D %= x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq =3D %x\= n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay = =3D %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay)); - DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Win10Support =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.Win10Support)); - - return; -} - -/** - Install Tbt Policy - - @param[in] ImageHandle Image handle of this driver. - - @retval EFI_SUCCESS The policy is installed. - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer - -**/ -EFI_STATUS -EFIAPI -InstallTbtPolicy ( - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - DXE_TBT_POLICY_PROTOCOL *DxeTbtPolicy; - - DEBUG ((DEBUG_INFO, "Install DXE TBT Policy\n")); - - DxeTbtPolicy =3D NULL; - //Alloc memory for DxeTbtPolicy - DxeTbtPolicy =3D (DXE_TBT_POLICY_PROTOCOL *) AllocateZeroPool (sizeof (D= XE_TBT_POLICY_PROTOCOL)); - if (DxeTbtPolicy =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - Status =3D gBS->InstallProtocolInterface ( - &ImageHandle, - &gDxeTbtPolicyProtocolGuid, - EFI_NATIVE_INTERFACE, - DxeTbtPolicy - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Install Tbt Secure Boot List protocol failed\n")= ); - } - return Status; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSm= mTbtCommonLib/TbtCommonLib.c b/Platform/Intel/ClevoOpenBoardPkg/Features/Tb= t/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c deleted file mode 100644 index 7afdc25f67..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCom= monLib/TbtCommonLib.c +++ /dev/null @@ -1,315 +0,0 @@ -/** @file - Common Thunderbolt functions. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include - - -/** - Selects the proper TBT Root port to assign resources - based on the user input value - - @param[in] SetupData Pointer to Setup data - - @retval TbtSelectorChosen Rootport number. -**/ -VOID -GetRootporttoSetResourcesforTbt ( - IN UINTN RpIndex, - OUT UINT8 *RsvdExtraBusNum, - OUT UINT16 *RsvdPcieMegaMem, - OUT UINT8 *PcieMemAddrRngMax, - OUT UINT16 *RsvdPciePMegaMem, - OUT UINT8 *PciePMemAddrRngMax, - OUT BOOLEAN *SetResourceforTbt - ) -{ - UINTN TbtRpNumber; - TbtRpNumber =3D (UINTN) PcdGet8 (PcdDTbtPcieRpNumber); - - if (RpIndex =3D=3D (TbtRpNumber - 1)) { - *RsvdExtraBusNum =3D PcdGet8 (PcdDTbtPcieExtraBusRsvd); - *RsvdPcieMegaMem =3D PcdGet16 (PcdDTbtPcieMemRsvd); - *PcieMemAddrRngMax =3D PcdGet8 (PcdDTbtPcieMemAddrRngMax); - *RsvdPciePMegaMem =3D PcdGet16 (PcdDTbtPciePMemRsvd); - *PciePMemAddrRngMax =3D PcdGet8 (PcdDTbtPciePMemAddrRngMax); - *SetResourceforTbt =3D TRUE; - } - else { - *SetResourceforTbt =3D FALSE; - } - } - -/** - Internal function to Wait for Tbt2PcieDone Bit.to Set or clear - @param[in] CommandOffsetAddress Tbt2Pcie Register Address - @param[in] TimeOut Time out with 100 ms garnularity - @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl= ear/Set) - @param[out] *Tbt2PcieValue Function Register value -**/ -BOOLEAN -InternalWaitforCommandCompletion( - IN UINT64 CommandOffsetAddress, - IN UINT32 TimeOut, - IN BOOLEAN Tbt2PcieDone, - OUT UINT32 *Tbt2PcieValue - ) -{ - BOOLEAN ReturnFlag; - UINT32 Tbt2PcieCheck; - - ReturnFlag =3D FALSE; - while (TimeOut-- > 0) { - *Tbt2PcieValue =3D PciSegmentRead32 (CommandOffsetAddress); - - if (0xFFFFFFFF =3D=3D *Tbt2PcieValue ) { - // - // Device is not here return now - // - ReturnFlag =3D FALSE; - break; - } - - if(Tbt2PcieDone) { - Tbt2PcieCheck =3D *Tbt2PcieValue & TBT2PCIE_DON_R; - } else { - Tbt2PcieCheck =3D !(*Tbt2PcieValue & TBT2PCIE_DON_R); - } - - if (Tbt2PcieCheck) { - ReturnFlag =3D TRUE; - break; - } - - MicroSecondDelay(TBT_MAIL_BOX_DELAY); - } - return ReturnFlag; -} -/** - Get Security Level. - @param[in] Bus Bus number Host Router (DTBT) - @param[in] Device Device number for Host Router (DTBT) - @param[in] Function Function number for Host Router (DTBT) - @param[in] Command Command for Host Router (DTBT) - @param[in] Timeout Time out with 100 ms garnularity -**/ -UINT8 -GetSecLevel ( - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 Command, - IN UINT32 Timeout - ) -{ - UINT64 Pcie2Tbt; - UINT64 Tbt2Pcie; - UINT32 RegisterValue; - UINT8 ReturnFlag; - - ReturnFlag =3D 0xFF; - - DEBUG ((DEBUG_INFO, "GetSecLevel() \n")); - - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) - - PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); - - if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterVa= lue)) { - ReturnFlag =3D (UINT8) (0xFF & (RegisterValue >> 8)); - } - - PciSegmentWrite32 (Pcie2Tbt, 0); - - InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu= e); - DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag)); - - return ReturnFlag; -} - -/** - Set Security Level. - @param[in] Data Security State - @param[in] Bus Bus number for Host Router (DTBT) - @param[in] Device Device number for Host Router (DTBT) - @param[in] Function Function number for Host Router (DTBT) - @param[in] Command Command for Host Router (DTBT) - @param[in] Timeout Time out with 100 ms garnularity -**/ -BOOLEAN -SetSecLevel ( - IN UINT8 Data, - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 Command, - IN UINT32 Timeout - ) -{ - UINT64 Pcie2Tbt; - UINT64 Tbt2Pcie; - UINT32 RegisterValue; - BOOLEAN ReturnFlag; - - ReturnFlag =3D FALSE; - - DEBUG ((DEBUG_INFO, "SetSecLevel() \n")); - - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) - - PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B); - - ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,= &RegisterValue); - DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue)); - PciSegmentWrite32 (Pcie2Tbt, 0); - - InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu= e); - DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag)); - return ReturnFlag; -} - -/** -Based on the Security Mode Selection, BIOS drives FORCE_PWR. - -@param[in] GpioNumber -@param[in] Value -**/ -VOID -ForceDtbtPower( - IN UINT8 GpioAccessType, - IN UINT8 Expander, - IN UINT32 GpioNumber, - IN BOOLEAN Value -) -{ - if (GpioAccessType =3D=3D 0x01) { - // PCH - GpioSetOutputValue (GpioNumber, (UINT32)Value); - } else if (GpioAccessType =3D=3D 0x02) { - // IoExpander {TCA6424A} - GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value); - } -} - -/** -Execute TBT Mail Box Command - -@param[in] Command TBT Command -@param[in] Bus Bus number for Host Router (DTBT) -@param[in] Device Device number for Host Router (DTBT) -@param[in] Function Function number for Host Router (DTBT) -@param[in] Timeout Time out with 100 ms garnularity -@Retval true if command executes succesfully -**/ -BOOLEAN -TbtSetPcie2TbtCommand( - IN UINT8 Command, - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT32 Timeout -) -{ - UINT64 Pcie2Tbt; - UINT64 Tbt2Pcie; - UINT32 RegisterValue; - BOOLEAN ReturnFlag; - - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) - - PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); - - ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE= , &RegisterValue); - - PciSegmentWrite32(Pcie2Tbt, 0); - - return ReturnFlag; -} -/** - Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po= rt physical Number - - @param[in] RpNumber Root port physical number. (0-based) - @param[out] RpDev Return corresponding root port device = number. - @param[out] RpFun Return corresponding root port functio= n number. - - @retval EFI_SUCCESS Root port device and function is retri= eved - @retval EFI_INVALID_PARAMETER If Invalid Root Port Number or TYPE is= Passed -**/ -EFI_STATUS -EFIAPI -GetDTbtRpDevFun ( - IN BOOLEAN Type, - IN UINTN RpNumber, - OUT UINTN *RpDev, - OUT UINTN *RpFunc - ) -{ - EFI_STATUS Status; - UINTN TbtRpDev; - UINTN TbtRpFunc; - - Status =3D EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS if= valid input found. - // - // CNL PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will be - // with device number 0x1 and Function number 0,1 and 2 respectively. - // - if (Type =3D=3D DTBT_TYPE_PEG) - { - // - // PEG Rootport - // - if (RpNumber <=3D 2) { - *RpDev =3D 0x01; - *RpFunc =3D RpNumber; - Status =3D EFI_SUCCESS; - } - } - if (Type =3D=3D DTBT_TYPE_PCH) - { - // - // PCH Rootport - // - if (RpNumber <=3D 23) { - Status =3D GetPchPcieRpDevFun (RpNumber, &TbtRpDev, &TbtRpFunc); - *RpDev =3D TbtRpDev; - *RpFunc =3D TbtRpFunc; - } - } - - ASSERT_EFI_ERROR (Status); - return Status; -} - -BOOLEAN -IsTbtHostRouter ( - IN UINT16 DeviceID - ) -{ - switch (DeviceID) { - case AR_HR_2C: - case AR_HR_4C: - case AR_HR_LP: - case AR_HR_C0_2C: - case AR_HR_C0_4C: - case TR_HR_2C: - case TR_HR_4C: - return TRUE; - } - - return FALSE; -} // IsTbtHostRouter - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPo= licyLib/PeiTbtPolicyLib.c b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/L= ibrary/PeiTbtPolicyLib/PeiTbtPolicyLib.c deleted file mode 100644 index d6105a0c67..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib= /PeiTbtPolicyLib.c +++ /dev/null @@ -1,204 +0,0 @@ -/** @file - This file is PeiTbtPolicyLib library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include -#include -#include -#include - -/** - Update PEI TBT Policy Callback -**/ -VOID -EFIAPI -UpdatePeiTbtPolicy ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; - PEI_TBT_POLICY *PeiTbtConfig; - - PeiTbtConfig =3D NULL; - Status =3D EFI_NOT_FOUND; - - DEBUG ((DEBUG_INFO, "UpdatePeiTbtPolicy \n")); - - Status =3D PeiServicesLocatePpi ( - &gEfiPeiReadOnlyVariable2PpiGuid, - 0, - NULL, - (VOID **) &VariableServices - ); - ASSERT_EFI_ERROR (Status); - - Status =3D PeiServicesLocatePpi ( - &gPeiTbtPolicyPpiGuid, - 0, - NULL, - (VOID **) &PeiTbtConfig - ); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); - } - ASSERT_EFI_ERROR (Status); - - // - // Update DTBT Policy - // - PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D PcdGet8 (PcdDTb= tControllerEn); - if (PcdGet8 (PcdDTbtControllerType) =3D=3D TYPE_PEG) - { - PeiTbtConfig-> DTbtControllerConfig.Type =3D (UINT8) TYPE_PEG; - PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D 1; // PEG RP 1 (F= unction no. 0) - } - else { - PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D PcdGet8 (PcdDTbtP= cieRpNumber); - PeiTbtConfig-> DTbtControllerConfig.Type =3D PcdGet8 (PcdDTbtControlle= rType); - } - PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D (GPIO_PA= D) PcdGet32 (PcdDTbtCioPlugEventGpioPad); - if (GpioCheckFor2Tier(PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpi= o.GpioPad)) { - PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo= rting =3D 0; - PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = =3D SIGNATURE_32('X', 'T', 'B', 'T'); - } - else { - PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo= rting =3D 1; - // - // Update Signature based on platform GPIO. - // - PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = =3D SIGNATURE_32('X', 'T', 'B', 'T'); - } - PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D PcdGet8 (PcdDTbtBootOn); - PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D PcdGet8 (PcdDTbtUsbOn); - PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D PcdGet8 (PcdDTbtGpio3Fo= rcePwr); - PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D PcdGet16 (PcdDTbtGpi= o3ForcePwrDly); - - return; -} - -/** - Print PEI TBT Policy -**/ -VOID -EFIAPI -TbtPrintPeiPolicyConfig ( - VOID - ) -{ - DEBUG_CODE_BEGIN (); - EFI_STATUS Status; - PEI_TBT_POLICY *PeiTbtConfig; - - PeiTbtConfig =3D NULL; - Status =3D EFI_NOT_FOUND; - DEBUG ((DEBUG_INFO, "TbtPrintPolicyConfig Start\n")); - - Status =3D PeiServicesLocatePpi ( - &gPeiTbtPolicyPpiGuid, - 0, - NULL, - (VOID **) &PeiTbtConfig - ); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); - } - ASSERT_EFI_ERROR (Status); - - // - // Print DTBT Policy - // - DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print B= EGIN -----------------\n")); - DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", PEI_TBT_POLICY_REVISION)); - DEBUG ((DEBUG_INFO, "------------------------ PEI_TBT_CONFIG ----------= -------\n")); - DEBUG ((DEBUG_INFO, " Revision : %d\n", PEI_TBT_POLICY_REVISION)); - - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.DTbtControllerEn= =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.Type =3D %x\n", = PeiTbtConfig-> DTbtControllerConfig.Type)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRpNumber =3D= %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi= oPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi= oLevel =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLeve= l)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio= Pad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio= Level =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel)= ); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .GpioPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.Gp= ioPad)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .AcpiGpeSignature =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEve= ntGpio.AcpiGpeSignature)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .AcpiGpeSignaturePorting =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.Cio= PlugEventGpio.AcpiGpeSignaturePorting)); - - - // - // Print DTBT Common Policy - // - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D %x\n",= PeiTbtConfig->DTbtCommonConfig.TbtBootOn)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D %x\n", = PeiTbtConfig->DTbtCommonConfig.TbtUsbOn)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D %x= \n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D= %x\n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfig= uration =3D %x\n", PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfigurati= on)); - DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.PcieRstSupport =3D %= x\n", PeiTbtConfig->DTbtCommonConfig.PcieRstSupport)); - - DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print E= ND -----------------\n")); - DEBUG_CODE_END (); - - return; -} - -/** - Install Tbt Policy - - @retval EFI_SUCCESS The policy is installed. - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer - -**/ -EFI_STATUS -EFIAPI -InstallPeiTbtPolicy ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_PPI_DESCRIPTOR *PeiTbtPolicyPpiDesc; - PEI_TBT_POLICY *PeiTbtConfig; - - DEBUG ((DEBUG_INFO, "Install PEI TBT Policy\n")); - - PeiTbtConfig =3D NULL; - - // - // Allocate memory for PeiTbtPolicyPpiDesc - // - PeiTbtPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (siz= eof (EFI_PEI_PPI_DESCRIPTOR)); - ASSERT (PeiTbtPolicyPpiDesc !=3D NULL); - if (PeiTbtPolicyPpiDesc =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - // - // Allocate memory and initialize all default to zero for PeiTbtPolicy - // - PeiTbtConfig =3D (PEI_TBT_POLICY *) AllocateZeroPool (sizeof (PEI_TBT_PO= LICY)); - ASSERT (PeiTbtConfig !=3D NULL); - if (PeiTbtConfig =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - // - // Initialize PPI - // - PeiTbtPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_= DESCRIPTOR_TERMINATE_LIST; - PeiTbtPolicyPpiDesc->Guid =3D &gPeiTbtPolicyPpiGuid; - PeiTbtPolicyPpiDesc->Ppi =3D PeiTbtConfig; - - Status =3D PeiServicesInstallPpi (PeiTbtPolicyPpiDesc); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "Install PEI TBT Policy failed\n")); - } - return Status; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/= PeiDTbtInitLib/PeiDTbtInitLib.c b/Platform/Intel/ClevoOpenBoardPkg/Features= /Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c deleted file mode 100644 index 9c4bddfc2d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library/Private/PeiDTbt= InitLib/PeiDTbtInitLib.c +++ /dev/null @@ -1,566 +0,0 @@ -/**@file - Thunderbolt(TM) Pei Library - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** -Is host router (For dTBT) or End Point (For iTBT) present before sleep - -@param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER -@param[in] Controller - Controller begin offset of CMOS - -@Retval TRUE There is a TBT HostRouter presented before sleep -@Retval FALSE There is no TBT HostRouter presented before sleep - -BOOLEAN -IsHostRouterPresentBeforeSleep( -IN UINT8 ControllerType, -IN UINT8 Controller -) -{ - UINT8 SavedState; - - SavedState =3D (UINT8)GetTbtHostRouterStatus(); - if (ControllerType =3D=3D DTBT_CONTROLLER){ - return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) =3D=3D (= DTBT_SAVE_STATE_OFFSET << Controller)); - } else { - if (ControllerType =3D=3D ITBT_CONTROLLER) { - return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) =3D=3D= (ITBT_SAVE_STATE_OFFSET << Controller)); - } - } - return 0; -} -**/ - -/** -Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 mode wi= th PreBootAclEnable - -@param[in] Bus Bus number for Host Router (DTBT) -@param[in] Device Device number for Host Router (DTBT) -@param[in] Function Function number for Host Router (DTBT) -@param[in] Timeout Time out with 100 ms garnularity -@Retval true if command executes succesfully -**/ -BOOLEAN -TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable( - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT32 Timeout -) -{ - UINT64 Pcie2Tbt; - UINT64 Tbt2Pcie; - UINT32 RegisterValue; - BOOLEAN ReturnFlag; - UINT32 Command; - - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) - GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) - -// If PreBootAcl is Enable, we need to enable DATA bit while sending SX EX= IT MAIL BOX Command - Command =3D (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED; - PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); - - ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,= &RegisterValue); - - PciSegmentWrite32(Pcie2Tbt, 0); - - return ReturnFlag; -} - -/** -Set the Sleep Mode if the HR is up. -@param[in] Bus Bus number for Host Router (DTBT) -@param[in] Device Device number for Host Router (DTBT) -@param[in] Function Function number for Host Router (DTBT) -**/ -VOID -TbtSetSxMode( -IN UINT8 Bus, -IN UINT8 Device, -IN UINT8 Function, -IN UINT8 TbtBootOn -) -{ - UINT64 TbtUsDevId; - UINT64 Tbt2Pcie; - UINT32 RegVal; - UINT32 MaxLoopCount; - UINTN Delay; - UINT8 RetCode; - EFI_BOOT_MODE BootMode; - EFI_STATUS Status; - - TbtUsDevId =3D PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0); - GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) - - MaxLoopCount =3D TBT_5S_TIMEOUT; // Wait 5 sec - Delay =3D 100 * 1000; - RetCode =3D 0x62; - - Status =3D PeiServicesGetBootMode(&BootMode); - ASSERT_EFI_ERROR(Status); - - if ((BootMode =3D=3D BOOT_ON_S4_RESUME) && (TbtBootOn =3D=3D 2)) { - MaxLoopCount =3D TBT_3S_TIMEOUT; - if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, Func= tion, MaxLoopCount)) { - // - // Nothing to wait, HR is not responsive - // - return; - } - } - else { - if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, Device= , Function, MaxLoopCount)) { - // - // Nothing to wait, HR is not responsive - // - return; - } - } - - DEBUG((DEBUG_INFO, "Wait for Dev ID !=3D 0xFF\n")); - - while (MaxLoopCount-- > 0) { - // - // Check what HR still here - // - RegVal =3D PciSegmentRead32(Tbt2Pcie); - if (0xFFFFFFFF =3D=3D RegVal) { - RetCode =3D 0x6F; - break; - } - // - // Check completion of TBT link - // - RegVal =3D PciSegmentRead32(TbtUsDevId); - if (0xFFFFFFFF !=3D RegVal) { - RetCode =3D 0x61; - break; - } - - MicroSecondDelay(Delay); - } - - DEBUG((DEBUG_INFO, "Return code =3D 0x%x\n", RetCode)); -} -/** - set tPCH25 Timing to 10 ms for DTBT. - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtSetTPch25Timing ( - IN PEI_TBT_POLICY *PeiTbtConfig -) -{ - DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n")); - UINT32 PchPwrmBase; - - // - //During boot, reboot and wake tPCH25 Timing should be set to 10 ms - // - PchPwrmBaseGet (&PchPwrmBase); - MmioOr32 ( - (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG), - (BIT0 | BIT1) - ); - - DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n")); - return EFI_SUCCESS; -} - -/** - Do ForcePower for DTBT Controller - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtForcePower ( - IN PEI_TBT_POLICY *PeiTbtConfig -) -{ - - DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n")); - - if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) { - DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad =3D %x \n", PeiTbtConfig-= > DTbtControllerConfig.ForcePwrGpio.GpioPad)); - ForceDtbtPower(PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Gp= ioAccessType,PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Expander, Pei= TbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> DTbtC= ontrollerConfig.ForcePwrGpio.GpioLevel); - DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n")); - MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly *= 1000); - DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower =3D 0x%x ms \n", Pe= iTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); - } - - DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n")); - return EFI_SUCCESS; -} - -/** - Clear VGA Registers for DTBT. - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtClearVgaRegisters ( - IN PEI_TBT_POLICY *PeiTbtConfig -) -{ - UINTN RpDev; - UINTN RpFunc; - EFI_STATUS Status; - UINT64 BridngeBaseAddress; - UINT16 Data16; - - DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n")); - - Status =3D EFI_SUCCESS; - - Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, Pei= TbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); - ASSERT_EFI_ERROR(Status); - // - // VGA Enable and VGA 16-bit decode registers of Bridge control register= of Root port where - // Host router resides should be cleaned - // - - BridngeBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, (UIN= T32)RpFunc, 0); - Data16 =3D PciSegmentRead16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGI= STER_OFFSET); - Data16 &=3D (~(EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_1= 6)); - PciSegmentWrite16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSE= T, Data16); - - DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n")); - return Status; -} - -/** - Exectue Mail box command "Boot On". - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtBootOn( - IN PEI_TBT_POLICY *PeiTbtConfig -) -{ - EFI_STATUS Status; - UINT32 OrgBusNumberConfiguration; - UINTN RpDev; - UINTN RpFunc; - - DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n")); - - Status =3D EFI_SUCCESS; - - Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); - ASSERT_EFI_ERROR(Status); - OrgBusNumberConfiguration =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDR= ESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); - // - // Set Sec/Sub buses to 0xF0 - // - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); - // - //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup we = need to do the below: - //Bios should send "Boot On" message through PCIE2TBT register - //The Boot On command as described above would include the command a= nd acknowledge from FW (with the default timeout in BIOS), - //once the Boot On command is completed it is guaranteed that the Al= pineRidge(AR) device is there and the PCI tunneling was done by FW, - //next step from BIOS is enumeration using SMI - // - - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { - // - // Exectue Mail box command "Boot On / Pre-Boot ACL" - // - //Command may be executed only during boot/reboot and not during S= x exit flow - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 1) { - if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, TBT_5S_= TIMEOUT)) { - // - // Nothing to wait, HR is not responsive - // - DEBUG((DEBUG_INFO, " DTbtBootOn - Boot On message sent= failed \n")); - } - } - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2) { - if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, TBT_= 3S_TIMEOUT)) { - // - // Nothing to wait, HR is not responsive - // - DEBUG((DEBUG_INFO, " DTbtBootOn - Pre-Boot ACL message= sent failed \n")); - } - } - } - // - // Reset Sec/Sub buses to original value - // - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); - - DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n")); - return Status; -} - -/** - Exectue Mail box command "USB On". - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtUsbOn( - IN PEI_TBT_POLICY *PeiTbtConfig -) -{ - EFI_STATUS Status; - UINTN RpDev; - UINTN RpFunc; - UINT32 OrgBusNumberConfiguration; - UINT64 TbtBaseAddress; - UINT32 MaxWaitIter; - UINT32 RegVal; - EFI_BOOT_MODE BootMode; - - DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n")); - - Status =3D EFI_SUCCESS; - - Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); - ASSERT_EFI_ERROR(Status); - OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE= SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); - // - // Set Sec/Sub buses to 0xF0 - // - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); - - // - //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setup = we need to do the below: - //Bios should send "Usb On" message through PCIE2TBT register - //The Usb On command as described above would include the command an= d acknowledge from FW (with the default timeout in BIOS), - //once the Usb On command is completed it is guaranteed that the Alp= ineRidge(AR) device is there and the PCI tunneling was done by FW, - //next step from BIOS is enumeration using SMI - // - if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) { - if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { - MaxWaitIter =3D 50; // Wait 5 sec - TbtBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0); - // - // Driver clears the PCIe2TBT Valid bit to support two consicuti= ve mailbox commands - // - PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0); - DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R =3D 0x%lx \= n", TbtBaseAddress + PCIE2TBT_DTBT_R)); - while (MaxWaitIter-- > 0) { - RegVal =3D PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R); - if (0xFFFFFFFF =3D=3D RegVal) { - // - // Device is not here return now - // - DEBUG((DEBUG_INFO, "TBT device is not present \n")); - break; - } - - if (!(RegVal & TBT2PCIE_DON_R)) { - break; - } - MicroSecondDelay(100 * 1000); - } - } - - Status =3D PeiServicesGetBootMode(&BootMode); - ASSERT_EFI_ERROR(Status); - - // - // Exectue Mail box command "Usb On" - // - //Command may be executed only during boot/reboot and not during S= 3 exit flow - //In case of S4 Exit send USB ON cmd only if Host Router was inact= ive/not present during S4 entry - if ((BootMode =3D=3D BOOT_ON_S4_RESUME) ) { - // USB_ON cmd not required - } else { - if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, TBT_5S_T= IMEOUT)) { - // - // Nothing to wait, HR is not responsive - // - DEBUG((DEBUG_INFO, " TbtBootSupport - Usb On message s= ent failed \n")); - } - } - } - // - // Reset Sec/Sub buses to original value - // - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); - - DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n")); - return Status; -} - -/** - Exectue Mail box command "Sx Exit". - - @param[in] PEI_TBT_POLICY PeiTbtConfig - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_UNSUPPORTED dTBT is not supported. -**/ -EFI_STATUS -EFIAPI -DTbtSxExitFlow( - IN PEI_TBT_POLICY *PeiTbtConfig -) -{ - EFI_STATUS Status; - UINT32 OrgBusNumberConfiguration; - UINTN RpDev; - UINTN RpFunc; - UINT32 Count; - - DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n")); - - Status =3D EFI_SUCCESS; - Count =3D 0; - - Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); - ASSERT_EFI_ERROR(Status); - OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE= SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); - // - // Set Sec/Sub buses to 0xF0 - // - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); - - if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2)) { - // - // WA: When system with TBT 3.1 device, resume SX system need to w= ait device ready. In document that maximum time out should be 500ms. - // - while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, 0x0,= 0x08)) =3D=3D 0xffffffff) { //End Device will be with Device Number 0x0, F= unction Number 0x0. - MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec - Count++; - if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S bo= ard. - break; - } - } - - // - // Upon wake, if BIOS saved pre-Sx Host Router state as active (sy= stem went to sleep with - // attached devices), BIOS should: - // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. - // 2. If procedure above returns true, BIOS should perform "wait f= or fast link bring-up" loop - // 3. Continue regular wake flow. - // - // - // Exectue Mail box command and perform "wait for fast link bring-= up" loop - // - TbtSetSxMode(0xF0, 0, 0, PeiTbtConfig->DTbtCommonConfig.TbtBootOn)= ; - } - // - // Reset Sec/Sub buses to original value - // - PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); - - DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n")); - return Status; -} - - -/** - Initialize Thunderbolt(TM) - - @retval EFI_SUCCESS The function completes successfully - @retval others -**/ -EFI_STATUS -EFIAPI -TbtInit ( - VOID - ) -{ - EFI_STATUS Status; - PEI_TBT_POLICY *PeiTbtConfig; - - // - // Get the TBT Policy - // - Status =3D PeiServicesLocatePpi ( - &gPeiTbtPolicyPpiGuid, - 0, - NULL, - (VOID **) &PeiTbtConfig - ); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); - } - ASSERT_EFI_ERROR (Status); - // - // Exectue Mail box command "Boot On" - // - Status =3D DTbtBootOn (PeiTbtConfig); - // - // Exectue Mail box command "Usb On" - // - Status =3D DTbtUsbOn (PeiTbtConfig); - // - //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register shou= ld be - //set to 11b - 10 ms (default value is 0b - 10 us) - // - Status =3D DTbtSetTPch25Timing (PeiTbtConfig); - // - // Configure Tbt Force Power - // - Status =3D DTbtForcePower (PeiTbtConfig); - // - // VGA Enable and VGA 16-bit decode registers of Bridge control register= of Root port where - // Host router resides should be cleaned - // - Status =3D DTbtClearVgaRegisters (PeiTbtConfig); - // - // Upon wake, if BIOS saved pre-Sx Host Router state as active (system w= ent to sleep with - // attached devices), BIOS should: - // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. - // 2. If procedure above returns true, BIOS should perform "wait for fas= t link bring-up" loop - // 3. Continue regular wake flow. - // - Status =3D DTbtSxExitFlow (PeiTbtConfig); - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtD= xe.c b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c deleted file mode 100644 index 5e8f80fa59..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c +++ /dev/null @@ -1,228 +0,0 @@ -/** @file - Thunderbolt initialization in DXE. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA_PROTOCOL mT= btNvsAreaProtocol; -GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *g= TbtInfoHob =3D NULL; - -/** - TBT NVS Area Initialize - -**/ - -VOID -TbtNvsAreaInit ( - IN VOID **mTbtNvsAreaPtr - ) -{ - UINTN Pages; - EFI_PHYSICAL_ADDRESS Address; - EFI_STATUS Status; - TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol; - DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; - - DEBUG ((DEBUG_INFO, "TbtNvsAreaInit Start\n")); - Status =3D gBS->LocateProtocol ( - &gDxeTbtPolicyProtocolGuid, - NULL, - (VOID **) &DxeTbtConfig - ); - ASSERT_EFI_ERROR (Status); - - Pages =3D EFI_SIZE_TO_PAGES (sizeof (TBT_NVS_AREA)); - Address =3D 0xffffffff; // allocate address below 4G. - - Status =3D gBS->AllocatePages ( - AllocateMaxAddress, - EfiACPIMemoryNVS, - Pages, - &Address - ); - ASSERT_EFI_ERROR (Status); - - *mTbtNvsAreaPtr =3D (VOID *) (UINTN) Address; - SetMem (*mTbtNvsAreaPtr, sizeof (TBT_NVS_AREA), 0); - - // - // TBTNvsAreaProtocol default value init here - // - TbtNvsAreaProtocol =3D (TBT_NVS_AREA_PROTOCOL *) &Address; - - // - // Initialize default values - // - TbtNvsAreaProtocol->Area->WAKFinished =3D 0; - TbtNvsAreaProtocol->Area->DiscreteTbtSupport =3D ((gTbtInfoHob-> DT= btControllerConfig.DTbtControllerEn =3D=3D 1 ) ? TRUE : FALSE); - TbtNvsAreaProtocol->Area->TbtAcpiRemovalSupport =3D 0; - TbtNvsAreaProtocol->Area->TbtGpioFilter =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Gpio5Filter; -// TbtNvsAreaProtocol->Area->TrOsup =3D (UINT8) DxeTbtCo= nfig->TbtCommonConfig.TrA0OsupWa; - TbtNvsAreaProtocol->Area->TbtFrcPwrEn =3D gTbtInfoHob->DTbtC= ommonConfig.Gpio3ForcePwr; - TbtNvsAreaProtocol->Area->TbtAspm =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtAspm; -// TbtNvsAreaProtocol->Area->TbtL1SubStates =3D (UINT8) DxeTbtCo= nfig->TbtCommonConfig.TbtL1SubStates; - TbtNvsAreaProtocol->Area->TbtSetClkReq =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtSetClkReq; - TbtNvsAreaProtocol->Area->TbtLtr =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtLtr; -// TbtNvsAreaProtocol->Area->TbtPtm =3D (UINT8) DxeTbtCo= nfig->TbtCommonConfig.TbtPtm; - TbtNvsAreaProtocol->Area->TbtWakeupSupport =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtWakeupSupport; - TbtNvsAreaProtocol->Area->TbtAcDcSwitch =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtAcDcSwitch; - TbtNvsAreaProtocol->Area->Rtd3TbtSupport =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Rtd3Tbt; // TBT RTD3 Enable. - TbtNvsAreaProtocol->Area->Rtd3TbtOffDelay =3D (UINT16) DxeTbtCon= fig->TbtCommonConfig.Rtd3TbtOffDelay; // TBT RTD3 Off delay in ms. - TbtNvsAreaProtocol->Area->Rtd3TbtClkReq =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Rtd3TbtClkReq; // TBT RTD3 ClkReq Mask Enable. - TbtNvsAreaProtocol->Area->Rtd3TbtClkReqDelay =3D (UINT16) DxeTbtCon= fig->TbtCommonConfig.Rtd3TbtClkReqDelay; // TBT RTD3 ClkReq mask delay in m= s. - TbtNvsAreaProtocol->Area->TbtWin10Support =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Win10Support; // TBT FW Execution Mode - - // - // DTBT Controller 1 - // - TbtNvsAreaProtocol->Area->DTbtControllerEn0 =3D gTbtInfoHob-> DTbt= ControllerConfig.DTbtControllerEn; - TbtNvsAreaProtocol->Area->RootportSelected0 =3D gTbtInfoHob-> DTbt= ControllerConfig.PcieRpNumber; - TbtNvsAreaProtocol->Area->RootportSelected0Type =3D gTbtInfoHob-> DTbt= ControllerConfig.Type; - TbtNvsAreaProtocol->Area->RootportEnabled0 =3D gTbtInfoHob-> DTbt= ControllerConfig.DTbtControllerEn; - TbtNvsAreaProtocol->Area->TbtFrcPwrGpioNo0 =3D gTbtInfoHob-> DTbt= ControllerConfig.ForcePwrGpio.GpioPad; - TbtNvsAreaProtocol->Area->TbtFrcPwrGpioLevel0 =3D gTbtInfoHob-> DTbt= ControllerConfig.ForcePwrGpio.GpioLevel; - TbtNvsAreaProtocol->Area->TbtCioPlugEventGpioNo0 =3D gTbtInfoHob-> DTbt= ControllerConfig.CioPlugEventGpio.GpioPad; - TbtNvsAreaProtocol->Area->TbtPcieRstGpioNo0 =3D gTbtInfoHob-> DTbt= ControllerConfig.PcieRstGpio.GpioPad; - TbtNvsAreaProtocol->Area->TbtPcieRstGpioLevel0 =3D gTbtInfoHob-> DTbt= ControllerConfig.PcieRstGpio.GpioLevel; - - TbtNvsAreaProtocol->Area->TBtCommonGpioSupport =3D gTbtInfoHob->DTbtC= ommonConfig.DTbtSharedGpioConfiguration; - - DEBUG ((DEBUG_INFO, "TbtNvsAreaInit End\n")); -} - -/** - This function gets registered as a callback to patch TBT ASL code - - @param[in] Event - A pointer to the Event that triggered the callbac= k. - @param[in] Context - A pointer to private data registered with the cal= lback function. - can we put this also in read me -**/ -VOID -EFIAPI -TbtAcpiEndOfDxeCallback ( - IN EFI_EVENT Event, - IN VOID *Context - ) -{ - EFI_STATUS Status; - UINT32 Address; - UINT16 Length; - UINT32 Signature; - - Status =3D InitializeAslUpdateLib (); - ASSERT_EFI_ERROR (Status); - - Address =3D (UINT32) (UINTN) mTbtNvsAreaProtocol.Area; - Length =3D (UINT16) sizeof (TBT_NVS_AREA); - DEBUG ((DEBUG_INFO, "Patch TBT NvsAreaAddress: TBT NVS Address %x Length= %x\n", Address, Length)); - Status =3D UpdateNameAslCode (SIGNATURE_32 ('T','N','V','B'), &Address,= sizeof (Address)); - ASSERT_EFI_ERROR (Status); - Status =3D UpdateNameAslCode (SIGNATURE_32 ('T','N','V','L'), &Length, = sizeof (Length)); - ASSERT_EFI_ERROR (Status); - - if (gTbtInfoHob !=3D NULL) { - if (gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn =3D=3D 1) { - if (gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSigna= turePorting =3D=3D TRUE) { - DEBUG ((DEBUG_INFO, "Patch ATBT Method Name\n")); - Signature =3D gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.= AcpiGpeSignature; - Status =3D UpdateNameAslCode (SIGNATURE_32 ('A','T','B','T'), &Si= gnature, sizeof (Signature)); - ASSERT_EFI_ERROR (Status); - } - } - } - - return; -} - -/** - Initialize Thunderbolt(TM) SSDT ACPI tables - - @retval EFI_SUCCESS ACPI tables are initialized successfully - @retval EFI_NOT_FOUND ACPI tables not found -**/ - -EFI_STATUS -EFIAPI -TbtDxeEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - EFI_HANDLE Handle; - // EFI_EVENT EndOfDxeEvent; - - DEBUG ((DEBUG_INFO, "TbtDxeEntryPoint \n")); - - // - // Get TBT INFO HOB - // - gTbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid); - if (gTbtInfoHob =3D=3D NULL) { - return EFI_NOT_FOUND; - } - InstallTbtPolicy (ImageHandle); - // - // Update DXE TBT Policy - // - UpdateTbtPolicyCallback (); - - // - // Print DXE TBT Policy - // - TbtPrintDxePolicyConfig (); - - // - // Initialize Tbt Nvs Area - // - TbtNvsAreaInit ((VOID **) &mTbtNvsAreaProtocol.Area); - - - // - // [ACPI] Thunderbolt ACPI table - // - - - Handle =3D NULL; - - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gTbtNvsAreaProtocolGuid, - &mTbtNvsAreaProtocol, - NULL - ); - ASSERT_EFI_ERROR (Status); - - // - // Register an end of DXE event for TBT ACPI to do some patch can be put= as description - // - /** - Status =3D gBS->CreateEventEx ( - EVT_NOTIFY_SIGNAL, - TPL_CALLBACK, - TbtAcpiEndOfDxeCallback, - NULL, - &gEfiEndOfDxeEventGroupGuid, - &EndOfDxeEvent - ); - ASSERT_EFI_ERROR (Status); -**/ - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiT= btInit.c b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbt= Init.c deleted file mode 100644 index a824886697..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit.= c +++ /dev/null @@ -1,193 +0,0 @@ -/** @file - Thunderbolt initialization in PEI. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - This function pass PEI TBT Policy to Hob at the end of PEI - - @param[in] PeiServices Pointer to PEI Services Table. - @param[in] NotifyDesc Pointer to the descriptor for the Notification = event that - caused this function to execute. - @param[in] Ppi Pointer to the PPI data associated with this fu= nction. - - @retval EFI_SUCCESS The function completes successfully - @retval others -**/ -EFI_STATUS -EFIAPI -PassTbtPolicyToHob ( -VOID - ) -{ - EFI_STATUS Status; - EFI_BOOT_MODE BootMode; - TBT_INFO_HOB *TbtInfoHob; - PEI_TBT_POLICY *PeiTbtConfig; - - DEBUG ((DEBUG_INFO, "PassTbtPolicyToHob\n")); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - if (BootMode =3D=3D BOOT_ON_S3_RESUME ) { - return EFI_SUCCESS; - } - - Status =3D PeiServicesLocatePpi ( - &gPeiTbtPolicyPpiGuid, - 0, - NULL, - (VOID **) &PeiTbtConfig - ); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); - } - ASSERT_EFI_ERROR (Status); - - // - // Create HOB for TBT Data - // - Status =3D PeiServicesCreateHob ( - EFI_HOB_TYPE_GUID_EXTENSION, - sizeof (TBT_INFO_HOB), - (VOID **) &TbtInfoHob - ); - DEBUG ((DEBUG_INFO, "TbtInfoHob Created \n")); - ASSERT_EFI_ERROR (Status); - - // - // Initialize the TBT INFO HOB data. - // - TbtInfoHob->EfiHobGuidType.Name =3D gTbtInfoHobGuid; - - // - // Update DTBT Policy - // - TbtInfoHob-> DTbtControllerConfig.DTbtControllerEn =3D PeiTbtConfig-> DT= btControllerConfig.DTbtControllerEn; - TbtInfoHob-> DTbtControllerConfig.Type =3D PeiTbtConfig-> DTbtController= Config.Type; - TbtInfoHob-> DTbtControllerConfig.PcieRpNumber =3D PeiTbtConfig-> DTbtCo= ntrollerConfig.PcieRpNumber; - TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioPad =3D PeiTbtConfig-= > DTbtControllerConfig.ForcePwrGpio.GpioPad; - TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioLevel =3D PeiTbtConfi= g-> DTbtControllerConfig.ForcePwrGpio.GpioLevel; - TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D PeiTbtCon= fig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad; - TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =3D = PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature; - TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorti= ng =3D PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignatur= ePorting; - TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioPad =3D PeiTbtConfig->= DTbtControllerConfig.PcieRstGpio.GpioPad; - TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioLevel =3D PeiTbtConfig= -> DTbtControllerConfig.PcieRstGpio.GpioLevel; - - TbtInfoHob->DTbtCommonConfig.TbtBootOn =3D PeiTbtConfig->DTbtCommonConfi= g.TbtBootOn; - TbtInfoHob->DTbtCommonConfig.TbtUsbOn =3D PeiTbtConfig->DTbtCommonConfig= .TbtUsbOn; - TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwr =3D PeiTbtConfig->DTbtCommonC= onfig.Gpio3ForcePwr; - TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwrDly =3D PeiTbtConfig->DTbtComm= onConfig.Gpio3ForcePwrDly; - TbtInfoHob->DTbtCommonConfig.DTbtSharedGpioConfiguration =3D PeiTbtConfi= g->DTbtCommonConfig.DTbtSharedGpioConfiguration; - TbtInfoHob->DTbtCommonConfig.PcieRstSupport =3D PeiTbtConfig->DTbtCommon= Config.PcieRstSupport; - - return EFI_SUCCESS; -} - -/** - This function handles TbtInit task at the end of PEI - - @param[in] PeiServices Pointer to PEI Services Table. - @param[in] NotifyDesc Pointer to the descriptor for the Notification = event that - caused this function to execute. - @param[in] Ppi Pointer to the PPI data associated with this fu= nction. - - @retval EFI_SUCCESS The function completes successfully - @retval others -**/ -EFI_STATUS -EFIAPI -TbtInitEndOfPei ( - VOID - ) -{ - EFI_STATUS Status; - BOOLEAN DTbtExisted; - PEI_TBT_POLICY *PeiTbtConfig; - - DEBUG ((DEBUG_INFO, "TbtInitEndOfPei Entry\n")); - - Status =3D EFI_SUCCESS; - PeiTbtConfig =3D NULL; - DTbtExisted =3D FALSE; - - Status =3D PeiServicesLocatePpi ( - &gPeiTbtPolicyPpiGuid, - 0, - NULL, - (VOID **) &PeiTbtConfig - ); - if (EFI_ERROR(Status)) { - DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); - } - ASSERT_EFI_ERROR (Status); - - if (PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D=3D 1) { - DTbtExisted =3D TRUE; - } - - if (DTbtExisted =3D=3D TRUE) { - // - // Call Init function - // - Status =3D TbtInit (); - } - - return EFI_SUCCESS; -} - -/** - TBT Init PEI module entry point - - @param[in] FileHandle Not used. - @param[in] PeiServices General purpose services available to e= very PEIM. - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se -**/ -EFI_STATUS -EFIAPI -TbtInitEntryPoint ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "TBT PEI EntryPoint\n")); - - // - // Install PEI TBT Policy - // - Status =3D InstallPeiTbtPolicy (); - ASSERT_EFI_ERROR (Status); - - - UpdatePeiTbtPolicy (); - - TbtPrintPeiPolicyConfig (); - // - // Performing PassTbtPolicyToHob and TbtInitEndOfPei - // - Status =3D PassTbtPolicyToHob (); - - Status =3D TbtInitEndOfPei (); - - return Status; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS= miHandler.c b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tbt= SmiHandler.c deleted file mode 100644 index 216a7b155c..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHandl= er.c +++ /dev/null @@ -1,1610 +0,0 @@ -/**@file - Thunderbolt SMI handler. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "TbtSmiHandler.h" -#include -#include -#include -#include -#include -#include -#include -#define MEM_PER_SLOT (DEF_RES_MEM_PER_DEV << 4) -#define PMEM_PER_SLOT (DEF_RES_PMEM_PER_DEV << 4) -#define IO_PER_SLOT (DEF_RES_IO_PER_DEV << 2) - -GLOBAL_REMOVE_IF_UNREFERENCED UINTN gDeviceBaseAddress; -// -//US(X:0:0), DS(X+1:3:0),DS(X+1:4:0),DS(X+1:5:0),DS(X+1:6:0) -// -GLOBAL_REMOVE_IF_UNREFERENCED BRDG_CONFIG HrConfigs[MAX_CFG_PORT= S]; - -extern UINT8 gCurrentDiscreteTbtRootPort; -extern UINT8 gCurrentDiscreteTbtRootPortType; - -BOOLEAN isLegacyDevice =3D FALSE; -STATIC UINT8 TbtSegment =3D 0; - -STATIC -VOID -PortInfoInit ( - IN OUT PORT_INFO *PortInfo - ) -{ - PortInfo->BusNumLimit =3D 4; -} - -STATIC -VOID -UnsetVesc ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun - ) -{ - UINT8 Dbus; - UINT32 Data32; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fu= n, 0); - - // - // Check for abcence of DS bridge - // - if(0xFFFF =3D=3D PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFF= SET)) { - return; - } - - // - // Unset vesc_reg2[23] bit (to have an option to access below DS) - // - Data32 =3D PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2); - Data32 &=3D 0xFF7FFFFF; - PciSegmentWrite32(gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32); - // - // Go to Device behind DS - // - Dbus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_= REGISTER_OFFSET); - DEBUG((DEBUG_INFO, "Dbus =3D %d\n",Dbus)); - // - // Check if there is something behind this Downstream Port (Up or Ep) - // If there nothing behind Downstream Port Set vesc_reg2[23] bit -> thi= s will flush all future MemWr - // - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus, 0x00, = 0x00, 0); - if(0xFFFF =3D=3D PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFF= SET)) - { - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fu= n, 0); - Data32 =3D PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2); - Data32 |=3D 0x00800000; - PciSegmentWrite32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32); - } -}// Unset_VESC_REG2 - -STATIC -UINT16 -MemPerSlot ( - IN UINT16 CurrentUsage - ) -{ - if (CurrentUsage =3D=3D 0) { - return 0; - } - - if (CurrentUsage <=3D 16) { - return 16; - } - - if (CurrentUsage <=3D 64) { - return 64; - } - - if (CurrentUsage <=3D 128) { - return 128; - } - - if (CurrentUsage <=3D 256) { - return 256; - } - - if (CurrentUsage <=3D 512) { - return 512; - } - - if (CurrentUsage <=3D 1024) { - return 1024; - } - - return CurrentUsage; -} // MemPerSlot - -STATIC -UINT64 -PMemPerSlot ( - IN UINT64 CurrentUsage - ) -{ - if (CurrentUsage =3D=3D 0) { - return 0; - } - - if (CurrentUsage <=3D 1024ULL) { - return 1024ULL; - } - - if (CurrentUsage <=3D 4096ULL) { - return 4096ULL; - } - - return CurrentUsage; -} // PMemPerSlot - -STATIC -VOID -SetPhyPortResources ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 SubBus, - IN INT8 Depth, - IN PORT_INFO *CurrentPi, - IN OUT PORT_INFO *PortInfo - ) -{ - UINT8 Cmd; - UINT16 DeltaMem; - UINT64 DeltaPMem; - - Cmd =3D CMD_BUS_MASTER; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0x= 00, 0); - - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIST= ER_OFFSET, SubBus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); - - DeltaMem =3D PortInfo->MemBase - CurrentPi->MemBase; - if (isLegacyDevice) { - if (Depth >=3D 0 && (DeltaMem < MEM_PER_SLOT)) { - PortInfo->MemBase +=3D MEM_PER_SLOT - DeltaMem; - } - } else { - if (DeltaMem < MemPerSlot (DeltaMem)) { - PortInfo->MemBase +=3D MemPerSlot (DeltaMem) - DeltaMem; - } - } - - if (PortInfo->MemBase > CurrentPi->MemBase && (PortInfo->MemBase - 0x10)= <=3D PortInfo->MemLimit) { - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), CurrentPi->MemBase); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryLimit), PortInfo->MemBase - 0x10); - Cmd |=3D CMD_BM_MEM; - } else { - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), DISBL_MEM32_REG20); - PortInfo->MemBase =3D CurrentPi->MemBase; - } - - DeltaPMem =3D PortInfo->PMemBase64 - CurrentPi->PMemBase64; - if (isLegacyDevice) { - if ((Depth >=3D 0) && ((UINTN)DeltaPMem < (UINTN)PMEM_PER_SLOT)) { - PortInfo->PMemBase64 +=3D PMEM_PER_SLOT - DeltaPMem; - } - } else { - if (DeltaPMem < PMemPerSlot (DeltaPMem)) { - PortInfo->PMemBase64 +=3D PMemPerSlot (DeltaPMem) - DeltaPMem; - } - } - - if (PortInfo->PMemBase64 > CurrentPi->PMemBase64 && (PortInfo->PMemBase6= 4 - 0x10) <=3D PortInfo->PMemLimit64) { - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), (UINT16) (CurrentPi->PMemBase64 & 0xFFFF)); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryLimit), (UINT16) ((PortInfo->PMemBase64 - 0x10) & 0xFFFF)= ); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), (UINT32) (CurrentPi->PMemBase64 >> 16)); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), (UINT32) ((PortInfo->PMemBase64 - 0x10) >> 16)); - Cmd |=3D CMD_BM_MEM; - } else { - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), DISBL_PMEM_REG24); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), 0); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), 0); - PortInfo->PMemBase64 =3D CurrentPi->PMemBase64; - } - - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA= CHE_LINE_SIZE); -} // SetPhyPortResources - -STATIC -UINT32 -SaveSetGetRestoreBar ( - IN UINTN Bar - ) -{ - UINT32 BarReq; - UINT32 OrigBar; - - OrigBar =3D PciSegmentRead32(Bar); // Save BAR - PciSegmentWrite32(Bar, 0xFFFFFFFF); // Set BAR - BarReq =3D PciSegmentRead32(Bar); // Get BAR - PciSegmentWrite32(Bar, OrigBar); // Restore BAR - - return BarReq; -} // SaveSetGetRestoreBar - -STATIC -VOID -SetIoBar ( - IN UINTN BAR, - IN UINT32 BarReq, - IN OUT UINT8 *Cmd, - IN OUT IO_REGS *IoReg - ) -{ - UINT16 Alignment; - UINT16 Size; - UINT16 NewBase; - - Alignment =3D ~(BarReq & 0xFFFC); - Size =3D Alignment + 1; - - if (IoReg->Base > IoReg->Limit || !Size) { - return ; - - } - - NewBase =3D BAR_ALIGN (IoReg->Base, Alignment); - if (NewBase > IoReg->Limit || NewBase + Size - 1 > IoReg->Limit) { - return ; - - } - PciSegmentWrite16(BAR, NewBase); - IoReg->Base =3D NewBase + Size; // Advance to new position - *Cmd |=3D CMD_BM_IO; // Set Io Space Enable -} // SetIoBar - -STATIC -VOID -SetMemBar ( - IN UINTN BAR, - IN UINT32 BarReq, - IN OUT UINT8 *Cmd, - IN OUT MEM_REGS *MemReg - ) -{ - UINT32 Alignment; - UINT32 Size; - UINT32 NewBase; - - Alignment =3D ~(BarReq & 0xFFFFFFF0); - Size =3D Alignment + 1; - - if (MemReg->Base > MemReg->Limit || !Size) { - return ; - - } - - NewBase =3D BAR_ALIGN (MemReg->Base, Alignment); - if (NewBase > MemReg->Limit || NewBase + Size - 1 > MemReg->Limit) { - return ; - - } - - PciSegmentWrite32(BAR, NewBase); - MemReg->Base =3D NewBase + Size; // Advance to new position - *Cmd |=3D CMD_BM_MEM; // Set Memory Space Enable -} // SetMemBar - -STATIC -VOID -SetPMem64Bar ( - IN UINTN BAR, - IN BOOLEAN IsMaxBar, - IN UINT32 BarReq, - IN OUT UINT8 *Cmd, - IN OUT PMEM_REGS *MemReg - ) -{ - UINT32 Alignment; - UINT32 Size; - UINT64 NewBase; - - Alignment =3D ~(BarReq & 0xFFFFFFF0); - Size =3D Alignment + 1; - - if (MemReg->Base64 > MemReg->Limit64 || !Size) { - return ; - } - - NewBase =3D BAR_ALIGN (MemReg->Base64, Alignment); - if (NewBase > MemReg->Limit64 || NewBase + Size - 1 > MemReg->Limit64) { - return ; - } - PciSegmentWrite32(BAR, (UINT32)(NewBase & 0xFFFFFFFF)); - if (!IsMaxBar) { - BAR++; - PciSegmentWrite32(BAR, (UINT32)(NewBase >> 32)); - } - MemReg->Base64 =3D NewBase + Size; // Advance to new position - *Cmd |=3D CMD_BM_MEM; // Set Memory Space Enable -} // SetPMem64Bar - -STATIC -VOID -SetDevResources ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 MaxFun, // PCI_MAX_FUNC for devices, 1 for bridge - IN UINT8 MaxBar, // PCI_BAR5 for devices, PCI_BAR1 for br= idge - IN OUT PORT_INFO *PortInfo - ) -{ - UINT8 Fun; - UINT8 Reg; - UINT32 BarReq; - IO_REGS Io; - MEM_REGS Mem; - PMEM_REGS PMem; - UINT8 Cmd; - - Io.Base =3D PortInfo->IoBase << 8; - Io.Limit =3D (PortInfo->IoLimit << 8) | 0xFF; - Mem.Base =3D PortInfo->MemBase << 16; - Mem.Limit =3D (PortInfo->MemLimit << 16) | 0xFFFF; - PMem.Base64 =3D PortInfo->PMemBase64 << 16; - PMem.Limit64 =3D (PortInfo->PMemLimit64 << 16) | 0xFFFF; - - for (Fun =3D 0; Fun < MaxFun; ++Fun) { - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, = Fun, 0); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MAS= TER); - Cmd =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET); - if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID= _OFFSET)) { - continue; - - } - - for (Reg =3D PCI_BASE_ADDRESSREG_OFFSET; Reg <=3D MaxBar; Reg +=3D 4) = { - BarReq =3D SaveSetGetRestoreBar(gDeviceBaseAddress + Reg); // Perfor= m BAR sizing - - if (BarReq & BIT0) { - // - // I/O BAR - // - SetIoBar ( - (gDeviceBaseAddress + Reg), - BarReq, - &Cmd, - &Io - ); - continue; - } - - if (BarReq & BIT3) { - // - // P-Memory BAR - // - SetPMem64Bar ((gDeviceBaseAddress + Reg), MaxBar =3D=3D Reg, BarRe= q, &Cmd, &PMem); - } else { - SetMemBar ((gDeviceBaseAddress + Reg), BarReq, &Cmd, &Mem); - } - - if (BIT2 =3D=3D (BarReq & (BIT2 | BIT1))) { - // - // Base address is 64 bits wide - // - Reg +=3D 4; - if (!(BarReq & BIT3)) { - // - // 64-bit memory bar - // - PciSegmentWrite32 (gDeviceBaseAddress + Reg, 0); - } - } - } - - if (Cmd & BIT1) { - // - // If device uses I/O and MEM mapping use only MEM mepping - // - Cmd &=3D ~BIT0; - } - - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_= CACHE_LINE_SIZE); - } - // - // Update PortInfo if any changes - // - if (Io.Base > ((UINT32) PortInfo->IoBase << 8)) { - PortInfo->IoBase =3D (UINT8) (BAR_ALIGN (Io.Base, 0xFFF) >> 8); - } - - if (Mem.Base > ((UINT32) PortInfo->MemBase << 16)) { - PortInfo->MemBase =3D (UINT16) (BAR_ALIGN (Mem.Base, 0xFFFFF) >> 16); - } - - if (PMem.Base64 > (PortInfo->PMemBase64 << 16)) { - PortInfo->PMemBase64 =3D (BAR_ALIGN (PMem.Base64, 0xFFFFF) >> 16); - } -} // SetDevResources - -STATIC -VOID -InitARHRConfigs( - IN HR_CONFIG *Hr_Config, - IN UINT8 BusNumLimit, - IN OUT BRDG_RES_CONFIG* HrResConf -) -{ - UINT8 i,j; - - // - // DS port for USB device - // - HrConfigs[AR_DS_PORT2].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1= ; - HrConfigs[AR_DS_PORT2].DevId.Dev =3D 2; - HrConfigs[AR_DS_PORT2].DevId.Fun =3D 0; - HrConfigs[AR_DS_PORT2].PBus =3D HrConfigs[AR_DS_PORT2].DevId.Bus; - HrConfigs[AR_DS_PORT2].SBus =3D HrConfigs[AR_DS_PORT2].PBus + 1; - HrConfigs[AR_DS_PORT2].SubBus =3D HrConfigs[AR_DS_PORT2].PBus + 1; - // - // CIO port - // - HrConfigs[AR_DS_PORT1].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1= ; - HrConfigs[AR_DS_PORT1].DevId.Dev =3D 1; - HrConfigs[AR_DS_PORT1].DevId.Fun =3D 0; - HrConfigs[AR_DS_PORT1].PBus =3D HrConfigs[AR_DS_PORT1].DevId.Bus; - HrConfigs[AR_DS_PORT1].SBus =3D HrConfigs[HR_DS_PORT0].SubBus + 1; - HrConfigs[AR_DS_PORT1].SubBus =3D BusNumLimit; - - switch(Hr_Config->DeviceId) - { - // - // HR with 1 DS and 1 USB - // - case AR_HR_2C: - case AR_HR_LP: - case AR_HR_C0_2C: - case TR_HR_2C: - Hr_Config->MinDSNumber =3D HrConfigs[AR_DS_PORT1].DevId.Dev; - Hr_Config->MaxDSNumber =3D HrConfigs[AR_DS_PORT2].DevId.Dev; - Hr_Config->BridgeLoops =3D 4; - break; - // - // HR with 2 DS and 1 USB - // - case AR_HR_4C: - case TR_HR_4C: - case AR_HR_C0_4C: - Hr_Config->MinDSNumber =3D 1; - Hr_Config->MaxDSNumber =3D 4; - Hr_Config->BridgeLoops =3D 6; - for(j =3D 2, i =3D Hr_Config->MinDSNumber; j < count(HrConfigs) && i= <=3D Hr_Config->MaxDSNumber; ++j, ++i) - { - HrConfigs[j].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1; - HrConfigs[j].DevId.Dev =3D i; - HrConfigs[j].DevId.Fun =3D 0; - HrConfigs[j].PBus =3D HrConfigs[j].DevId.Bus; - HrConfigs[j].Res.Cls =3D DEF_CACHE_LINE_SIZE; - } - break; - } -}//InitARHRConfigs - - -STATIC -VOID -InitCommonHRConfigs ( - IN HR_CONFIG *Hr_Config, - IN UINT8 BusNumLimit, - IN OUT BRDG_RES_CONFIG *HrResConf - ) -{ - UINT8 i; - - UINT8 j; - for(i =3D 0; i < count(HrConfigs); ++i) { - HrConfigs[i].IsDSBridge =3D TRUE; - } - // - // US(HRBus:0:0) - // - HrConfigs[HR_US_PORT].DevId.Bus =3D Hr_Config->HRBus; - HrConfigs[HR_US_PORT].DevId.Dev =3D 0; - HrConfigs[HR_US_PORT].DevId.Fun =3D 0; - HrConfigs[HR_US_PORT].Res =3D *HrResConf; - HrConfigs[HR_US_PORT].Res.IoBase =3D 0xF1; - HrConfigs[HR_US_PORT].Res.IoLimit =3D 0x01; - HrConfigs[HR_US_PORT].PBus =3D HrConfigs[HR_US_PORT].DevId.Bus; - HrConfigs[HR_US_PORT].SBus =3D HrConfigs[HR_US_PORT].PBus + 1; - HrConfigs[HR_US_PORT].SubBus =3D BusNumLimit; - HrConfigs[HR_US_PORT].IsDSBridge =3D FALSE; - - // - // HIA resides here - // - HrConfigs[HR_DS_PORT0].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus = + 1; - HrConfigs[HR_DS_PORT0].DevId.Dev =3D 0; - HrConfigs[HR_DS_PORT0].DevId.Fun =3D 0; - HrConfigs[HR_DS_PORT0].Res =3D NOT_IN_USE_BRIDGE; - HrConfigs[HR_DS_PORT0].Res.MemBase =3D HrResConf->MemLimit; - HrConfigs[HR_DS_PORT0].Res.MemLimit =3D HrResConf->MemLimit; - HrResConf->MemLimit -=3D 0x10; //This 1 MB chunk will be = used by HIA - HrConfigs[HR_DS_PORT0].Res.Cmd =3D CMD_BM_MEM; - HrConfigs[HR_DS_PORT0].Res.Cls =3D DEF_CACHE_LINE_SIZE; - HrConfigs[HR_DS_PORT0].PBus =3D HrConfigs[HR_DS_PORT0].DevId.Bus= ; - HrConfigs[HR_DS_PORT0].SBus =3D HrConfigs[HR_DS_PORT0].PBus + 1; - HrConfigs[HR_DS_PORT0].SubBus =3D HrConfigs[HR_DS_PORT0].PBus + 1; - - switch (Hr_Config->DeviceId) { - // - // Alpine Ridge - // - case AR_HR_2C: - case AR_HR_C0_2C: - case AR_HR_LP: - case AR_HR_4C: - case AR_HR_C0_4C: - // - // Titan Ridge - // - case TR_HR_2C: - case TR_HR_4C: - InitARHRConfigs(Hr_Config, BusNumLimit, HrResConf); - break; - - default: - // - // DS(HRBus+2:3-6:0) - // - Hr_Config->MinDSNumber =3D 3; - Hr_Config->MaxDSNumber =3D 6; - Hr_Config->BridgeLoops =3D count (HrConfigs); - - for (j =3D 2, i =3D Hr_Config->MinDSNumber; j < count (HrConfigs) && i= <=3D Hr_Config->MaxDSNumber; ++j, ++i) { - HrConfigs[j].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1; - HrConfigs[j].DevId.Dev =3D i; - HrConfigs[j].DevId.Fun =3D 0; - HrConfigs[j].PBus =3D HrConfigs[j].DevId.Bus; - HrConfigs[j].Res.Cls =3D DEF_CACHE_LINE_SIZE; - } - } -} // InitCommonHRConfigs - -STATIC -VOID -InitHRDSPort_Disable ( - IN UINT8 id, - IN OUT BRDG_CONFIG *BrdgConf - ) -{ - HrConfigs[id].Res =3D NOT_IN_USE_BRIDGE; - HrConfigs[id].SBus =3D BrdgConf->SBus; - HrConfigs[id].SubBus =3D BrdgConf->SBus; - - BrdgConf->SBus++; -} // InitHRDSPort_Disable - -//AR only - -STATIC -VOID -InitARDSPort_1Port( - IN OUT BRDG_CONFIG* BrdgConf -) -{ - UINT16 MemBase =3D BrdgConf->Res.MemBase & 0xFFF0; - UINT64 PMemBase64 =3D BrdgConf->Res.PMemBase64 & ~0xFULL; - UINT8 BusRange =3D BrdgConf->SubBus - BrdgConf->PBus - 2; - - HrConfigs[AR_DS_PORT1].Res =3D NOT_IN_USE_BRIDGE; - HrConfigs[AR_DS_PORT1].Res.Cls =3D DEF_CACHE_LINE_SIZE; - HrConfigs[AR_DS_PORT1].Res.Cmd =3D CMD_BM_MEM; - HrConfigs[AR_DS_PORT1].Res.MemBase =3D MemBase; - HrConfigs[AR_DS_PORT1].Res.MemLimit =3D BrdgConf->Res.MemLimit - 1; - HrConfigs[AR_DS_PORT1].Res.PMemBase64 =3D PMemBase64; - HrConfigs[AR_DS_PORT1].Res.PMemLimit64 =3D BrdgConf->Res.PMemLimit64; - HrConfigs[AR_DS_PORT1].SBus =3D BrdgConf->SBus; - HrConfigs[AR_DS_PORT1].SubBus =3D BrdgConf->SBus + BusRange; - - BrdgConf->SBus =3D HrConfigs[AR_DS_PORT1].SubBus + 1; - - HrConfigs[AR_DS_PORT2].Res =3D NOT_IN_USE_BRIDGE; - HrConfigs[AR_DS_PORT2].Res.Cls =3D DEF_CACHE_LINE_SIZE; - HrConfigs[AR_DS_PORT2].Res.Cmd =3D CMD_BM_MEM; - HrConfigs[AR_DS_PORT2].Res.MemBase =3D BrdgConf->Res.MemLimit; - HrConfigs[AR_DS_PORT2].Res.MemLimit =3D BrdgConf->Res.MemLimit; - HrConfigs[AR_DS_PORT2].SBus =3D BrdgConf->SBus; - HrConfigs[AR_DS_PORT2].SubBus =3D BrdgConf->SBus; - - BrdgConf->SBus =3D HrConfigs[AR_DS_PORT2].SubBus + 1; -}//InitARDSPort_1Port - -STATIC -VOID -InitARDSPort_2Port( - IN OUT BRDG_CONFIG* BrdgConf -) -{ - UINT16 MemBase =3D BrdgConf->Res.MemBase & 0xFFF0; - UINT64 PMemBase64 =3D BrdgConf->Res.PMemBase64 & ~0xFULL; - UINT8 BusRange =3D BrdgConf->SubBus - BrdgConf->PBus - 3; - - // Busses are split between ports 1 and 4 - BusRange /=3D 2; - - HrConfigs[AR_DS_PORT1].Res =3D NOT_IN_USE_BRIDGE; - HrConfigs[AR_DS_PORT1].Res.Cls =3D DEF_CACHE_LINE_SIZE; - HrConfigs[AR_DS_PORT1].Res.Cmd =3D CMD_BM_MEM; - HrConfigs[AR_DS_PORT1].Res.MemBase =3D MemBase; - HrConfigs[AR_DS_PORT1].Res.MemLimit =3D MemBase + 0x17F0 - 1; - HrConfigs[AR_DS_PORT1].Res.PMemBase64 =3D PMemBase64; - HrConfigs[AR_DS_PORT1].Res.PMemLimit64 =3D PMemBase64 + 0x2000 - 1; - HrConfigs[AR_DS_PORT1].SBus =3D BrdgConf->SBus; - HrConfigs[AR_DS_PORT1].SubBus =3D BrdgConf->SBus + BusRange; - - BrdgConf->SBus =3D HrConfigs[AR_DS_PORT1].SubBus + 1; - - HrConfigs[AR_DS_PORT2].Res =3D NOT_IN_USE_BRIDGE; - HrConfigs[AR_DS_PORT2].Res.Cls =3D DEF_CACHE_LINE_SIZE; - HrConfigs[AR_DS_PORT2].Res.Cmd =3D CMD_BM_MEM; - HrConfigs[AR_DS_PORT2].Res.MemBase =3D MemBase + 0x17F0; - HrConfigs[AR_DS_PORT2].Res.MemLimit =3D MemBase + 0x1800 - 1; - HrConfigs[AR_DS_PORT2].SBus =3D BrdgConf->SBus; - HrConfigs[AR_DS_PORT2].SubBus =3D BrdgConf->SBus; - - BrdgConf->SBus =3D HrConfigs[AR_DS_PORT2].SubBus + 1; - - - HrConfigs[AR_DS_PORT4].Res =3D NOT_IN_USE_BRIDGE; - HrConfigs[AR_DS_PORT4].Res.Cls =3D DEF_CACHE_LINE_SIZE; - HrConfigs[AR_DS_PORT4].Res.Cmd =3D CMD_BM_MEM; - HrConfigs[AR_DS_PORT4].Res.MemBase =3D MemBase + 0x1800; - HrConfigs[AR_DS_PORT4].Res.MemLimit =3D BrdgConf->Res.MemLimit; - HrConfigs[AR_DS_PORT4].Res.PMemBase64 =3D PMemBase64 + 0x2000; - HrConfigs[AR_DS_PORT4].Res.PMemLimit64 =3D BrdgConf->Res.PMemLimit64; - HrConfigs[AR_DS_PORT4].SBus =3D BrdgConf->SBus; - HrConfigs[AR_DS_PORT4].SubBus =3D BrdgConf->SubBus; - - BrdgConf->SBus =3D HrConfigs[AR_DS_PORT4].SubBus + 1; -}//InitARDSPort_2Port - - -STATIC -BOOLEAN -CheckLimits ( - IN BOOLEAN Is2PortDev, - IN BRDG_RES_CONFIG *HrResConf, - IN UINT8 BusRange - ) -{ - UINT16 MemBase; - UINT16 MemLimit; - UINT64 PMemBase64; - UINT64 PMemLimit64; - - MemBase =3D HrResConf->MemBase & 0xFFF0; - MemLimit =3D HrResConf->MemLimit & 0xFFF0; - PMemBase64 =3D HrResConf->PMemBase64 & 0xFFF0; - PMemLimit64 =3D HrResConf->PMemLimit64 & 0xFFF0; - // - // Check memoty alignment - // - if (MemBase & 0x3FF) { - DEBUG((DEBUG_INFO, "M alig\n")); - return FALSE; - } - - if (PMemBase64 & 0xFFF) { - DEBUG((DEBUG_INFO, "PM alig\n")); - return FALSE; - } - - if (Is2PortDev) { - // - // Check mem size - // - if (MemLimit + 0x10 - MemBase < 0x2E00) { - DEBUG((DEBUG_INFO, "M size\n")); - return FALSE; - } - // - // Check P-mem size - // - if (PMemLimit64 + 0x10 - PMemBase64 < 0x4A00) { - DEBUG((DEBUG_INFO, "PM size\n")); - return FALSE; - } - // - // Check bus range - // - if (BusRange < 106) { - DEBUG((DEBUG_INFO, "Bus range\n")); - return FALSE; - } - } else { - // - // Check mem size - // - if (MemLimit + 0x10 - MemBase < 0x1600) { - DEBUG((DEBUG_INFO, "M size\n")); - return FALSE; - } - // - // Check P-mem size - // - if (PMemLimit64 + 0x10 - PMemBase64 < 0x2200) { - DEBUG((DEBUG_INFO, "PM size\n")); - return FALSE; - } - // - // Check bus range - // - if (BusRange < 56) { - DEBUG((DEBUG_INFO, "Bus range\n")); - return FALSE; - } - } - - return TRUE; -} // CheckLimits - -STATIC -BOOLEAN -InitHRResConfigs ( - IN OUT HR_CONFIG *Hr_Config, - IN UINT8 BusNumLimit, - IN OUT BRDG_RES_CONFIG*HrResConf - ) -{ - BRDG_CONFIG BrdgConf =3D { { 0 } }; - - InitCommonHRConfigs (Hr_Config, BusNumLimit, HrResConf); - BrdgConf.PBus =3D Hr_Config->HRBus + 2;// Take into account busses - BrdgConf.SBus =3D Hr_Config->HRBus + 3;// for US and DS of HIA - BrdgConf.SubBus =3D BusNumLimit; - BrdgConf.Res =3D *HrResConf; - while (TRUE) { - switch (Hr_Config->DeviceId) { - case AR_HR_4C: - case TR_HR_4C: - case AR_HR_C0_4C: - // - // 2 Port host - // - if (CheckLimits (TRUE, HrResConf, BusNumLimit - Hr_Config->HRBus)) { - - - InitARDSPort_2Port(&BrdgConf); - DEBUG((DEBUG_INFO, "AR2\n")); - - return TRUE; - } else { - return FALSE; - } - // AR only - case AR_HR_2C: // 1 port host - case AR_HR_C0_2C: - case AR_HR_LP: - case TR_HR_2C: - DEBUG((DEBUG_INFO, "AR1\n")); - InitARDSPort_1Port(&BrdgConf); - return TRUE; - - default: - InitHRDSPort_Disable (HR_DS_PORT3, &BrdgConf); - InitHRDSPort_Disable (HR_DS_PORT4, &BrdgConf); - InitHRDSPort_Disable (HR_DS_PORT5, &BrdgConf); - InitHRDSPort_Disable (HR_DS_PORT6, &BrdgConf); - return FALSE; - } - } -} // InitHRResConfigs - -STATIC -BOOLEAN -InitializeHostRouter ( - OUT HR_CONFIG *Hr_Config, - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction - ) -{ - UINT8 BusNumLimit; - BRDG_RES_CONFIG HrResConf =3D { 0 }; - UINT8 i; - BOOLEAN Ret; - - Ret =3D TRUE; - - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDe= vice, RpFunction, 0); - Hr_Config->HRBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE= _SECONDARY_BUS_REGISTER_OFFSET); - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, Hr_Config->= HRBus, 0x00, 0x00, 0); - Hr_Config->DeviceId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVIC= E_ID_OFFSET); - if (!(IsTbtHostRouter (Hr_Config->DeviceId))) { - return FALSE; - } - TbtSegment =3D (UINT8)RpSegment; - - HrResConf.Cmd =3D CMD_BM_MEM; - HrResConf.Cls =3D DEF_CACHE_LINE_SIZE; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, R= pDevice, RpFunction, 0); - HrResConf.IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET_= OF (PCI_TYPE01, Bridge.IoBase)); - HrResConf.IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET_= OF (PCI_TYPE01, Bridge.IoLimit)); - HrResConf.MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.MemoryBase)); - HrResConf.MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.MemoryLimit)); - HrResConf.PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)); - HrResConf.PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)); - HrResConf.PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddress= + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16; - HrResConf.PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddress= + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16; - BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDI= NATE_BUS_REGISTER_OFFSET); - - Ret =3D InitHRResConfigs (Hr_Config, BusNumLimit, &HrResConf); - - for (i =3D 0; i < Hr_Config->BridgeLoops; ++i) { - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; - Bus =3D HrConfigs[i].DevId.Bus; - Dev =3D HrConfigs[i].DevId.Dev; - Fun =3D HrConfigs[i].DevId.Fun; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, F= un, 0); - - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, HrCo= nfigs[i].Res.Cls); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER= _OFFSET, HrConfigs[i].PBus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST= ER_OFFSET, HrConfigs[i].SBus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI= STER_OFFSET, HrConfigs[i].SubBus); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), HrConfigs[i].Res.MemBase); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryLimit), HrConfigs[i].Res.MemLimit); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), (UINT16) (HrConfigs[i].Res.PMemBase64 & 0xFFFF)); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryLimit), (UINT16) (HrConfigs[i].Res.PMemLimit64 & 0xFFFF))= ; - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), (UINT32) (HrConfigs[i].Res.PMemBase64 >> 16)); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), (UINT32) (HrConfigs[i].Res.PMemLimit64 >> 16)); - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oBase), HrConfigs[i].Res.IoBase); - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oLimit), HrConfigs[i].Res.IoLimit); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBaseUpper16), 0x00000000); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, HrConfigs[i= ].Res.Cmd); - } - if (Hr_Config->DeviceId =3D=3D AR_HR_2C || Hr_Config->DeviceId =3D=3D AR= _HR_4C || Hr_Config->DeviceId =3D=3D AR_HR_LP) { - for (i =3D 0; i < Hr_Config->BridgeLoops; ++i) { - if(HrConfigs[i].IsDSBridge) { - UnsetVesc(HrConfigs[i].DevId.Bus, HrConfigs[i].DevId.Dev, HrConfig= s[i].DevId.Fun); - } - } - } - - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,(Hr_Config->H= RBus + 2), 0x00, 0x00, 0); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PC= I_BAR_IDX0 * 4), HrConfigs[HR_DS_PORT0].Res.MemLimit << 16); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PC= I_BAR_IDX1 * 4), (HrConfigs[HR_DS_PORT0].Res.MemLimit + 0x4) << 16); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA= CHE_LINE_SIZE); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM); - return Ret; -} // InitializeHostRouter -STATIC -UINT8 -ConfigureSlot ( - IN UINT8 Bus, - IN UINT8 MAX_DEVICE, - IN INT8 Depth, - IN BOOLEAN ArPcie, - IN OUT PORT_INFO *PortInfo - ) -{ - UINT8 Device; - UINT8 SBus; - UINT8 UsedBusNumbers; - UINT8 RetBusNum; - PORT_INFO CurrentSlot; - - RetBusNum =3D 0; - - for (Device =3D 0; Device < MAX_DEVICE; Device++) { - // - // Continue if device is absent - // - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Devic= e, 0x00, 0); - if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID= _OFFSET)) { - continue; - - } - - if (P2P_BRIDGE !=3D PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSC= ODE_OFFSET + 1))) { - SetDevResources ( - Bus, - Device, - PCI_MAX_FUNC, - PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX5 * 4), - PortInfo - ); - continue; - } - // - // Else Bridge - // - CopyMem (&CurrentSlot, PortInfo, sizeof (PORT_INFO)); - - ++RetBusNum; // UP Bridge - SBus =3D Bus + RetBusNum; // DS Bridge - - if (SBus + 1 >=3D PortInfo->BusNumLimit) { - continue; - - } - - SetDevResources (Bus, Device, 1, PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR= _IDX1 * 4), PortInfo); - - // - // Init UP Bridge to reach DS Bridge - // - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER= _OFFSET, Bus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST= ER_OFFSET, SBus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI= STER_OFFSET, PortInfo->BusNumLimit); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM)= ; - - if(ArPcie) { - UnsetVesc(Bus, Device, 0x00); - } - - UsedBusNumbers =3D ConfigureSlot(SBus, PCI_MAX_DEVICE + 1, -1, FALSE, Po= rtInfo); - RetBusNum +=3D UsedBusNumbers; - - SetPhyPortResources ( - Bus, - Device, - SBus + UsedBusNumbers, - Depth, - &CurrentSlot, - PortInfo - ); - } - // - // for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) - // - return RetBusNum; -} // ConfigureSlot - -STATIC -VOID -SetCioPortResources ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 SBus, - IN UINT8 SubBus, - IN PORT_INFO *portInfoBeforeChange, - IN OUT PORT_INFO *PortInfo - ) -{ - UINT8 Cmd; - Cmd =3D CMD_BUS_MASTER; - - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, 0x0= 0, 0); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_O= FFSET, Bus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER= _OFFSET, SBus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIST= ER_OFFSET, SubBus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); - - if (PortInfo->IoBase <=3D PortInfo->IoLimit) { - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oBase), PortInfo->IoBase); - PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oLimit), PortInfo->IoLimit); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBaseUpper16), 0x00000000); - Cmd |=3D CMD_BM_IO; - } else { - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBase), DISBL_IO_REG1C); - } - - if (PortInfo->MemBase <=3D PortInfo->MemLimit) { - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), PortInfo->MemBase); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryLimit), PortInfo->MemLimit); - Cmd |=3D CMD_BM_MEM; - } else { - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), DISBL_MEM32_REG20); - } - - if (PortInfo->PMemBase64 <=3D PortInfo->PMemLimit64) { - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), (UINT16) (PortInfo->PMemBase64 & 0xFFFF)); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryLimit), (UINT16) (PortInfo->PMemLimit64 & 0xFFFF)); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), (UINT32) (PortInfo->PMemBase64 >> 16)); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), (UINT32) (PortInfo->PMemLimit64 >> 16)); - Cmd |=3D CMD_BM_MEM; - } else { - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), DISBL_PMEM_REG24); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), 0); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), 0); - } - - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA= CHE_LINE_SIZE); -} // SetCioPortResources - -STATIC -VOID -SetSlotsAsUnused ( - IN UINT8 Bus, - IN UINT8 MaxSlotNum, - IN UINT8 CioSlot, - IN OUT PORT_INFO *PortInfo - ) -{ - UINT8 Slot; - for (Slot =3D MaxSlotNum; Slot > CioSlot; --Slot) { - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Slot, = 0x00, 0); - if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID= _OFFSET)) { - continue; - } - - PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_= CACHE_LINE_SIZE); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER= _OFFSET, Bus); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST= ER_OFFSET, PortInfo->BusNumLimit); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI= STER_OFFSET, PortInfo->BusNumLimit); - PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBase), DISBL_IO_REG1C); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), DISBL_MEM32_REG20); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), DISBL_PMEM_REG24); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MAS= TER); - PortInfo->BusNumLimit--; - } -} // SetSlotsAsUnused - -STATIC -UINT16 -FindVendorSpecificHeader( - IN UINT8 Bus -) -{ - PCI_EXP_EXT_HDR *ExtHdr; - UINT32 ExtHdrValue; - UINT16 ExtendedRegister; - - ExtHdr =3D (PCI_EXP_EXT_HDR*) &ExtHdrValue; - ExtendedRegister =3D 0x100; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x= 00, 0); - while (ExtendedRegister) { - ExtHdrValue =3D PciSegmentRead32 (gDeviceBaseAddress + ExtendedRegiste= r); - if (ExtHdr->CapabilityId =3D=3D 0xFFFF) { - return 0x0000; // No Vendor-Specific Extended Capability header - } - - if (PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID =3D=3D ExtHdr->= CapabilityId) { - return ExtendedRegister; - } - - ExtendedRegister =3D (UINT16) ExtHdr->NextCapabilityOffset; - } - return 0x0000; // No Vendor-Specific Extended Capability header -} - -STATIC -UINT8 -FindSsid_SsvidHeader ( - IN UINT8 Bus - ) -{ - UINT8 CapHeaderId; - UINT8 CapHeaderOffset; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x= 00, 0); - CapHeaderOffset =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_CAPBILIT= Y_POINTER_OFFSET); - - while (CapHeaderOffset !=3D 0) { - CapHeaderId =3D PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOffset)= ; - - if (CapHeaderId =3D=3D PCIE_CAP_ID_SSID_SSVID) { - return CapHeaderOffset; - } - - CapHeaderOffset =3D PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOff= set + 1); - } - - DEBUG((DEBUG_INFO, "SID0\n")); - return 0; -} // FindSsid_SsvidHeader - -STATIC -BOOLEAN -GetCioSlotByDevId ( - IN UINT8 Bus, - OUT UINT8 *CioSlot, - OUT UINT8 *MaxSlotNum, - OUT BOOLEAN *ArPcie - ) -{ - UINT16 VSECRegister; - BRDG_CIO_MAP_REG BridgMap; - UINT32 BitScanRes; - UINT16 DevId; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, 0x00, 0= x00, 0); - DevId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_= ID_OFFSET); - - // - // Init out params in case device is not recognised - // - *CioSlot =3D 4; - *MaxSlotNum =3D 7; - *ArPcie =3D FALSE; - - switch (DevId) { - // - // For known device IDs - // - case 0x1578: - *ArPcie =3D TRUE; - } - - switch (DevId) { - // - // For known device IDs - // - case 0x1513: - case 0x151A: - case 0x151B: - case 0x1547: - case 0x1548: - return TRUE; // Just return - case 0x1549: - return FALSE; // Just return - } - - VSECRegister =3D FindVendorSpecificHeader(Bus); - if (!VSECRegister) { - return TRUE; // Just return - } - // - // Go to Bridge/CIO map register - // - VSECRegister +=3D 0x18; - BridgMap.AB_REG =3D PciSegmentRead32(gDeviceBaseAddress + VSECRegister); - // - // Check for range - // - if (BridgMap.Bits.NumOfDSPorts < 1 || BridgMap.Bits.NumOfDSPorts > 27) { - return TRUE; - // - // Not a valid register - // - } - // - // Set OUT params - // - *MaxSlotNum =3D (UINT8) BridgMap.Bits.NumOfDSPorts; - -#ifdef _MSC_VER - if(!_BitScanForward(&BitScanRes, BridgMap.Bits.CioPortMap)) { // No DS b= ridge which is CIO port - return FALSE; - } -#else -#ifdef __GNUC__ - if (BridgMap.Bits.CioPortMap =3D=3D 0) { - return FALSE; - } - BitScanRes =3D __builtin_ctz (BridgMap.Bits.CioPortMap); -#else -#error Unsupported Compiler -#endif -#endif - - *CioSlot =3D (UINT8)BitScanRes; - return TRUE; -} // GetCioSlotByDevId - -#define TBT_LEGACY_SUB_SYS_ID 0x11112222 - -STATIC -BOOLEAN -IsLegacyDevice ( - IN UINT8 Bus - ) -{ - UINT32 Sid; - UINT8 SidRegister; - UINT16 DevId; - - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x= 00, 0); - DevId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_= ID_OFFSET); - switch (DevId) { - // - // For known device IDs - // - case 0x1513: - case 0x151A: - case 0x151B: - DEBUG((DEBUG_INFO, "Legacy ")); - DEBUG((DEBUG_INFO, "DevId =3D %d\n",DevId)); - return TRUE; - // - // Legacy device by Device Id - // - } - - SidRegister =3D FindSsid_SsvidHeader(Bus); - - if (!SidRegister) { - return TRUE; // May be absent for legacy devices - } - // - // Go to register - // - SidRegister +=3D 0x4; - Sid =3D PciSegmentRead32(gDeviceBaseAddress + SidRegister); - DEBUG((DEBUG_INFO, "SID")); - DEBUG((DEBUG_INFO, " =3D %d\n", Sid)); - -return TBT_LEGACY_SUB_SYS_ID =3D=3D Sid || 0 =3D=3D Sid; -} // IsLegacyDevice - -STATIC -VOID -UnsetVescEp( - IN UINT8 Bus, - IN UINT8 MaxSlotNum - ) -{ - UINT8 i; - - for (i =3D 0; i <=3D MaxSlotNum; ++i) - { - UnsetVesc(Bus, i, 0); - } -}// Unset_VESC_REG2_EP - -STATIC -BOOLEAN -ConfigureEP ( - IN INT8 Depth, - IN OUT UINT8 *Bus, - IN OUT PORT_INFO *PortInfo - ) -{ - UINT8 SBus; - UINT8 CioSlot; - UINT8 MaxSlotNum; - BOOLEAN ArPcie; - UINT8 MaxPHYSlots; - UINT8 UsedBusNumbers; - UINT8 cmd; - BOOLEAN CioSlotPresent; - BOOLEAN Continue; - PORT_INFO PortInfoOrg; - UINT8 CioBus; - - CioSlot =3D 4; - MaxSlotNum =3D 7; - CopyMem (&PortInfoOrg, PortInfo, sizeof (PORT_INFO)); - - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, *Bus, 0x00, = 0x00, 0); - cmd =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_= OFFSET); - // AR ONLY - // Endpoint on CIO slot, but not a bridge device - if (P2P_BRIDGE !=3D PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSCOD= E_OFFSET + 1))) { - DEBUG((DEBUG_INFO, "UEP\n")); - // Check whether EP already configured by examining CMD register - if(cmd & CMD_BUS_MASTER) // Yes, no need to touch this EP - { - DEBUG((DEBUG_INFO, "BMF\n")); - return FALSE; - } - // Configure it as regular PCIe device - ConfigureSlot(*Bus, PCI_MAX_DEVICE + 1, -1, FALSE, PortInfo); - - return FALSE; - } - - // - // Based on Device ID assign Cio slot and max number of PHY slots to sca= n - // - CioSlotPresent =3D GetCioSlotByDevId(*Bus, &CioSlot, &MaxSlotNum, &ArP= cie); - MaxPHYSlots =3D MaxSlotNum; - // - // Check whether EP already configured by examining CMD register - // - - if (cmd & CMD_BUS_MASTER) { - // - // Yes no need to touch this EP, just move to next one in chain - // - CioBus =3D *Bus + 1; - if(ArPcie){ - UnsetVescEp(CioBus, MaxSlotNum); - } - if (!CioSlotPresent) { - // - // Cio slot is not present in EP, just return FALSE - // - DEBUG((DEBUG_INFO, "BMF\n")); - return FALSE; - } - // - // Take all resources from Cio slot and return - // - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,CioBus, Cio= Slot, 0x00, 0); - PortInfo->BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_= BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); - PortInfo->IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFS= ET_OF (PCI_TYPE01, Bridge.IoBase)); - PortInfo->IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFS= ET_OF (PCI_TYPE01, Bridge.IoLimit)); - PortInfo->MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.MemoryBase)); - PortInfo->MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.MemoryLimit)); - PortInfo->PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0; - PortInfo->PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0; - PortInfo->PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddr= ess + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16; - PortInfo->PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddr= ess + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16; - PortInfo->PMemLimit64 |=3D 0xF; - // - // Jump to next EP - // - *Bus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BU= S_REGISTER_OFFSET); - // - // Should we continue? - // - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00,= 0x00, 0); - Continue =3D 0xFFFF !=3D PciSegmentRead16 (gDeviceBaseAddress= + PCI_DEVICE_ID_OFFSET); - return Continue; - } - // - // Set is legacy dvice - // - isLegacyDevice =3D IsLegacyDevice (*Bus); - - SetCioPortResources ( - *Bus, - 0, // Assign all available resources to US port of EP - *Bus + 1, - PortInfo->BusNumLimit, - 0, - PortInfo - ); - - SBus =3D *Bus + 1;// Jump to DS port - - if (CioSlotPresent) { - MaxPHYSlots =3D CioSlot; - } - - UsedBusNumbers =3D ConfigureSlot(SBus, MaxPHYSlots, Depth, ArPcie, PortI= nfo); - if (!CioSlotPresent) { - return FALSE; - // - // Stop resource assignment on this chain - // - } - // - // Set rest of slots us unused - // - SetSlotsAsUnused (SBus, MaxSlotNum, CioSlot, PortInfo); - - SetCioPortResources ( - SBus, - CioSlot, - SBus + UsedBusNumbers + 1, - PortInfo->BusNumLimit, - &PortInfoOrg, - PortInfo - ); - *Bus =3D SBus + UsedBusNumbers + 1;// Go to next EP - if(ArPcie) { - UnsetVesc(SBus, CioSlot, 0x00); - } - if (*Bus > PortInfo->BusNumLimit - 2) { - // - // In case of bus numbers are exhausted stop enumeration - // - return FALSE; - } - // - // Check whether we should continue on this chain - // - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00, 0= x00, 0); - Continue =3D 0xFFFF !=3D PciSegmentRead16 (gDeviceBaseAddress += PCI_DEVICE_ID_OFFSET); - return Continue; -} // ConfigureEP - -STATIC -VOID -GetPortResources ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN OUT PORT_INFO *PortInfo - ) -{ - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun= , 0); - PortInfo->BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BR= IDGE_SUBORDINATE_BUS_REGISTER_OFFSET); - PortInfo->IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.IoBase)) & 0xF0; - PortInfo->IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.IoLimit)) & 0xF0; - PortInfo->MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xFFF0; - PortInfo->MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xFFF0; - PortInfo->PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0; - PortInfo->PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0; - PortInfo->PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddres= s + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16; - PortInfo->PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddres= s + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16; - PortInfo->IoLimit |=3D 0xF; - PortInfo->MemLimit |=3D 0xF; - PortInfo->PMemLimit64 |=3D 0xF; -} // GetPortResources - -STATIC -VOID -ConfigurePort ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN OUT PORT_INFO *PortInfo - ) -{ - INT8 i; - UINT8 USBusNum; - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun= , 0); - USBusNum =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_S= ECONDARY_BUS_REGISTER_OFFSET); - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, USBusNum, 0x= 00, 0x00, 0); - if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_O= FFSET)) { - // - // Nothing to do if TBT device is not connected - // - return ; - } - - GetPortResources(Bus, Dev, Fun, PortInfo);// Take reserved resources fro= m DS port - // - // Assign resources to EPs - // - for (i =3D 0; i < MAX_TBT_DEPTH; ++i) { - PortInfo->ConfedEP++; - if (!ConfigureEP (i, &USBusNum, PortInfo)) { - return ; - } - } -} // ConfigurePort - -VOID -ThunderboltCallback ( - IN UINT8 Type - ) -{ - PORT_INFO PortInfoOrg =3D { 0 }; - HR_CONFIG HrConfig =3D { 0 }; - UINT8 i; - UINTN Segment =3D 0; - UINTN Bus =3D 0; - UINTN Device; - UINTN Function; - - DEBUG((DEBUG_INFO, "ThunderboltCallback.Entry\n")); - - DEBUG((DEBUG_INFO, "PortInfo Initialization\n")); - PortInfoInit (&PortInfoOrg); - if(Type =3D=3D DTBT_CONTROLLER) { - if (gCurrentDiscreteTbtRootPort =3D=3D 0) { - DEBUG((DEBUG_ERROR, "Invalid RP Input\n")); - return; - } - GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRo= otPort - 1, &Device, &Function); - DEBUG((DEBUG_INFO, "InitializeHostRouter. \n")); - if (!InitializeHostRouter (&HrConfig, Segment, Bus, Device, Function))= { - return ; - } - // - // Configure DS ports - // - for (i =3D HrConfig.MinDSNumber; i <=3D HrConfig.MaxDSNumber; ++i) { - DEBUG((DEBUG_INFO, "ConfigurePort. \n")); - ConfigurePort (HrConfig.HRBus + 1, i,0, &PortInfoOrg); - } - - DEBUG((DEBUG_INFO, "EndOfThunderboltCallback.\n")); - EndOfThunderboltCallback (Segment, Bus, Device, Function); - - } - DEBUG((DEBUG_INFO, "ThunderboltCallback.Exit\n")); -} // ThunderboltCallback - -VOID -DisablePCIDevicesAndBridges ( - IN UINT8 MinBus, - IN UINT8 MaxBus - ) -{ - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; - UINT8 RegVal; - // - // Disable PCI device First, and then Disable PCI Bridge - // - for (Bus =3D MaxBus; Bus > MinBus; --Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, De= v, Fun, 0); - if (INVALID_PCI_DEVICE =3D=3D PciSegmentRead32 (gDeviceBaseAddress= + PCI_VENDOR_ID_OFFSET)) { - if (Fun =3D=3D 0) { - break; - - } - - continue; - } - - RegVal =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_O= FFSET); - if (HEADER_TYPE_DEVICE =3D=3D (RegVal & 1)) { - // - // ******** Disable PCI Device ******** - // BIT0 I/O Space Enabled BIT1 Memory Space Enabled - // BIT2 Bus Master Enabled BIT4 Memory Write and Invalidatio= n Enable - // - PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)= ~(BIT0 | BIT1 | BIT2 | BIT4)); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX0 * 4), 0); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX1 * 4), 0); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX2 * 4), 0); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX3 * 4), 0); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX4 * 4), 0); - PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX5 * 4), 0); - } - } - } - } - // - // now no more PCI dev on another side of PCI Bridge can safty disable P= CI Bridge - // - for (Bus =3D MaxBus; Bus > MinBus; --Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, De= v, Fun, 0); - if (INVALID_PCI_DEVICE =3D=3D PciSegmentRead32 (gDeviceBaseAddress= + PCI_VENDOR_ID_OFFSET)) { - if (Fun =3D=3D 0) { - break; - } - - continue; - } - - RegVal =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_O= FFSET); - if (HEADER_TYPE_PCI_TO_PCI_BRIDGE =3D=3D (RegVal & BIT0)) { - PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)= ~(BIT0 | BIT1 | BIT2 | BIT4)); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_RE= GISTER_OFFSET, 0); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BU= S_REGISTER_OFFSET, 0); - PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_= REGISTER_OFFSET, 0); - PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, B= ridge.PrefetchableBaseUpper32), 0); - } - } // for ( Fun .. ) - } // for ( Dev ... ) - } // for ( Bus ... ) -} // DisablePCIDevicesAndBridges - -VOID -TbtDisablePCIDevicesAndBridges ( - IN UINT8 Type - ) -{ - UINTN Segment =3D 0; - UINTN Bus =3D 0; - UINTN Device; - UINTN Function; - UINT8 MinBus; - UINT8 MaxBus; - UINT16 DeviceId; - - MinBus =3D 1; - if(Type =3D=3D DTBT_CONTROLLER) { - // - // for(Dev =3D 0; Dev < 8; ++Dev) - // { - // PciOr8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSE= T), 0x40); - // gBS->Stall(2000); // 2msec - // PciAnd8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFS= ET), 0xBF); - // } - // gBS->Stall(200 * 1000); // 200 msec - // - if (gCurrentDiscreteTbtRootPort =3D=3D 0) { - DEBUG((DEBUG_ERROR, "Invalid RP Input\n")); - return; - } - GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRo= otPort - 1, &Device, &Function); - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, = Function, 0); - MinBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE= _SECONDARY_BUS_REGISTER_OFFSET); - MaxBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE= _SUBORDINATE_BUS_REGISTER_OFFSET); - gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, MinBus, 0x00,= 0x00, 0); - DeviceId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVIC= E_ID_OFFSET); - if (!(IsTbtHostRouter (DeviceId))) { - return; - } - TbtSegment =3D (UINT8)Segment; - MinBus++; - // - // @todo : Move this out when we dont have Loop for ITBT - // - DisablePCIDevicesAndBridges(MinBus, MaxBus); - - } -} // DisablePCIDevicesAndBridges - - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS= mm.c b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c deleted file mode 100644 index 5810447792..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c +++ /dev/null @@ -1,1764 +0,0 @@ -/** @file - Thunderbolt initialization in SMM. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -// -// Module specific Includes -// -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "TbtSmiHandler.h" -#include -#include -#include -#include -#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CL= ASS_BRIDGE_P2P)) - -#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0) - -#define DISBL_IO_REG1C 0x01F1 -#define DISBL_MEM32_REG20 0x0000FFF0 -#define DISBL_PMEM_REG24 0x0001FFF1 - -#define DOCK_BUSSES 8 - -#define PCI_CAPABILITY_ID_PCIEXP 0x10 -#define PCI_CAPBILITY_POINTER_OFFSET 0x34 - -#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Snoop Latency can we put like this ? -#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Non-Snoop Latency can we put like this ? - - -GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA *mTbtNvsAreaPtr; -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscrete= TbtRootPort; -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscrete= TbtRootPortType; -GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxSnoopLa= tency; -GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxNoSnoop= Latency; -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gDTbtPcieRstSupp= ort; -GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *gTbtInfoHob =3D= NULL; -STATIC UINTN mPciExpressBaseA= ddress; -STATIC UINT8 TbtSegment =3D 0; -VOID -GpioWrite ( - IN UINT32 GpioNumber, - IN BOOLEAN Value - ) -{ - GpioSetOutputValue (GpioNumber, (UINT32)Value); -} - -/** - Search and return the offset of desired Pci Express Capability ID - CAPID list: - 0x0001 =3D Advanced Error Reporting Capability - 0x0002 =3D Virtual Channel Capability - 0x0003 =3D Device Serial Number Capability - 0x0004 =3D Power Budgeting Capability - - @param[in] Bus Pci Bus Number - @param[in] Device Pci Device Number - @param[in] Function Pci Function Number - @param[in] CapId Extended CAPID to search for - - @retval 0 CAPID not found - @retval Other CAPID found, Offset of desired CAPID -**/ -UINT16 -PcieFindExtendedCapId ( - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT16 CapId - ) -{ - UINT16 CapHeaderOffset; - UINT16 CapHeaderId; - UINT64 DeviceBase; - - DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Functio= n, 0); - - /// - /// Start to search at Offset 0x100 - /// Get Capability Header, A pointer value of 00h is used to indicate th= e last capability in the list. - /// - CapHeaderId =3D 0; - CapHeaderOffset =3D 0x100; - while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFFFF) { - CapHeaderId =3D PciSegmentRead16 (DeviceBase + CapHeaderOffset); - if (CapHeaderId =3D=3D CapId) { - return CapHeaderOffset; - } - /// - /// Each capability must be DWORD aligned. - /// The bottom two bits of all pointers are reserved and must be imple= mented as 00b - /// although software must mask them to allow for future uses of these= bits. - /// - CapHeaderOffset =3D (PciSegmentRead16 (DeviceBase + CapHeaderOffset + = 2) >> 4) & ((UINT16) ~(BIT0 | BIT1)); - } - - return 0; -} - -/** - Find the Offset to a given Capabilities ID - CAPID list: - 0x01 =3D PCI Power Management Interface - 0x04 =3D Slot Identification - 0x05 =3D MSI Capability - 0x10 =3D PCI Express Capability - - @param[in] Bus Pci Bus Number - @param[in] Device Pci Device Number - @param[in] Function Pci Function Number - @param[in] CapId CAPID to search for - - @retval 0 CAPID not found - @retval Other CAPID found, Offset of desired CAPID -**/ -UINT8 -PcieFindCapId ( - IN UINT8 Segment, - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 CapId - ) -{ - UINT8 CapHeaderOffset; - UINT8 CapHeaderId; - UINT64 DeviceBase; - - DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, = 0); - - if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_= STATUS_CAPABILITY) =3D=3D 0x00) { - /// - /// Function has no capability pointer - /// - return 0; - } - - /// - /// Check the header layout to determine the Offset of Capabilities Poin= ter Register - /// - if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LAYO= UT_CODE) =3D=3D (HEADER_TYPE_CARDBUS_BRIDGE)) { - /// - /// If CardBus bridge, start at Offset 0x14 - /// - CapHeaderOffset =3D 0x14; - } else { - /// - /// Otherwise, start at Offset 0x34 - /// - CapHeaderOffset =3D 0x34; - } - /// - /// Get Capability Header, A pointer value of 00h is used to indicate th= e last capability in the list. - /// - CapHeaderId =3D 0; - CapHeaderOffset =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset) & ((U= INT8) ~(BIT0 | BIT1)); - while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFF) { - CapHeaderId =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset); - if (CapHeaderId =3D=3D CapId) { - return CapHeaderOffset; - } - /// - /// Each capability must be DWORD aligned. - /// The bottom two bits of all pointers (including the initial pointer= at 34h) are reserved - /// and must be implemented as 00b although software must mask them to= allow for future uses of these bits. - /// - CapHeaderOffset =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset + 1)= & ((UINT8) ~(BIT0 | BIT1)); - } - - return 0; -} -/** - This function configures the L1 Substates. - It can be used for Rootport and endpoint devices. - - @param[in] DownstreamPort Indicates if the device about to= be programmed is a downstream port - @param[in] DeviceBase Device PCI configuration base ad= dress - @param[in] L1SubstateExtCapOffset Pointer to L1 Substate Capabilit= y Structure - @param[in] PortL1SubstateCapSupport L1 Substate capability setting - @param[in] PortCommonModeRestoreTime Common Mode Restore Time - @param[in] PortTpowerOnValue Tpower_on Power On Wait Time - @param[in] PortTpowerOnScale Tpower-on Scale - - @retval none -**/ -VOID -ConfigureL1s ( - IN UINTN DeviceBase, - IN UINT16 L1SubstateExtCapOffset, - IN UINT32 PortL1SubstateCapSupport, - IN UINT32 PortCommonModeRestoreTime, - IN UINT32 PortTpowerOnValue, - IN UINT32 PortTpowerOnScale, - IN UINT16 MaxLevel - ) -{ - - PciSegmentAndThenOr32 ( - DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, - (UINT32) ~(0xFF00), - (UINT32) PortCommonModeRestoreTime << 8 - ); - - PciSegmentAnd32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_= OFFSET, 0xFFFFFF04); - - PciSegmentOr32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_O= FFSET,(UINT32) ((PortTpowerOnValue << N_PCIE_EX_L1SCTL2_POWT) | PortTpowerO= nScale)); - - PciSegmentAndThenOr32 ( - DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, - (UINT32) ~(0xE3FF0000), - (UINT32) (BIT30 | BIT23 | BIT21) - ); - -} - -VOID -RootportL1sSupport ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN UINT16 RootL1SubstateExtCapOffset, - IN UINT16 MaxL1Level - ) -{ - UINTN ComponentABaseAddress; - UINTN ComponentBBaseAddress; - UINT8 SecBus; - UINT32 PortL1SubstateCapSupport; - UINT32 PortCommonModeRestoreTime; - UINT32 PortTpowerOnValue; - UINT32 PortTpowerOnScale; - UINT16 ComponentBL1SubstateExtCapOffset; - UINT32 ComponentBL1Substates; - UINT32 ComponentBCommonModeRestoreTime; - UINT32 ComponentBTpowerOnValue; - UINT32 ComponentBTpowerOnScale; - UINT32 Data32; - - PortL1SubstateCapSupport =3D 0; - PortCommonModeRestoreTime =3D 0; - PortTpowerOnValue =3D 0; - PortTpowerOnScale =3D 0; - Data32 =3D 0; - - ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev= , Fun, 0); - if (RootL1SubstateExtCapOffset !=3D 0) { - Data32 =3D PciSegmentRead32 (ComponentABaseAddress + RootL1SubstateExt= CapOffset + R_PCIE_EX_L1SCAP_OFFSET); - PortL1SubstateCapSupport =3D (Data32) & 0x0F; - PortCommonModeRestoreTime =3D (Data32 >> 8) & 0xFF; - PortTpowerOnScale =3D (Data32 >> 16) & 0x3; - PortTpowerOnValue =3D (Data32 >> 19) & 0x1F; - } else { - MaxL1Level =3D 0; // If L1 Substates from Root Port sid= e is disable, then Disable from Device side also. - } - - SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B= RIDGE_SECONDARY_BUS_REGISTER_OFFSET); - ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0= , 0, 0); - - if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) =3D= =3D 0xFFFF) { - ComponentBL1SubstateExtCapOffset =3D PcieFindExtendedCapId ( - SecBus, - 0, - 0, - V_PCIE_EX_L1S_CID - ); - if (ComponentBL1SubstateExtCapOffset !=3D 0) { - ComponentBL1Substates =3D PciSegmentRead32 (ComponentBBaseAddress + = ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET); - ComponentBCommonModeRestoreTime =3D (ComponentBL1Substates >> 8) & 0= xFF; - ComponentBTpowerOnScale =3D (ComponentBL1Substates >> 16) & = 0x3; - ComponentBTpowerOnValue =3D (ComponentBL1Substates >> 19) & = 0x1F; - - if (MaxL1Level =3D=3D 3) { - if (Data32 >=3D ComponentBL1Substates) { - if (~(Data32 | BIT2)) { - MaxL1Level =3D 1; - } - } - else { - if (~(ComponentBL1Substates | BIT2)) { - MaxL1Level =3D 1; - } - } - } - - if (MaxL1Level =3D=3D 3) { - ConfigureL1s ( - ComponentABaseAddress, - RootL1SubstateExtCapOffset, - PortL1SubstateCapSupport, - ComponentBCommonModeRestoreTime, - ComponentBTpowerOnValue, - ComponentBTpowerOnScale, - MaxL1Level - ); - - ConfigureL1s ( - ComponentBBaseAddress, - ComponentBL1SubstateExtCapOffset, - ComponentBL1Substates, - PortCommonModeRestoreTime, - PortTpowerOnValue, - PortTpowerOnScale, - MaxL1Level - ); - } - - if (MaxL1Level =3D=3D 1) { - PciSegmentOr32 ( - ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L= 1SCTL1_OFFSET, - (UINT32) (BIT3 | BIT1) - ); - - PciSegmentOr32 ( - ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCI= E_EX_L1SCTL1_OFFSET, - (UINT32) (BIT3 | BIT1) - ); - } - else { - if (RootL1SubstateExtCapOffset !=3D 0) { - PciSegmentOr32 ( - ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX= _L1SCTL1_OFFSET, - (UINT32) (BIT3 | BIT1) - ); - - PciSegmentOr32 ( - ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX= _L1SCTL1_OFFSET, - (UINT32) (BIT2 | BIT0) - ); - } - if (ComponentBL1SubstateExtCapOffset !=3D 0) { - PciSegmentOr32 ( - ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_P= CIE_EX_L1SCTL1_OFFSET, - (UINT32) (BIT3 | BIT1) - ); - - PciSegmentOr32 ( - ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_P= CIE_EX_L1SCTL1_OFFSET, - (UINT32) (BIT2 | BIT0) - ); - } - } - } - } -} - -VOID -MultiFunctionDeviceAspm ( - IN UINT8 Bus, - IN UINT8 Dev - ) -{ - UINT16 LowerAspm; - UINT16 AspmVal; - UINT8 Fun; - UINT64 DeviceBaseAddress; - UINT8 CapHeaderOffset; - - LowerAspm =3D 3; // L0s and L1 Supported - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, F= un, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=3D= 0xFFFF) { - // Device not present - continue; - } - - CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); - - AspmVal =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0= x00C) >> 10) & 3; - if (LowerAspm > AspmVal) { - LowerAspm =3D AspmVal; - } - } //Fun - - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, F= un, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=3D= 0xFFFF) { - // - // Device not present - // - continue; - } - - CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); - - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xF= FFC, LowerAspm); - } //Fun -} - -UINT16 -LimitAspmLevel ( - IN UINT16 SelectedAspm, - IN UINT16 MaxAspmLevel - ) -{ - SelectedAspm =3D SelectedAspm & MaxAspmLevel; - - return SelectedAspm; -} - -UINT16 -FindOptimalAspm ( - IN UINT16 ComponentAaspm, - IN UINT16 ComponentBaspm - ) -{ - UINT16 SelectedAspm; - - SelectedAspm =3D ComponentAaspm & ComponentBaspm; - - return SelectedAspm; -} - -UINT16 -FindComponentBaspm ( - IN UINT8 Bus, - IN UINT8 MaxBus - ) -{ - UINT8 BusNo; - UINT8 DevNo; - UINT8 FunNo; - UINT64 DevBaseAddress; - UINT8 RegVal; - UINT8 SecBusNo; - UINT16 SelectedAspm; // No ASPM Support - UINT8 CapHeaderOffset_B; - BOOLEAN AspmFound; - - SelectedAspm =3D 0; - AspmFound =3D FALSE; - - for (BusNo =3D MaxBus; (BusNo !=3D 0xFF) && (!AspmFound); --BusNo) { - for (DevNo =3D 0; (DevNo <=3D PCI_MAX_DEVICE) && (!AspmFound); ++DevNo= ) { - for (FunNo =3D 0; (FunNo <=3D PCI_MAX_FUNC) && (!AspmFound); ++FunNo= ) { - // - // Check for Device availability - // - DevBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, BusNo, Dev= No, FunNo, 0); - if (PciSegmentRead16 (DevBaseAddress + PCI_DEVICE_ID_OFFSET) =3D= =3D 0xFFFF) { - // - // Device not present - // - continue; - } - - RegVal =3D PciSegmentRead8 (DevBaseAddress + PCI_HEADER_TYPE_OFFSE= T); - if ((RegVal & (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6)) != =3D 0x01) { - // - // Not a PCI-to-PCI bridges device - // - continue; - } - - SecBusNo =3D PciSegmentRead8 (DevBaseAddress + PCI_BRIDGE_SECONDAR= Y_BUS_REGISTER_OFFSET); - - if (SecBusNo =3D=3D Bus) { - // - // This is the Rootbridge for the given 'Bus' device - // - CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, BusNo, DevNo, F= unNo, 0x10); - SelectedAspm =3D (PciSegmentRead16 (DevBaseAddress + CapHea= derOffset_B + 0x00C) >> 10) & 3; - AspmFound =3D TRUE; - } - } //FunNo - } //DevNo - } //BusNo - - return (SelectedAspm); -} - -VOID -NoAspmSupport ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN UINT8 CapHeaderOffset - ) -{ - UINT64 DeviceBaseAddress; - - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF= C, 0x00); -} - -VOID -EndpointAspmSupport ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN UINT8 CapHeaderOffset, - IN UINT8 MaxBus, - IN UINT16 MaxAspmLevel - ) -{ - UINT64 DeviceBaseAddress; - UINT16 ComponentAaspm; - UINT16 ComponentBaspm; - UINT16 SelectedAspm; - - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); - ComponentAaspm =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOf= fset + 0x00C) >> 10) & 3; - ComponentBaspm =3D FindComponentBaspm (Bus, MaxBus); - SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); - SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF= C, SelectedAspm); -} - -VOID -UpstreamAspmSupport ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN UINT8 CapHeaderOffset, - IN UINT8 MaxBus, - IN UINT16 MaxAspmLevel - ) -{ - UINT64 DeviceBaseAddress; - UINT16 ComponentAaspm; - UINT16 ComponentBaspm; - UINT16 SelectedAspm; - - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); - ComponentAaspm =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOf= fset + 0x00C) >> 10) & 3; - ComponentBaspm =3D FindComponentBaspm (Bus, MaxBus); - SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); - SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF= C, SelectedAspm); -} - -VOID -DownstreamAspmSupport ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN UINT8 CapHeaderOffset, - IN UINT16 MaxAspmLevel - ) -{ - UINT64 ComponentABaseAddress; - UINT64 ComponentBBaseAddress; - UINT16 ComponentAaspm; - UINT16 ComponentBaspm; - UINT16 SelectedAspm; - UINT8 SecBus; - UINT8 CapHeaderOffset_B; - - ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,= Fun, 0); - ComponentAaspm =3D (PciSegmentRead16 (ComponentABaseAddress + Cap= HeaderOffset + 0x00C) >> 10) & 3; - - SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B= RIDGE_SECONDARY_BUS_REGISTER_OFFSET); - ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0= , 0, 0); - ComponentBaspm =3D 0; // No ASPM Support - if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) !=3D= 0xFFFF) { - CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); - ComponentBaspm =3D (PciSegmentRead16 (ComponentBBaseAddress + CapHe= aderOffset_B + 0x00C) >> 10) & 3; - } - - SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); - SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); - PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0= xFFFC, SelectedAspm); -} - -VOID -RootportAspmSupport ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN UINT8 CapHeaderOffset, - IN UINT16 MaxAspmLevel - ) -{ - UINT64 ComponentABaseAddress; - UINT64 ComponentBBaseAddress; - UINT16 ComponentAaspm; - UINT16 ComponentBaspm; - UINT16 SelectedAspm; - UINT8 SecBus; - UINT8 CapHeaderOffset_B; - - ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,= Fun, 0); - ComponentAaspm =3D (PciSegmentRead16 (ComponentABaseAddress + Cap= HeaderOffset + 0x00C) >> 10) & 3; - - SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B= RIDGE_SECONDARY_BUS_REGISTER_OFFSET); - ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0= , 0, 0); - ComponentBaspm =3D 0; // No ASPM Support - if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) !=3D= 0xFFFF) { - CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); - ComponentBaspm =3D (PciSegmentRead16 (ComponentBBaseAddress + CapHe= aderOffset_B + 0x00C) >> 10) & 3; - } - - SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); - SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); - PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0= xFFFC, SelectedAspm); -} - -VOID -ThunderboltEnableAspmWithoutLtr ( - IN UINT16 MaxAspmLevel, - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction - ) -{ - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; - UINT8 RootBus; - UINT8 RootDev; - UINT8 RootFun; - UINT8 MinBus; - UINT8 MaxBus; - UINT16 DeviceId; - UINT64 DeviceBaseAddress; - UINT8 RegVal; - UINT8 CapHeaderOffset; - UINT16 DevicePortType; - - MinBus =3D 0; - MaxBus =3D 0; - - MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); - MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); - DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); - if (!(IsTbtHostRouter (DeviceId))) { - return; - } - - TbtSegment =3D (UINT8)RpSegment; - - RootBus =3D (UINT8)RpBus; - RootDev =3D (UINT8)RpDevice; - RootFun =3D (UINT8)RpFunction; - - // - // Enumerate all the bridges and devices which are available on TBT hos= t controller - // - for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,= 0, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D= =3D 0xFFFF) { - // - // Device not present - // - continue; - } - - RegVal =3D PciSegmentRead8 (DeviceBaseAddress + PCI_HEADER_TYPE_OFFS= ET); - if ((RegVal & BIT7) =3D=3D 0) { - // - // Not a multi-function device - // - continue; - } - - MultiFunctionDeviceAspm(Bus, Dev); - } //Dev - } //Bus - - - for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { - // - // Device not present - // - continue; - } - - CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10= ); - DevicePortType =3D (PciSegmentRead16 (DeviceBaseAddress + CapHead= erOffset + 0x002) >> 4) & 0xF; - if(PciSegmentRead8 (DeviceBaseAddress + PCI_CLASSCODE_OFFSET) =3D= =3D PCI_CLASS_SERIAL) { - MaxAspmLevel =3D (UINT16) 0x1; - } - - switch (DevicePortType) { - case 0: - // - // PCI Express Endpoint - // - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); - break; - - case 1: - // - // Legacy PCI Express Endpoint - // - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); - break; - - case 4: - // - // Root Port of PCI Express Root Complex - // - RootportAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLeve= l); - break; - - case 5: - // - // Upstream Port of PCI Express Switch - // - UpstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); - break; - - case 6: - // - // Downstream Port of PCI Express Switch - // - DownstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLe= vel); - break; - - case 7: - // - // PCI Express to PCI/PCI-X Bridge - // - NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset); - break; - - case 8: - // - // PCI/PCI-X to PCI Express Bridge - // - NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset); - break; - - case 9: - // - // Root Complex Integrated Endpoint - // - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); - break; - - case 10: - // - // Root Complex Event Collector - // - EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); - break; - - default: - break; - } - // - // switch(DevicePortType) - // - } - // - // Fun - // - } - // - // Dev - // - } - // - // Bus - // - CapHeaderOffset =3D PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun= , 0x10); - RootportAspmSupport (RootBus, RootDev, RootFun, CapHeaderOffset, MaxAspm= Level); -} - -VOID -ThunderboltEnableL1Sub ( - IN UINT16 MaxL1Level, - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction - ) -{ - UINT16 CapHeaderOffsetExtd; - - RpBus =3D 0; - - CapHeaderOffsetExtd =3D PcieFindExtendedCapId ((UINT8) RpBus, (UINT8) Rp= Device, (UINT8) RpFunction, V_PCIE_EX_L1S_CID); - RootportL1sSupport ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction,= CapHeaderOffsetExtd, MaxL1Level); -} - -VOID -ThunderboltDisableAspmWithoutLtr ( - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction - ) -{ - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; - UINT8 RootBus; - UINT8 RootDev; - UINT8 RootFun; - UINT8 MinBus; - UINT8 MaxBus; - UINT16 DeviceId; - UINT64 DeviceBaseAddress; - UINT8 CapHeaderOffset; - - MinBus =3D 0; - MaxBus =3D 0; - - MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); - MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); - DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); - if (!(IsTbtHostRouter (DeviceId))) { - return; - } - - TbtSegment =3D (UINT8)RpSegment; - RootBus =3D (UINT8)RpBus; - RootDev =3D (UINT8)RpDevice; - RootFun =3D (UINT8)RpFunction; - - // - // Enumerate all the bridges and devices which are available on TBT hos= t controller - // - for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { - // - // Device not present - // - continue; - } - - CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10= ); - PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10,= 0xFFFC, 0x00); - } //Fun - } //Dev - } //Bus - - CapHeaderOffset =3D PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun= , 0x10); - NoAspmSupport(RootBus, RootDev, RootFun, CapHeaderOffset); -} - -VOID -TbtProgramClkReq ( - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 ClkReqSetup - ) -{ - UINT64 DeviceBaseAddress; - UINT8 CapHeaderOffset; - UINT16 Data16; - - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, = Function, 0); - CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Device, Function, = 0x10); - - // - // Check if CLKREQ# is supported - // - if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x0C) & BIT= 18) !=3D 0) { - Data16 =3D PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x0= 10); - - if (ClkReqSetup) { - Data16 =3D Data16 | BIT8; // Enable Clock Power Management - } else { - Data16 =3D Data16 & (UINT16)(~BIT8); // Disable Clock Power Managem= ent - } - - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x010, Data16= ); - } -} -VOID -TbtProgramPtm( - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 PtmSetup, - IN BOOLEAN IsRoot -) -{ - UINT64 DeviceBaseAddress; - UINT16 CapHeaderOffset; - UINT16 PtmControlRegister; - UINT16 PtmCapabilityRegister; - - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(TbtSegment, Bus, Device, = Function, 0); - CapHeaderOffset =3D PcieFindExtendedCapId(Bus, Device, Function, 0x001F= /*V_PCIE_EX_PTM_CID*/); - if(CapHeaderOffset !=3D 0) { - PtmCapabilityRegister =3D PciSegmentRead16(DeviceBaseAddress + CapHe= aderOffset + 0x04); - // - // Check if PTM Requester/ Responder capability for the EP/Down strea= m etc - // - if ((PtmCapabilityRegister & (BIT1 | BIT0)) !=3D 0) { - PtmControlRegister =3D PciSegmentRead16(DeviceBaseAddress + CapHea= derOffset + 0x08); - - if (PtmSetup) { - PtmControlRegister =3D PtmControlRegister | BIT0; // Enable PTM - if(IsRoot) { - PtmControlRegister =3D PtmControlRegister | BIT1; // Enable P= TM - } - PtmControlRegister =3D PtmControlRegister | (PtmCapabilityRegis= ter & 0xFF00); // Programm Local Clock Granularity - } else { - PtmControlRegister =3D PtmControlRegister & (UINT16)(~(BIT0 | B= IT1)); // Disable Clock Power Management - } - - PciSegmentWrite16(DeviceBaseAddress + CapHeaderOffset + 0x08, PtmC= ontrolRegister); - } - } -} - -VOID -ConfigureTbtPm ( - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction, - IN UINT8 Configuration // 1- Clk Request , 2- PTM , - ) -{ - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; - UINT8 MinBus; - UINT8 MaxBus; - UINT16 DeviceId; - UINT64 DeviceBaseAddress; - - MinBus =3D 0; - MaxBus =3D 0; - - if ((Configuration !=3D 1) && (Configuration !=3D 2)) { - return; - } - MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); - MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); - DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); - if (!(IsTbtHostRouter (DeviceId))) { - return; - } - - TbtSegment =3D (UINT8)RpSegment; - // - // Enumerate all the bridges and devices which are available on TBT hos= t controller - // - for (Bus =3D MaxBus; Bus >=3D MinBus; --Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { - if (Fun =3D=3D 0) { - // - // IF Fun is zero, stop enumerating other functions of the par= ticular bridge - // - break; - } - // - // otherwise, just skip checking for CLKREQ support - // - continue; - } - switch (Configuration) { - case 1: - TbtProgramClkReq (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtSe= tClkReq); - break; - case 2: - TbtProgramPtm (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtPtm, = FALSE); - TbtProgramPtm((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunct= ion, (UINT8) mTbtNvsAreaPtr->TbtPtm, TRUE); - break; - default: - break; - } - } //Fun - } // Dev - } // Bus -} - -/** - 1) Check LTR support in device capabilities 2 register (bit 11). - 2) If supported enable LTR in device control 2 register (bit 10). - -**/ -VOID -TbtProgramLtr ( - IN UINT8 Bus, - IN UINT8 Device, - IN UINT8 Function, - IN UINT8 LtrSetup - ) -{ - UINT64 DeviceBaseAddress; - UINT8 CapHeaderOffset; - UINT16 Data16; - - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, = Function, 0); - CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Device, Function, = 0x10); - - // - // Check if LTR# is supported - // - if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x24) & BIT= 11) !=3D 0) { - Data16 =3D PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x0= 28); - - if (LtrSetup) { - Data16 =3D Data16 | BIT10; // LTR Mechanism Enable - } else { - Data16 =3D Data16 & (UINT16)(~BIT10); // LTR Mechanism Disable - } - - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x028, Data16= ); - } -} - -VOID -ConfigureLtr ( - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction - ) -{ - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; - UINT8 MinBus; - UINT8 MaxBus; - UINT16 DeviceId; - UINT64 DeviceBaseAddress; - - MinBus =3D 0; - MaxBus =3D 0; - - MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); - MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); - DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); - if (!(IsTbtHostRouter (DeviceId))) { - return; - } - - TbtSegment =3D (UINT8)RpSegment; - // - // Enumerate all the bridges and devices which are available on TBT hos= t controller - // - for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { - if (Fun =3D=3D 0) { - // - // IF Fun is zero, stop enumerating other functions of the par= ticular bridge - // - break; - } - // - // otherwise, just skip checking for LTR support - // - continue; - } - - TbtProgramLtr (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtLtr); - - } //Fun - } // Dev - } // Bus - TbtProgramLtr ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, (UIN= T8) mTbtNvsAreaPtr->TbtLtr); -} - -/* - US ports and endpoints which declare support must also have the LTR capa= bility structure (cap ID 18h). - In this structure you need to enter the max snoop latency and max non-sn= oop latency in accordance with the format specified in the PCIe spec. - The latency value itself is platform specific so you'll need to get it f= rom the platform architect or whatever. -*/ -VOID -ThunderboltGetLatencyLtr ( - VOID - ) -{ - PCH_SERIES PchSeries; - - PchSeries =3D GetPchSeries (); - - if(gCurrentDiscreteTbtRootPortType =3D=3D DTBT_TYPE_PEG) { - // PEG selector - TbtLtrMaxSnoopLatency =3D LTR_MAX_SNOOP_LATENCY_VALUE; - TbtLtrMaxNoSnoopLatency =3D LTR_MAX_NON_SNOOP_LATENCY_VALUE; - } else if (gCurrentDiscreteTbtRootPortType =3D=3D DTBT_TYPE_PCH) { - // PCH selector - - if (PchSeries =3D=3D PchLp) { - TbtLtrMaxSnoopLatency =3D 0x1003; - TbtLtrMaxNoSnoopLatency =3D 0x1003; - } - if (PchSeries =3D=3D PchH) { - TbtLtrMaxSnoopLatency =3D 0x0846; - TbtLtrMaxNoSnoopLatency =3D 0x0846; - } - } -} - -VOID -SetLatencyLtr ( - IN UINT8 Bus, - IN UINT8 Dev, - IN UINT8 Fun, - IN UINT16 CapHeaderOffsetExtd, - IN UINT16 LtrMaxSnoopLatency, - IN UINT16 LtrMaxNoSnoopLatency - ) -{ - UINT64 DeviceBaseAddress; - if(CapHeaderOffsetExtd =3D=3D 0) { - return; - } - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x004, LtrM= axSnoopLatency); - PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x006, LtrM= axNoSnoopLatency); -} - -VOID -ThunderboltSetLatencyLtr ( - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction - ) -{ - UINT8 Bus; - UINT8 Dev; - UINT8 Fun; - UINT8 MinBus; - UINT8 MaxBus; - UINT16 DeviceId; - UINT64 DeviceBaseAddress; - UINT8 CapHeaderOffsetStd; - UINT16 CapHeaderOffsetExtd; - UINT16 DevicePortType; - - MinBus =3D 0; - MaxBus =3D 0; - - MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); - MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); - DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); - if (!(IsTbtHostRouter (DeviceId))) { - return; - } - - TbtSegment =3D (UINT8)RpSegment; - - for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { - for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { - for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { - // - // Check for Device availability - // - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); - if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { - // - // Device not present - // - continue; - } - - CapHeaderOffsetStd =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0= x10); - DevicePortType =3D (PciSegmentRead16 (DeviceBaseAddress + CapHead= erOffsetStd + 0x002) >> 4) & 0xF; - - CapHeaderOffsetExtd =3D PcieFindExtendedCapId (Bus, Dev, Fun, 0x00= 18); - - switch (DevicePortType) { - case 0: - // - // PCI Express Endpoint - // - SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo= pLatency, TbtLtrMaxNoSnoopLatency); - break; - - case 1: - // - // Legacy PCI Express Endpoint - // - SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo= pLatency, TbtLtrMaxNoSnoopLatency); - break; - - case 4: - // - // Root Port of PCI Express Root Complex - // - // Do-nothing - break; - - case 5: - // - // Upstream Port of PCI Express Switch - // - SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo= pLatency, TbtLtrMaxNoSnoopLatency); - break; - - case 6: - // - // Downstream Port of PCI Express Switch - // - // Do-nothing - break; - - case 7: - // - // PCI Express to PCI/PCI-X Bridge - // - // Do-nothing - break; - - case 8: - // - // PCI/PCI-X to PCI Express Bridge - // - // Do-nothing - break; - - case 9: - // - // Root Complex Integrated Endpoint - // - // Do-nothing - break; - - case 10: - // - // Root Complex Event Collector - // - // Do-nothing - break; - - default: - break; - } - // - // switch(DevicePortType) - // - } - // - // Fun - // - } - // - // Dev - // - } - // - // Bus - // -} - -static -VOID -Stall ( - UINTN Usec - ) -{ - UINTN Index; - UINT32 Data32; - UINT32 PrevData; - UINTN Counter; - - Counter =3D (UINTN) ((Usec * 10) / 3); - // - // Call WaitForTick for Counter + 1 ticks to try to guarantee Counter ti= ck - // periods, thus attempting to ensure Microseconds of stall time. - // - if (Counter !=3D 0) { - - PrevData =3D IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_= TMR); - for (Index =3D 0; Index < Counter;) { - Data32 =3D IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_= TMR); - if (Data32 < PrevData) { - // - // Reset if there is a overlap - // - PrevData =3D Data32; - continue; - } - - Index +=3D (Data32 - PrevData); - PrevData =3D Data32; - } - } - - return ; -} -/** - Called during Sx entry, initates TbtSetPcie2TbtCommand HandShake to set = GO2SX_NO_WAKE - for Tbt devices if WakeupSupport is not present. - - @param[in] DispatchHandle - The unique handle assigned to this h= andler by SmiHandlerRegister(). - @param[in] DispatchContext - Points to an optional handler contex= t which was specified when the - handler was registered. - @param[in, out] CommBuffer - A pointer to a collection of data in= memory that will - be conveyed from a non-SMM environme= nt into an SMM environment. - @param[in, out] CommBufferSize - The size of the CommBuffer. - - @retval EFI_SUCCESS - The interrupt was handled successful= ly. -**/ -EFI_STATUS -EFIAPI -SxDTbtEntryCallback ( - IN EFI_HANDLE DispatchHandle, - IN CONST VOID *DispatchContext, - IN OUT VOID *CommBuffer OPTIONAL, - IN UINTN *CommBufferSize OPTIONAL - ) -{ - UINT16 DeviceId; - UINT8 CableConnected; - UINT8 RootportSelected; - UINT8 HoustRouteBus; - volatile UINT32 *PowerState; - UINT32 PowerStatePrev; - BOOLEAN SecSubBusAssigned; - UINT64 DeviceBaseAddress; - UINT8 CapHeaderOffset; - UINTN RpDev; - UINTN RpFunc; - EFI_STATUS Status; - UINT32 Timeout; - UINT32 RegisterValue; - UINT64 Tbt2Pcie; - UINTN Index; - UINT32 TbtCioPlugEventGpioNo; - UINT32 TbtFrcPwrGpioNo; - UINT8 TbtFrcPwrGpioLevel; - UINT32 TbtPcieRstGpioNo; - UINT8 TbtPcieRstGpioLevel; - EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext; - - CableConnected =3D 0; - HoustRouteBus =3D 3; - SecSubBusAssigned =3D FALSE; - Timeout =3D 600; - RootportSelected =3D 0; - TbtCioPlugEventGpioNo =3D 0; - TbtFrcPwrGpioNo =3D 0; - TbtFrcPwrGpioLevel =3D 0; - TbtPcieRstGpioNo =3D 0; - TbtPcieRstGpioLevel =3D 0; - Index =3D 0; - - EntryDispatchContext =3D (EFI_SMM_SX_REGISTER_CONTEXT*) DispatchContext; - -// CableConnected =3D GetTbtHostRouterStatus (); - //SaveTbtHostRouterStatus (CableConnected & 0xF0); - // - // Get the Power State and Save - // - if (((mTbtNvsAreaPtr->DTbtControllerEn0 =3D=3D 0) && (Index =3D=3D 0))) = { - - RootportSelected =3D mTbtNvsAreaPtr->RootportSelected0; - TbtCioPlugEventGpioNo =3D mTbtNvsAreaPtr->TbtCioPlugEventGpioNo0; - TbtFrcPwrGpioNo =3D mTbtNvsAreaPtr->TbtFrcPwrGpioNo0; - TbtFrcPwrGpioLevel =3D mTbtNvsAreaPtr->TbtFrcPwrGpioLevel0; - TbtPcieRstGpioNo =3D mTbtNvsAreaPtr->TbtPcieRstGpioNo0; - TbtPcieRstGpioLevel =3D mTbtNvsAreaPtr->TbtPcieRstGpioLevel0; - } - - Status =3D GetDTbtRpDevFun (gCurrentDiscreteTbtRootPortType, RootportSel= ected - 1, &RpDev, &RpFunc); - ASSERT_EFI_ERROR (Status); - CapHeaderOffset =3D PcieFindCapId (TbtSegment, 0x00, (UINT8)RpDev, (UINT= 8)RpFunc, 0x01); - DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, 0x00, (UINT32= )RpDev, (UINT32)RpFunc, 0); - PowerState =3D &*((volatile UINT32 *) (mPciExpressBaseAddress + D= eviceBaseAddress + CapHeaderOffset + 4)); //PMCSR - PowerStatePrev =3D *PowerState; - *PowerState &=3D 0xFFFFFFFC; - - HoustRouteBus =3D PciSegmentRead8 (DeviceBaseAddress + PCI_BRIDGE_SECOND= ARY_BUS_REGISTER_OFFSET); - // - // Check the Subordinate bus .If it is Zero ,assign temporary bus to - // find the device presence . - // - if (HoustRouteBus =3D=3D 0) { - PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTE= R_OFFSET, 0xF0); - PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIS= TER_OFFSET, 0xF0); - HoustRouteBus =3D 0xF0; - SecSubBusAssigned =3D TRUE; - } - // - // Clear Interrupt capability of TBT CIO Plug Event Pin to make sure no = SCI is getting generated, - // This GPIO will be reprogrammed while resuming as part of Platform GPI= O Programming. - // - GpioSetPadInterruptConfig (TbtCioPlugEventGpioNo, GpioIntDis); - // - // Read the TBT Host router DeviceID - // - DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Hous= tRouteBus, 0, 0, PCI_DEVICE_ID_OFFSET)); - - // - // Check For HostRouter Presence - // - if (IsTbtHostRouter (DeviceId)) { - // CableConnected =3D GetTbtHostRouterStatus (); - if (!((CableConnected & (DTBT_SAVE_STATE_OFFSET << Index)) =3D=3D (DTB= T_SAVE_STATE_OFFSET << Index))) { - CableConnected =3D CableConnected | (DTBT_SAVE_STATE_OFFSET << Index= ); - // SaveTbtHostRouterStatus (CableConnected); - } - } - - // - // Check value of Tbt2Pcie reg, if Tbt is not present, bios needs to app= ly force power prior to sending mailbox command - // - GET_TBT2PCIE_REGISTER_ADDRESS(TbtSegment, HoustRouteBus, 0x00, 0x00, Tbt= 2Pcie) - RegisterValue =3D PciSegmentRead32 (Tbt2Pcie); - if (0xFFFFFFFF =3D=3D RegisterValue) { - - GpioWrite (TbtFrcPwrGpioNo,TbtFrcPwrGpioLevel); - - while (Timeout -- > 0) { - RegisterValue =3D PciSegmentRead32 (Tbt2Pcie); - if (0xFFFFFFFF !=3D RegisterValue) { - break; - } - Stall(1* (UINTN)1000); - } - // - // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox = command for AIC. - // However BIOS shall not execute go2sx mailbox command on S5/reboot c= ycle. - // - - if( (EntryDispatchContext->Type =3D=3D SxS3) || (EntryDispatchContext-= >Type =3D=3D SxS4)) - { - if(!mTbtNvsAreaPtr->TbtWakeupSupport) { - //Wake Disabled, GO2SX_NO_WAKE Command - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0= , TBT_5S_TIMEOUT); - } else { - //Wake Enabled, GO2SX Command - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S= _TIMEOUT); - } - } - if (mTbtNvsAreaPtr->TbtFrcPwrEn =3D=3D 0) { - GpioWrite (TbtFrcPwrGpioNo,!(TbtFrcPwrGpioLevel)); - } - } else { - // - // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox = command for AIC. - // However BIOS shall not execute go2sx mailbox command on S5/reboot c= ycle. - // - if( (EntryDispatchContext->Type =3D=3D SxS3) || (EntryDispatchContext-= >Type =3D=3D SxS4)) - { - if(!mTbtNvsAreaPtr->TbtWakeupSupport) { - //Wake Disabled, GO2SX_NO_WAKE Command - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0= , TBT_5S_TIMEOUT); - } else { - //Wake Enabled, GO2SX Command - TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S= _TIMEOUT); - } - } - } - *PowerState =3D PowerStatePrev; - // - // Restore the bus number in case we assigned temporarily - // - if (SecSubBusAssigned) { - PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTE= R_OFFSET, 0x00); - PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIS= TER_OFFSET, 0x00); - } - if (gDTbtPcieRstSupport) { - GpioWrite (TbtPcieRstGpioNo,TbtPcieRstGpioLevel); - } - return EFI_SUCCESS; -} - -VOID -ThunderboltSwSmiCallback ( - IN UINT8 Type - ) -{ - UINT8 ThunderboltSmiFunction; - - DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Entry\n")); - ThunderboltSmiFunction =3D mTbtNvsAreaPtr->ThunderboltSmiFunction; - DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback. ThunderboltSmiFunction=3D= %d\n", ThunderboltSmiFunction)); - if (Type =3D=3D DTBT_CONTROLLER) { - gCurrentDiscreteTbtRootPort =3D mTbtNvsAreaPtr->CurrentDiscreteTbt= RootPort; - gCurrentDiscreteTbtRootPortType =3D mTbtNvsAreaPtr->CurrentDiscreteTbt= RootPortType; - } - - switch (ThunderboltSmiFunction) { - case 21: - ThunderboltCallback (Type); - break; - - case 22: - TbtDisablePCIDevicesAndBridges (Type); - break; - - case 23: - ConfigureTbtAspm (Type, (UINT16) 0x02); - break; - - case 24: - ConfigureTbtAspm (Type, (UINT16) 0x01); - break; - - default: - break; - } - DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Exit.\n")); -} -STATIC -EFI_STATUS -EFIAPI -DiscreteThunderboltSwSmiCallback ( - IN EFI_HANDLE DispatchHandle, - IN CONST VOID *DispatchContext, - IN OUT VOID *CommBuffer OPTIONAL, - IN UINTN *CommBufferSize OPTIONAL - ) -{ - ThunderboltSwSmiCallback(DTBT_CONTROLLER); - return EFI_SUCCESS; -} -EFI_STATUS -TbtRegisterHandlers ( - IN BOOLEAN Type - ) -{ - EFI_STATUS Status; - UINTN SmiInputValue; - EFI_SMM_HANDLER_ENTRY_POINT2 SxHandler; - EFI_SMM_HANDLER_ENTRY_POINT2 SwHandler; - EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatchProtocol; - EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch; - EFI_SMM_SX_REGISTER_CONTEXT EntryDispatchContext; - EFI_SMM_SW_REGISTER_CONTEXT SwContext; - EFI_HANDLE SwDispatchHandle; - EFI_HANDLE S3DispatchHandle; - EFI_HANDLE S4DispatchHandle; - EFI_HANDLE S5DispatchHandle; - - Status =3D EFI_UNSUPPORTED; - - if(Type =3D=3D DTBT_CONTROLLER) { - SxHandler =3D SxDTbtEntryCallback; - SwHandler =3D DiscreteThunderboltSwSmiCallback; - SmiInputValue =3D PcdGet8 (PcdSwSmiDTbtEnumerate); - gDTbtPcieRstSupport =3D gTbtInfoHob->DTbtCommonConfig.PcieRstSupport; - Status =3D EFI_SUCCESS; - } - if (EFI_ERROR (Status)) { - return Status; - } - - SwDispatchHandle =3D NULL; - S3DispatchHandle =3D NULL; - S4DispatchHandle =3D NULL; - S5DispatchHandle =3D NULL; - - Status =3D gSmst->SmmLocateProtocol ( - &gEfiSmmSxDispatch2ProtocolGuid, - NULL, - (VOID **) &SxDispatchProtocol - ); - ASSERT_EFI_ERROR (Status); - // - // Register S3 entry phase call back function - // - EntryDispatchContext.Type =3D SxS3; - EntryDispatchContext.Phase =3D SxEntry; - Status =3D SxDispatchProtocol->Register ( - SxDispatchProtocol, - SxHandler, - &EntryDispatchContext, - &S3DispatchHandle - ); - ASSERT_EFI_ERROR (Status); - // - // Register S4 entry phase call back function - // - EntryDispatchContext.Type =3D SxS4; - EntryDispatchContext.Phase =3D SxEntry; - Status =3D SxDispatchProtocol->Register ( - SxDispatchProtocol, - SxHandler, - &EntryDispatchContext, - &S4DispatchHandle - ); - ASSERT_EFI_ERROR (Status); - // - // Register S5 entry phase call back function - // - EntryDispatchContext.Type =3D SxS5; - EntryDispatchContext.Phase =3D SxEntry; - Status =3D SxDispatchProtocol->Register ( - SxDispatchProtocol, - SxHandler, - &EntryDispatchContext, - &S5DispatchHandle - ); - ASSERT_EFI_ERROR (Status); - // - // Locate the SMM SW dispatch protocol - // - Status =3D gSmst->SmmLocateProtocol ( - &gEfiSmmSwDispatch2ProtocolGuid, - NULL, - (VOID **) &SwDispatch - ); - - ASSERT_EFI_ERROR (Status); - // - // Register SWSMI handler - // - SwContext.SwSmiInputValue =3D SmiInputValue; - Status =3D SwDispatch->Register ( - SwDispatch, - SwHandler, - &SwContext, - &SwDispatchHandle - ); - ASSERT_EFI_ERROR (Status); - - return Status; -} -EFI_STATUS -InSmmFunction ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - - Status =3D EFI_SUCCESS; - - Status =3D TbtRegisterHandlers(DTBT_CONTROLLER); - return Status; -} - -EFI_STATUS -EFIAPI -TbtSmmEntryPoint ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol; - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "TbtSmmEntryPoint\n")); - - mPciExpressBaseAddress =3D PcdGet64 (PcdPciExpressBaseAddress); - // - // Locate Tbt shared data area - // - Status =3D gBS->LocateProtocol (&gTbtNvsAreaProtocolGuid, NULL, (VOID **= ) &TbtNvsAreaProtocol); - ASSERT_EFI_ERROR (Status); - mTbtNvsAreaPtr =3D TbtNvsAreaProtocol->Area; - - // - // Get TBT INFO HOB - // - gTbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid); - if (gTbtInfoHob =3D=3D NULL) { - return EFI_NOT_FOUND; - } - - return InSmmFunction (ImageHandle, SystemTable); -} - -VOID -EndOfThunderboltCallback ( - IN UINTN RpSegment, - IN UINTN RpBus, - IN UINTN RpDevice, - IN UINTN RpFunction - ) -{ - if(mTbtNvsAreaPtr->TbtL1SubStates !=3D 0) { - ThunderboltEnableL1Sub (mTbtNvsAreaPtr->TbtL1SubStates, RpSegment, RpB= us, RpDevice, RpFunction); - } - ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 1); - if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case - ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFuncti= on); - } else { //Aspm enable case - ThunderboltEnableAspmWithoutLtr ((UINT16)mTbtNvsAreaPtr->TbtAspm, RpSe= gment, RpBus, RpDevice, RpFunction); - } - - if (mTbtNvsAreaPtr->TbtLtr) { - ThunderboltGetLatencyLtr (); - ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction); - } - ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction); - ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 2); -} // EndOfThunderboltCallback - -VOID -ConfigureTbtAspm ( - IN UINT8 Type, - IN UINT16 Aspm - ) -{ - UINTN RpSegment =3D 0; - UINTN RpBus =3D 0; - UINTN RpDevice; - UINTN RpFunction; - - if(Type =3D=3D DTBT_CONTROLLER) { - if (gCurrentDiscreteTbtRootPort =3D=3D 0) { - return; - } - GetDTbtRpDevFun(DTBT_CONTROLLER, gCurrentDiscreteTbtRootPort - 1, &RpD= evice, &RpFunction); - - ConfigureTbtPm (RpSegment, RpBus, RpDevice, RpFunction, 1); - if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case - ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFunc= tion); - } else { //Aspm enable case - ThunderboltEnableAspmWithoutLtr ((UINT16) Aspm, RpSegment, RpBus, Rp= Device, RpFunction); - } - - if (mTbtNvsAreaPtr->TbtLtr) { - ThunderboltGetLatencyLtr (); - ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction); - } - ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction); - } // EndOfThunderboltCallback -} \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/B= aseGpioExpanderLib.c b/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExp= anderLib/BaseGpioExpanderLib.c deleted file mode 100644 index cc70f15c24..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpio= ExpanderLib.c +++ /dev/null @@ -1,306 +0,0 @@ -/** @file - Support for IO expander TCA6424. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include - -// -// Addresses of registers inside expander -// -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mInputRegister[3] =3D {0x0,0x1,0x2= }; -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mOutputRegister[3] =3D {0x4,0x5,0x6= }; -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mConfigRegister[3] =3D {0xC,0xD,0xE= }; -GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPolarityRegister[3] =3D {0x8,0x9,0xA= }; - -#define PCH_SERIAL_IO_I2C4 4 -#define TCA6424_I2C_ADDRESS 0x22 -#define PINS_PER_REGISTER 8 -#define GPIO_EXP_PIN_DIRECTION_OUT 1 -#define GPIO_EXP_PIN_DIRECTION_IN 0 -#define GPIO_EXP_PIN_POLARITY_NORMAL 0 -#define GPIO_EXP_PIN_POLARITY_INVERTED 1 -#define GPIO_EXP_SET_OUTPUT 0 -#define GPIO_EXP_SET_DIR 1 -#define GPIO_EXP_GET_INPUT 2 -#define GPIO_EXP_SET_POLARITY 3 -#define AUTO_INCREMENT 0x80 - -/** - Returns the Controller on which GPIO expander is present. - - This function returns the Controller value - - @param[out] Controller Pointer to a Controller value on - which I2C expander is configured. - - @retval EFI_SUCCESS non. -**/ -EFI_STATUS -GpioExpGetController ( - OUT UINT8 *Controller - ) -{ - *Controller =3D PCH_SERIAL_IO_I2C4; - return EFI_SUCCESS; -} - -/** - Returns the data from register value giving in the input. - - This function is to get the data from the Expander - Registers by following the I2C Protocol communication - - - @param[in] Bar0 Bar address of the SerialIo Controller - @param[in] Address Expander Value with in the Contoller - @param[in] Register Address of Input/Output/Configure/Polarity - registers with in the Expander - - @retval UINT8 Value returned from the register -**/ -UINT8 -GpioExpGetRegister ( - IN UINTN Bar0, - IN UINT8 Address, - IN UINT8 Register - ) -{ - UINT8 WriBuf[1]; - UINT8 ReBuf[1] =3D {0}; - - WriBuf[0] =3D Register; - I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 1, WriBuf, 1, ReBuf, = WAIT_1_SECOND); - - return ReBuf[0]; -} -/** - Set the input register to a give value mentioned in the function. - - This function is to Programm the data value to the Expander - Register by following the I2C Protocol communication. - - @param[in] Bar0 Bar address of the SerialIo Controller - @param[in] Address Expander Value with in the Contoller - @param[in] Register Address of Input/Output/Configure/Polarity - registers with in the Expander - @param[in] Value Value to set in the mentioned the register -**/ -VOID -GpioExpSetRegister ( - IN UINTN Bar0, - IN UINT8 Address, - IN UINT8 Register, - IN UINT8 Value - ) -{ - UINT8 WriBuf[2]; - - WriBuf[0] =3D Register; - WriBuf[1] =3D Value; - I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 2, WriBuf, 0, NULL, W= AIT_1_SECOND); -} -/** - Set the input register to a give value mentioned in the function. - - This function is to update the status of the Gpio Expander - pin based on the input Operation value of the caller.This - function calculates the exact address of the register with - the help of the Register Bank - - @param[in] Controller SerialIo Controller value - @param[in] Expander Expander Value with in the Contoller - @param[in] Pin Pin with in the Expnader Value - @param[in] Value none - @param[in] Operation Type of operation (Setoutput/Setdirection - /Getinput/Setpolarity) - @retval UINT8 Final Value returned from the register -**/ -UINT8 -GpioExpDecodeRegAccess ( - IN UINT8 Controller, - IN UINT8 Expander, - IN UINT8 Pin, - IN UINT8 Value, - IN UINT8 Operation - ) -{ - UINT8* RegisterBank; - UINT8 OldValue; - UINT8 NewValue; - UINT8 RegisterAddress; - UINT8 PinNumber; - UINT8 ReturnValue =3D 0; - - DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n", Control= ler, Expander, Pin, Value, Operation)); - ASSERT(Controller<6); - ASSERT(Expander<2); - ASSERT(Pin<24); - ASSERT(Value<2); - ASSERT(Operation<4); - // - // Find the register Address value based on the OPeration - // - switch(Operation) { - case GPIO_EXP_SET_OUTPUT: - RegisterBank =3D mOutputRegister; - break; - case GPIO_EXP_SET_DIR: - RegisterBank =3D mConfigRegister; - break; - case GPIO_EXP_GET_INPUT: - RegisterBank =3D mInputRegister; - break; - case GPIO_EXP_SET_POLARITY: - RegisterBank =3D mPolarityRegister; - break; - default: - ASSERT(FALSE); - return 0; - } - // - // Each bit of register represents each Pin - // calaulate the register address and Pinnumber(offset with in register) - // - if (Pin >=3D 24) { - // - // Avoid out-of-bound usage of RegisterBank - // - return 0; - } - - RegisterAddress =3D RegisterBank[(Pin/PINS_PER_REGISTER)]; - PinNumber =3D Pin%PINS_PER_REGISTER; - - OldValue =3D GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expander= , RegisterAddress); - // - // If it to get the data ,just returned otherwise mark the input value a= nd write the register - // - if (Operation =3D=3D GPIO_EXP_GET_INPUT) { - ReturnValue =3D 0x1 & (OldValue>>PinNumber); - } else { - NewValue =3D OldValue; - NewValue &=3D ~(BIT0<>8) & 0xFF; - WriteBuf[3] =3D (Output>>16) & 0xFF; - I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); - WriteBuf[0] =3D mPolarityRegister[0] + AUTO_INCREMENT; - WriteBuf[1] =3D Polarity & 0xFF; - WriteBuf[2] =3D (Polarity>>8) & 0xFF; - WriteBuf[3] =3D (Polarity>>16) & 0xFF; - I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); - WriteBuf[0] =3D mConfigRegister[0] + AUTO_INCREMENT; - WriteBuf[1] =3D Direction & 0xFF; - WriteBuf[2] =3D (Direction>>8) & 0xFF; - WriteBuf[3] =3D (Direction>>16) & 0xFF; - I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); - -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2= cAccessLib.c b/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/Pei= I2cAccessLib.c deleted file mode 100644 index d66571bdc4..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAccess= Lib.c +++ /dev/null @@ -1,115 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include - -EFI_STATUS -I2cWriteRead ( - IN UINTN MmioBase, - IN UINT8 SlaveAddress, - IN UINT8 WriteLength, - IN UINT8 *WriteBuffer, - IN UINT8 ReadLength, - IN UINT8 *ReadBuffer, - IN UINT64 TimeBudget - //TODO: add Speed parameter - ) -{ - UINT8 ReadsNeeded =3D ReadLength; - UINT64 CutOffTime; - - if ((WriteLength =3D=3D 0 && ReadLength =3D=3D 0) || - (WriteLength !=3D 0 && WriteBuffer =3D=3D NULL) || - (ReadLength !=3D 0 && ReadBuffer =3D=3D NULL) ) { - DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n")); - return EFI_INVALID_PARAMETER; - } - - // - // Sanity checks to verify the I2C controller is alive - // Conveniently, ICON register's values of 0 or FFFFFFFF indicate - // I2c controller is out-of-order: either disabled, in D3 or in reset. - // - if (MmioRead32(MmioBase+R_IC_CON) =3D=3D 0xFFFFFFFF || MmioRead32(MmioBa= se+R_IC_CON) =3D=3D 0x0) { - DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n")); - return EFI_DEVICE_ERROR; - } - - MmioWrite32(MmioBase+R_IC_ENABLE, 0x0); - MmioRead32(MmioBase+0x40); - MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); - MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C); - // - // Set I2C Bus Speed at 400 kHz for GPIO Expander - // - MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128); - MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160); - MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress); - MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE | V_IC_SPEED_FAST | B_= IC_RESTART_EN | B_IC_SLAVE_DISABLE ); - MmioWrite32(MmioBase+R_IC_ENABLE, 0x1); - CutOffTime =3D AsmReadTsc() + TimeBudget; - - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D0 ) { - if (AsmReadTsc() > CutOffTime) { - DEBUG ((DEBUG_ERROR, "I2cWR timeout\n")); - return EFI_TIMEOUT; - } - } - - while(1) { - if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) { - DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason =3D 0x%08x\n",M= mioRead32(MmioBase+R_IC_TX_ABRT_SOURCE))); - MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); - MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} - return EFI_DEVICE_ERROR; - } - if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) { - if (WriteLength > 1) { - MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); - WriteBuffer++; - WriteLength--; - } else if (WriteLength=3D=3D1 && ReadLength !=3D 0) { - MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); - WriteBuffer++; - WriteLength--; - } else if (WriteLength=3D=3D1 && ReadLength =3D=3D 0) { - MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer | B_IC_CMD_STOP); - WriteBuffer++; - WriteLength--; - } else if (ReadLength > 1) { - MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ); - ReadLength--; - } else if (ReadLength =3D=3D 1) { - MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ|B_IC_CMD_STOP); - ReadLength--; - } - } - - if (ReadsNeeded) { - if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) { - *ReadBuffer =3D (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD); - ReadBuffer++; - ReadsNeeded--; - } - } - if (WriteLength=3D=3D0 && ReadsNeeded=3D=3D0 && !(MmioRead32(MmioBase+= R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) { - MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} - DEBUG ((DEBUG_INFO, "I2cWR success\n")); - return EFI_SUCCESS; - } - if (AsmReadTsc() > CutOffTime) { - MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); - while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} - DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n")); - return EFI_TIMEOUT; - } - - } -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFl= ash/PeiSerialPortLibSpiFlash.c b/Platform/Intel/ClevoOpenBoardPkg/Library/P= eiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.c deleted file mode 100644 index 0230149a38..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/Pei= SerialPortLibSpiFlash.c +++ /dev/null @@ -1,320 +0,0 @@ -/** @file - Serial I/O Port library implementation for output to SPI flash - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -typedef struct { - PCH_SPI_PPI *PchSpiPpi; - UINT32 CurrentWriteOffset; -} SPI_FLASH_DEBUG_CONTEXT; - -/** - Update reference to the most recent PCH SPI PPI installed - - @param PeiServices An indirect pointer to the EFI_PEI_SERVICES tab= le published by the PEI Foundation - @param NotifyDescriptor Address of the notification descriptor data str= ucture. - @param Ppi Address of the PPI that was installed. - - @retval EFI_SUCCESS Successfully update the PCH SPI PPI reference - @retval EFI_NOT_FOUND An error occurred locating a required interface - @retval EFI_NOT_SUPPORTED - -**/ -EFI_STATUS -EFIAPI -SpiPpiNotifyCallback ( - IN EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, - IN VOID *Ppi - ) -{ - EFI_STATUS Status; - EFI_HOB_GUID_TYPE *GuidHob; - PCH_SPI_PPI *PchSpiPpi; - SPI_FLASH_DEBUG_CONTEXT *Context; - - GuidHob =3D GetFirstGuidHob (&gSpiFlashDebugHobGuid); - if (GuidHob =3D=3D NULL) { - return EFI_NOT_FOUND; - } - Context =3D GET_GUID_HOB_DATA (GuidHob); - - Status =3D PeiServicesLocatePpi ( - &gPchSpiPpiGuid, - 0, - NULL, - (VOID **) &PchSpiPpi - ); - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - Context->PchSpiPpi =3D PchSpiPpi; - - return EFI_SUCCESS; -} - -EFI_PEI_NOTIFY_DESCRIPTOR mSpiPpiNotifyList[] =3D { - { - (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMI= NATE_LIST), - &gPchSpiPpiGuid, - SpiPpiNotifyCallback - } -}; - -/** - Common function to write trace data to a chosen debug interface like - UART Serial device, USB Serial device or Trace Hub device - - @param Buffer Point of data buffer which need to be writed. - @param NumberOfBytes Number of output bytes which are cached in Buff= er. - -**/ -UINTN -EFIAPI -SerialPortWrite ( - IN UINT8 *Buffer, - IN UINTN NumberOfBytes - ) -{ - EFI_STATUS Status; - EFI_HOB_GUID_TYPE *GuidHob; - SPI_FLASH_DEBUG_CONTEXT *Context; - UINT32 BytesWritten; - UINT32 SourceBufferOffset; - UINT32 NvMessageAreaSize; - UINT32 LinearOffset; - - BytesWritten =3D NumberOfBytes; - SourceBufferOffset =3D 0; - - NvMessageAreaSize =3D (UINT32) FixedPcdGet32 (PcdFlashNvDebugMessageSize= ); - - if (NumberOfBytes =3D=3D 0 || NvMessageAreaSize =3D=3D 0) { - return 0; - } - GuidHob =3D GetFirstGuidHob (&gSpiFlashDebugHobGuid); - if (GuidHob =3D=3D NULL) { - return 0; - } - Context =3D GET_GUID_HOB_DATA (GuidHob); - if (Context =3D=3D NULL || Context->PchSpiPpi =3D=3D NULL || Context->Cu= rrentWriteOffset >=3D NvMessageAreaSize) { - return 0; - } - - if ((Context->CurrentWriteOffset + NumberOfBytes) / NvMessageAreaSize > = 0) { - LinearOffset =3D (UINT32) (FixedPcdGet32 (PcdFlashNvDebugMessageBase) = - FixedPcdGet32 (PcdFlashAreaBaseAddress)); - Status =3D Context->PchSpiPpi->FlashErase ( - Context->PchSpiPpi, - FlashRegionBios, - LinearOffset, - NvMessageAreaSize - ); - if (!EFI_ERROR (Status)) { - Context->CurrentWriteOffset =3D 0; - } else { - return 0; - } - } - - if (NumberOfBytes > NvMessageAreaSize) { - BytesWritten =3D NvMessageAreaSize; - SourceBufferOffset =3D NumberOfBytes - NvMessageAreaSize; - } - - LinearOffset =3D (FixedPcdGet32 (PcdFlashNvDebugMessageBase) + Context->= CurrentWriteOffset) - FixedPcdGet32 (PcdFlashAreaBaseAddress); - - Status =3D Context->PchSpiPpi->FlashWrite ( - Context->PchSpiPpi, - FlashRegionBios, - LinearOffset, - BytesWritten, - (UINT8 *) &Buffer[SourceBufferOffset] - ); - if (!EFI_ERROR (Status)) { - Context->CurrentWriteOffset +=3D BytesWritten; - return BytesWritten; - } - - return 0; -} - -/** - Common function to Read data from UART serial device, USB serial device = and save the datas in buffer. - - @param Buffer Point of data buffer which need to be writed. - @param NumberOfBytes Number of output bytes which are cached in Buff= er. - - @retval 0 Read data failed, no data is to be read. - @retval >0 Actual number of bytes read from debug device. - -**/ -UINTN -EFIAPI -SerialPortRead ( - OUT UINT8 *Buffer, - IN UINTN NumberOfBytes -) -{ - return 0; -} - -/** - Polls a serial device to see if there is any data waiting to be read. - - Polls a serial device to see if there is any data waiting to be read. - If there is data waiting to be read from the serial device, then TRUE is= returned. - If there is no data waiting to be read from the serial device, then FALS= E is returned. - - @retval TRUE Data is waiting to be read from the serial devi= ce. - @retval FALSE There is no data waiting to be read from the se= rial device. - -**/ -BOOLEAN -EFIAPI -SerialPortPoll ( - VOID - ) -{ - return FALSE; -} - -/** - Sets the control bits on a serial device. - - @param Control Sets the bits of Control that are settable= . - - @retval RETURN_SUCCESS The new control bits were set on the seria= l device. - @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. - @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortSetControl ( - IN UINT32 Control - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Retrieve the status of the control bits on a serial device. - - @param Control A pointer to return the current control si= gnals from the serial device. - - @retval RETURN_SUCCESS The control bits were read from the serial= device. - @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. - @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortGetControl ( - OUT UINT32 *Control - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Sets the baud rate, receive FIFO depth, transmit/receice time out, parit= y, - data bits, and stop bits on a serial device. - - @param BaudRate The requested baud rate. A BaudRate value of 0= will use the - device's default interface speed. - On output, the value actually set. - @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side of the - serial interface. A ReceiveFifoDepth value of = 0 will use - the device's default FIFO depth. - On output, the value actually set. - @param Timeout The requested time out for a single character = in microseconds. - This timeout applies to both the transmit and = receive side of the - interface. A Timeout value of 0 will use the d= evice's default time - out value. - On output, the value actually set. - @param Parity The type of parity to use on this serial devic= e. A Parity value of - DefaultParity will use the device's default pa= rity value. - On output, the value actually set. - @param DataBits The number of data bits to use on the serial d= evice. A DataBits - vaule of 0 will use the device's default data = bit setting. - On output, the value actually set. - @param StopBits The number of stop bits to use on this serial = device. A StopBits - value of DefaultStopBits will use the device's= default number of - stop bits. - On output, the value actually set. - - @retval RETURN_SUCCESS The new attributes were set on the ser= ial device. - @retval RETURN_UNSUPPORTED The serial device does not support thi= s operation. - @retval RETURN_INVALID_PARAMETER One or more of the attributes has an u= nsupported value. - @retval RETURN_DEVICE_ERROR The serial device is not functioning c= orrectly. - -**/ -RETURN_STATUS -EFIAPI -SerialPortSetAttributes ( - IN OUT UINT64 *BaudRate, - IN OUT UINT32 *ReceiveFifoDepth, - IN OUT UINT32 *Timeout, - IN OUT EFI_PARITY_TYPE *Parity, - IN OUT UINT8 *DataBits, - IN OUT EFI_STOP_BITS_TYPE *StopBits - ) -{ - return EFI_UNSUPPORTED; -} - -/** - Initialize the serial device hardware. - - If no initialization is required, then return RETURN_SUCCESS. - If the serial device was successfully initialized, then return RETURN_SU= CCESS. - If the serial device could not be initialized, then return RETURN_DEVICE= _ERROR. - - @retval RETURN_SUCCESS The serial device was initialized. - @retval RETURN_DEVICE_ERROR The serial device could not be initialized= . - -**/ -RETURN_STATUS -EFIAPI -SerialPortInitialize ( - VOID - ) -{ - EFI_STATUS Status; - SPI_FLASH_DEBUG_CONTEXT *Context; - - Context =3D (SPI_FLASH_DEBUG_CONTEXT *) BuildGuidHob (&gSpiFlashDebugHob= Guid, sizeof (SPI_FLASH_DEBUG_CONTEXT)); - if (Context =3D=3D NULL) { - return EFI_DEVICE_ERROR; - } - ZeroMem ((VOID *) Context, sizeof (SPI_FLASH_DEBUG_CONTEXT)); - - Status =3D PeiServicesNotifyPpi (&mSpiPpiNotifyList[0]); - if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; - } - - // - // Perform silicon specific initialization required to enable write to S= PI flash. - // - Status =3D SpiServiceInit (); - if (EFI_ERROR (Status)) { - Status =3D EFI_DEVICE_ERROR; - } - - return Status; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c b/Platform/Intel/C= levoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPre= MemSiliconPolicyNotifyLib.c deleted file mode 100644 index 0fedd81cd0..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c +++ /dev/null @@ -1,103 +0,0 @@ -/** @file - This library implements constructor function to register notify call bac= k - when policy PPI installed. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#include -#include -#include -#include -#include - -/** - Callback function to update policy when policy PPI installed. - - @param[in] PeiServices General purpose services available to ev= ery PEIM. - @param[in] NotifyDescriptor The notification structure this PEIM reg= istered on install. - @param[in] Ppi The memory discovered PPI. Not used. - - @retval EFI_SUCCESS Succeeds. - @retval Others Error code returned by sub-functions. -**/ -EFI_STATUS -EFIAPI -SiPreMemPolicyPpiNotify ( - IN EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, - IN VOID *Ppi - ) -{ - EFI_STATUS Status; - SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; - SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; - - DEBUG ((DEBUG_INFO, "SiPreMemPolicyPpiNotify() Start\n")); - - Status =3D PeiServicesLocatePpi ( - &gSiPreMemPolicyPpiGuid, - 0, - NULL, - (VOID **)&SiPreMemPolicyPpi - ); - ASSERT_EFI_ERROR (Status); - if (SiPreMemPolicyPpi !=3D NULL) { - // - // Get requisite IP Config Blocks which needs to be used here - // - Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreM= emConfigGuid, (VOID *) &MiscPeiPreMemConfig); - ASSERT_EFI_ERROR (Status); - - // - // Update SpdAddressTable policy when it is installed. - // - if (MiscPeiPreMemConfig !=3D NULL) { - MiscPeiPreMemConfig->SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddres= sTable0); - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[0] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[0])); - MiscPeiPreMemConfig->SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddres= sTable1); - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[1] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[1])); - MiscPeiPreMemConfig->SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddres= sTable2); - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[2] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[2])); - MiscPeiPreMemConfig->SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddres= sTable3); - DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[3] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[3])); - } - } - return Status; -} - -static EFI_PEI_NOTIFY_DESCRIPTOR mSiPreMemPolicyPpiNotifyList[] =3D { - { - EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMIN= ATE_LIST, - &gSiPreMemPolicyPpiGuid, - SiPreMemPolicyPpiNotify - } -}; - -/** - The library constructuor. - The function register a policy install notify callback. - - @param[in] ImageHandle The firmware allocated handle for the UEFI= image. - @param[in] SystemTable A pointer to the EFI system table. - - @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. - It will ASSERT on error for debug version. -**/ -EFI_STATUS -EFIAPI -PeiPreMemSiliconPolicyNotifyLibConstructor ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - // - // Register call back after PPI produced - // - Status =3D PeiServicesNotifyPpi (mSiPreMemPolicyPpiNotifyList); - ASSERT_EFI_ERROR (Status); - - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/ClevoOpenBoard= Pkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.= c deleted file mode 100644 index 7898dc3592..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PcieDeviceTable.c +++ /dev/null @@ -1,115 +0,0 @@ -/** @file - Intel PCH PEI Policy initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "PeiPchPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PCI_CLASS_NETWORK 0x02 -#define PCI_CLASS_NETWORK_ETHERNET 0x00 -#define PCI_CLASS_NETWORK_OTHER 0x80 - -GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D { - // - // Intel PRO/Wireless - // - { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel WiMAX/WiFi Link - // - { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Crane Peak WLAN NIC - // - { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Crane Peak w/BT WLAN NIC - // - { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Kelsey Peak WiFi, WiMax - // - { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 105 - // - { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 135 - // - { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 2200 - // - { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 2230 - // - { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel Centrino Wireless-N 6235 - // - { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel CampPeak 2 Wifi - // - { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - // - // Intel WilkinsPeak 1 Wifi - // - { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, - { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, - // - // Intel Wilkins Peak 2 Wifi - // - { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, - { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, - // - // Intel Wilkins Peak PF Wifi - // - { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, - - // - // End of Table - // - { 0 } -}; - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/ClevoOp= enBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMis= cUpdUpdateLib.c deleted file mode 100644 index 9d6c0176f6..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ /dev/null @@ -1,87 +0,0 @@ -/** @file - Implementation of Fsp Misc UPD Initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/** - Performs FSP Misc UPD initialization. - - @param[in][out] FspmUpd Pointer to FSPM_UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. -**/ -EFI_STATUS -EFIAPI -PeiFspMiscUpdUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - EFI_STATUS Status; - UINTN VariableSize; - VOID *MemorySavedData; - UINT8 MorControl; - VOID *MorControlPtr; - - // - // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. - // - VariableSize =3D 0; - MemorySavedData =3D NULL; - Status =3D PeiGetVariable ( - L"MemoryConfig", - &gFspNonVolatileStorageHobGuid, - &MemorySavedData, - &VariableSize - ); - DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid= - %r\n", Status)); - DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize)); - FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; - - if (FspmUpd->FspmArchUpd.NvsBufferPtr !=3D NULL) { - // - // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_P= MCON_A[23]), - // after memory Data is saved to NVRAM. - // - PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUN= CTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB); - } - - // - // MOR - // - MorControl =3D 0; - MorControlPtr =3D &MorControl; - VariableSize =3D sizeof (MorControl); - Status =3D PeiGetVariable ( - MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, - &gEfiMemoryOverwriteControlDataGuid, - &MorControlPtr, - &VariableSize - ); - DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { - FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); - } - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/ClevoOpe= nBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPoli= cyUpdateLib.c deleted file mode 100644 index c665f7888d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c +++ /dev/null @@ -1,186 +0,0 @@ -/** @file - Provides FSP policy update functionality. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/** - Performs FSP Misc UPD initialization. - - @param[in][out] FspmUpd Pointer to FSPM_UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. -**/ -EFI_STATUS -EFIAPI -PeiFspMiscUpdUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP PCH PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP PCH PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ); - -/** - Performs FSP SA PEI Policy initialization in pre-memory. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ); - -/** - Performs FSP SA PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ); - -VOID -InternalPrintVariableData ( - IN UINT8 *Data8, - IN UINTN DataSize - ) -{ - UINTN Index; - - for (Index =3D 0; Index < DataSize; Index++) { - if (Index % 0x10 =3D=3D 0) { - DEBUG ((DEBUG_INFO, "\n%08X:", Index)); - } - DEBUG ((DEBUG_INFO, " %02X", *Data8++)); - } - DEBUG ((DEBUG_INFO, "\n")); -} - -/** - Performs silicon pre-mem policy update. - - The meaning of Policy is defined by silicon code. - It could be the raw data, a handle, a PPI, etc. - - The input Policy must be returned by SiliconPolicyDonePreMem(). - - 1) In FSP path, the input Policy should be FspmUpd. - A platform may use this API to update the FSPM UPD policy initialized - by the silicon module or the default UPD data. - The output of FSPM UPD data from this API is the final UPD data. - - 2) In non-FSP path, the board may use additional way to get - the silicon policy data field based upon the input Policy. - - @param[in, out] Policy Pointer to policy. - - @return the updated policy. -**/ -VOID * -EFIAPI -SiliconPolicyUpdatePreMem ( - IN OUT VOID *FspmUpd - ) -{ - FSPM_UPD *FspmUpdDataPtr; - - FspmUpdDataPtr =3D FspmUpd; - PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr); - PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr); - PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); - - InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD)); - - return FspmUpd; -} - -/** - Performs silicon post-mem policy update. - - The meaning of Policy is defined by silicon code. - It could be the raw data, a handle, a PPI, etc. - - The input Policy must be returned by SiliconPolicyDonePostMem(). - - 1) In FSP path, the input Policy should be FspsUpd. - A platform may use this API to update the FSPS UPD policy initialized - by the silicon module or the default UPD data. - The output of FSPS UPD data from this API is the final UPD data. - - 2) In non-FSP path, the board may use additional way to get - the silicon policy data field based upon the input Policy. - - @param[in, out] Policy Pointer to policy. - - @return the updated policy. -**/ -VOID * -EFIAPI -SiliconPolicyUpdatePostMem ( - IN OUT VOID *FspsUpd - ) -{ - FSPS_UPD *FspsUpdDataPtr; - - FspsUpdDataPtr =3D FspsUpd; - PeiFspSaPolicyUpdate (FspsUpdDataPtr); - PeiFspPchPolicyUpdate (FspsUpdDataPtr); - - InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD)); - - return FspsUpd; -} - - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/ClevoOpenBo= ardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyU= pdate.c deleted file mode 100644 index 0bdd51d288..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiPchPolicyUpdate.c +++ /dev/null @@ -1,153 +0,0 @@ -/** @file - Intel PCH PEI Policy initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "PeiPchPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[]; - -/** - Add verb table helper function. - This function calculates verbtable number and shows verb table informati= on. - - @param[in,out] VerbTableEntryNum Input current VerbTable number and= output the number after adding new table - @param[in,out] VerbTableArray Pointer to array of VerbTable - @param[in] VerbTable VerbTable which is going to add in= to array -**/ -STATIC -VOID -InternalAddVerbTable ( - IN OUT UINT8 *VerbTableEntryNum, - IN OUT UINT32 *VerbTableArray, - IN HDAUDIO_VERB_TABLE *VerbTable - ) -{ - if (VerbTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable =3D= =3D NULL\n")); - return; - } - - VerbTableArray[*VerbTableEntryNum] =3D (UINT32) VerbTable; - *VerbTableEntryNum +=3D 1; - - DEBUG ((DEBUG_INFO, - "Add verb table for vendor =3D 0x%04X devId =3D 0x%04X (size =3D %d DW= ords)\n", - VerbTable->Header.VendorId, - VerbTable->Header.DeviceId, - VerbTable->Header.DataDwords) - ); -} - -enum HDAUDIO_CODEC_SELECT { - PchHdaCodecPlatformOnboard =3D 0, - PchHdaCodecExternalKit =3D 1 -}; - -/** - Add verb table function. - This function update the verb table number and verb table ptr of policy. - - @param[in] HdAudioConfig HDAudie config block - @param[in] CodecType Platform codec type indicator - @param[in] AudioConnectorType Platform audio connector type -**/ -STATIC -VOID -InternalAddPlatformVerbTables ( - IN OUT FSPS_UPD *FspsUpd, - IN UINT8 CodecType, - IN UINT8 AudioConnectorType - ) -{ - UINT8 VerbTableEntryNum; - UINT32 VerbTableArray[32]; - UINT32 *VerbTablePtr; - - VerbTableEntryNum =3D 0; - - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINT= N) PcdGet32 (PcdDisplayAudioHdaVerbTable)); - - if (CodecType =3D=3D PchHdaCodecPlatformOnboard) { - DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); - if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) !=3D NULL) { - if (AudioConnectorType =3D=3D 0) { //Type-C Audio connector selected= in Bios Setup menu - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)= (UINTN) PcdGet32 (PcdExtHdaVerbTable)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n")); - } else { //Stacked Jack Audio connector selected in Bios Setup menu - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)= (UINTN) PcdGet32 (PcdHdaVerbTable)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)= (UINTN) PcdGet32 (PcdHdaVerbTable2)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n= ")); - } - } else { - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (= UINTN) PcdGet32 (PcdHdaVerbTable)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (= UINTN) PcdGet32 (PcdHdaVerbTable2)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL); - } - } else { - DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UI= NTN) PcdGet32 (PcdCommonHdaVerbTable1)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UI= NTN) PcdGet32 (PcdCommonHdaVerbTable2)); - InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UI= NTN) PcdGet32 (PcdCommonHdaVerbTable3)); - } - - FspsUpd->FspsConfig.PchHdaVerbTableEntryNum =3D VerbTableEntryNum; - - VerbTablePtr =3D (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTabl= eEntryNum); - CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryN= um); - FspsUpd->FspsConfig.PchHdaVerbTablePtr =3D (UINT32) VerbTablePtr; -} - -/** - Performs FSP PCH PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - - FspsUpd->FspsConfig.PchSubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID; - FspsUpd->FspsConfig.PchSubSystemId =3D V_PCH_DEFAULT_SID; - - FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) mPcieDevi= ceTable; - - InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdG= et8 (PcdAudioConnector)); - -DEBUG_CODE_BEGIN(); -if ((PcdGet8 (PcdSerialIoUartDebugEnable) =3D=3D 1) && - FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 = (PcdSerialIoUartNumber)] =3D=3D PchSerialIoDisabled ) { - FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (P= cdSerialIoUartNumber)] =3D PchSerialIoLegacyUart; - } -DEBUG_CODE_END(); - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/Clevo= OpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchP= olicyUpdatePreMem.c deleted file mode 100644 index 5a62f9bb72..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c +++ /dev/null @@ -1,248 +0,0 @@ -/** @file - Intel PCH PEI Policy initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "PeiPchPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -VOID -InstallPlatformHsioPtssTable ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - HSIO_PTSS_TABLES *UnknowPtssTables; - HSIO_PTSS_TABLES *SpecificPtssTables; - HSIO_PTSS_TABLES *PtssTables; - UINT8 PtssTableIndex; - UINT32 UnknowTableSize; - UINT32 SpecificTableSize; - UINT32 TableSize; - UINT32 Entry; - UINT8 LaneNum; - UINT8 Index; - UINT8 MaxSataPorts; - UINT8 MaxPciePorts; - UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS]; - UINT8 PciePort; - UINTN RpBase; - UINTN RpDevice; - UINTN RpFunction; - UINT32 StrapFuseCfg; - UINT8 PcieControllerCfg; - EFI_STATUS Status; - - UnknowPtssTables =3D NULL; - UnknowTableSize =3D 0; - SpecificPtssTables =3D NULL; - SpecificTableSize =3D 0; - - if (GetPchGeneration () =3D=3D SklPch) { - switch (PchStepping ()) { - case PchLpB0: - case PchLpB1: - UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable1); - UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable1Size); - SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable1); - SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable1Size); - break; - case PchLpC0: - case PchLpC1: - UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable2); - UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable2Size); - SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable2); - SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable2Size); - break; - case PchHB0: - case PchHC0: - UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table1); - UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable1Size); - SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable1); - SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable1Size); - break; - case PchHD0: - case PchHD1: - UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2); - UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); - SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2); - SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); - break; - default: - UnknowPtssTables =3D NULL; - UnknowTableSize =3D 0; - SpecificPtssTables =3D NULL; - SpecificTableSize =3D 0; - DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); - } - } else { - switch (PchStepping ()) { - case KblPchHA0: - UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2); - UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size); - SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2); - SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size); - break; - default: - UnknowPtssTables =3D NULL; - UnknowTableSize =3D 0; - SpecificPtssTables =3D NULL; - SpecificTableSize =3D 0; - DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n")); - } - } - - PtssTableIndex =3D 0; - MaxSataPorts =3D GetPchMaxSataPortNum (); - MaxPciePorts =3D GetPchMaxPciePortNum (); - ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal)); - - //Populate PCIe topology based on lane configuration - for (PciePort =3D 0; PciePort < MaxPciePorts; PciePort +=3D 4) { - Status =3D GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction); - ASSERT_EFI_ERROR (Status); - - RpBase =3D MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (= UINT32) RpFunction); - StrapFuseCfg =3D MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG); - PcieControllerCfg =3D (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_= RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC); - DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value =3D %d\n", PciePo= rt, PcieControllerCfg)); - } - for (Index =3D 0; Index < MaxPciePorts; Index++) { - DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology =3D %d\n", Inde= x, PcieTopologyReal[Index])); - } - - //Case 1: BoardId is known, Topology is known/unknown - //Case 1a: SATA - PtssTables =3D SpecificPtssTables; - TableSize =3D SpecificTableSize; - for (Index =3D 0; Index < MaxSataPorts; Index++) { - if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { - for (Entry =3D 0; Entry < TableSize; Entry++) { - if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_SATA) - ) - { - PtssTableIndex++; - if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD20) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD= 20_ICFGCTLEDATATAP_FULLRATE_5_0)) { - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = =3D TRUE; - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D (Pt= ssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.Bit= Mask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; - } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _PCH_HSIO_TX_DWORD8)) { - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE00MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Inde= x] =3D TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =3D= (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8= _ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); - } - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE01MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Inde= x] =3D TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =3D= (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8= _ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); - } - } else { - ASSERT (FALSE); - } - } - } - } - } - //Case 1b: PCIe - for (Index =3D 0; Index < MaxPciePorts; Index++) { - if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { - for (Entry =3D 0; Entry < TableSize; Entry++) { - if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_PCIEDMI) && - (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology)) { - PtssTableIndex++; - if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD25) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD25_= CTLE_ADAPT_OFFSET_CFG_4_0)) { - FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D TRUE= ; - FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D (UINT8)((P= tssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.Bi= tMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); - } else { - ASSERT (FALSE); - } - } - } - } - } - //Case 2: BoardId is unknown, Topology is known/unknown - if (PtssTableIndex =3D=3D 0) { - DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n= ")); - - PtssTables =3D UnknowPtssTables; - TableSize =3D UnknowTableSize; - - for (Index =3D 0; Index < MaxSataPorts; Index++) { - if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { - for (Entry =3D 0; Entry < TableSize; Entry++) { - if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_SATA) - ) - { - if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD20) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWO= RD20_ICFGCTLEDATATAP_FULLRATE_5_0)) { - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index]= =3D TRUE; - FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D (= PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.B= itMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0; - } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) = R_PCH_HSIO_TX_DWORD8) { - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE00MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[In= dex] =3D TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0); - } - if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE01MARGIN_5_0) { - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[In= dex] =3D TRUE; - FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0); - } - } else { - ASSERT (FALSE); - } - } - } - } - } - for (Index =3D 0; Index < MaxPciePorts; Index++) { - if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) { - for (Entry =3D 0; Entry < TableSize; Entry++) { - if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) && - (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_PCIEDMI) && - (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology))= { - if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD25) && - (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD2= 5_CTLE_ADAPT_OFFSET_CFG_4_0)) { - FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D TR= UE; - FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D (UINT8)(= (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.= BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0); - } else { - ASSERT (FALSE); - } - } - } - } - } - } -} - -/** - Performs FSP PCH PEI Policy pre mem initialization. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspPchPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - InstallPlatformHsioPtssTable (FspmUpd); - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/ClevoOpenBoa= rdPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpd= ate.c deleted file mode 100644 index 133b8c963f..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ /dev/null @@ -1,84 +0,0 @@ -/** @file - Intel System Agent policy initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "PeiSaPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - Performs FSP SA PEI Policy initialization. - - @param[in][out] FspsUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdate ( - IN OUT FSPS_UPD *FspsUpd - ) -{ - VOID *Buffer; - VOID *MemBuffer; - UINT32 Size; - - DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); - - FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; - - Size =3D 0; - Buffer =3D NULL; - PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); - if (Buffer =3D=3D NULL) { - DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { - MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); - if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { - CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); - FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32)(UINTN)MemBuffer= ; - } else { - DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); - FspsUpd->FspsConfig.GraphicsConfigPtr =3D 0; - } - } - DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", F= spsUpd->FspsConfig.GraphicsConfigPtr)); - DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= )); - - Size =3D 0; - Buffer =3D NULL; - PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, = &Size); - if (Buffer =3D=3D NULL) { - DEBUG((DEBUG_WARN, "Could not locate Logo\n")); - } else { - MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); - if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { - CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); - FspsUpd->FspsConfig.LogoPtr =3D (UINT32)(UINTN)MemBuffer; - FspsUpd->FspsConfig.LogoSize =3D Size; - } else { - DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); - FspsUpd->FspsConfig.LogoPtr =3D 0; - FspsUpd->FspsConfig.LogoSize =3D 0; - } - } - DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsU= pd->FspsConfig.LogoPtr)); - DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", Fsps= Upd->FspsConfig.LogoSize)); - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/ClevoO= penBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPol= icyUpdatePreMem.c deleted file mode 100644 index 93d79c2313..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c +++ /dev/null @@ -1,75 +0,0 @@ -/** @file - Intel System Agent policy initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "PeiSaPolicyUpdate.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/** - Performs FSP SA PEI Policy initialization in pre-memory. - - @param[in][out] FspmUpd Pointer to FSP UPD Data. - - @retval EFI_SUCCESS FSP UPD Data is updated. - @retval EFI_NOT_FOUND Fail to locate required PPI. - @retval Other FSP UPD Data update process fail. -**/ -EFI_STATUS -EFIAPI -PeiFspSaPolicyUpdatePreMem ( - IN OUT FSPM_UPD *FspmUpd - ) -{ - VOID *Buffer; - -// -// Update UPD:DqPinsInterleaved -// - FspmUpd->FspmConfig.DqPinsInterleaved =3D (UINT8)PcdGetBool(PcdMrcDqPins= Interleaved); - - // - // Update UPD:DqPinsInterleaved - // - FspmUpd->FspmConfig.CaVrefConfig =3D PcdGet8(PcdMrcCaVrefConfig); - - DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings= ...\n")); - Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); - CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1= 2, 12); - } - Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); - CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe= r + 8, 8); - } - - DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp = Target Settings...\n")); - Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); - } - Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); - if (Buffer) { - CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); - } - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHo= okLib/BasePlatformHookLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Libra= ry/BasePlatformHookLib/BasePlatformHookLib.c deleted file mode 100644 index 5c5d6a25b4..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BasePlatformHookLib/B= asePlatformHookLib.c +++ /dev/null @@ -1,662 +0,0 @@ -/** @file - Platform Hook Library - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define COM1_BASE 0x3f8 -#define COM2_BASE 0x2f8 - -#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690 - -#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E -#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F -#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20 - -#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E -#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F -#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E -#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F - -typedef struct { - UINT8 Register; - UINT8 Value; -} EFI_SIO_TABLE; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] =3D { - {0x002, 0x88}, // Power On UARTs - {0x024, COM1_BASE >> 2}, - {0x025, COM2_BASE >> 2}, - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4, - {0x029, 0x080}, // SIRQ_CLKRUN_EN - {0x02A, 0x000}, - {0x02B, 0x0DE}, - {0x00A, 0x040}, - {0x00C, 0x00E}, - {0x02c, 0x002}, - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, - {0x03a, 0x00A}, // LPC Docking Enabling - {0x031, 0x01f}, - {0x032, 0x000}, - {0x033, 0x004}, - {0x038, 0x0FB}, - {0x035, 0x0FE}, - {0x036, 0x000}, - {0x037, 0x0FF}, - {0x039, 0x000}, - {0x034, 0x001}, - {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, //= Relocate configuration ports base address - {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} //= to ensure SIO config address can be accessed in OS -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] =3D { - {0x002, 0x88}, // Power On UARTs - {0x007, 0x00}, - {0x024, COM1_BASE >> 2}, - {0x025, COM2_BASE >> 2}, - {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4, - {0x029, 0x080}, // SIRQ_CLKRUN_EN - {0x02A, 0x000}, - {0x02B, 0x0DE}, - {0x00A, 0x040}, - {0x00C, 0x00E}, - {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4}, - {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8}, - {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff}, - {0x03a, 0x00A}, // LPC Docking Enabling - {0x031, 0x01f}, - {0x032, 0x000}, - {0x033, 0x004}, - {0x038, 0x0FB}, - {0x035, 0x0FE}, - {0x036, 0x000}, - {0x037, 0x0FE}, - {0x039, 0x000}, - {0x034, 0x001} -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] =3D { - {0x29, 0x0A0}, // Enable super I/O clock and set to 48M= Hz - {0x22, 0x003}, // - {0x07, 0x003}, // Select UART0 device - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB - {0x70, 0x004}, // Set to IRQ4 - {0x30, 0x001}, // Enable it with Activation bit - {0x07, 0x002}, // Select UART1 device - {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB - {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB - {0x70, 0x003}, // Set to IRQ3 - {0x30, 0x001}, // Enable it with Activation bit - {0x07, 0x007}, // Select GPIO device - {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address= MSB - {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address= LSB - {0x30, 0x001}, // Enable it with Activation bit - {0x21, 0x001}, // Global Device Enable - {0x26, 0x000} // Fast Enable UART 0 & 1 as their enabl= e & activation bit -}; - -// -// National PC8374L -// -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] =3D { - {0x007, 0x03}, // Select Com1 - {0x061, 0xF8}, // 0x3F8 - {0x060, 0x03}, // 0x3F8 - {0x070, 0x04}, // IRQ4 - {0x030, 0x01} // Active -}; - -// -// IT8628 -// -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = =3D { - {0x023, 0x09}, // Clock Selection register - {0x007, 0x01}, // Com1 Logical Device Number select - {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register - {0x060, 0x03}, // Serial Port 1 Base Address LSB Register - {0x070, 0x04}, // Serial Port 1 Interrupt Level Select - {0x030, 0x01}, // Serial Port 1 Activate - {0x007, 0x02}, // Com1 Logical Device Number select - {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register - {0x060, 0x02}, // Serial Port 2 Base Address MSB Register - {0x070, 0x03}, // Serial Port 2 Interrupt Level Select - {0x030, 0x01} // Serial Port 2 Activate -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = =3D { - {0x007, 0x03}, // Parallel Port Logical Device Number select - {0x030, 0x00}, // Parallel port Activate - {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register - {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register - {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register - {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register - {0x0F0, 0x03} // Special Configuration register -}; - - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] =3D { - {0x07, 0x03}, // Select UART0 device - {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB - {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB - {0x70, 0x04}, // Set to IRQ4 - {0x30, 0x01} // Enable it with Activation bit -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] =3D { - {0x07, 0x02}, // Set logical device SP Serial port Com0 - {0x61, 0xF8}, // Write Base Address LSB register 0x3F8 - {0x60, 0x03}, // Write Base Address MSB register 0x3F8 - {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard - {0x30, 0x01} // Enable serial port with Activation bit -}; - -/** - Detect if a National 393 SIO is docked. If yes, enable the docked SIO - and its serial port, and disable the onboard serial port. - - @retval EFI_SUCCESS Operations performed successfully. -**/ -STATIC -VOID -CheckNationalSio ( - VOID - ) -{ - UINT8 Data8; - - // - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). - // We use (0x2e, 0x2f) which is determined by BADD default strapping - // - - // - // Read the Pc87393 signature - // - IoWrite8 (0x2e, 0x20); - Data8 =3D IoRead8 (0x2f); - - if (Data8 =3D=3D 0xea) { - // - // Signature matches - National PC87393 SIO is docked - // - - // - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at - // SIO_BASE_ADDRESS + 0x10) - // - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7= F), 0x20); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); - - // - // Turn on docking power - // - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); - - // - // GPIO setting - // - IoWrite8 (0x2e, 0x24); - IoWrite8 (0x2f, 0x29); - - // - // Enable chip clock - // - IoWrite8 (0x2e, 0x29); - IoWrite8 (0x2f, 0x1e); - - - // - // Enable serial port - // - - // - // Select com1 - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x3); - - // - // Base address: 0x3f8 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf8); - - // - // Interrupt: 4 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x04); - - // - // Enable bank selection - // - IoWrite8 (0x2e, 0xf0); - IoWrite8 (0x2f, 0x82); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - // - // Disable onboard serial port - // - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); - - // - // Power Down UARTs - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); - - // - // Dissable COM1 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable COM2 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable interrupt - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); - - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); - - // - // Enable floppy - // - - // - // Select floppy - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x0); - - // - // Base address: 0x3f0 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf0); - - // - // Interrupt: 6 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x06); - - // - // DMA 2 - // - IoWrite8 (0x2e, 0x74); - IoWrite8 (0x2f, 0x02); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - } else { - - // - // No National pc87393 SIO is docked, turn off dock power and - // disable port switch - // - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); - // IoWrite8 (0x690, 0); - - // - // If no National pc87393, just return - // - return; - } -} - - -/** -Check whether the IT8628 SIO present on LPC. If yes, enable its serial -ports, parallel port, and port 80. - -@retval EFI_SUCCESS Operations performed successfully. -**/ -STATIC -VOID -It8628SioSerialPortInit ( - VOID - ) -{ - UINT8 ChipId0 =3D 0; - UINT8 ChipId1 =3D 0; - UINT16 LpcIoDecondeRangeSet =3D 0; - UINT16 LpcIoDecoodeSet =3D 0; - UINT8 Index; - UINTN LpcBaseAddr; - - - // - // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2= Eh/2Fh. - // - LpcBaseAddr =3D MmPciBase ( - DEFAULT_PCI_BUS_NUMBER_PCH, - PCI_DEVICE_NUMBER_PCH_LPC, - PCI_FUNCTION_NUMBER_PCH_LPC - ); - - LpcIoDecondeRangeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IO= D); - LpcIoDecoodeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE); - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_= PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8))); - MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LP= C_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE))); - - // - // Enter MB PnP Mode - // - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87); - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01); - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55); - - // - // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) - // - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); - ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); - - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); - ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); - - // - // Enable Serial Port 1, Port 2 - // - if ((ChipId0 =3D=3D 0x86) && (ChipId1 =3D=3D 0x28)) { - for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof = (EFI_SIO_TABLE); Index++) { - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[In= dex].Register); - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Ind= ex].Value); - } - } - - // - // Exit MB PnP Mode - // - IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02); - IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02); - - return; -} - - -/** - Performs platform specific initialization required for the CPU to access - the hardware associated with a SerialPortLib instance. This function do= es - not initialize the serial port hardware itself. Instead, it initializes - hardware devices that are required for the CPU to access the serial port - hardware. This function may be called more than once. - - @retval RETURN_SUCCESS The platform specific initialization succee= ded. - @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed. - -**/ -RETURN_STATUS -EFIAPI -PlatformHookSerialPortInitialize ( - VOID - ) -{ - UINT16 ConfigPort; - UINT16 IndexPort; - UINT16 DataPort; - UINT16 DeviceId; - UINT8 Index; - UINT16 AcpiBase; - - // - // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit - // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use. - // - IndexPort =3D 0; - DataPort =3D 0; - Index =3D 0; - AcpiBase =3D 0; - PchAcpiBaseGet (&AcpiBase); - if (AcpiBase =3D=3D 0) { - PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress)); - } - - // - // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. - // - PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); - PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); - - // Configure Sio IT8628 - It8628SioSerialPortInit (); - - DeviceId =3D MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID= ); - if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) { - // - // if no EC, it is SV Bidwell Bar board - // - if ((IoRead8 (0x66) !=3D 0xFF) && (IoRead8 (0x62) !=3D 0xFF)) { - // - // Super I/O initialization for SMSC SI1007 - // - ConfigPort =3D FixedPcdGet16 (PcdLpcSioConfigDefaultPort); - DataPort =3D PcdGet16 (PcdLpcSioDataDefaultPort); - IndexPort =3D PcdGet16 (PcdLpcSioIndexDefaultPort); - - // - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; - // - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x= 10); - - // - // Program and Enable Default Super IO Configuration Port Addresses = and range - // - PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~= 0xF), 0x10); - - // - // Enter Config Mode - // - IoWrite8 (ConfigPort, 0x55); - - // - // Check for SMSC SIO1007 - // - IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is = 0x0D - if (IoRead8 (DataPort) =3D=3D 0x20) { // SMSC SIO1007 Device ID is= 0x20 - // - // Configure SIO - // - for (Index =3D 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TAB= LE); Index++) { - IoWrite8 (IndexPort, mSioTable[Index].Register); - IoWrite8 (DataPort, mSioTable[Index].Value); - } - - // - // Exit Config Mode - // - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); - - // - // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH - // - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f); - } - - // - // Check if a National Pc87393 SIO is docked - // - CheckNationalSio (); - - // - // Super I/O initialization for SMSC SIO1000 - // - ConfigPort =3D PcdGet16 (PcdLpcSioIndexPort); - IndexPort =3D PcdGet16 (PcdLpcSioIndexPort); - DataPort =3D PcdGet16 (PcdLpcSioDataPort); - - // - // Enter Config Mode - // - IoWrite8 (ConfigPort, 0x55); - - // - // Check for SMSC SIO1000 - // - if (IoRead8 (ConfigPort) !=3D 0xFF) { - // - // Configure SIO - // - for (Index =3D 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI= _SIO_TABLE); Index++) { - IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register); - IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value); - } - - // - // Exit Config Mode - // - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); - } - - // - // Super I/O initialization for Winbond WPCN381U - // - IndexPort =3D LPC_SIO_INDEX_DEFAULT_PORT_2; - DataPort =3D LPC_SIO_DATA_DEFAULT_PORT_2; - - // - // Check for Winbond WPCN381U - // - IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID re= gister is 0x20 - if (IoRead8 (DataPort) =3D=3D 0xF4) { // Winbond WPCN381U Device I= D is 0xF4 - // - // Configure SIO - // - for (Index =3D 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI= _SIO_TABLE); Index++) { - IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register); - IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value); - } - } - } //EC is not exist, skip mobile board detection for SV board - - // - //add for SV Bidwell Bar board - // - if (IoRead8 (COM1_BASE) =3D=3D 0xFF) { - // - // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC= ) - // Looking for LDC2 card first - // - IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55); - if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) =3D=3D 0x55) { - IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; - DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; - } else { - IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; - DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; - } - - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID regist= er is 0x20 - if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is= 0xF1 - for (Index =3D 0; Index < sizeof (mSioTableWinbondX374) / sizeof (= EFI_SIO_TABLE); Index++) { - IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register); - IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value); - } - } - }// end of Bidwell Bar SIO initialization - } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER= (DeviceId)) { - // - // If we are in debug mode, we will allow serial status codes - // - - // - // National PC8374 SIO & Winbond WPCD374 (LDC2) - // - IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; - - IoWrite8 (IndexPort, 0x55); - if (IoRead8 (IndexPort) =3D=3D 0x55) { - IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT; - DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT; - } else { - IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT; - DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT; - } - - // - // Configure SIO - // - IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register= is 0x20 - if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is 0= xF1 - for (Index =3D 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SI= O_TABLE); Index++) { - IoWrite8 (IndexPort, mDesktopSioTable[Index].Register); - //PrePpiStall (200); - IoWrite8 (DataPort, mDesktopSioTable[Index].Value); - //PrePpiStall (200); - } - return RETURN_SUCCESS; - } - // - // Configure Pilot3 SIO - // - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mo= de. - IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot= 3 SIO Device ID register is 0x20. - if (IoRead8 (PILOTIII_SIO_DATA_PORT) =3D=3D PILOTIII_CHIP_ID) { // = Pilot3 SIO Device ID register is 0x03. - // - // Configure SIO - // - for (Index =3D 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO= _TABLE); Index++) { - IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register= ); - IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value); - } - } - IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode= . - } - - - return RETURN_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/D= xeBoardAcpiTableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Boa= rdAcpiLib/DxeBoardAcpiTableLib.c deleted file mode 100644 index c56334e82b..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeBoard= AcpiTableLib.c +++ /dev/null @@ -1,36 +0,0 @@ -/** @file - DXE board-specific ACPI functionality. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardUpdateAcpiTable ( - IN OUT EFI_ACPI_COMMON_HEADER *Table, - IN OUT EFI_ACPI_TABLE_VERSION *Version - ); - -EFI_STATUS -EFIAPI -BoardUpdateAcpiTable ( - IN OUT EFI_ACPI_COMMON_HEADER *Table, - IN OUT EFI_ACPI_TABLE_VERSION *Version - ) -{ - N1xxWUBoardUpdateAcpiTable (Table, Version); - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/D= xeMultiBoardAcpiSupportLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Libr= ary/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c deleted file mode 100644 index 4171d4ad6d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeMulti= BoardAcpiSupportLib.c +++ /dev/null @@ -1,43 +0,0 @@ -/** @file - DXE multi-board ACPI table support functionality. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardUpdateAcpiTable ( - IN OUT EFI_ACPI_COMMON_HEADER *Table, - IN OUT EFI_ACPI_TABLE_VERSION *Version - ); - -BOARD_ACPI_TABLE_FUNC mN1xxWUBoardAcpiTableFunc =3D { - N1xxWUBoardUpdateAcpiTable -}; - -EFI_STATUS -EFIAPI -DxeN1xxWUMultiBoardAcpiSupportLibConstructor ( - VOID - ) -{ - if (LibPcdGetSku () =3D=3D BoardIdN1xxWU) { - return RegisterBoardAcpiTableFunc (&mN1xxWUBoardAcpiTableFunc); - } - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/D= xeN1xxWUAcpiTableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Bo= ardAcpiLib/DxeN1xxWUAcpiTableLib.c deleted file mode 100644 index 96a3232fe5..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/DxeN1xxW= UAcpiTableLib.c +++ /dev/null @@ -1,74 +0,0 @@ -/** @file - Clevo N1xxWU board DXE ACPI table functionality. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mG= lobalNvsArea; - -VOID -N1xxWUUpdateGlobalNvs ( - VOID - ) -{ - - // - // Allocate and initialize the NVS area for SMM and ASL communication. - // - mGlobalNvsArea.Area =3D (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress); - - // - // Update global NVS area for ASL and SMM init code to use - // - - // - // Enable PowerState - // - mGlobalNvsArea.Area->PowerState =3D 1; // AC =3D1; for mobile platform, = will update this value in SmmPlatform.c - - mGlobalNvsArea.Area->NativePCIESupport =3D PcdGet8 (PcdPciExpNati= ve); - - // - // Enable APIC - // - mGlobalNvsArea.Area->ApicEnable =3D GLOBAL_NVS_DEVICE_ENABLE; - - // - // Low Power S0 Idle - Enabled/Disabled - // - mGlobalNvsArea.Area->LowPowerS0Idle =3D PcdGet8 (PcdLowPowerS0Idle); - - mGlobalNvsArea.Area->Ps2MouseEnable =3D FALSE; - mGlobalNvsArea.Area->Ps2KbMsEnable =3D PcdGet8 (PcdPs2KbMsEnable); -} - -EFI_STATUS -EFIAPI -N1xxWUBoardUpdateAcpiTable ( - IN OUT EFI_ACPI_COMMON_HEADER *Table, - IN OUT EFI_ACPI_TABLE_VERSION *Version - ) -{ - if (Table->Signature =3D=3D EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTI= ON_TABLE_SIGNATURE) { - N1xxWUUpdateGlobalNvs (); - } - - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/S= mmBoardAcpiEnableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Bo= ardAcpiLib/SmmBoardAcpiEnableLib.c deleted file mode 100644 index 2d9e9e98da..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmBoard= AcpiEnableLib.c +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - Clevo N1xxWU board SMM ACPI table enable/disable functionality. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardEnableAcpi ( - IN BOOLEAN EnableSci - ); - -EFI_STATUS -EFIAPI -N1xxWUBoardDisableAcpi ( - IN BOOLEAN DisableSci - ); - -EFI_STATUS -EFIAPI -SiliconEnableAcpi ( - IN BOOLEAN EnableSci - ); - -EFI_STATUS -EFIAPI -SiliconDisableAcpi ( - IN BOOLEAN DisableSci - ); - -EFI_STATUS -EFIAPI -BoardEnableAcpi ( - IN BOOLEAN EnableSci - ) -{ - SiliconEnableAcpi (EnableSci); - return N1xxWUBoardEnableAcpi (EnableSci); -} - -EFI_STATUS -EFIAPI -BoardDisableAcpi ( - IN BOOLEAN DisableSci - ) -{ - SiliconDisableAcpi (DisableSci); - return N1xxWUBoardDisableAcpi (DisableSci); -} - - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/S= mmMultiBoardAcpiSupportLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Libr= ary/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c deleted file mode 100644 index a06505a34a..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmMulti= BoardAcpiSupportLib.c +++ /dev/null @@ -1,81 +0,0 @@ -/** @file - SMM multi-board ACPI support functionality. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardEnableAcpi ( - IN BOOLEAN EnableSci - ); - -EFI_STATUS -EFIAPI -N1xxWUBoardDisableAcpi ( - IN BOOLEAN DisableSci - ); - -EFI_STATUS -EFIAPI -SiliconEnableAcpi ( - IN BOOLEAN EnableSci - ); - -EFI_STATUS -EFIAPI -SiliconDisableAcpi ( - IN BOOLEAN DisableSci - ); - -EFI_STATUS -EFIAPI -N1xxWUMultiBoardEnableAcpi ( - IN BOOLEAN EnableSci - ) -{ - SiliconEnableAcpi (EnableSci); - return N1xxWUBoardEnableAcpi (EnableSci); -} - -EFI_STATUS -EFIAPI -N1xxWUMultiBoardDisableAcpi ( - IN BOOLEAN DisableSci - ) -{ - SiliconDisableAcpi (DisableSci); - return N1xxWUBoardDisableAcpi (DisableSci); -} - -BOARD_ACPI_ENABLE_FUNC mN1xxWUBoardAcpiEnableFunc =3D { - N1xxWUMultiBoardEnableAcpi, - N1xxWUMultiBoardDisableAcpi, -}; - -EFI_STATUS -EFIAPI -SmmN1xxWUMultiBoardAcpiSupportLibConstructor ( - VOID - ) -{ - if (LibPcdGetSku () =3D=3D BoardIdN1xxWU) { - return RegisterBoardAcpiEnableFunc (&mN1xxWUBoardAcpiEnableFunc); - } - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/S= mmN1xxWUAcpiEnableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/B= oardAcpiLib/SmmN1xxWUAcpiEnableLib.c deleted file mode 100644 index 8c1caa1898..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmN1xxW= UAcpiEnableLib.c +++ /dev/null @@ -1,39 +0,0 @@ -/** @file - Platform Hook Library instances - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardEnableAcpi ( - IN BOOLEAN EnableSci - ) -{ - // enable additional board register - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -N1xxWUBoardDisableAcpi ( - IN BOOLEAN DisableSci - ) -{ - // enable additional board register - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/S= mmSiliconAcpiEnableLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/= BoardAcpiLib/SmmSiliconAcpiEnableLib.c deleted file mode 100644 index 1baa8daa70..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardAcpiLib/SmmSilic= onAcpiEnableLib.c +++ /dev/null @@ -1,168 +0,0 @@ -/** @file - SMM ACPI enable library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - Clear Port 80h - - SMI handler to enable ACPI mode - - Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI - - Disables the SW SMI Timer. - ACPI events are disabled and ACPI event status is cleared. - SCI mode is then enabled. - - Clear SLP SMI status - Enable SLP SMI - - Disable SW SMI Timer - - Clear all ACPI event status and disable all ACPI events - - Disable PM sources except power button - Clear status bits - - Disable GPE0 sources - Clear status bits - - Disable GPE1 sources - Clear status bits - - Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) - - Enable SCI -**/ -EFI_STATUS -EFIAPI -SiliconEnableAcpi ( - IN BOOLEAN EnableSci - ) -{ - UINT32 OutputValue; - UINT32 SmiEn; - UINT32 SmiSts; - UINT32 ULKMC; - UINTN LpcBaseAddress; - UINT16 AcpiBaseAddr; - UINT32 Pm1Cnt; - - LpcBaseAddress =3D MmPciBase ( - DEFAULT_PCI_BUS_NUMBER_PCH, - PCI_DEVICE_NUMBER_PCH_LPC, - PCI_FUNCTION_NUMBER_PCH_LPC - ); - - // - // Get the ACPI Base Address - // - PchAcpiBaseGet (&AcpiBaseAddr); - - // - // BIOS must also ensure that CF9GR is cleared and locked before handing= control to the - // OS in order to prevent the host from issuing global resets and resett= ing ME - // - // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Res= et - // MmioWrite32 ( - // PmcBaseAddress + R_PCH_PMC_ETR3), - // PmInit); - - // - // Clear Port 80h - // - IoWrite8 (0x80, 0); - - // - // Disable SW SMI Timer and clean the status - // - SmiEn =3D IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN); - SmiEn &=3D ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_S= MI_EN_LEGACY_USB); - IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn); - - SmiSts =3D IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS); - SmiSts |=3D B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SM= I_EN_LEGACY_USB; - IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts); - - // - // Disable port 60/64 SMI trap if they are enabled - // - ULKMC =3D MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_UL= KMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC= _64WEN | B_PCH_LPC_ULKMC_A20PASSEN); - MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC); - - // - // Disable PM sources except power button - // - IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN); - - // - // Clear PM status except Power Button status for RapidStart Resume - // - IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF); - - // - // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) - // - IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD); - IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0); - - // - // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#) - // - OutputValue =3D IoRead32 (AcpiBaseAddr + 0x38); - OutputValue =3D OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPos= ition)); - IoWrite32 (AcpiBaseAddr + 0x38, OutputValue); - - - // - // Enable SCI - // - if (EnableSci) { - Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); - Pm1Cnt |=3D B_PCH_ACPI_PM1_CNT_SCI_EN; - IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); - } - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -SiliconDisableAcpi ( - IN BOOLEAN DisableSci - ) -{ - UINT16 AcpiBaseAddr; - UINT32 Pm1Cnt; - - // - // Get the ACPI Base Address - // - PchAcpiBaseGet (&AcpiBaseAddr); - - // - // Disable SCI - // - if (DisableSci) { - Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT); - Pm1Cnt &=3D ~B_PCH_ACPI_PM1_CNT_SCI_EN; - IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt); - } - - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N= 1xxWUGpioTable.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardIni= tLib/N1xxWUGpioTable.c deleted file mode 100644 index 27f70df001..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUGp= ioTable.c +++ /dev/null @@ -1,370 +0,0 @@ -/** @file - GPIO definition table for N1xxWU - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _N1_XX_WU_GPIO_TABLE_H_ -#define _N1_XX_WU_GPIO_TABLE_H_ - -#include -#include -#include -#include -#include - - -#define END_OF_GPIO_TABLE 0xFFFFFFFF - -GPIO_INIT_CONFIG mGpioTableN1xxWU[] =3D -{ - {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //RCI= NB_TIME_SYNC_1 - {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNative}}, //L= AD_0_ESPI_IO_0 - {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LAD= _1_ESPI_IO_1 - {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNative}}, //L= AD_2_ESPI_IO_2 - {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LAD= _3_ESPI_IO_3 - {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //LFR= AMEB_ESPI_CSB - {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= Out, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SER= IRQ - {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //PIR= QAB_GSPI0_CS1B - {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CLK= RUNB - {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //C= LKOUT_LPC_0_ESPI_CLK - {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //C= LKOUT_LPC_1 - {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //P= MEB_GSPI1_CS1B - {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //BM_= BUSYB_ISH_GP_6 - {GPIO_SKL_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SUS= WARNB_SUSPWRDNACK - {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SUS= _STATB_ESPI_RESETB - {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //S= USACKB - {GPIO_SKL_LP_GPP_A16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SD_= 1P8_SEL - {GPIO_SKL_LP_GPP_A17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SD_= VDD1_PWR_EN_B_ISH_GP_7 - {GPIO_SKL_LP_GPP_A18, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _GP_0 - {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _GP_1 - {GPIO_SKL_LP_GPP_A20, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _GP_2 - {GPIO_SKL_LP_GPP_A21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //ISH= _GP_3 - {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //ISH= _GP_4 - {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //ISH= _GP_5 - {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //COR= E_VID_0 - {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //COR= E_VID_1 - {GPIO_SKL_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //VRA= LERTB - {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CPU= _GP_2 - {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CPU= _GP_3 - {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRC= CLKREQB_0 - {GPIO_SKL_LP_GPP_B6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRC= CLKREQB_1 - {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRC= CLKREQB_2 - {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRC= CLKREQB_3 - {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRC= CLKREQB_4 - {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SRC= CLKREQB_5 - {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EXT= _PWR_GATEB - {GPIO_SKL_LP_GPP_B12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SLP= _S0B - {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //PLT= RSTB - {GPIO_SKL_LP_GPP_B14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //S= PKR - {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSP= I0_CS0B - {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSP= I0_CLK - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSP= I0_MISO - {GPIO_SKL_LP_GPP_B18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpu20K}}, //G= SPI0_MOSI - {GPIO_SKL_LP_GPP_B19, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSP= I1_CS0B - {GPIO_SKL_LP_GPP_B20, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSP= I1_CLK_NFC_CLK - {GPIO_SKL_LP_GPP_B21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GSP= I1_MISO_NFC_CLKREQ - {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //G= SPI1_MOSI - {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML= 1ALERTB_PCHHOTB - {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_0_SD3_CMD - {GPIO_SKL_LP_GPP_G1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_1_SD3_D0_SD4_RCLK_P - {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_2_SD3_D1_SD4_RCLK_N - {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_3_SD3_D2 - {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_4_SD3_D3 - {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_5_SD3_CDB - {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_6_SD3_CLK - {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //GPP= C_G_7_SD3_WP - {GPIO_SKL_LP_GPP_D0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI= 1_CSB_BK_0 - {GPIO_SKL_LP_GPP_D1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI= 1_CLK_BK_1 - {GPIO_SKL_LP_GPP_D2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI= 1_MISO_IO_1_BK_2 - {GPIO_SKL_LP_GPP_D3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI= 1_MOSI_IO_0_BK_3 - {GPIO_SKL_LP_GPP_D4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //IMG= CLKOUT_0_BK_4 - {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _I2C0_SDA - {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _I2C0_SCL - {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _I2C1_SDA - {GPIO_SKL_LP_GPP_D8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _I2C1_SCL - {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _SPI_CSB - {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _SPI_CLK - {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _SPI_MISO_GP_BSSB_CLK - {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _SPI_MOSI_GP_BSSB_DI - {GPIO_SKL_LP_GPP_D13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _UART0_RXD_SML0BDATA - {GPIO_SKL_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _UART0_TXD_SML0BCLK - {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _UART0_RTSB_GSPI2_CS1B - {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //ISH= _UART0_CTSB_SML0BALERTB - {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMI= C_CLK_1_SNDW3_CLK - {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMI= C_DATA_1_SNDW3_DATA - {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMI= C_CLK_0_SNDW4_CLK - {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DMI= C_DATA_0_SNDW4_DATA - {GPIO_SKL_LP_GPP_D21, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI= 1_IO_2 - {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SPI= 1_IO_3 - {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SSP= _MCLK - {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _GNSS_PA_BLANKING - {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _GNSS_FTA - {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _GNSS_SYSCK - {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, // - {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _BRI_DT_UART0_RTSB - {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _BRI_RSP_UART0_RXD - {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _RGI_DT_UART0_TXD - {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _RGI_RSP_UART0_CTSB - {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _MFUART2_RXD - {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CNV= _MFUART2_TXD - {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnDefault, GpioDirDe= fault, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, // - {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_CMD - {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA0 - {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA1 - {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA2 - {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA3 - {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA4 - {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA5 - {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA6 - {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_DATA7 - {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_RCLK - {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_CLK - {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EMM= C_RESETB - {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn= , GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioT= ermNone}}, //A4WP_PRESENT - {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //BATL= OWB - {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNative}}, //AC= PRESENT - {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn= Inv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetDefault, GpioTer= mNone}}, //LAN_WAKEB - {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermWpu20K}}, //PW= RBTNB - {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_= S3B - {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_= S4B - {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_= AB - {GPIO_SKL_LP_GPD7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, // - {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SUSC= LK - {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_= WLANB - {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //SLP_= S5B - {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone}}, //LANP= HYPC - {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SMB= CLK - {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SMB= DATA - {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}}, //S= MBALERTB - {GPIO_SKL_LP_GPP_C3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML= 0CLK - {GPIO_SKL_LP_GPP_C4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML= 0DATA - {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML= 0ALERTB - {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML= 1CLK - {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SML= 1DATA - {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T0_RXD - {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T0_TXD - {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T0_RTSB - {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T0_CTSB - {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T1_RXD_ISH_UART1_RXD - {GPIO_SKL_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn= Inv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTer= mNone}}, //UART1_TXD_ISH_UART1_TXD - {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T1_RTSB_ISH_UART1_RTSB - {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T1_CTSB_ISH_UART1_CTSB - {GPIO_SKL_LP_GPP_C16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2C= 0_SDA - {GPIO_SKL_LP_GPP_C17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2C= 0_SCL - {GPIO_SKL_LP_GPP_C18, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //I2C= 1_SDA - {GPIO_SKL_LP_GPP_C19, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn= Inv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTe= rmNone}}, //I2C1_SCL - {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T2_RXD - {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T2_TXD - {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T2_RTSB - {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //UAR= T2_CTSB - {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTe= rmWpd20K}}, //SATAXPCIE_0_SATAGP_0 - {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SAT= AXPCIE_1_SATAGP_1 - {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SAT= AXPCIE_2_SATAGP_2 - {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= Out, GpioOutLow, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTe= rmNone}}, //CPU_GP_0 - {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //SATA_= DEVSLP_0 - {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone}}, //SATA_= DEVSLP_1 - {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SAT= A_DEVSLP_2 - {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //CPU= _GP_1 - {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //SAT= A_LEDB - {GPIO_SKL_LP_GPP_E9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB= 2_OCB_0_GP_BSSB_CLk - {GPIO_SKL_LP_GPP_E10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB= 2_OCB_1_GP_BSSB_DI - {GPIO_SKL_LP_GPP_E11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB= 2_OCB_2 - {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //USB= 2_OCB_3 - {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDS= P_HPD_0_DISP_MISC_0 - {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDS= P_HPD_1_DISP_MISC_1 - {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn= Inv, GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTer= mNone}}, //DDSP_HPD_2_DISP_MISC_2 - {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn= Inv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTe= rmNone}}, //DDSP_HPD_3_DISP_MISC_3 - {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //EDP= _HPD_DISP_MISC_4 - {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirDe= fault, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDP= B_CTRLCLK - {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDP= B_CTRLDATA - {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDP= C_CTRLCLK - {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnDefault, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDP= C_CTRLDATA - {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= Out, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioT= ermNone}}, //DDPD_CTRLCLK - {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}}, //DDP= D_CTRLDATA - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking = End of Table -}; - -UINT16 mGpioTableN1xxWUSize =3D sizeof (mGpioTableN1xxWU) / sizeof (GPIO_I= NIT_CONFIG) - 1; - -GPIO_INIT_CONFIG mGpioTableN1xxWUUcmcDevice[] =3D -{ - { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone = } }, //GPP_B0 - { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone = } }, //GPP_B1 -}; - -UINT16 mGpioTableN1xxWUUcmcDeviceSize =3D sizeof (mGpioTableN1xxWUUcmcDevi= ce) / sizeof (GPIO_INIT_CONFIG); - -GPIO_INIT_CONFIG mGpioTableN1xxWUTouchpanel =3D - {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNo= ne}}; - -GPIO_INIT_CONFIG mGpioTableN1xxWUSdhcSidebandCardDetect =3D - {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, GpioTermNone}}; //SD_C= DB D3 - -//IO Expander Table for SKL RVP7, RVP13 and RVP15 -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =3D -{ - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //DGPU_PRSNT_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SW_GFX_PWERGD_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26 - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27 - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}/= /M.2_WIGIG_PWREN_IOEXP -}; - -UINT16 mGpioTableIoExpanderSize =3D sizeof (mGpioTableIoExpander) / sizeof= (IO_EXPANDER_GPIO_CONFIG); - -//IO Expander Table for KBL -Refresh -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =3D -{ - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //Unused pin - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RTD3_USB_PD1_PWR_EN - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //HRESET_PD1_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N - //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPAN= DER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED= },//M.2_WWAN_RST_CNTRL_R - // We want the initial state to be high. - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_RST_CNTRL_R - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_WAKE_CTRL_R_N - // Turn off WWAN power and will turn it on later. - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP -}; -UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 =3D sizeof (mGpioTableIoExpan= derKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG); - -//IO Expander Table for KBL -kc -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =3D -{ - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26 - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27 - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FPS_LOCK_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_FLEX_PWREN - {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB_UART_SEL - {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_DOCK_PWREN_IOEXP_R -}; -UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 =3D sizeof (mGpioTableIoExpa= nderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG); -//IO Expander Table Full table for N 1XX WU -IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderN1xxWU[] =3D -{ - {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //DGPU_PRSNT_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED }= ,//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD) -//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD) - {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SW_GFX_PWERGD_IOEXP - {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N - {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26 - {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27 - {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED }= ,//Not Connected (KBK_RVP3_BOARD) -//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD) - {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N - {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP - {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN (KBL_RVP3_BOARD) - {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FPS_LOCK_N (KBL_RVP3_BOARD) -}; - -UINT16 mGpioTableIoExpanderN1xxWUSize =3D sizeof (mGpioTableIoExpanderN1xx= WU) / sizeof (IO_EXPANDER_GPIO_CONFIG); - -#endif // _N1_XX_WU_GPIO_TABLE_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N= 1xxWUHdaVerbTables.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Boar= dInitLib/N1xxWUHdaVerbTables.c deleted file mode 100644 index 26d7401c6c..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHd= aVerbTables.c +++ /dev/null @@ -1,232 +0,0 @@ -/** @file - HDA Verb table for N1xxWU - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _N1_XX_WU_HDA_VERB_TABLES_H_ -#define _N1_XX_WU_HDA_VERB_TABLES_H_ - -#include - -HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 =3D HDAUDIO_VERB_TABLE_INIT ( - // - // VerbTable: (Realtek ALC286) for RVP3 - // Revision ID =3D 0xff - // Codec Verb Table for SKL PCH boards - // Codec Address: CAd value (0/1/2) - // Codec Vendor: 0x10EC0286 - // - 0x10EC, 0x0286, - 0xFF, 0xFF, - //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D - // - // Realtek Semiconductor Corp. - // - //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D - - //Realtek High Definition Audio Configuration - Version : 5.0.2.9 - //Realtek HD Audio Codec : ALC286 - //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 - //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E - //The number of verb command block : 16 - - // NID 0x12 : 0x411111F0 - // NID 0x13 : 0x40000000 - // NID 0x14 : 0x9017011F - // NID 0x17 : 0x90170110 - // NID 0x18 : 0x03A11040 - // NID 0x19 : 0x411111F0 - // NID 0x1A : 0x411111F0 - // NID 0x1D : 0x4066A22D - // NID 0x1E : 0x411111F0 - // NID 0x21 : 0x03211020 - - - //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D - //HDA Codec Subsystem ID : 0x10EC108E - 0x0017208E, - 0x00172110, - 0x001722EC, - 0x00172310, - - //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D - //Widget node 0x01 : - 0x0017FF00, - 0x0017FF00, - 0x0017FF00, - 0x0017FF00, - //Pin widget 0x12 - DMIC - 0x01271CF0, - 0x01271D11, - 0x01271E11, - 0x01271F41, - //Pin widget 0x13 - DMIC - 0x01371C00, - 0x01371D00, - 0x01371E00, - 0x01371F40, - //Pin widget 0x14 - SPEAKER-OUT (Port-D) - 0x01771C1F, - 0x01771D01, - 0x01771E17, - 0x01771F90, - //Pin widget 0x17 - I2S-OUT - 0x01771C10, - 0x01771D01, - 0x01771E17, - 0x01771F90, - //Pin widget 0x18 - MIC1 (Port-B) - 0x01871C40, - 0x01871D10, - 0x01871EA1, - 0x01871F03, - //Pin widget 0x19 - I2S-IN - 0x01971CF0, - 0x01971D11, - 0x01971E11, - 0x01971F41, - //Pin widget 0x1A - LINE1 (Port-C) - 0x01A71CF0, - 0x01A71D11, - 0x01A71E11, - 0x01A71F41, - //Pin widget 0x1D - PC-BEEP - 0x01D71C2D, - 0x01D71DA2, - 0x01D71E66, - 0x01D71F40, - //Pin widget 0x1E - S/PDIF-OUT - 0x01E71CF0, - 0x01E71D11, - 0x01E71E11, - 0x01E71F41, - //Pin widget 0x21 - HP-OUT (Port-A) - 0x02171C20, - 0x02171D10, - 0x02171E21, - 0x02171F03, - //Widget node 0x20 : - 0x02050071, - 0x02040014, - 0x02050010, - 0x02040C22, - //Widget node 0x20 - 1 : - 0x0205004F, - 0x02045029, - 0x0205004F, - 0x02045029, - //Widget node 0x20 - 2 : - 0x0205002B, - 0x02040DD0, - 0x0205002D, - 0x02047020, - //Widget node 0x20 - 3 : - 0x0205000E, - 0x02046C80, - 0x01771F90, - 0x01771F90, - //TI AMP settings : - 0x02050022, - 0x0204004C, - 0x02050023, - 0x02040000, - 0x02050025, - 0x02040000, - 0x02050026, - 0x0204B010, - - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - - 0x02050022, - 0x0204004C, - 0x02050023, - 0x02040002, - 0x02050025, - 0x02040011, - 0x02050026, - 0x0204B010, - - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - - 0x02050022, - 0x0204004C, - 0x02050023, - 0x0204000D, - 0x02050025, - 0x02040010, - 0x02050026, - 0x0204B010, - - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - - 0x02050022, - 0x0204004C, - 0x02050023, - 0x02040025, - 0x02050025, - 0x02040008, - 0x02050026, - 0x0204B010, - - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - - 0x02050022, - 0x0204004C, - 0x02050023, - 0x02040002, - 0x02050025, - 0x02040000, - 0x02050026, - 0x0204B010, - - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - 0x000F0000, - - 0x02050022, - 0x0204004C, - 0x02050023, - 0x02040003, - 0x02050025, - 0x02040000, - 0x02050026, - 0x0204B010 -); - -#endif // _N1_XX_WU_HDA_VERB_TABLES_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N= 1xxWUHsioPtssTables.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Boa= rdInitLib/N1xxWUHsioPtssTables.c deleted file mode 100644 index 9e52dd2671..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUHs= ioPtssTables.c +++ /dev/null @@ -1,105 +0,0 @@ -/** @file - N1xxWU HSIO PTSS H File - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef N1_XX_WU_HSIO_PTSS_H_ -#define N1_XX_WU_HSIO_PTSS_H_ - -#include - -#ifndef HSIO_PTSS_TABLE_SIZE -#define HSIO_PTSS_TABLE_SIZE(A) A##_Size =3D sizeof (A) / sizeof (HSIO_PTS= S_TABLES) -#endif - -//BoardId N1xxWU -HSIO_PTSS_TABLES PchLpHsioPtss_Cx_N1xxWU[] =3D { - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoM2}, - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoM2}, - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F0000= 00}, PchSataTopoDirectConnect}, - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoM2}, - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoM2}, - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1}, - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}= , PchSataTopoM2}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}= , PchSataTopoDirectConnect}, - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoM2}, - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1}, - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown} -}; - -UINT16 PchLpHsioPtss_Cx_N1xxWU_Size =3D sizeof(PchLpHsioPtss_Cx_N1xxWU) / = sizeof(HSIO_PTSS_TABLES); - -HSIO_PTSS_TABLES PchLpHsioPtss_Bx_N1xxWU[] =3D { - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchPcieTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F0000= 00}, PchSataTopoDirectConnect}, - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown}, - {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown}, - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4}, - {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1}, - {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}= , PchPcieTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}= , PchSataTopoDirectConnect}, - {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1}, - {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown}, - {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, - {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}, -}; - -UINT16 PchLpHsioPtss_Bx_N1xxWU_Size =3D sizeof(PchLpHsioPtss_Bx_N1xxWU) / = sizeof(HSIO_PTSS_TABLES); - -#endif // N1_XX_WU_HSIO_PTSS_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N= 1xxWUSpdTable.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInit= Lib/N1xxWUSpdTable.c deleted file mode 100644 index 18a04eba17..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/N1xxWUSp= dTable.c +++ /dev/null @@ -1,426 +0,0 @@ -/** @file - GPIO definition table for N1xxWU - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _N1_XX_WU_SPD_TABLE_H_ -#define _N1_XX_WU_SPD_TABLE_H_ - -// -// DQByteMap[0] - ClkDQByteMap: -// If clock is per rank, program to [0xFF, 0xFF] -// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] -// If clock is shared by 2 ranks but does not go to all bytes, -// Entry[i] defines which DQ bytes Group i services -// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN= /CAB -// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS= /CAB -// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE = /CAB -// For DDR, DQByteMap[3:1] =3D [0xFF, 0] -// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have= 1 CTL / rank -// Variable only exists to make the code eas= ier to use -// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have= 1 CA Vref -// Variable only exists to make the code eas= ier to use -// -// -// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL S= DS - used by SKL/KBL MRC -// -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] =3D { - // Channel 0: - { - { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] - { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4] - { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4] - { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes - { 0xFF, 0x00 } // CA Vref is one for all bytes - }, - // Channel 1: - { - { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] - { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4] - { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4] - { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB - { 0xFF, 0x00 }, // CTL (CS) goes to all bytes - { 0xFF, 0x00 } // CA Vref is one for all bytes - } -}; - -// -// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP -// - -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] =3D= { - { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0 - { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1 -}; - -// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16 -// or Hynix H9CCNNNBLTALAR-NUD -// or similar -// 1867, 14-17-17-40 -// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb =3D 4GB total per channel -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] =3D { - 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size - 0x20, ///< 1 SPD Revision - 0x0F, ///< 2 DRAM Device Type - 0x0E, ///< 3 Module Type - 0x14, ///< 4 SDRAM Density and Banks: = 8 Banks, 4 Gb SDRAM density - 0x12, ///< 5 SDRAM Addressing: 14 Rows= , 11 Columns - 0xB5, ///< 6 SDRAM Package Type: QDP, = 1 Channel per die, Signal Loading Matrix 1 - 0x00, ///< 7 SDRAM Optional Features - 0x00, ///< 8 SDRAM Thermal and Refresh= Options - 0x00, ///< 9 Other SDRAM Optional Feat= ures - 0x00, ///< 10 Reserved - must be coded = as 0x00 - 0x03, ///< 11 Module Nominal Voltage, V= DD - 0x0A, ///< 12 Module Organization, SDRA= M width: 16 bits, 2 Ranks - 0x23, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width - 0x00, ///< 14 Module Thermal Sensor - 0x00, ///< 15 Extended Module Type - 0x00, ///< 16 Reserved - must be coded = as 0x00 - 0x00, ///< 17 Timebases - 0x09, ///< 18 SDRAM Minimum Cycle Time = (tCKmin): tCKmin =3D 1.071ns (LPDDR3-1867) - 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax) - 0xD4, ///< 20 CAS Latencies Supported, = First Byte (tCK): 14, 12, 10, 8 - 0x00, ///< 21 CAS Latencies Supported, = Second Byte - 0x00, ///< 22 CAS Latencies Supported, = Third Byte - 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte - 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin) =3D 14.994 ns - 0x00, ///< 25 Read and Write Latency Se= t Options - 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin) - 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab) - 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb) - 0x10, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte - 0x04, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte - 0xE0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte - 0x01, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping - 0, 0, ///< 78 - 79 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 - 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb) - 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab) - 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin) - 0xFA, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867) - 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax): 32.002 ns - 0xCA, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867) - 0x00, ///< 126 CRC A - 0x00, ///< 127 CRC B - 0, 0, ///< 128 - 129 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 - 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte - 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte - 0x00, ///< 322 Module Manufacturing Loca= tion - 0x00, ///< 323 Module Manufacturing Date= Year - 0x00, ///< 324 Module Manufacturing Date= Week - 0x55, ///< 325 Module Serial Number A - 0x00, ///< 326 Module Serial Number B - 0x00, ///< 327 Module Serial Number C - 0x00, ///< 328 Module Serial Number D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20) - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number - 0x00, ///< 349 Module Revision Code - 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte - 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte - 0x00, ///< 352 DRAM Stepping - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 - 0, 0 ///< 510 - 511 -}; - -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize =3D sizeof= (mSkylakeRvp16Spd); - -//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die -//1867 -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] =3D { - 0x91, ///< 0 Number of Serial PD Byt= es Written / SPD Device Size / CRC Coverage 1, 2 - 0x20, ///< 1 SPD Revision - 0xF1, ///< 2 DRAM Device Type - 0x03, ///< 3 Module Type - 0x05, ///< 4 SDRAM Density and Banks= , 8Gb - 0x19, ///< 5 SDRAM Addressing: 15 Ro= ws, 10 Columns - 0x05, ///< 6 Module Nominal Voltage - 0x0B, ///< 7 Module Organization: 32= bits, 2 Ranks - 0x03, ///< 8 Module Memory Bus Width - 0x11, ///< 9 Fine Timebase (FTB) Div= idend / Divisor - 0x01, ///< 10 Medium Timebase (MTB) D= ividend - 0x08, ///< 11 Medium Timebase (MTB) D= ivisor - 0x09, ///< 12 SDRAM Minimum Cycle Tim= e (tCKmin): tCKmin =3D 1.071 ns (LPDDR3-1867) - 0x00, ///< 13 Reserved0 - 0x50, ///< 14 CAS Latencies supported= (tCK): 14, 12, 10, 8 (LSB) - 0x05, ///< 15 CAS Latencies supported= (tCK): 14, 12, 10, 8 (LSB) - 0x78, ///< 16 Minimum CAS Latency (tA= Amin) =3D 14.994 ns - 0x78, ///< 17 Minimum Write Recovery = Time (tWRmin) - 0x90, ///< 18 Minimum RAS# to CAS# De= lay Time (tRCDmin) - 0x50, ///< 19 Minimum Row Active to R= ow Active Delay Time (tRRDmin) - 0x90, ///< 20 Minimum Row Precharge D= elay Time (tRPmin) - 0x11, ///< 21 Upper Nibbles for tRAS = and tRC - 0x50, ///< 22 Minimum Active to Prech= arge Delay Time (tRASmin), Least Significant Byte - 0xE0, ///< 23 Minimum Active to Activ= e/Refresh Delay Time (tRCmin), Least Significant Byte - 0x90, ///< 24 Minimum Refresh Recover= y Delay Time (tRFCmin), Least Significant Byte - 0x06, ///< 25 Minimum Refresh Recover= y Delay Time (tRFCmin), Most Significant Byte - 0x3C, ///< 26 Minimum Internal Write = to Read Command Delay Time (tWTRmin) - 0x3C, ///< 27 Minimum Internal Read t= o Precharge Command Delay Time (tRTPmin) - 0x01, ///< 28 Upper Nibble for tFAW - 0x90, ///< 29 Minimum Four Activate W= indow Delay Time (tFAWmin) - 0x00, ///< 30 SDRAM Optional Features - 0x00, ///< 31 SDRAMThermalAndRefreshO= ptions - 0x00, ///< 32 ModuleThermalSensor - 0x00, ///< 33 SDRAM Device Type - 0xCA, ///< 34 Fine Offset for SDRAM M= inimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867) - 0xFA, ///< 35 Fine Offset for Minimum= CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867) - 0x00, ///< 36 Fine Offset for Minimum= RAS# to CAS# Delay Time (tRCDmin) - 0x00, ///< 37 Fine Offset for Minimum= Row Precharge Delay Time (tRPmin) - 0x00, ///< 38 Fine Offset for Minimum= Active to Active/Refresh Delay Time (tRCmin) - 0xA8, ///< 39 Row precharge time for = all banks (tRPab) - 0x00, ///< 40 FTB for Row precharge t= ime for all banks (tRPab) - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 - 0, 0, ///< 60 - 61 - 0x00, ///< 62 Reference Raw Card Used - 0x00, ///< 63 Address Mapping from Ed= ge Connector to DRAM - 0x00, ///< 64 ThermalHeatSpreaderSolu= tion - 0, 0, 0, 0, 0, ///< 65 - 69 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116 - 0x00, ///< 117 Module Manufacturer ID = Code, Least Significant Byte - 0x00, ///< 118 Module Manufacturer ID = Code, Most Significant Byte - 0x00, ///< 119 Module Manufacturing Lo= cation - 0x00, ///< 120 Module Manufacturing Da= te Year - 0x00, ///< 121 Module Manufacturing Da= te creation work week - 0x55, ///< 122 Module Serial Number A - 0x00, ///< 123 Module Serial Number B - 0x00, ///< 124 Module Serial Number C - 0x00, ///< 125 Module Serial Number D - 0x00, ///< 126 CRC A - 0x00 ///< 127 CRC B -}; - -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size =3D size= of (mSkylakeRvp3Spd110); - -// -// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32 -// -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] =3D { - 0x91, ///< 0 128 SPD bytes used, 256= total, CRC covers 0..116 - 0x20, ///< 1 SPD Revision 2.0 - 0xF1, ///< 2 DRAM Type: LPDDR3 SDRAM - 0x03, ///< 3 Module Type: SO-DIMM - 0x05, ///< 4 8 Banks, 8 Gb SDRAM den= sity - 0x19, ///< 5 SDRAM Addressing: 15 Ro= ws, 10 Columns - 0x05, ///< 6 Module Nominal Voltage = VDD: 1.2v - 0x0B, ///< 7 SDRAM width: 32 bits, 2= Ranks - 0x03, ///< 8 SDRAM bus width: 64 bit= s, no ECC - 0x11, ///< 9 Fine Timebase (FTB) gra= nularity: 1 ps - 0x01, ///< 10 Medium Timebase (MTB) := 0.125 ns - 0x08, ///< 11 Medium Timebase Divisor - 0x08, ///< 12 tCKmin =3D 0.938 ns (LP= DDR3-2133) - 0x00, ///< 13 Reserved - 0x50, ///< 14 CAS Latencies supported= (tCK): 16, 14, 12, 10, 8 (LSB) - 0x15, ///< 15 CAS Latencies supported= (tCK): 16, 14, 12, 10, 8 (MSB) - 0x78, ///< 16 Minimum CAS Latency (tA= Amin) =3D 15.008 ns - 0x78, ///< 17 tWR =3D 15 ns - 0x90, ///< 18 Minimum RAS-to-CAS dela= y (tRCDmin) =3D 18 ns - 0x50, ///< 19 tRRD =3D 10 ns - 0x90, ///< 20 Minimum row precharge t= ime (tRPmin) =3D 18 ns - 0x11, ///< 21 Upper nibbles for tRAS = and tRC - 0x50, ///< 22 tRASmin =3D 42 ns - 0xE0, ///< 23 tRCmin =3D (tRASmin + = tRPmin) =3D 60 ns - 0x90, ///< 24 tRFCmin =3D (tRFCab) = =3D 210 ns (8Gb) - 0x06, ///< 25 tRFCmin MSB - 0x3C, ///< 26 tWTRmin =3D 7.5 ns - 0x3C, ///< 27 tRTPmin =3D 7.5 ns - 0x01, ///< 28 tFAWmin upper nibble - 0x90, ///< 29 tFAWmin =3D 50 ns - 0x00, ///< 30 SDRAM Optional Features= - none - 0x00, ///< 31 SDRAM Thermal / Refresh= options - none - 0x00, ///< 32 ModuleThermalSensor - 0x00, ///< 33 SDRAM Device Type - 0xC2, ///< 34 FTB for tCKmin =3D 0.93= 8 ns (LPDDR3-2133) - 0x08, ///< 35 FTB for tAAmin =3D 15.0= 08 ns (LPDDR3-2133) - 0x00, ///< 36 Fine Offset for Minimum= RAS# to CAS# Delay Time (tRCDmin) - 0x00, ///< 37 Fine Offset for Minimum= Row Precharge Delay Time (tRPmin) - 0x00, ///< 38 Fine Offset for Minimum= Active to Active/Refresh Delay Time (tRCmin) - 0xA8, ///< 39 Row precharge time for = all banks (tRPab)=3D 21 ns - 0x00, ///< 40 FTB for Row precharge t= ime for all banks (tRPab) =3D 0 - 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 - 0, 0, ///< 60 - 61 - 0x00, ///< 62 Reference Raw Card Used - 0x00, ///< 63 Rank1 Mapping: Standard - 0x00, ///< 64 ThermalHeatSpreaderSolu= tion - 0, 0, 0, 0, 0, ///< 65 - 69 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 - 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116 - 0x00, ///< 117 Module Manufacturer ID = Code, Least Significant Byte - 0x00, ///< 118 Module Manufacturer ID = Code, Most Significant Byte - 0x00, ///< 119 Module Manufacturing Lo= cation - 0x00, ///< 120 Module Manufacturing Da= te Year - 0x00, ///< 121 Module Manufacturing Da= te creation work week - 0x55, ///< 122 Module ID: Module Seria= l Number - 0x00, ///< 123 Module Serial Number B - 0x00, ///< 124 Module Serial Number C - 0x00, ///< 125 Module Serial Number D - 0x00, ///< 126 CRC A - 0x00 ///< 127 CRC B -}; -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size =3D size= of (mKblRSpdLpddr32133); - -GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] =3D { - 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size - 0x01, ///< 1 SPD Revision - 0x0F, ///< 2 DRAM Device Type - 0x0E, ///< 3 Module Type - 0x15, ///< 4 SDRAM Density and Banks: = 8 Banks, 8 Gb SDRAM density - 0x19, ///< 5 SDRAM Addressing: 15 Rows= , 10 Columns - 0x90, ///< 6 SDRAM Package Type: QDP, = 1 Channel per die, Signal Loading Matrix 1 - 0x00, ///< 7 SDRAM Optional Features - 0x00, ///< 8 SDRAM Thermal and Refresh= Options - 0x00, ///< 9 Other SDRAM Optional Feat= ures - 0x00, ///< 10 Reserved - must be coded = as 0x00 - 0x0B, ///< 11 Module Nominal Voltage, V= DD - 0x0B, ///< 12 Module Organization, SDRA= M width: 32 bits, 2 Ranks - 0x03, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width - 0x00, ///< 14 Module Thermal Sensor - 0x00, ///< 15 Extended Module Type - 0x00, ///< 16 Reserved - must be coded = as 0x00 - 0x00, ///< 17 Timebases - 0x08, ///< 18 SDRAM Minimum Cycle Time = (tCKmin) - 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax) - 0xD4, ///< 20 CAS Latencies Supported, = First Byte - 0x01, ///< 21 CAS Latencies Supported, = Second Byte - 0x00, ///< 22 CAS Latencies Supported, = Third Byte - 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte - 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin) - 0x00, ///< 25 Read and Write Latency Se= t Options - 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin) - 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab) - 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb) - 0x90, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte - 0x06, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte - 0xD0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte - 0x02, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte - 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping - 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping - 0, 0, ///< 78 - 79 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 - 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb) - 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab) - 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin) - 0x08, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin) - 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax) - 0xC2, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin) - 0x00, ///< 126 CRC A - 0x00, ///< 127 CRC B - 0, 0, ///< 128 - 129 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 - 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte - 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte - 0x00, ///< 322 Module Manufacturing Loca= tion - 0x00, ///< 323 Module Manufacturing Date= Year - 0x00, ///< 324 Module Manufacturing Date= Week - 0x55, ///< 325 Module Serial Number A - 0x00, ///< 326 Module Serial Number B - 0x00, ///< 327 Module Serial Number C - 0x00, ///< 328 Module Serial Number D - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20) - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number - 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number - 0x00, ///< 349 Module Revision Code - 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte - 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte - 0x00, ///< 352 DRAM Stepping - 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 - 0, 0 ///< 510 - 511 -}; -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size =3D sizeof (= mSpdLpddr32133); - -#endif // _N1_XX_WU_SPD_TABLE_H_ diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiBoardInitPostMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/B= oardInitLib/PeiBoardInitPostMemLib.c deleted file mode 100644 index b7ff3062b2..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoard= InitPostMemLib.c +++ /dev/null @@ -1,39 +0,0 @@ -/** @file - Board post-memory initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardInitBeforeSiliconInit ( - VOID - ); - -EFI_STATUS -EFIAPI -BoardInitBeforeSiliconInit ( - VOID - ) -{ - N1xxWUBoardInitBeforeSiliconInit (); - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -BoardInitAfterSiliconInit ( - VOID - ) -{ - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiBoardInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Bo= ardInitLib/PeiBoardInitPreMemLib.c deleted file mode 100644 index c1fe2a55c0..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiBoard= InitPreMemLib.c +++ /dev/null @@ -1,105 +0,0 @@ -/** @file - Board post-memory initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardDetect ( - VOID - ); - -EFI_BOOT_MODE -EFIAPI -N1xxWUBoardBootModeDetect ( - VOID - ); - -EFI_STATUS -EFIAPI -N1xxWUBoardDebugInit ( - VOID - ); - -EFI_STATUS -EFIAPI -N1xxWUBoardInitBeforeMemoryInit ( - VOID - ); - -EFI_STATUS -EFIAPI -BoardDetect ( - VOID - ) -{ - N1xxWUBoardDetect (); - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -BoardDebugInit ( - VOID - ) -{ - N1xxWUBoardDebugInit (); - return EFI_SUCCESS; -} - -EFI_BOOT_MODE -EFIAPI -BoardBootModeDetect ( - VOID - ) -{ - return N1xxWUBoardBootModeDetect (); -} - -EFI_STATUS -EFIAPI -BoardInitBeforeMemoryInit ( - VOID - ) -{ - N1xxWUBoardInitBeforeMemoryInit (); - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -BoardInitAfterMemoryInit ( - VOID - ) -{ - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -BoardInitBeforeTempRamExit ( - VOID - ) -{ - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -BoardInitAfterTempRamExit ( - VOID - ) -{ - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiMultiBoardInitPostMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Libr= ary/BoardInitLib/PeiMultiBoardInitPostMemLib.c deleted file mode 100644 index 8570039624..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMulti= BoardInitPostMemLib.c +++ /dev/null @@ -1,40 +0,0 @@ -/** @file - Multi-board post-memory initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include - -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardInitBeforeSiliconInit ( - VOID - ); - -BOARD_POST_MEM_INIT_FUNC mN1xxWUBoardInitFunc =3D { - N1xxWUBoardInitBeforeSiliconInit, - NULL, // BoardInitAfterSiliconInit -}; - -EFI_STATUS -EFIAPI -PeiN1xxWUMultiBoardInitLibConstructor ( - VOID - ) -{ - if (LibPcdGetSku () =3D=3D BoardIdN1xxWU) { - return RegisterBoardPostMemInit (&mN1xxWUBoardInitFunc); - } - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Libra= ry/BoardInitLib/PeiMultiBoardInitPreMemLib.c deleted file mode 100644 index 842316e610..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMulti= BoardInitPreMemLib.c +++ /dev/null @@ -1,82 +0,0 @@ -/** @file - Board pre-memory initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include - -#include - -EFI_STATUS -EFIAPI -N1xxWUBoardDetect ( - VOID - ); - -EFI_STATUS -EFIAPI -N1xxWUMultiBoardDetect ( - VOID - ); - -EFI_BOOT_MODE -EFIAPI -N1xxWUBoardBootModeDetect ( - VOID - ); - -EFI_STATUS -EFIAPI -N1xxWUBoardDebugInit ( - VOID - ); - -EFI_STATUS -EFIAPI -N1xxWUBoardInitBeforeMemoryInit ( - VOID - ); - -BOARD_DETECT_FUNC mN1xxWUBoardDetectFunc =3D { - N1xxWUMultiBoardDetect -}; - -BOARD_PRE_MEM_INIT_FUNC mN1xxWUBoardPreMemInitFunc =3D { - N1xxWUBoardDebugInit, - N1xxWUBoardBootModeDetect, - N1xxWUBoardInitBeforeMemoryInit, - NULL, // BoardInitAfterMemoryInit - NULL, // BoardInitBeforeTempRamExit - NULL, // BoardInitAfterTempRamExit -}; - -EFI_STATUS -EFIAPI -N1xxWUMultiBoardDetect ( - VOID - ) -{ - N1xxWUBoardDetect (); - if (LibPcdGetSku () =3D=3D BoardIdN1xxWU) { - RegisterBoardPreMemInit (&mN1xxWUBoardPreMemInitFunc); - } - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -PeiN1xxWUMultiBoardInitPreMemLibConstructor ( - VOID - ) -{ - return RegisterBoardDetect (&mN1xxWUBoardDetectFunc); -} \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiN1xxWUDetect.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardIni= tLib/PeiN1xxWUDetect.c deleted file mode 100644 index 9e31a92926..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW= UDetect.c +++ /dev/null @@ -1,66 +0,0 @@ -/** @file - Clevo N1xxWU board detection. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "PeiN1xxWUInitLib.h" - -#include -#include - -BOOLEAN -IsN1xxWU ( - VOID - ) -{ - // TBD: Do detection - BoardIdN1xxWU v.s. BoardIdN1xxWU - return TRUE; -} - -EFI_STATUS -EFIAPI -N1xxWUBoardDetect ( - VOID - ) -{ - if (LibPcdGetSku () !=3D 0) { - return EFI_SUCCESS; - } - - DEBUG ((EFI_D_INFO, "N1xxWUDetectionCallback\n")); - - if (IsN1xxWU ()) { - LibPcdSetSku (BoardIdN1xxWU); - - DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); - ASSERT (LibPcdGetSku() =3D=3D BoardIdN1xxWU); - } - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiN1xxWUInitPostMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/= BoardInitLib/PeiN1xxWUInitPostMemLib.c deleted file mode 100644 index 832130e15e..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW= UInitPostMemLib.c +++ /dev/null @@ -1,209 +0,0 @@ -/** @file - Clevo N1xxWU board post-memory initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "PeiN1xxWUInitLib.h" - -/** - N 1XX WU board configuration init function for PEI post memory phase. - - PEI_BOARD_CONFIG_PCD_INIT - - @param Content pointer to the buffer contain init information for boar= d init. - - @retval EFI_SUCCESS The function completed successfully. - @retval EFI_INVALID_PARAMETER The parameter is NULL. -**/ -EFI_STATUS -EFIAPI -N1xxWUInit ( - VOID - ) -{ - PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3); - - // - // Assign the GPIO table with pin configs to be used for UCMC - // - PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableN1xxWUUcmcDevice); - PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableN1xxWUUcmcDeviceSize); - - return EFI_SUCCESS; -} - -#define EXPANDERS 2 // = defines expander's quantity - -/** - Configures GPIO - - @param[in] GpioTable Point to Platform Gpio table - @param[in] GpioTableCount Number of Gpio table entries - -**/ -VOID -ConfigureGpio ( - IN GPIO_INIT_CONFIG *GpioDefinition, - IN UINT16 GpioTableCount - ) -{ - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); - - Status =3D GpioConfigurePads (GpioTableCount, GpioDefinition); - - DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); -} - -VOID -SetBit ( - IN OUT UINT32 *Value, - IN UINT32 BitNumber, - IN BOOLEAN NewBitValue - ) -{ - if (NewBitValue) { - *Value |=3D 1 << BitNumber; - } else { - *Value &=3D ~(1 << BitNumber); - } -} - -/** - Configures IO Expander GPIO device - - @param[in] IOExpGpioDefinition Point to IO Expander Gpio table - @param[in] IOExpGpioTableCount Number of Gpio table entries - -**/ -void -ConfigureIoExpanderGpio ( - IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition, - IN UINT16 IoExpGpioTableCount - ) -{ - UINT8 Index; - UINT32 Direction[EXPANDERS] =3D {0x00FFFFFF, 0x00FFFFFF}; - UINT32 Level[EXPANDERS] =3D {0}; - UINT32 Polarity[EXPANDERS] =3D {0}; - - // IoExpander {TCA6424A} - DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n")); - for (Index =3D 0; Index < IoExpGpioTableCount; Index++) { //Program IO= Expander as per the table defined in PeiPlatformHooklib.c - SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpG= pioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].Gpi= oDirection); - SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioD= efinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLev= el); - SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGp= ioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].Gpio= Inversion); - } - for (Index =3D 0; Index < EXPANDERS; Index++) { - GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Inde= x]); - } - DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n")); - return; -} - -/** - Configure GPIO behind IoExpander. - - @param[in] PeiServices General purpose services available to ever= y PEIM. - @param[in] NotifyDescriptor - @param[in] Interface - - @retval EFI_SUCCESS Operation success. -**/ -VOID -ExpanderGpioInit ( - VOID - ) -{ - ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize); -} - -/** - Configure single GPIO pad for touchpanel interrupt - -**/ -VOID -TouchpanelGpioInit ( - VOID - ) -{ - GPIO_INIT_CONFIG* TouchpanelPad; - GPIO_PAD_OWN PadOwnVal; - - PadOwnVal =3D 0; - TouchpanelPad =3D &mGpioTableN1xxWUTouchpanel; - - GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal); - if (PadOwnVal =3D=3D GpioPadOwnHost) { - GpioConfigurePads (1, TouchpanelPad); - } -} - - -/** - Configure GPIO - -**/ -VOID -GpioInit ( - VOID - ) -{ - ConfigureGpio (mGpioTableN1xxWU, mGpioTableN1xxWUSize); - - TouchpanelGpioInit(); - - return; -} - - -/** - Configure GPIO and SIO - - @retval EFI_SUCCESS Operation success. -**/ -EFI_STATUS -EFIAPI -N1xxWUBoardInitBeforeSiliconInit ( - VOID - ) -{ - N1xxWUInit (); - - GpioInit (); - ExpanderGpioInit (); - - /// - /// Do Late PCH init - /// - LateSiliconInit (); - - return EFI_SUCCESS; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiN1xxWUInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/B= oardInitLib/PeiN1xxWUInitPreMemLib.c deleted file mode 100644 index b8eb0e67c6..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW= UInitPreMemLib.c +++ /dev/null @@ -1,236 +0,0 @@ -/** @file - Clevo N1xxWU board pre-memory initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "PeiN1xxWUInitLib.h" - -#include -#include - -// -// Reference RCOMP resistors on motherboard - for SKL RVP1 -// -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX= _RCOMP] =3D { 200, 81, 162 }; -// -// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SK= L RVP1 -// -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 40, 23, 40 }; - -// -// Reference RCOMP resistors on motherboard - for SKL RVP2 -// -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp2[SA_MRC_MAX= _RCOMP] =3D { 121, 81, 100 }; -// -// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SK= L RVP2 -// -GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp2[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 20, 20, 26 }; - -/** - N 1XX WU board configuration init function for PEI pre-memory phase. - - PEI_BOARD_CONFIG_PCD_INIT - - @param Content pointer to the buffer contain init information for boar= d init. - - @retval EFI_SUCCESS The function completed successfully. - @retval EFI_INVALID_PARAMETER The parameter is NULL. -**/ -EFI_STATUS -EFIAPI -N1xxWUInitPreMem ( - VOID - ) -{ - PcdSet32S (PcdPcie0WakeGpioNo, 0); - PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); - PcdSet32S (PcdPcie0HoldRstGpioNo, 8); - PcdSetBoolS (PcdPcie0HoldRstActive, TRUE); - PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); - PcdSet32S (PcdPcie0PwrEnableGpioNo, 16); - PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); - - // - // HSIO PTSS Table - // - PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_N1x= xWU); - PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_N1x= xWU_Size); - PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_N1x= xWU); - PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_N1x= xWU_Size); - - // - // DRAM related definition - // - PcdSet8S (PcdSaMiscUserBd, 5); - - PcdSet8S (PcdMrcSpdAddressTable0, 0xA0); - PcdSet8S (PcdMrcSpdAddressTable1, 0xA2); - PcdSet8S (PcdMrcSpdAddressTable2, 0xA4); - PcdSet8S (PcdMrcSpdAddressTable3, 0xA6); - - - PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE); - PcdSetBoolS(PcdMrcDqPinsInterleaved, TRUE); - PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorSklRvp2); - PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetSklRvp2); - PcdSet8S(PcdMrcCaVrefConfig, 2); // DDR4 boards - - PcdSetBoolS (PcdIoExpanderPresent, TRUE); - - return EFI_SUCCESS; -} - -#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 - -/** - Configures GPIO - - @param[in] GpioTable Point to Platform Gpio table - @param[in] GpioTableCount Number of Gpio table entries - -**/ -VOID -ConfigureGpio ( - IN GPIO_INIT_CONFIG *GpioDefinition, - IN UINT16 GpioTableCount - ) -{ - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); - - Status =3D GpioConfigurePads (GpioTableCount, GpioDefinition); - - DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); -} - -/** - Configure GPIO Before Memory is not ready. - -**/ -VOID -GpioInitPreMem ( - VOID - ) -{ - // ConfigureGpio (); -} - -/** - Configure Super IO - -**/ -VOID -SioInit ( - VOID - ) -{ - // - // Program and Enable Default Super IO Configuration Port Addresses and = range - // - PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x1= 0); - - // - // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF; - // - PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10); - - return; -} - -/** - Configues the IC2 Controller on which GPIO Expander Communicates. - This Function is to enable the I2CGPIOExapanderLib to programm the Gpios - Complete intilization will be done in later Stage - -**/ -VOID -EFIAPI -I2CGpioExpanderInitPreMem( - VOID - ) -{ - ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden= ); - SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSer= ialIoIs33V); -} - -/** - Configure GPIO and SIO before memory ready - - @retval EFI_SUCCESS Operation success. -**/ -EFI_STATUS -EFIAPI -N1xxWUBoardInitBeforeMemoryInit ( - VOID - ) -{ - N1xxWUInitPreMem (); - - // - // Configures the I2CGpioExpander - // - if (PcdGetBool (PcdIoExpanderPresent)) { - I2CGpioExpanderInitPreMem(); - } - - GpioInitPreMem (); - SioInit (); - - /// - /// Do basic PCH init - /// - SiliconInit (); - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -N1xxWUBoardDebugInit ( - VOID - ) -{ - /// - /// Do Early PCH init - /// - EarlySiliconInit (); - return EFI_SUCCESS; -} - -EFI_BOOT_MODE -EFIAPI -N1xxWUBoardBootModeDetect ( - VOID - ) -{ - return BOOT_WITH_FULL_CONFIGURATION; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Inte= l/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platfo= rm/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/Pl= atformInit/PlatformInitPei/PlatformInitPreMem.c deleted file mode 100644 index b784026c1b..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPl= atformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c +++ /dev/null @@ -1,640 +0,0 @@ -/** @file - Source code file for Platform Init Pre-Memory PEI module - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -EFI_STATUS -EFIAPI -MemoryDiscoveredPpiNotifyCallback ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, - IN VOID *Ppi - ); - -EFI_STATUS -EFIAPI -GetPlatformMemorySize ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, - IN OUT UINT64 *MemorySize - ); - -/** - - This function checks the memory range in PEI. - - @param PeiServices Pointer to PEI Services. - @param This Pei memory test PPI pointer. - @param BeginAddress Beginning of the memory address to be checked. - @param MemoryLength Bytes of memory range to be checked. - @param Operation Type of memory check operation to be performed. - @param ErrorAddress Return the address of the error memory address. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. - -**/ -EFI_STATUS -EFIAPI -BaseMemoryTest ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_BASE_MEMORY_TEST_PPI *This, - IN EFI_PHYSICAL_ADDRESS BeginAddress, - IN UINT64 MemoryLength, - IN PEI_MEMORY_TEST_OP Operation, - OUT EFI_PHYSICAL_ADDRESS *ErrorAddress - ); - -static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D { - (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), - &gEfiPeiMemoryDiscoveredPpiGuid, - (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootM= ode =3D { - (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), - &gEfiPeiBootInRecoveryModePpiGuid, - NULL -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode =3D { - (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), - &gEfiPeiMasterBootModePpiGuid, - NULL -}; - -static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi =3D { BaseMemory= Test }; - -static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi =3D { GetPlatfor= mMemorySize }; - -static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] =3D { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gPeiBaseMemoryTestPpiGuid, - &mPeiBaseMemoryTestPpi - }, - { - (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), - &gPeiPlatformMemorySizePpiGuid, - &mMemoryMemorySizePpi - }, -}; - -/// -/// Memory Reserved should be between 125% to 150% of the Current required= memory -/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum= e issues. -/// -GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { - { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL - { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) - { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) - { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)= }, // Runtime Service Data - { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)= }, // Runtime Service Code - { EfiMaxMemoryType, 0 } -}; - -VOID -BuildMemoryTypeInformation ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; - UINTN DataSize; - EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; - - // - // Locate system configuration variable - // - Status =3D PeiServicesLocatePpi( - &gEfiPeiReadOnlyVariable2PpiGuid, // GUID - 0, // INSTANCE - NULL, // EFI_PEI_PPI_DESCRIPTOR - (VOID **) &VariableServices // PPI - ); - ASSERT_EFI_ERROR(Status); - - DataSize =3D sizeof (MemoryData); - Status =3D VariableServices->GetVariable ( - VariableServices, - EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, - &gEfiMemoryTypeInformationGuid, - NULL, - &DataSize, - &MemoryData - ); - if (EFI_ERROR(Status)) { - DataSize =3D sizeof (mDefaultMemoryTypeInformation); - CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize); - } - - /// - /// Build the GUID'd HOB for DXE - /// - BuildGuidDataHob ( - &gEfiMemoryTypeInformationGuid, - MemoryData, - DataSize - ); -} - -EFI_STATUS -EFIAPI -GetPlatformMemorySize ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, - IN OUT UINT64 *MemorySize - ) -{ - EFI_STATUS Status; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; - UINTN DataSize; - EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; - UINTN Index; - EFI_BOOT_MODE BootMode; - UINTN IndexNumber; - -#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x1= 00000)) - - *MemorySize =3D PEI_MIN_MEMORY_SIZE; - Status =3D PeiServicesLocatePpi ( - &gEfiPeiReadOnlyVariable2PpiGuid, - 0, - NULL, - (VOID **)&Variable - ); - - ASSERT_EFI_ERROR (Status); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - DataSize =3D sizeof (MemoryData); - - Status =3D Variable->GetVariable ( - Variable, - EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, - &gEfiMemoryTypeInformationGuid, - NULL, - &DataSize, - &MemoryData - ); - IndexNumber =3D sizeof (mDefaultMemoryTypeInformation) / sizeof (EFI_MEM= ORY_TYPE_INFORMATION); - - // - // Accumulate maximum amount of memory needed - // - - DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n", DivU64x32(*MemorySize= ,1024))); - DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n", IndexNumber,= DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION))); - if (EFI_ERROR (Status)) { - // - // Start with minimum memory - // - for (Index =3D 0; Index < IndexNumber; Index++) { - DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformat= ion[Index].NumberOfPages)); - *MemorySize +=3D mDefaultMemoryTypeInformation[Index].NumberOfPages = * EFI_PAGE_SIZE; - } - DEBUG((DEBUG_ERROR, "No memory type, Total platform memory:%dKB \n", = DivU64x32(*MemorySize,1024))); - } else { - // - // Start with at least 0x200 pages of memory for the DXE Core and the = DXE Stack - // - for (Index =3D 0; Index < IndexNumber; Index++) { - DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages)); - *MemorySize +=3D MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; - - } - DEBUG((DEBUG_ERROR, "has memory type, Total platform memory:%dKB \n",= DivU64x32(*MemorySize,1024))); - } - - return EFI_SUCCESS; -} - -/** - - This function checks the memory range in PEI. - - @param PeiServices Pointer to PEI Services. - @param This Pei memory test PPI pointer. - @param BeginAddress Beginning of the memory address to be checked. - @param MemoryLength Bytes of memory range to be checked. - @param Operation Type of memory check operation to be performed. - @param ErrorAddress Return the address of the error memory address. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. - -**/ -EFI_STATUS -EFIAPI -BaseMemoryTest ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_BASE_MEMORY_TEST_PPI *This, - IN EFI_PHYSICAL_ADDRESS BeginAddress, - IN UINT64 MemoryLength, - IN PEI_MEMORY_TEST_OP Operation, - OUT EFI_PHYSICAL_ADDRESS *ErrorAddress - ) -{ - UINT32 TestPattern; - UINT32 SpanSize; - EFI_PHYSICAL_ADDRESS TempAddress; - -#define MEMORY_TEST_PATTERN 0x5A5A5A5A -#define MEMORY_TEST_COVER_SPAN 0x40000 - - TestPattern =3D MEMORY_TEST_PATTERN; - SpanSize =3D 0; - - // - // Make sure we don't try and test anything above the max physical addre= ss range - // - ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS); - - switch (Operation) { - case Extensive: - SpanSize =3D 0x4; - break; - - case Sparse: - case Quick: - SpanSize =3D MEMORY_TEST_COVER_SPAN; - break; - - case Ignore: - goto Done; - break; - } - // - // Write the test pattern into memory range - // - TempAddress =3D BeginAddress; - while (TempAddress < BeginAddress + MemoryLength) { - (*(UINT32 *) (UINTN) TempAddress) =3D TestPattern; - TempAddress +=3D SpanSize; - } - // - // Read pattern from memory and compare it - // - TempAddress =3D BeginAddress; - while (TempAddress < BeginAddress + MemoryLength) { - if ((*(UINT32 *) (UINTN) TempAddress) !=3D TestPattern) { - *ErrorAddress =3D TempAddress; - return EFI_DEVICE_ERROR; - } - - TempAddress +=3D SpanSize; - } - -Done: - - return EFI_SUCCESS; -} - -/** - Set Cache Mtrr. -**/ -VOID -SetCacheMtrr ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_HOB_POINTERS Hob; - MTRR_SETTINGS MtrrSetting; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 LowMemoryLength; - UINT64 HighMemoryLength; - EFI_BOOT_MODE BootMode; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - UINT64 CacheMemoryLength; - - /// - /// Reset all MTRR setting. - /// - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - /// - /// Cache the Flash area as WP to boost performance - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), - (UINTN) PcdGet32 (PcdFlashAreaSize), - CacheWriteProtected - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance - /// - MtrrSetAllMtrrs (&MtrrSetting); - - /// - /// Set low to 1 MB. Since 1MB cacheability will always be set - /// until override by CSM. - /// Initialize high memory to 0. - /// - LowMemoryLength =3D 0x100000; - HighMemoryLength =3D 0; - ResourceAttribute =3D ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode !=3D BOOT_ON_S3_RESUME) { - ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; - } - - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || - ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && - (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) - ) { - if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { - HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { - LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } - } - } - - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); - DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); - - /// - /// Assume size of main memory is multiple of 256MB - /// - MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; - MemoryBase =3D 0; - - CacheMemoryLength =3D MemoryLength; - /// - /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB - /// - if (MemoryLength > 0xDC000000) { - CacheMemoryLength =3D 0xC0000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xC0000000; - CacheMemoryLength =3D MemoryLength - 0xC0000000; - if (MemoryLength > 0xE0000000) { - CacheMemoryLength =3D 0x20000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xE0000000; - CacheMemoryLength =3D MemoryLength - 0xE0000000; - } - } - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - if (LowMemoryLength !=3D MemoryLength) { - MemoryBase =3D LowMemoryLength; - MemoryLength -=3D LowMemoryLength; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - MemoryLength, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } - - /// - /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer - /// - MtrrSetAllMtrrs (&MtrrSetting); - - return ; -} - -VOID -ReportCpuHob ( - VOID - ) -{ - UINT8 PhysicalAddressBits; - UINT32 RegEax; - - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); - if (RegEax >=3D 0x80000008) { - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PhysicalAddressBits =3D (UINT8) RegEax; - } else { - PhysicalAddressBits =3D 36; - } - - /// - /// Create a CPU hand-off information - /// - BuildCpuHob (PhysicalAddressBits, 16); -} - -/** - Install Firmware Volume Hob's once there is main memory - - @param[in] PeiServices General purpose services available to ever= y PEIM. - @param[in] NotifyDescriptor Notify that this module published. - @param[in] Ppi PPI that was installed. - - @retval EFI_SUCCESS The function completed successfully. -**/ -EFI_STATUS -EFIAPI -MemoryDiscoveredPpiNotifyCallback ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, - IN VOID *Ppi - ) -{ - EFI_STATUS Status; - EFI_BOOT_MODE BootMode; - - Status =3D BoardInitAfterMemoryInit (); - ASSERT_EFI_ERROR (Status); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - - ReportCpuHob (); - - TestPointMemoryDiscoveredMtrrFunctional (); - - TestPointMemoryDiscoveredMemoryResourceFunctional (); - - /// - /// If S3 resume, then we are done - /// - if (BootMode =3D=3D BOOT_ON_S3_RESUME) { - return EFI_SUCCESS; - } - - TestPointMemoryDiscoveredDmaProtectionEnabled (); - - if (PcdGetBool (PcdStopAfterMemInit)) { - CpuDeadLoop (); - } - - return Status; -} - - -/** - This function handles PlatformInit task after PeiReadOnlyVariable2 PPI p= roduced - - @param[in] PeiServices Pointer to PEI Services Table. - - @retval EFI_SUCCESS The function completes successfully - @retval others -**/ -EFI_STATUS -EFIAPI -PlatformInitPreMem ( - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - EFI_BOOT_MODE BootMode; - - // - // Start board detection - // - BoardDetect (); - - BoardDebugInit (); - - TestPointDebugInitDone (); - - if (PcdGetBool (PcdStopAfterDebugInit)) { - CpuDeadLoop (); - } - - BootMode =3D BoardBootModeDetect (); - Status =3D PeiServicesSetBootMode (BootMode); - ASSERT_EFI_ERROR (Status); - if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { - Status =3D PeiServicesInstallPpi (&mPpiListRecoveryBootMode); - } - /// - /// Signal possible dependent modules that there has been a - /// final boot mode determination, it is used to build BIST - /// Hob for Dxe use. - /// - Status =3D PeiServicesInstallPpi (&mPpiBootMode); - ASSERT_EFI_ERROR (Status); - - BuildMemoryTypeInformation (); - - if (!PcdGetBool(PcdFspWrapperBootMode)) { - Status =3D PeiServicesInstallPpi (mMemPpiList); - ASSERT_EFI_ERROR (Status); - } - - Status =3D BoardInitBeforeMemoryInit (); - ASSERT_EFI_ERROR (Status); - - return Status; -} - - -/** - Platform Init before memory PEI module entry point - - @param[in] FileHandle Not used. - @param[in] PeiServices General purpose services available to e= very PEIM. - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se -**/ -EFI_STATUS -EFIAPI -PlatformInitPreMemEntryPoint ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - - Status =3D PlatformInitPreMem (PeiServices); - - /// - /// After code reorangized, memorycallback will run because the PPI is a= lready - /// installed when code run to here, it is supposed that the InstallEfiM= emory is - /// done before. - /// - Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList); - - return Status; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSili= conPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/ClevoOpenBoardPkg/N1= xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c deleted file mode 100644 index 99c7d42c4e..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli= cyUpdateLib/DxeGopPolicyInit.c +++ /dev/null @@ -1,175 +0,0 @@ -/** @file - DXE GOP policy initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "DxeGopPolicyInit.h" -#include - -GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy; -GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0; -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress =3D 0= ; - -// -// Function implementations -// - -/** - - @param[out] CurrentLidStatus - - @retval EFI_SUCCESS - @retval EFI_UNSUPPORTED -**/ -EFI_STATUS -EFIAPI -GetPlatformLidStatus ( - OUT LID_STATUS *CurrentLidStatus - ) -{ - return EFI_UNSUPPORTED; -} -/** - - @param[out] CurrentDockStatus - - @retval EFI_SUCCESS - @retval EFI_UNSUPPORTED -**/ -EFI_STATUS -EFIAPI -GetPlatformDockStatus ( - OUT DOCK_STATUS CurrentDockStatus - ) -{ - return EFI_UNSUPPORTED; -} - - -/** - - @param[out] VbtAddress - @param[out] VbtSize - - @retval EFI_SUCCESS - @retval EFI_NOT_FOUND -**/ -EFI_STATUS -EFIAPI -GetVbtData ( - OUT EFI_PHYSICAL_ADDRESS *VbtAddress, - OUT UINT32 *VbtSize - ) -{ - EFI_STATUS Status; - UINTN FvProtocolCount; - EFI_HANDLE *FvHandles; - EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; - UINTN Index; - UINT32 AuthenticationStatus; - UINT8 *Buffer; - UINTN VbtBufferSize; - - - Status =3D EFI_NOT_FOUND; - if ( mVbtAddress =3D=3D 0) { - Fv =3D NULL; - - Buffer =3D 0; - FvHandles =3D NULL; - Status =3D gBS->LocateHandleBuffer ( - ByProtocol, - &gEfiFirmwareVolume2ProtocolGuid, - NULL, - &FvProtocolCount, - &FvHandles - ); - if (!EFI_ERROR (Status)) { - for (Index =3D 0; Index < FvProtocolCount; Index++) { - Status =3D gBS->HandleProtocol ( - FvHandles[Index], - &gEfiFirmwareVolume2ProtocolGuid, - (VOID **) &Fv - ); - VbtBufferSize =3D 0; - Status =3D Fv->ReadSection ( - Fv, - PcdGetPtr (PcdGraphicsVbtGuid), - EFI_SECTION_RAW, - 0, - (VOID **) &Buffer, - &VbtBufferSize, - &AuthenticationStatus - ); - if (!EFI_ERROR (Status)) { - *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)Buffer; - *VbtSize =3D (UINT32)VbtBufferSize; - mVbtAddress =3D *VbtAddress; - mVbtSize =3D *VbtSize; - Status =3D EFI_SUCCESS; - break; - } - } - } else { - Status =3D EFI_NOT_FOUND; - } - - if (FvHandles !=3D NULL) { - FreePool (FvHandles); - FvHandles =3D NULL; - } - } else { - *VbtAddress =3D mVbtAddress; - *VbtSize =3D mVbtSize; - Status =3D EFI_SUCCESS; - } - - return Status; -} - - - -/** -Initialize GOP DXE Policy - -@param[in] ImageHandle Image handle of this driver. - -@retval EFI_SUCCESS Initialization complete. -@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. -@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. -@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. -**/ - -EFI_STATUS -EFIAPI -GopPolicyInitDxe ( - IN EFI_HANDLE ImageHandle - ) -{ - EFI_STATUS Status; - - // - // Initialize the EFI Driver Library - // - SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); - - mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03; - mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus; - mGOPPolicy.GetVbtData =3D GetVbtData; - mGOPPolicy.GetPlatformDockStatus =3D GetPlatformDockStatus; - - // - // Install protocol to allow access to this Policy. - // - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &ImageHandle, - &gGopPolicyProtocolGuid, - &mGOPPolicy, - NULL - ); - - return Status; -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSili= conPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/ClevoOpenBoardPkg/N= 1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c deleted file mode 100644 index d140237576..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli= cyUpdateLib/DxeSaPolicyUpdate.c +++ /dev/null @@ -1,65 +0,0 @@ -/** @file - This file is the library for SA DXE Policy initialization. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "DxeSaPolicyInit.h" - -#define SA_VTD_RMRR_USB_LENGTH 0x20000 - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddre= ss; -GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize; - -/** - Update RMRR Base and Limit Address for USB. - -**/ -VOID -UpdateRmrrUsbAddress ( - IN OUT SA_POLICY_PROTOCOL *SaPolicy - ) -{ - EFI_STATUS Status; - MISC_DXE_CONFIG *MiscDxeConfig; - - Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID = *)&MiscDxeConfig); - ASSERT_EFI_ERROR (Status); - - if (1) { - mSize =3D EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH); - mAddress =3D SIZE_4GB; - - Status =3D (gBS->AllocatePages) ( - AllocateMaxAddress, - EfiReservedMemoryType, - mSize, - &mAddress - ); - ASSERT_EFI_ERROR (Status); - - MiscDxeConfig->RmrrUsbBaseAddress[0] =3D mAddress; - MiscDxeConfig->RmrrUsbBaseAddress[1] =3D mAddress + SA_VTD_RMRR_USB_LE= NGTH - 1; - } -} - -/** - Get data for platform policy from setup options. - - @param[in] SaPolicy The pointer to get SA Policy protoc= ol instance - - @retval EFI_SUCCESS Operation success. - -**/ -EFI_STATUS -EFIAPI -UpdateDxeSaPolicy ( - IN OUT SA_POLICY_PROTOCOL *SaPolicy - ) -{ - UpdateRmrrUsbAddress (SaPolicy); - return EFI_SUCCESS; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSili= conPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Intel/ClevoOpenBo= ardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpda= teLib.c deleted file mode 100644 index 5c7f388213..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPoli= cyUpdateLib/DxeSiliconPolicyUpdateLib.c +++ /dev/null @@ -1,54 +0,0 @@ -/** @file - DXE silicon policy update library. - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include - -#include "DxeSaPolicyInit.h" -#include "DxeGopPolicyInit.h" - -/** - Performs silicon late policy update. - - The meaning of Policy is defined by silicon code. - It could be the raw data, a handle, a Protocol, etc. - - The input Policy must be returned by SiliconPolicyDoneLate(). - - In FSP or non-FSP path, the board may use additional way to get - the silicon policy data field based upon the input Policy. - - @param[in, out] Policy Pointer to policy. - - @return the updated policy. -**/ -VOID * -EFIAPI -SiliconPolicyUpdateLate ( - IN VOID *Policy - ) -{ - SA_POLICY_PROTOCOL *SaPolicy; - EFI_STATUS Status; - - SaPolicy =3D Policy; - UpdateDxeSaPolicy (SaPolicy); - - if (PcdGetBool(PcdIntelGopEnable)) { - // - // GOP Dxe Policy Initialization - // - Status =3D GopPolicyInitDxe(gImageHandle); - DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); - ASSERT_EFI_ERROR(Status); - } - - return Policy; -} - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.AS= L b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL deleted file mode 100644 index bcc3405e33..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/ALS.ASL +++ /dev/null @@ -1,37 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Device(ALSD) -{ - Name(_HID,"ACPI0008") - - Method(_STA,0) - { - If(LEqual(ALSE,2)) - { - Return(0x000B) // ALS Enabled. Don't show it in UI. - } - - Return(0x0000) // ALS Disabled. Hide it. - } - - Method(_ALI) - { - Return (Or(ShiftLeft(LHIH,8),LLOW)) - } - - Name(_ALR, Package() - { - Package() {70, 0}, - Package() {73, 10}, - Package() {85, 80}, - Package() {100, 300}, - Package() {150, 1000} - }) - -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD= .asl b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl deleted file mode 100644 index 30b3e57c4b..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl +++ /dev/null @@ -1,21 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - - -//////////////////////////////////////////////////////////////////////////= ///////// -//Values are set like this to have ASL compiler reserve enough space for o= bjects -//////////////////////////////////////////////////////////////////////////= ///////// -// -// Available Sleep states -// -Name(SS1,0) -Name(SS2,0) -Name(SS3,1) -Name(SS4,1) - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.as= l b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl deleted file mode 100644 index 84c151cbf6..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CPU.asl +++ /dev/null @@ -1,246 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(\_PR) -{ - Processor(PR00, // Unique name for Processor 0. - 1, // Unique ID for Processor 0. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR01, // Unique name for Processor 1. - 2, // Unique ID for Processor 1. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR02, // Unique name for Processor 2. - 3, // Unique ID for Processor 2. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR03, // Unique name for Processor 3. - 4, // Unique ID for Processor 3. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR04, // Unique name for Processor 4. - 5, // Unique ID for Processor 4. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR05, // Unique name for Processor 5. - 6, // Unique ID for Processor 5. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR06, // Unique name for Processor 6. - 7, // Unique ID for Processor 6. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR07, // Unique name for Processor 7. - 8, // Unique ID for Processor 7. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR08, // Unique name for Processor 8. - 9, // Unique ID for Processor 8. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR09, // Unique name for Processor 9. - 10, // Unique ID for Processor 9. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR10, // Unique name for Processor 10. - 11, // Unique ID for Processor 10. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR11, // Unique name for Processor 11. - 12, // Unique ID for Processor 11. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR12, // Unique name for Processor 12. - 13, // Unique ID for Processor 12. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR13, // Unique name for Processor 13. - 14, // Unique ID for Processor 13. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR14, // Unique name for Processor 14. - 15, // Unique ID for Processor 14. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} - - Processor(PR15, // Unique name for Processor 15. - 16, // Unique ID for Processor 15. - 0x1810, // P_BLK address =3D ACPIBASE + 10h. - 6) // P_BLK length =3D 6 bytes. - {} -} // End Scope(\_PR) - -// -// _CPC (Continuous Performance Control) Package declaration -// Package -// { -// NumEntries, // Integer -// Revision, // Integer -// HighestPerformance, // Generic Register Descriptor -// NominalPerformance, // Generic Register Descriptor -// LowestNonlinearPerformance, // Generic Register Descriptor -// LowestPerformance, // Generic Register Descriptor -// GuaranteedPerformanceRegister, // Generic Register Descriptor -// DesiredPerformanceRegister, // Generic Register Descriptor -// MinimumPerformanceRegister, // Generic Register Descriptor -// MaximumPerformanceRegister, // Generic Register Descriptor -// PerformanceReductionToleranceRegister,// Generic Register Descriptor -// TimeWindowRegister, // Generic Register Descriptor -// CounterWraparoundTime, // Generic Register Descriptor -// NominalCounterRegister, // Generic Register Descriptor -// DeliveredCounterRegister, // Generic Register Descriptor -// PerformanceLimitedRegister, // Generic Register Descriptor -// EnableRegister // Generic Register Descriptor -// } -// -Scope(\_PR.PR00) -{ - Name(CPC2, Package() - { - 21, // Number of entries - 02, // Revision - // - // Describe processor capabilities - // - ResourceTemplate() {Register(FFixedHW, 8, 0, 0x771, 4)}, // HighestPer= formance - ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Pe= rformance - Maximum Non Turbo Ratio - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonl= inear Performance - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPer= formance - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guarantee= d Performance - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired = PerformanceRegister - ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum Pe= rformanceRegister - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum Pe= rformanceRegister - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performanc= e ReductionToleranceRegister (Null) - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time windo= w register(Null) - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wr= ap around time(Null) - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference = counter register (PPERF) - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered = counter register (APERF) - ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performanc= e limited register - ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable reg= ister - 1, // Autonomous selection enable register (Exclusively autonomous) - ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomo= us activity window register - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomou= s energy performance preference register - 0 // Reference performance (not supported) - }) - - Name(CPOC, Package() - { - 21, // Number of entries - 02, // Revision - // - // Describe processor capabilities - // - 255, // HighestPerformance - ResourceTemplate() {Register(FFixedHW, 8, 8, 0xCE, 4)}, // Nominal Pe= rformance - Maximum Non Turbo Ratio - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x771, 4)},//Lowest nonl= inear Performance - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x771, 4)}, // LowestPer= formance - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x0771, 4)}, // Guarantee= d Performance - ResourceTemplate() {Register(FFixedHW, 8, 16, 0x0774, 4)}, // Desired = PerformanceRegister - ResourceTemplate() {Register(FFixedHW, 8, 0, 0x774, 4)}, // Minimum Pe= rformanceRegister - ResourceTemplate() {Register(FFixedHW, 8, 8, 0x774, 4)}, // Maximum Pe= rformanceRegister - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Performanc= e ReductionToleranceRegister (Null) - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Time windo= w register(Null) - ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)}, // Counter wr= ap around time(Null) - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE7, 4)}, // Reference = counter register (PPERF) - ResourceTemplate() {Register(FFixedHW, 64, 0, 0xE8, 4)}, // Delivered = counter register (APERF) - ResourceTemplate() {Register(FFixedHW, 2, 1, 0x777, 4)}, // Performanc= e limited register - ResourceTemplate() {Register(FFixedHW, 1, 0, 0x770, 4)}, // Enable reg= ister - 1, // Autonomous selection enable register (Exclusively autonomous) - ResourceTemplate() {Register(FFixedHW, 10, 32, 0x774, 4)}, // Autonomo= us activity window register - ResourceTemplate() {Register(FFixedHW, 8, 24, 0x774, 4)}, // Autonomou= s energy performance preference register - 0 // Reference performance (not supported) - }) - -}// end Scope(\_PR.PR00) - -#ifndef SPS_SUPPORT // SPS is using Processor Aggregator Device different = way -Scope(\_SB) -{ - // The Processor Aggregator Device provides a control point that enables= the platform to perform - // specific processor configuration and control that applies to all proc= essors in the platform. - Device (PAGD) - { - Name (_HID, "ACPI000C") // Processor Aggregator Device - - // _STA (Status) - // - // This object returns the current status of a device. - // - // Arguments: (0) - // None - // Return Value: - // An Integer containing a device status bitmap: - // Bit 0 - Set if the device is present. - // Bit 1 - Set if the device is enabled and decoding its resources. - // Bit 2 - Set if the device should be shown in the UI. - // Bit 3 - Set if the device is functioning properly (cleared if de= vice failed its diagnostics). - // Bit 4 - Set if the battery is present. - // Bits 5-31 - Reserved (must be cleared). - // - Method(_STA) - { - If(\_OSI("Processor Aggregator Device")){ - Return (0x0F) // Processor Aggregator Device is supported by this = OS. - } Else { - Return (0) // No support in this OS. - } - } - - - // _PUR (Processor Utilization Request) - // - // The _PUR object is an optional object that may be declared under th= e Processor Aggregator Device - // and provides a means for the platform to indicate to OSPM the numbe= r of logical processors - // to be idled. OSPM evaluates the _PUR object as a result of the proc= essing of a Notify event - // on the Processor Aggregator device object of type 0x80. - // - // Arguments: (0) - // None - // Return Value: - // Package - // - Name (_PUR, Package() // Requests a number of logical processors to be= placed in an idle state. - { - 1, // RevisionID, Integer: Current value i= s 1 - 0 // NumProcessors, Integer - }) - - } // end Device(PAGD) -}// end Scope(\_SB) -#endif // ndef SPS_SUPPORT - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.A= SL b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL deleted file mode 100644 index 93bca6827e..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL +++ /dev/null @@ -1,121 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -DefinitionBlock ( - "DSDT.aml", - "DSDT", - 0x02, // DSDT revision. - // A Revision field value greater than or equal to 2 signifies tha= t integers - // declared within the Definition Block are to be evaluated as 64-= bit values - "INTEL", // OEM ID (6 byte string) - "SKL ",// OEM table ID (8 byte string) - 0x0 // OEM version of DSDT table (4 byte Integer) -) - -// BEGIN OF ASL SCOPE -{ - External(LHIH) - External(LLOW) - External(IGDS) - External(LIDS) - External(BRTL) - External(ALSE) - External(GSMI) - External(\_SB.PCI0.GFX0.ALSI) - External(\_SB.PCI0.GFX0.CDCK) - External(\_SB.PCI0.GFX0.CBLV) - External(\_SB.PCI0.GFX0.GSSE) - External(\_SB.PCI0.PEG0, DeviceObj) - External(\_SB.PCI0.PEG0.PEGP, DeviceObj) - External(\_SB.PCI0.PEG1, DeviceObj) - External(\_SB.PCI0.PEG2, DeviceObj) - External(\_SB.PCI0.GFX0.DD1F, DeviceObj) - External(\_SB.PCI0.GFX0.GDCK, MethodObj) - External(\_SB.PCI0.GFX0.GHDS, MethodObj) - External(\_SB.PCI0.GFX0.AINT, MethodObj) - External(\_SB.PCI0.GFX0.GLID, MethodObj) - External(\_SB.PCI0.GFX0.GSCI, MethodObj) - External(\_PR.PR00._PSS, MethodObj) - External(\_PR.PR00.LPSS, PkgObj) - External(\_PR.PR00.TPSS, PkgObj) - External(\_PR.PR00._PPC, MethodObj) - External(\_PR.CPPC, IntObj) - External(\_TZ.TZ00, DeviceObj) - External(\_TZ.TZ01, DeviceObj) - External(\_TZ.ETMD, IntObj) - External(\_TZ.FN00._OFF, MethodObj) - // Miscellaneous services enabled in Project - Include ("AMLUPD.asl") - Include ("Acpi/GlobalNvs.asl") - Include ("PciTree.asl") - - if(LEqual(ECR1,1)){ - Scope(\_SB.PCI0) { - // - // PCI-specific method's GUID - // - Name(PCIG, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) - // - // PCI's _DSM - an attempt at modular _DSM implementation - // When writing your own _DSM function that needs to include PCI-spe= cific methods, do this: - // - // Method(_YOUR_DSM,4){ - // if(Lequal(Arg0,PCIG)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) } - // ...continue your _DSM by checking different GUIDs... - // else { return(0) } - // } - // - Method(PCID, 4, Serialized) { - If(LEqual(Arg0, PCIG)) { // PCIE capabilities UUID - If(LGreaterEqual(Arg1,3)) { = // revision at least 3 - If(LEqual(Arg2,0)) { Return (Buffer(2){0x01,0x03}) } = // function 0: list of supported functions - If(LEqual(Arg2,8)) { Return (1) } = // function 8: Avoiding Power-On Reset Delay Duplication on Sx Res= ume - If(LEqual(Arg2,9)) { Return (Package(5){50000,Ones,Ones,50000,= Ones}) } // function 9: Specifying Device Readiness Durations - } - } - return (Buffer(1){0}) - } - }//scope - }//if - - Scope(\_SB.PCI0) { - //PciCheck, Arg0=3DUUID, returns true if support for 'PCI delays optim= ization ECR' is enabled and the UUID is correct - Method(PCIC,1,Serialized) { - If(LEqual(ECR1,1)) { - If(LEqual(Arg0, PCIG)) { - return (1) - } - } - return (0) - } - } - - Include ("Pch.asl") // Not in this package. Refer to the PCH Reference = Code accordingly - Include ("LpcB.asl") - Include ("Platform.asl") - Include ("CPU.asl") - Include ("PCI_DRC.ASL") - Include ("Video.asl") - Include ("PlatformGnvs.asl") - Include ("Gpe.asl") - - Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state - if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})} - if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})} - if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})} - Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state - - Method(PTS, 1) { // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SL= EEP STATE - If(Arg0) // entering any sleep state - { - } - } - Method(WAK, 1) { // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP - } -}// End of ASL File - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.as= l b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl deleted file mode 100644 index 8976c7a0ff..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Gpe.asl +++ /dev/null @@ -1,850 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - // General Purpose Events. This Scope handles the Run-time and - // Wake-time SCIs. The specific method called will be determined by - // the _Lxx value, where xx equals the bit location in the General - // Purpose Event register(s). - - - External(D1F0) - External(D1F1) - External(D1F2) - External(\_SB.PCI0.PEG0.HPME, MethodObj) - External(\_SB.PCI0.PEG1.HPME, MethodObj) - External(\_SB.PCI0.PEG2.HPME, MethodObj) - External(\_GPE.AL6F, MethodObj) - External(\_SB.THDR, MethodObj) - External(\_GPE.P0L6, MethodObj) - External(\_GPE.P1L6, MethodObj) - External(\_GPE.P2L6, MethodObj) - External(SGGP) - External(P1GP) - External(P2GP) - External(P0WK) - External(P1WK) - External(P2WK) - External(\CPG0) - External(\RPS0) - External(\RPT0) - External(\_PR.HWPI, IntObj) - External(\_PR.DTSI, IntObj) - - Scope(\_GPE) - { - // Note: - // Originally, the two GPE methods below are automatically generated, bu= t, for ASL code restructuring, - // disabled the automatic generation and declare the ASL code here. - // - - // - // This PME event (PCH's GPE 69h) is received on one or more of the PCI = Express* ports or - // an assert PMEGPE message received via DMI - // - Method(_L69, 0, serialized) { - \_SB.PCI0.RP01.HPME() - \_SB.PCI0.RP02.HPME() - \_SB.PCI0.RP03.HPME() - \_SB.PCI0.RP04.HPME() - \_SB.PCI0.RP05.HPME() - \_SB.PCI0.RP06.HPME() - \_SB.PCI0.RP07.HPME() - \_SB.PCI0.RP08.HPME() - \_SB.PCI0.RP09.HPME() - \_SB.PCI0.RP10.HPME() - \_SB.PCI0.RP11.HPME() - \_SB.PCI0.RP12.HPME() - \_SB.PCI0.RP13.HPME() - \_SB.PCI0.RP14.HPME() - \_SB.PCI0.RP15.HPME() - \_SB.PCI0.RP16.HPME() - \_SB.PCI0.RP17.HPME() - \_SB.PCI0.RP18.HPME() - \_SB.PCI0.RP19.HPME() - \_SB.PCI0.RP20.HPME() - \_SB.PCI0.RP21.HPME() - \_SB.PCI0.RP22.HPME() - \_SB.PCI0.RP23.HPME() - \_SB.PCI0.RP24.HPME() - - If(LEqual(D1F0,1)) - { - \_SB.PCI0.PEG0.HPME() - Notify(\_SB.PCI0.PEG0, 0x02) - Notify(\_SB.PCI0.PEG0.PEGP, 0x02) - } - - If(LEqual(D1F1,1)) - { - \_SB.PCI0.PEG1.HPME() - Notify(\_SB.PCI0.PEG1, 0x02) - } - - If(LEqual(D1F2,1)) - { - \_SB.PCI0.PEG2.HPME() - Notify(\_SB.PCI0.PEG2, 0x02) - } - } - - // PCI Express Hot-Plug caused the wake event. - - Method(_L61) - { - Add(L01C,1,L01C) // Increment L01 Entry Count. - - P8XH(0,0x01) // Output information to Port 80h. - P8XH(1,L01C) - - - // Check Root Port 1 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF),\_SB.PCI0.RP01.HPSX)= ) - { - // Delay for 100ms to meet the timing requirements - // of the PCI Express Base Specification, Revision - // 1.0A, Section 6.6 ("...software must wait at - // least 100ms from the end of reset of one or more - // device before it is permitted to issue - // Configuration Requests to those devices"). - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS1,= 0x1)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP01.PDCX) - { - // Clear all status bits first. - - Store(1,\_SB.PCI0.RP01.PDCX) - Store(1,\_SB.PCI0.RP01.HPSX) - - // - // PCH BIOS Spec Update Rev 1.03, Section 8.9 PCI Express* Hot-Plu= g BIOS Support - // In addition, BIOS should intercept Presence Detect Changed inte= rrupt, enable L0s on - // hot plug and disable L0s on hot unplug. BIOS should also make s= ure the L0s is - // disabled on empty slots prior booting to OS. - // - If(LNot(\_SB.PCI0.RP01.PDSX)) { - // The PCI Express slot is empty, so disable L0s on hot unplug - // - Store(0,\_SB.PCI0.RP01.L0SE) - - } - - // Perform proper notification - // to the OS. - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x1),LNotEqual(TBS= 1,0x1)))) { - Notify(\_SB.PCI0.RP01,0) - } - } - Else - { - // False event. Clear Hot-Plug Status - // then exit. - - Store(1,\_SB.PCI0.RP01.HPSX) - } - } - - // Check Root Port 2 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF),\_SB.PCI0.RP02.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS1,= 0x2)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP02.PDCX) - { - Store(1,\_SB.PCI0.RP02.PDCX) - Store(1,\_SB.PCI0.RP02.HPSX) - - If(LNot(\_SB.PCI0.RP02.PDSX)) { - Store(0,\_SB.PCI0.RP02.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x2),LNotEqual(TBS= 1,0x2)))) { - Notify(\_SB.PCI0.RP02,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP02.HPSX) - } - } - - // Check Root Port 3 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF),\_SB.PCI0.RP03.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS1,= 0x3)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP03.PDCX) - { - Store(1,\_SB.PCI0.RP03.PDCX) - Store(1,\_SB.PCI0.RP03.HPSX) - - If(LNot(\_SB.PCI0.RP03.PDSX)) { - Store(0,\_SB.PCI0.RP03.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x3),LNotEqual(TBS= 1,0x3)))) { - Notify(\_SB.PCI0.RP03,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP03.HPSX) - } - } - - // Check Root Port 4 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF),\_SB.PCI0.RP04.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS1,= 0x4)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP04.PDCX) - { - Store(1,\_SB.PCI0.RP04.PDCX) - Store(1,\_SB.PCI0.RP04.HPSX) - - If(LNot(\_SB.PCI0.RP04.PDSX)) { - Store(0,\_SB.PCI0.RP04.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x4),LNotEqual(TBS= 1,0x4)))) { - Notify(\_SB.PCI0.RP04,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP04.HPSX) - } - } - - // Check Root Port 5 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF),\_SB.PCI0.RP05.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,= 0x5)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP05.PDCX) - { - Store(1,\_SB.PCI0.RP05.PDCX) - Store(1,\_SB.PCI0.RP05.HPSX) - - If(LNot(\_SB.PCI0.RP05.PDSX)) { - Store(0,\_SB.PCI0.RP05.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x5),LNotEqual(TBS1,= 0x5)))) { - Notify(\_SB.PCI0.RP05,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP05.HPSX) - } - } - - // Check Root Port 6 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF),\_SB.PCI0.RP06.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS1,= 0x6)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP06.PDCX) - { - Store(1,\_SB.PCI0.RP06.PDCX) - Store(1,\_SB.PCI0.RP06.HPSX) - - If(LNot(\_SB.PCI0.RP06.PDSX)) { - Store(0,\_SB.PCI0.RP06.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x6),LNotEqual(TBS= 1,0x6)))) { - Notify(\_SB.PCI0.RP06,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP06.HPSX) - } - } - - // Check Root Port 7 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF),\_SB.PCI0.RP07.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x7),LNotEqual(TBS1,= 0x7)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP07.PDCX) - { - Store(1,\_SB.PCI0.RP07.PDCX) - Store(1,\_SB.PCI0.RP07.HPSX) - - If(LNot(\_SB.PCI0.RP07.PDSX)) { - Store(0,\_SB.PCI0.RP07.L0SE) - } - - } - Else - { - Store(1,\_SB.PCI0.RP07.HPSX) - } - } - - // Check Root Port 8 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF),\_SB.PCI0.RP08.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x8),LNotEqual(TBS1,= 0x8)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP08.PDCX) - { - Store(1,\_SB.PCI0.RP08.PDCX) - Store(1,\_SB.PCI0.RP08.HPSX) - - If(LNot(\_SB.PCI0.RP08.PDSX)) { - Store(0,\_SB.PCI0.RP08.L0SE) - } - - } - Else - { - Store(1,\_SB.PCI0.RP08.HPSX) - } - } - - // Check Root Port 9 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF),\_SB.PCI0.RP09.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS1,= 0x9)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP09.PDCX) - { - Store(1,\_SB.PCI0.RP09.PDCX) - Store(1,\_SB.PCI0.RP09.HPSX) - - If(LNot(\_SB.PCI0.RP09.PDSX)) { - Store(0,\_SB.PCI0.RP09.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x9),LNotEqual(TBS= 1,0x9)))) { - Notify(\_SB.PCI0.RP09,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP09.HPSX) - } - } - - // Check Root Port 10 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF),\_SB.PCI0.RP10.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS1,= 0xA)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP10.PDCX) - { - Store(1,\_SB.PCI0.RP10.PDCX) - Store(1,\_SB.PCI0.RP10.HPSX) - - If(LNot(\_SB.PCI0.RP10.PDSX)) { - Store(0,\_SB.PCI0.RP10.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xA),LNotEqual(TBS= 1,0xA)))) { - Notify(\_SB.PCI0.RP10,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP10.HPSX) - } - } - - // Check Root Port 11 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF),\_SB.PCI0.RP11.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS1,= 0xB)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP11.PDCX) - { - Store(1,\_SB.PCI0.RP11.PDCX) - Store(1,\_SB.PCI0.RP11.HPSX) - - If(LNot(\_SB.PCI0.RP11.PDSX)) { - Store(0,\_SB.PCI0.RP11.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xB),LNotEqual(TBS= 1,0xB)))) { - Notify(\_SB.PCI0.RP11,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP11.HPSX) - } - } - - // Check Root Port 12 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF),\_SB.PCI0.RP12.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS1,= 0xC)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP12.PDCX) - { - Store(1,\_SB.PCI0.RP12.PDCX) - Store(1,\_SB.PCI0.RP12.HPSX) - - If(LNot(\_SB.PCI0.RP12.PDSX)) { - Store(0,\_SB.PCI0.RP12.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xC),LNotEqual(TBS= 1,0xC)))) { - Notify(\_SB.PCI0.RP12,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP12.HPSX) - } - } - - // Check Root Port 13 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF),\_SB.PCI0.RP13.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS1,= 0xD)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP13.PDCX) - { - Store(1,\_SB.PCI0.RP13.PDCX) - Store(1,\_SB.PCI0.RP13.HPSX) - - If(LNot(\_SB.PCI0.RP13.PDSX)) { - Store(0,\_SB.PCI0.RP13.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xD),LNotEqual(TBS= 1,0xD)))) { - Notify(\_SB.PCI0.RP13,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP13.HPSX) - } - } - - // Check Root Port 14 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF),\_SB.PCI0.RP14.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS1,= 0xE)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP14.PDCX) - { - Store(1,\_SB.PCI0.RP14.PDCX) - Store(1,\_SB.PCI0.RP14.HPSX) - - If(LNot(\_SB.PCI0.RP14.PDSX)) { - Store(0,\_SB.PCI0.RP14.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xE),LNotEqual(TBS= 1,0xE)))) { - Notify(\_SB.PCI0.RP14,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP14.HPSX) - } - } - - // Check Root Port 15 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF),\_SB.PCI0.RP15.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS1,= 0xF)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP15.PDCX) - { - Store(1,\_SB.PCI0.RP15.PDCX) - Store(1,\_SB.PCI0.RP15.HPSX) - - If(LNot(\_SB.PCI0.RP15.PDSX)) { - Store(0,\_SB.PCI0.RP15.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0xF),LNotEqual(TBS= 1,0xF)))) { - Notify(\_SB.PCI0.RP15,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP15.HPSX) - } - } - - // Check Root Port 16 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF),\_SB.PCI0.RP16.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TBS1= ,0x10)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP16.PDCX) - { - Store(1,\_SB.PCI0.RP16.PDCX) - Store(1,\_SB.PCI0.RP16.HPSX) - - If(LNot(\_SB.PCI0.RP16.PDSX)) { - Store(0,\_SB.PCI0.RP16.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x10),LNotEqual(TB= S1,0x10)))) { - Notify(\_SB.PCI0.RP16,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP16.HPSX) - } - } - - // Check Root Port 17 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF),\_SB.PCI0.RP17.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TBS1= ,0x11)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP17.PDCX) - { - Store(1,\_SB.PCI0.RP17.PDCX) - Store(1,\_SB.PCI0.RP17.HPSX) - - If(LNot(\_SB.PCI0.RP17.PDSX)) { - Store(0,\_SB.PCI0.RP17.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x11),LNotEqual(TB= S1,0x11)))) { - Notify(\_SB.PCI0.RP17,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP17.HPSX) - } - } - - // Check Root Port 18 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF),\_SB.PCI0.RP18.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TBS1= ,0x12)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP18.PDCX) - { - Store(1,\_SB.PCI0.RP18.PDCX) - Store(1,\_SB.PCI0.RP18.HPSX) - - If(LNot(\_SB.PCI0.RP18.PDSX)) { - Store(0,\_SB.PCI0.RP18.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x12),LNotEqual(TB= S1,0x12)))) { - Notify(\_SB.PCI0.RP18,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP18.HPSX) - } - } - - // Check Root Port 19 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF),\_SB.PCI0.RP19.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TBS1= ,0x13)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP19.PDCX) - { - Store(1,\_SB.PCI0.RP19.PDCX) - Store(1,\_SB.PCI0.RP19.HPSX) - - If(LNot(\_SB.PCI0.RP19.PDSX)) { - Store(0,\_SB.PCI0.RP19.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x13),LNotEqual(TB= S1,0x13)))) { - Notify(\_SB.PCI0.RP19,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP19.HPSX) - } - } - - // Check Root Port 20 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF),\_SB.PCI0.RP20.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TBS1= ,0x14)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP20.PDCX) - { - Store(1,\_SB.PCI0.RP20.PDCX) - Store(1,\_SB.PCI0.RP20.HPSX) - - If(LNot(\_SB.PCI0.RP20.PDSX)) { - Store(0,\_SB.PCI0.RP20.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x14),LNotEqual(TB= S1,0x14)))) { - Notify(\_SB.PCI0.RP20,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP20.HPSX) - } - } - - // Check Root Port 21 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP21.VDID,0xFFFFFFFF),\_SB.PCI0.RP21.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TBS1= ,0x21)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP21.PDCX) - { - Store(1,\_SB.PCI0.RP21.PDCX) - Store(1,\_SB.PCI0.RP21.HPSX) - - If(LNot(\_SB.PCI0.RP21.PDSX)) { - Store(0,\_SB.PCI0.RP21.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x21),LNotEqual(TB= S1,0x21)))) { - Notify(\_SB.PCI0.RP21,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP21.HPSX) - } - } - - // Check Root Port 22 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP22.VDID,0xFFFFFFFF),\_SB.PCI0.RP22.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TBS1= ,0x22)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP22.PDCX) - { - Store(1,\_SB.PCI0.RP22.PDCX) - Store(1,\_SB.PCI0.RP22.HPSX) - - If(LNot(\_SB.PCI0.RP22.PDSX)) { - Store(0,\_SB.PCI0.RP22.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x22),LNotEqual(TB= S1,0x22)))) { - Notify(\_SB.PCI0.RP22,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP22.HPSX) - } - } - - // Check Root Port 23 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP23.VDID,0xFFFFFFFF),\_SB.PCI0.RP23.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TBS1= ,0x23)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP23.PDCX) - { - Store(1,\_SB.PCI0.RP23.PDCX) - Store(1,\_SB.PCI0.RP23.HPSX) - - If(LNot(\_SB.PCI0.RP23.PDSX)) { - Store(0,\_SB.PCI0.RP23.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x23),LNotEqual(TB= S1,0x23)))) { - Notify(\_SB.PCI0.RP23,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP23.HPSX) - } - } - - // Check Root Port 24 for a Hot Plug Event if the Port is - // enabled. - - If(LAnd(LNotEqual(\_SB.PCI0.RP24.VDID,0xFFFFFFFF),\_SB.PCI0.RP24.HPSX)= ) - { - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TBS1= ,0x24)))) { - Sleep(100) - } - - If(\_SB.PCI0.RP24.PDCX) - { - Store(1,\_SB.PCI0.RP24.PDCX) - Store(1,\_SB.PCI0.RP24.HPSX) - - If(LNot(\_SB.PCI0.RP24.PDSX)) { - Store(0,\_SB.PCI0.RP24.L0SE) - } - - If(LOr(LNotEqual(TBTS, 0x01),LOr(LNotEqual(TBSE,0x24),LNotEqual(TB= S1,0x24)))) { - Notify(\_SB.PCI0.RP24,0) - } - } - Else - { - Store(1,\_SB.PCI0.RP24.HPSX) - } - } - } - - // - // Software GPE caused the event. - // - Method(_L62) - { - // Clear GPE status bit. - Store(0,GPEC) - - // - // Handle DTS Thermal SCI Event. - // - If(CondRefOf(\_PR.DTSE)){ - If(LGreaterEqual(\_PR.DTSE, 0x01)){ - If(LEqual(\_PR.DTSI, 1)){ - Notify(\_TZ.TZ00,0x80) - Notify(\_TZ.TZ01,0x80) - /// - /// Clear HWP interrupt status - /// - Store(0,\_PR.DTSI) - } - } - } - /// - /// Handle HWP SCI event - /// - External(\_GPE.HLVT, MethodObj) - If(LEqual(\_PR.HWPI, 1)){ - If(CondRefOf(\_GPE.HLVT)){ - \_GPE.HLVT() - } - /// - /// Clear HWP interrupt status - /// - Store(0,\_PR.HWPI) - } - } - - // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC). - - Method(_L66) - { - If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI eve= nt? - { - \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI - } - } - // - // BIOS Needs to implement appropriate handler based on CIO_PLUG_EVENT G= PIO - // This is generic 2-tier GPIO handler - // - Method(_L6F) - { - \_SB.THDR(\CPG0,\RPS0,\RPT0) // Check for TBT Hotplug Handler event (2= -tier GPI GPE event architecture) - } -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.a= sl b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl deleted file mode 100644 index 827a37fbab..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Itss.asl +++ /dev/null @@ -1,33 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - -// ITSS -// Define the needed ITSS registers used by ASL on Interrupt -// mapping. - -scope(\_SB){ - OperationRegion(ITSS, SystemMemory, 0xfdc43100, 0x208) - Field(ITSS, ByteAcc, NoLock, Preserve) - { - PARC, 8, - PBRC, 8, - PCRC, 8, - PDRC, 8, - PERC, 8, - PFRC, 8, - PGRC, 8, - PHRC, 8, - Offset(0x200), // Offset 3300h ITSSPRC - ITSS Power Reduction Con= trol - , 1, - , 1, - SCGE, 1, // ITSSPRC[2]: 8254 Static Clock Gating Enable (82= 54CGE) - - } -} - - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DE= V.ASL b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL deleted file mode 100644 index ea09363b84..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL +++ /dev/null @@ -1,199 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Device(FWHD) // Firmware Hub Device -{ - Name(_HID,EISAID("INT0800")) - - Name(_CRS,ResourceTemplate() - { - Memory32Fixed(ReadOnly,0xFF000000,0x1000000) - }) -} - - -Device(HPET) // High Performance Event Timer -{ - Name(_HID,EISAID("PNP0103")) - Name(_UID, 0) - - Name(BUF0,ResourceTemplate() - { - Memory32Fixed(ReadWrite,0xFED00000,0x400,FED0) - }) - - Method(_STA,0) - { - // Show this Device only if the OS is WINXP or beyond. - If(HPTE) - { - Return(0x000F) // Enabled, do Display. - } - - Return(0x0000) // Return Nothing. - } - - Method(_CRS,0,Serialized) - { - If(HPTE) - { - // Check if HPETimer Base should be modified. - CreateDwordField(BUF0,^FED0._BAS,HPT0) - Store(HPTB,HPT0) - } - - Return(BUF0) - } -} - -Device(IPIC) // 8259 PIC -{ - Name(_HID,EISAID("PNP0000")) - - Name(_CRS,ResourceTemplate() - { - IO(Decode16,0x20,0x20,0x01,0x02) - IO(Decode16,0x24,0x24,0x01,0x02) - IO(Decode16,0x28,0x28,0x01,0x02) - IO(Decode16,0x2C,0x2C,0x01,0x02) - IO(Decode16,0x30,0x30,0x01,0x02) - IO(Decode16,0x34,0x34,0x01,0x02) - IO(Decode16,0x38,0x38,0x01,0x02) - IO(Decode16,0x3C,0x3C,0x01,0x02) - IO(Decode16,0xA0,0xA0,0x01,0x02) - IO(Decode16,0xA4,0xA4,0x01,0x02) - IO(Decode16,0xA8,0xA8,0x01,0x02) - IO(Decode16,0xAC,0xAC,0x01,0x02) - IO(Decode16,0xB0,0xB0,0x01,0x02) - IO(Decode16,0xB4,0xB4,0x01,0x02) - IO(Decode16,0xB8,0xB8,0x01,0x02) - IO(Decode16,0xBC,0xBC,0x01,0x02) - IO(Decode16,0x4D0,0x4D0,0x01,0x02) - IRQNoFlags() {2} - }) -} - - -Device(MATH) // Math Co-Processor -{ - Name(_HID,EISAID("PNP0C04")) - - Name(_CRS,ResourceTemplate() - { - IO(Decode16,0xF0,0xF0,0x01,0x01) - IRQNoFlags() {13} - }) - - // - // Report device present for LPT-H. - // - Method (_STA, 0x0, NotSerialized) - { - If(LEqual(PCHV(), SPTH)) { - Return(0x1F) - } else { - Return(0x0) - } - } -} - - -Device(LDRC) // LPC Device Resource Consumption -{ - Name(_HID,EISAID("PNP0C02")) - - Name(_UID,2) - - Name(_CRS,ResourceTemplate() // This is for Cougar = Point - { - IO(Decode16,0x2E,0x2E,0x1,0x02) // SIO Access. - IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access. - IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status. - IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F. - IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F. - IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F. - IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable. - IO(Decode16,0x80,0x80,0x1,0x1) // Port 80h. - IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F. - IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI. - IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O. - IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // ACPI IO Trap. - IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // DTS IO Trap. - IO(Decode16,0xFFFF,0xFFFF,0x1,0x1) // HotKey IO Trap. - - IO(Decode16, 0x1800,0x1800,0x1,0xFF) // PCH ACPI Base - - IO(Decode16,0x164e,0x164e,0x1,0x02) // 16 Byte I/O. - }) -} - -Device(LDR2) // LPC Device Resource Consumption for PCH GPIO -{ - Name(_HID,EISAID("PNP0C02")) - - Name(_UID, "LPC_DEV") - - // LPT-H GPIO resource map - Name(_CRS,ResourceTemplate() - { - IO(Decode16, 0x800,0x800,0x1,0x80) // PCH GPIO Base. - }) - - Method(_STA, 0, NotSerialized) - { - If(LEqual(PCHV(), SPTH)) { - Return(0xF) - } else { - Return(0) - } - } -} - -Device(RTC) // RTC -{ - Name(_HID,EISAID("PNP0B00")) - - Name(_CRS,ResourceTemplate() - { - IO(Decode16,0x70,0x70,0x01,0x08) - IRQNoFlags() {8} - }) -} - -Device(TIMR) // 8254 Timer -{ - Name(_HID,EISAID("PNP0100")) - - Name(_CRS,ResourceTemplate() - { - IO(Decode16,0x40,0x40,0x01,0x04) - IO(Decode16,0x50,0x50,0x10,0x04) - IRQNoFlags() {0} - }) -} - -Device(CWDT) -{ - Name(_HID,EISAID("INT3F0D")) - Name(_CID,EISAID("PNP0C02")) - Name(BUF0,ResourceTemplate() - { - IO(Decode16, 0x1854, 0x1854, 0x4, 0x4) // PMBS 0x1800 + Offset 0x54 - } - ) - - Method(_STA,0,Serialized) - { - Return(0x0F) - } - - Method(_CRS,0,Serialized) - { - Return(BUF0) - } -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.a= sl b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl deleted file mode 100644 index 6fbaf3a97f..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/LpcB.asl +++ /dev/null @@ -1,88 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - -// LPC Bridge - Device 31, Function 0 -scope (\_SB.PCI0.LPCB) { - Include ("LPC_DEV.ASL") - - // Define the KBC_COMMAND_REG-64, KBC_DATA_REG-60 Registers as an AC= PI Operating - // Region. These registers will be used to skip kbd mouse - // resource settings if not present. - OperationRegion(PKBS, SystemIO, 0x60, 0x05) - Field(PKBS, ByteAcc, Lock, Preserve) - { - PKBD, 8, - , 8, - , 8, - , 8, - PKBC, 8 - } - Device(PS2K) // PS2 Keyboard - { - Name(_HID,"MSFT0001") - Name(_CID,EISAID("PNP0303")) - - Method(_STA) - { - If (P2MK) //Ps2 Keyboard and Mouse Enable - { - Return(0x000F) - } - Return(0x0000) - } - - Name(_CRS,ResourceTemplate() - { - IO(Decode16,0x60,0x60,0x01,0x01) - IO(Decode16,0x64,0x64,0x01,0x01) - IRQ(Edge,ActiveHigh,Exclusive){0x01} - }) - - Name(_PRS, ResourceTemplate(){ - StartDependentFn(0, 0) { - FixedIO(0x60,0x01) - FixedIO(0x64,0x01) - IRQNoFlags(){1} - } - EndDependentFn() - }) - - } - - Device(PS2M) // PS/2 Mouse - { - Name(_HID,"MSFT0003") - Name(_CID,EISAID("PNP0F03")) - - Method(_STA) - { - If (P2ME) //Ps2 Mouse Enable - { - If (P2MK) //Ps2 Keyboard and Mouse Enable - { - Return(0x000F) - } - } - Return(0x0000) - } - - Name(_CRS,ResourceTemplate() - { - IRQ(Edge,ActiveHigh,Exclusive){0x0C} - }) - - Name(_PRS, ResourceTemplate(){ - StartDependentFn(0, 0) { - IRQNoFlags(){12} - } - EndDependentFn() - }) - } - -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DR= C.ASL b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL deleted file mode 100644 index fba792642d..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL +++ /dev/null @@ -1,116 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - -Scope (\_SB.PCI0){ - - Device(PDRC) - { - // - // PCI Device Resource Consumption - // - - Name(_HID,EISAID("PNP0C02")) - - Name(_UID,1) - - Name(BUF0,ResourceTemplate() - { - // - // MCH BAR _BAS will be updated in _CRS below according to B0:D0:F0:= Reg.48h - // - Memory32Fixed(ReadWrite,0,0x08000,MCHB) - // - // DMI BAR _BAS will be updated in _CRS below according to B0:D0:F0:= Reg.68h - // - Memory32Fixed(ReadWrite,0,0x01000,DMIB) - // - // EP BAR _BAS will be updated in _CRS below according to B0:D0:F0:R= eg.40h - // - Memory32Fixed(ReadWrite,0,0x01000,EGPB) - // - // PCI Express BAR _BAS and _LEN will be updated in _CRS below accor= ding to B0:D0:F0:Reg.60h - // - Memory32Fixed(ReadWrite,0,0,PCIX) - - // - // MISC ICH TTT base address reserved for the TxT module use. Check = if the hard code meets the real configuration. - // If not, dynamically update it like the _CRS method below. - // - Memory32Fixed(ReadWrite,0xFED20000,0x20000) - - // - // VTD engine memory range. Check if the hard code meets the real co= nfiguration. - // If not, dynamically update it like the _CRS method below. - // - Memory32Fixed(ReadOnly, 0xFED90000, 0x00004000) - - // - // MISC ICH. Check if the hard code meets the real configuration. - // If not, dynamically update it like the _CRS method below. - // - Memory32Fixed(ReadWrite,0xFED45000,0x4B000,TPMM) - - // - // FLASH range - // - Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) //16MB as per = IOH spec - - // - // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) - // - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) - - // - // Sx handler reserved MMIO - // - Memory32Fixed (ReadWrite, 0, 0, SXRE) - - // - // Reserve HPET address decode range - // - Memory32Fixed (ReadWrite, 0, 0, HPET) - - }) - - - Method(_CRS,0,Serialized) - { - - CreateDwordField(BUF0,^MCHB._BAS,MBR0) - Store(\_SB.PCI0.GMHB(), MBR0) - - CreateDwordField(BUF0,^DMIB._BAS,DBR0) - Store(\_SB.PCI0.GDMB(), DBR0) - - CreateDwordField(BUF0,^EGPB._BAS,EBR0) - Store(\_SB.PCI0.GEPB(), EBR0) - - CreateDwordField(BUF0,^PCIX._BAS,XBR0) - Store(\_SB.PCI0.GPCB(), XBR0) - - CreateDwordField(BUF0,^PCIX._LEN,XSZ0) - Store(\_SB.PCI0.GPCL(), XSZ0) - - CreateDwordField(BUF0,^SXRE._BAS,SXRA) - Store(SXRB, SXRA) - CreateDwordField(BUF0,^SXRE._LEN,SXRL) - Store(SXRS, SXRL) - - // HPET device claims the resource in LPC_DEV.ASL. - If(LNOT(HPTE)){ - CreateDwordField(BUF0,^HPET._BAS,HBAS) - CreateDwordField(BUF0,^HPET._LEN,HLEN) - Store(HPTB, HBAS) - Store(0x400, HLEN) - } - - Return(BUF0) - } - } //end of PDRC -} // end of SB diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTre= e.asl b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl deleted file mode 100644 index ef65cea0af..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl +++ /dev/null @@ -1,306 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -Scope(\_SB) { - Name(PR00, Package(){ -// PCI Bridge -// D31: cAVS, SMBus, GbE, Nothpeak - Package(){0x001FFFFF, 0, LNKA, 0 }, - Package(){0x001FFFFF, 1, LNKB, 0 }, - Package(){0x001FFFFF, 2, LNKC, 0 }, - Package(){0x001FFFFF, 3, LNKD, 0 }, -// D30: SerialIo and SCS - can't use PIC -// D29: PCI Express Port 9-16 - Package(){0x001DFFFF, 0, LNKA, 0 }, - Package(){0x001DFFFF, 1, LNKB, 0 }, - Package(){0x001DFFFF, 2, LNKC, 0 }, - Package(){0x001DFFFF, 3, LNKD, 0 }, -// D28: PCI Express Port 1-8 - Package(){0x001CFFFF, 0, LNKA, 0 }, - Package(){0x001CFFFF, 1, LNKB, 0 }, - Package(){0x001CFFFF, 2, LNKC, 0 }, - Package(){0x001CFFFF, 3, LNKD, 0 }, -// D27: PCI Express Port 17-20 - Package(){0x001BFFFF, 0, LNKA, 0 }, - Package(){0x001BFFFF, 1, LNKB, 0 }, - Package(){0x001BFFFF, 2, LNKC, 0 }, - Package(){0x001BFFFF, 3, LNKD, 0 }, -// D25: SerialIo - can't use PIC -// D23: SATA controller - Package(){0x0017FFFF, 0, LNKA, 0 }, -// D22: CSME (HECI, IDE-R, Keyboard and Text redirection - Package(){0x0016FFFF, 0, LNKA, 0 }, - Package(){0x0016FFFF, 1, LNKB, 0 }, - Package(){0x0016FFFF, 2, LNKC, 0 }, - Package(){0x0016FFFF, 3, LNKD, 0 }, -// D21: SerialIo - can't use PIC -// D20: xHCI, Thermal Subsystem, Camera IO Host Controller - Package(){0x0014FFFF, 0, LNKA, 0 }, - Package(){0x0014FFFF, 1, LNKB, 0 }, - Package(){0x0014FFFF, 2, LNKC, 0 }, - Package(){0x0014FFFF, 3, LNKD, 0 }, -// D19: Integrated Sensor Hub - can't use PIC - -// Host Bridge -// P.E.G. Root Port D1F0 - Package(){0x0001FFFF, 0, LNKA, 0 }, - Package(){0x0001FFFF, 1, LNKB, 0 }, - Package(){0x0001FFFF, 2, LNKC, 0 }, - Package(){0x0001FFFF, 3, LNKD, 0 }, -// P.E.G. Root Port D1F1 -// P.E.G. Root Port D1F2 -// SA IGFX Device - Package(){0x0002FFFF, 0, LNKA, 0 }, -// SA Thermal Device - Package(){0x0004FFFF, 0, LNKA, 0 }, -// SA SkyCam Device - Package(){0x0005FFFF, 0, LNKA, 0 }, -// SA GMM Device - Package(){0x0008FFFF, 0, LNKA, 0 }, - }) - Name(AR00, Package(){ -// PCI Bridge -// D31: cAVS, SMBus, GbE, Nothpeak - Package(){0x001FFFFF, 0, 0, 16 }, - Package(){0x001FFFFF, 1, 0, 17 }, - Package(){0x001FFFFF, 2, 0, 18 }, - Package(){0x001FFFFF, 3, 0, 19 }, -// D30: SerialIo and SCS - Package(){0x001EFFFF, 0, 0, 20 }, - Package(){0x001EFFFF, 1, 0, 21 }, - Package(){0x001EFFFF, 2, 0, 22 }, - Package(){0x001EFFFF, 3, 0, 23 }, -// D29: PCI Express Port 9-16 - Package(){0x001DFFFF, 0, 0, 16 }, - Package(){0x001DFFFF, 1, 0, 17 }, - Package(){0x001DFFFF, 2, 0, 18 }, - Package(){0x001DFFFF, 3, 0, 19 }, -// D28: PCI Express Port 1-8 - Package(){0x001CFFFF, 0, 0, 16 }, - Package(){0x001CFFFF, 1, 0, 17 }, - Package(){0x001CFFFF, 2, 0, 18 }, - Package(){0x001CFFFF, 3, 0, 19 }, -// D27: PCI Express Port 17-20 - Package(){0x001BFFFF, 0, 0, 16 }, - Package(){0x001BFFFF, 1, 0, 17 }, - Package(){0x001BFFFF, 2, 0, 18 }, - Package(){0x001BFFFF, 3, 0, 19 }, -// D25: SerialIo - Package(){0x0019FFFF, 0, 0, 32 }, - Package(){0x0019FFFF, 1, 0, 33 }, - Package(){0x0019FFFF, 2, 0, 34 }, -// D23: SATA controller - Package(){0x0017FFFF, 0, 0, 16 }, -// D22: CSME (HECI, IDE-R, Keyboard and Text redirection - Package(){0x0016FFFF, 0, 0, 16 }, - Package(){0x0016FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 2, 0, 18 }, - Package(){0x0016FFFF, 3, 0, 19 }, -// D21: SerialIo - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, -// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - Package(){0x0014FFFF, 3, 0, 19 }, -// D19: Integrated Sensor Hub - Package(){0x0013FFFF, 0, 0, 20 }, - -// Host Bridge -// P.E.G. Root Port D1F0 - Package(){0x0001FFFF, 0, 0, 16 }, - Package(){0x0001FFFF, 1, 0, 17 }, - Package(){0x0001FFFF, 2, 0, 18 }, - Package(){0x0001FFFF, 3, 0, 19 }, -// P.E.G. Root Port D1F1 -// P.E.G. Root Port D1F2 -// SA IGFX Device - Package(){0x0002FFFF, 0, 0, 16 }, -// SA Thermal Device - Package(){0x0004FFFF, 0, 0, 16 }, -// SA SkyCam Device - Package(){0x0005FFFF, 0, 0, 16 }, -// SA GMM Device - Package(){0x0008FFFF, 0, 0, 16 }, - }) - Name(PR04, Package(){ - Package(){0x0000FFFF, 0, LNKA, 0 }, - Package(){0x0000FFFF, 1, LNKB, 0 }, - Package(){0x0000FFFF, 2, LNKC, 0 }, - Package(){0x0000FFFF, 3, LNKD, 0 }, - }) - Name(AR04, Package(){ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - Name(PR05, Package(){ - Package(){0x0000FFFF, 0, LNKB, 0 }, - Package(){0x0000FFFF, 1, LNKC, 0 }, - Package(){0x0000FFFF, 2, LNKD, 0 }, - Package(){0x0000FFFF, 3, LNKA, 0 }, - }) - Name(AR05, Package(){ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PR06, Package(){ - Package(){0x0000FFFF, 0, LNKC, 0 }, - Package(){0x0000FFFF, 1, LNKD, 0 }, - Package(){0x0000FFFF, 2, LNKA, 0 }, - Package(){0x0000FFFF, 3, LNKB, 0 }, - }) - Name(AR06, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - Name(PR07, Package(){ - Package(){0x0000FFFF, 0, LNKD, 0 }, - Package(){0x0000FFFF, 1, LNKA, 0 }, - Package(){0x0000FFFF, 2, LNKB, 0 }, - Package(){0x0000FFFF, 3, LNKC, 0 }, - }) - Name(AR07, Package(){ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PR08, Package(){ - Package(){0x0000FFFF, 0, LNKA, 0 }, - Package(){0x0000FFFF, 1, LNKB, 0 }, - Package(){0x0000FFFF, 2, LNKC, 0 }, - Package(){0x0000FFFF, 3, LNKD, 0 }, - }) - Name(AR08, Package(){ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - Name(PR09, Package(){ - Package(){0x0000FFFF, 0, LNKB, 0 }, - Package(){0x0000FFFF, 1, LNKC, 0 }, - Package(){0x0000FFFF, 2, LNKD, 0 }, - Package(){0x0000FFFF, 3, LNKA, 0 }, - }) - Name(AR09, Package(){ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PR0E, Package(){ - Package(){0x0000FFFF, 0, LNKC, 0 }, - Package(){0x0000FFFF, 1, LNKD, 0 }, - Package(){0x0000FFFF, 2, LNKA, 0 }, - Package(){0x0000FFFF, 3, LNKB, 0 }, - }) - Name(AR0E, Package(){ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - Name(PR0F, Package(){ - Package(){0x0000FFFF, 0, LNKD, 0 }, - Package(){0x0000FFFF, 1, LNKA, 0 }, - Package(){0x0000FFFF, 2, LNKB, 0 }, - Package(){0x0000FFFF, 3, LNKC, 0 }, - }) - Name(AR0F, Package(){ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - Name(PR02, Package(){ - Package(){0x0000FFFF, 0, LNKA, 0 }, - Package(){0x0000FFFF, 1, LNKB, 0 }, - Package(){0x0000FFFF, 2, LNKC, 0 }, - Package(){0x0000FFFF, 3, LNKD, 0 }, - }) - Name(AR02, Package(){ -// P.E.G. Port Slot x16 - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - Name(PR0A, Package(){ -// P.E.G. Port Slot x8 - Package(){0x0000FFFF, 0, LNKB, 0 }, - Package(){0x0000FFFF, 1, LNKC, 0 }, - Package(){0x0000FFFF, 2, LNKD, 0 }, - Package(){0x0000FFFF, 3, LNKA, 0 }, - }) - Name(AR0A, Package(){ -// P.E.G. Port Slot x8 - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - Name(PR0B, Package(){ -// P.E.G. Port Slot x4 - Package(){0x0000FFFF, 0, LNKC, 0 }, - Package(){0x0000FFFF, 1, LNKD, 0 }, - Package(){0x0000FFFF, 2, LNKA, 0 }, - Package(){0x0000FFFF, 3, LNKB, 0 }, - }) - Name(AR0B, Package(){ -// P.E.G. Port Slot x4 - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) -//------------------------------------------------------------------------= --- -// List of IRQ resource buffers compatible with _PRS return format. -//------------------------------------------------------------------------= --- -// Naming legend: -// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "x= y" - last two characters of IRQ Link name. -// Note. PRSy name is generated if IRQ Link name starts from "LNK". -// HLxy , LLxy - reference names, can be used to access bit mask of availa= ble IRQs. HL and LL stand for active High(Low) Level triggered Irq model. -//------------------------------------------------------------------------= --- - Name(PRSA, ResourceTemplate(){ // Link name: LNKA - IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15} - }) - Alias(PRSA,PRSB) // Link name: LNKB - Alias(PRSA,PRSC) // Link name: LNKC - Alias(PRSA,PRSD) // Link name: LNKD - Alias(PRSA,PRSE) // Link name: LNKE - Alias(PRSA,PRSF) // Link name: LNKF - Alias(PRSA,PRSG) // Link name: LNKG - Alias(PRSA,PRSH) // Link name: LNKH -//------------------------------------------------------------------------= --- -// Begin PCI tree object scope -//------------------------------------------------------------------------= --- - Device(PCI0) { // PCI Bridge "Host Bridge" - Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 hos= t hierarchy - Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't und= erstand the new HID - Name(_ADR, 0x00000000) - Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for = Peer PCI busses. Name can be overriden with control method placed directly = under Device scope - Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root= PCI Bus - Name(_UID, 0x0000) // Unique Bus ID, optional - Method(_PRT,0) { - If(PICM) {Return(AR00)} // APIC mode - Return (PR00) // PIC Mode - } // end _PRT - - Include("HostBus.asl") - } // end PCI0 Bridge "Host Bridge" -} // end _SB scope diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platfo= rm.asl b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.a= sl deleted file mode 100644 index 063093a08c..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl +++ /dev/null @@ -1,1129 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#define TRAP_TYPE_DTS 0x02 -#define TRAP_TYPE_IGD 0x03 -#define TRAP_TYPE_BGD 0x04 // BIOS Guard - -// Define the following External variables to prevent a WARNING when -// using ASL.EXE and an ERROR when using IASL.EXE. - -External(\PC00, IntObj) // PR00 _PDC Flags -External(\PC01) -External(\PC02) -External(\PC03) -External(\PC04) -External(\PC05) -External(\PC06) -External(\PC07) -External(\PC08) -External(\PC09) -External(\PC10) -External(\PC11) -External(\PC12) -External(\PC13) -External(\PC14) -External(\PC15) -External(\_PR.CFGD) -External(\SGMD) - -// -// DTS externals -// -External(\_PR.DTSF) -External(\_PR.DTSE) -External(\_PR.TRPD) -External(\_PR.TRPF) -External(\_PR.DSAE) -// -// SGX -// -External(\_PR.EPCS) -External(\_PR.EMNA) -External(\_PR.ELNG) - -External(\_SB.PCI0.GFX0.TCHE) // Technology enabled indicator -External(\_SB.PCI0.GFX0.STAT) // State Indicator - -External(\_SB.TPM.PTS, MethodObj) -External(\_SB.PCI0.PAUD.PUAM, MethodObj) //PUAM - PowerResource User Absen= t Mode -External(\_SB.PCI0.XHC.DUAM, MethodObj) //DUAM - Device User Absent Mode = for XHCI controller -External(\_SB.PCI0.I2C4.GEXP.INVC, MethodObj) - -External(\_SB.PCI0.GFX0.IUEH, MethodObj) - -#define CONVERTIBLE_BUTTON 6 -#define DOCK_INDICATOR 7 - -Name(ECUP, 1) // EC State indicator: 1- Normal Mode 0- Low Power Mode -Mutex(EHLD, 0) // EC Hold indicator: 0- No one accessing the EC Power Stat= e 1- Someone else is accessing the EC Power State - - - -External(TBTD, MethodObj) -External(TBTF, MethodObj) -External(MMRP, MethodObj) -External(MMTB, MethodObj) -External(TBFF, MethodObj) -External(FFTB, MethodObj) -External(SXTB, MethodObj) - - -// Interrupt specific registers -include("Itss.asl") - -// Create a Global MUTEX. - -Mutex(MUTX,0) - -// OS Up mutex -Mutex(OSUM, 0) -// _WAK Finished Event -Event(WFEV) - -// Define Port 80 as an ACPI Operating Region to use for debugging. Pleas= e -// note that the Intel CRBs have the ability to ouput an entire DWord to -// Port 80h for debugging purposes, so the model implemented here may not = be -// able to be used on OEM Designs. - -OperationRegion(PRT0,SystemIO,0x80,4) -Field(PRT0,DwordAcc,Lock,Preserve) -{ - P80H, 32 -} - -// Port 80h Update: -// Update 8 bits of the 32-bit Port 80h. -// -// Arguments: -// Arg0: 0 =3D Write Port 80h, Bits 7:0 Only. -// 1 =3D Write Port 80h, Bits 15:8 Only. -// 2 =3D Write Port 80h, Bits 23:16 Only. -// 3 =3D Write Port 80h, Bits 31:24 Only. -// Arg1: 8-bit Value to write -// -// Return Value: -// None - -Method(D8XH,2,Serialized) -{ - If(LEqual(Arg0,0)) // Write Port 80h, Bits 7:0. - { - Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D) - } - - If(LEqual(Arg0,1)) // Write Port 80h, Bits 15:8. - { - Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D) - } - - If(LEqual(Arg0,2)) // Write Port 80h, Bits 23:16. - { - Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D) - } - - If(LEqual(Arg0,3)) // Write Port 80h, Bits 31:24. - { - Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D) - } - - Store(P80D,P80H) -} - -// Debug Port 80h Update: -// If Acpidebug is enabled only then call D8XH to update 8 bits of the = 32-bit Port 80h. -// -// Arguments: -// Arg0: 0 =3D Write Port 80h, Bits 7:0 Only. -// 1 =3D Write Port 80h, Bits 15:8 Only. -// 2 =3D Write Port 80h, Bits 23:16 Only. -// 3 =3D Write Port 80h, Bits 31:24 Only. -// Arg1: 8-bit Value to write -// -// Return Value: -// None -Method(P8XH,2,Serialized) -{ - // If ACPI debug is enabled, then display post codes on Port 80h - If(CondRefOf(MDBG)) {// Check if ACPI Debug SSDT is loaded - D8XH(Arg0,Arg1) - } -} - -Method(ADBG,1,Serialized) -{ - Return(0) -} - -// -// Define SW SMI port as an ACPI Operating Region to use for generate SW S= MI. -// -OperationRegion(SPRT,SystemIO, 0xB2,2) -Field (SPRT, ByteAcc, Lock, Preserve) { - SSMP, 8 -} - -// The _PIC Control Method is optional for ACPI design. It allows the -// OS to inform the ASL code which interrupt controller is being used, -// the 8259 or APIC. The reference code in this document will address -// PCI IRQ Routing and resource allocation for both cases. -// -// The values passed into _PIC are: -// 0 =3D 8259 -// 1 =3D IOAPIC - -Method(\_PIC,1) -{ - Store(Arg0,GPIC) - Store(Arg0,PICM) -} - -// Prepare to Sleep. The hook is called when the OS is about to -// enter a sleep state. The argument passed is the numeric value of -// the Sx state. - -Method(_PTS,1) -{ - Store(0,P80D) // Zero out the entire Port 80h DWord. - D8XH(0,Arg0) // Output Sleep State to Port 80h, Byte 0. - - ADBG(Concatenate("_PTS=3D",ToHexString(Arg0))) - - - // If code is executed, Wake from RI# via Serial Modem will be - // enabled. If code is not executed, COM Port Debugging throughout - // all Sx states will be enabled. - - If(LEqual(Arg0,3)) - { - // - // Disable update DTS temperature and threshold value in every SMI - // - If(CondRefOf(\_PR.DTSE)){ - If(LAnd(\_PR.DTSE, LGreater(TCNT, 1))) - { - TRAP(TRAP_TYPE_DTS,30) - } - } - } - - - // Generate a SW SMI trap to save some NVRAM data back to CMOS. - - // Don't enable IGD OpRegion support yet. - // TRAP(1, 81) - // - // Call TPM.PTS - // - If(CondRefOf(\_SB.TPM.PTS)) - { - // - // Call TPM PTS method - // - \_SB.TPM.PTS (Arg0) - } - -} - -// Wake. This hook is called when the OS is about to wake from a -// sleep state. The argument passed is the numeric value of the -// sleep state the system is waking from. - -Method(_WAK,1,Serialized) -{ - D8XH(1,0xAB) // Beginning of _WAK. - - ADBG("_WAK") - - // - // Only set 8254 CG if Low Power S0 Idle Capability is enabled - // - If (LEqual(S0ID, One)) { - // - // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2] - // - Store(0x01, \_SB.SCGE) - } - - If(NEXP) - { - // Reinitialize the Native PCI Express after resume - - If(And(OSCC,0x02)) - { - \_SB.PCI0.NHPG() - } - If(And(OSCC,0x04)) // PME control granted? - { - \_SB.PCI0.NPME() - } - } - - - If(LOr(LEqual(Arg0,3), LEqual(Arg0,4))) // If S3 or S4 Resume - { - - // Check to send Convertible/Dock state changes upon resume from Sx. - If(And(GBSX,0x40)) - { - \_SB.PCI0.GFX0.IUEH(6) - - // - // Do the same thing for Virtul Button device. - // Toggle Bit3 of PB1E(Slate/Notebook status) - // - Xor(PB1E, 0x08, PB1E) - - } - - If(And(GBSX,0x80)) - { - \_SB.PCI0.GFX0.IUEH(7) - - // - // Do the same thing for Virtul Button device. - // Toggle Bit4 of PB1E (Dock/Undock status) - // - Xor(PB1E, 0x10, PB1E) - - } - - - If(CondRefOf(\_PR.DTSE)){ - If(LAnd(\_PR.DTSE, LGreater(TCNT, 1))) - { - TRAP(TRAP_TYPE_DTS, 20) - } - } - - - // For PCI Express Express Cards, it is possible a device was - // either inserted or removed during an Sx State. The problem - // is that no wake event will occur for a given warm insertion - // or removal, so the OS will not become aware of any change. - // To get around this, re-enumerate all Express Card slots. - // - // If the Root Port is enabled, it may be assumed to be hot-pluggable. - - If(LNotEqual(\_SB.PCI0.RP01.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP01,0) - } - - If(LNotEqual(\_SB.PCI0.RP02.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP02,0) - } - - If(LNotEqual(\_SB.PCI0.RP03.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP03,0) - } - - If(LNotEqual(\_SB.PCI0.RP04.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP04,0) - } - - If(LNotEqual(\_SB.PCI0.RP05.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP05,0) - } - - If(LNotEqual(\_SB.PCI0.RP06.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP06,0) - } - - If(LNotEqual(\_SB.PCI0.RP07.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP07,0) - } - - If(LNotEqual(\_SB.PCI0.RP08.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP08,0) - } - - If(LNotEqual(\_SB.PCI0.RP09.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP09,0) - } - - If(LNotEqual(\_SB.PCI0.RP10.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP10,0) - } - - If(LNotEqual(\_SB.PCI0.RP11.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP11,0) - } - - If(LNotEqual(\_SB.PCI0.RP12.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP12,0) - } - - If(LNotEqual(\_SB.PCI0.RP13.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP13,0) - } - - If(LNotEqual(\_SB.PCI0.RP14.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP14,0) - } - - If(LNotEqual(\_SB.PCI0.RP15.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP15,0) - } - - If(LNotEqual(\_SB.PCI0.RP16.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP16,0) - } - - If(LNotEqual(\_SB.PCI0.RP17.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP17,0) - } - - If(LNotEqual(\_SB.PCI0.RP18.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP18,0) - } - - If(LNotEqual(\_SB.PCI0.RP19.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP19,0) - } - - If(LNotEqual(\_SB.PCI0.RP20.VDID,0xFFFFFFFF)) - { - Notify (\_SB.PCI0.RP20,0) - } - } - - - Return(Package(){0,0}) -} - -// Get Buffer: -// This method will take a buffer passed into the method and -// create then return a smaller buffer based on the pointer -// and size parameters passed in. -// -// Arguments: -// Arg0: Pointer to start of new Buffer in passed in Buffer. -// Arg1: Size of Buffer to create. -// Arg2: Original Buffer -// -// Return Value: -// Newly created buffer. - -Method(GETB,3,Serialized) -{ - Multiply(Arg0,8,Local0) // Convert Index. - Multiply(Arg1,8,Local1) // Convert Size. - CreateField(Arg2,Local0,Local1,TBF3) // Create Buffer. - - Return(TBF3) // Return Buffer. -} - -// Power Notification: -// Perform all needed OS notifications during a -// Power Switch. -// -// Arguments: -// None -// -// Return Value: -// None - -Method(PNOT,0,Serialized) -{ - // - // If MP enabled and driver support is present, notify all - // processors. - // - If(LGreater(TCNT, 1)) - { - If(And(\PC00,0x0008)){ - Notify(\_PR.PR00,0x80) // Eval PR00 _PPC. - } - If(And(\PC01,0x0008)){ - Notify(\_PR.PR01,0x80) // Eval PR01 _PPC. - } - If(And(\PC02,0x0008)){ - Notify(\_PR.PR02,0x80) // Eval PR02 _PPC. - } - If(And(\PC03,0x0008)){ - Notify(\_PR.PR03,0x80) // Eval PR03 _PPC. - } - If(And(\PC04,0x0008)){ - Notify(\_PR.PR04,0x80) // Eval PR04 _PPC. - } - If(And(\PC05,0x0008)){ - Notify(\_PR.PR05,0x80) // Eval PR05 _PPC. - } - If(And(\PC06,0x0008)){ - Notify(\_PR.PR06,0x80) // Eval PR06 _PPC. - } - If(And(\PC07,0x0008)){ - Notify(\_PR.PR07,0x80) // Eval PR07 _PPC. - } - If(And(\PC08,0x0008)){ - Notify(\_PR.PR08,0x80) // Eval PR08 _PPC. - } - If(And(\PC09,0x0008)){ - Notify(\_PR.PR09,0x80) // Eval PR09 _PPC. - } - If(And(\PC10,0x0008)){ - Notify(\_PR.PR10,0x80) // Eval PR10 _PPC. - } - If(And(\PC11,0x0008)){ - Notify(\_PR.PR11,0x80) // Eval PR11 _PPC. - } - If(And(\PC12,0x0008)){ - Notify(\_PR.PR12,0x80) // Eval PR12 _PPC. - } - If(And(\PC13,0x0008)){ - Notify(\_PR.PR13,0x80) // Eval PR13 _PPC. - } - If(And(\PC14,0x0008)){ - Notify(\_PR.PR14,0x80) // Eval PR14 _PPC. - } - If(And(\PC15,0x0008)){ - Notify(\_PR.PR15,0x80) // Eval PR15 _PPC. - } - }Else{ - Notify(\_PR.PR00,0x80) // Eval _PPC. - } - - If(LGreater(TCNT, 1)){ - If(LAnd(And(\PC00,0x0008),And(\PC00,0x0010))){ - Notify(\_PR.PR00,0x81) // Eval PR00 _CST. - } - If(LAnd(And(\PC01,0x0008),And(\PC01,0x0010))){ - Notify(\_PR.PR01,0x81) // Eval PR01 _CST. - } - If(LAnd(And(\PC02,0x0008),And(\PC02,0x0010))){ - Notify(\_PR.PR02,0x81) // Eval PR02 _CST. - } - If(LAnd(And(\PC03,0x0008),And(\PC03,0x0010))){ - Notify(\_PR.PR03,0x81) // Eval PR03 _CST. - } - If(LAnd(And(\PC04,0x0008),And(\PC04,0x0010))){ - Notify(\_PR.PR04,0x81) // Eval PR04 _CST. - } - If(LAnd(And(\PC05,0x0008),And(\PC05,0x0010))){ - Notify(\_PR.PR05,0x81) // Eval PR05 _CST. - } - If(LAnd(And(\PC06,0x0008),And(\PC06,0x0010))){ - Notify(\_PR.PR06,0x81) // Eval PR06 _CST. - } - If(LAnd(And(\PC07,0x0008),And(\PC07,0x0010))){ - Notify(\_PR.PR07,0x81) // Eval PR07 _CST. - } - If(LAnd(And(\PC08,0x0008),And(\PC08,0x0010))){ - Notify(\_PR.PR08,0x81) // Eval PR08 _CST. - } - If(LAnd(And(\PC09,0x0008),And(\PC09,0x0010))){ - Notify(\_PR.PR09,0x81) // Eval PR09 _CST. - } - If(LAnd(And(\PC10,0x0008),And(\PC10,0x0010))){ - Notify(\_PR.PR10,0x81) // Eval PR10 _CST. - } - If(LAnd(And(\PC11,0x0008),And(\PC11,0x0010))){ - Notify(\_PR.PR11,0x81) // Eval PR11 _CST. - } - If(LAnd(And(\PC12,0x0008),And(\PC12,0x0010))){ - Notify(\_PR.PR12,0x81) // Eval PR12 _CST. - } - If(LAnd(And(\PC13,0x0008),And(\PC13,0x0010))){ - Notify(\_PR.PR13,0x81) // Eval PR13 _CST. - } - If(LAnd(And(\PC14,0x0008),And(\PC14,0x0010))){ - Notify(\_PR.PR14,0x81) // Eval PR14 _CST. - } - If(LAnd(And(\PC15,0x0008),And(\PC15,0x0010))){ - Notify(\_PR.PR15,0x81) // Eval PR15 _CST. - } - } Else { - Notify(\_PR.PR00,0x81) // Eval _CST. - } - - -} // end of Method(PNOT) - -// -// Memory window to the CTDP registers starting at MCHBAR+5000h. -// - OperationRegion (MBAR, SystemMemory, Add(\_SB.PCI0.GMHB(),0x5000), 0x100= 0) - Field (MBAR, ByteAcc, NoLock, Preserve) - { - Offset (0x938), // PACKAGE_POWER_SKU_UNIT (MCHBAR+0x5938) - PWRU, 4, // Power Units [3:0] unit value is calculated by 1 W /= Power(2,PWR_UNIT). The default value of 0011b corresponds to 1/8 W. - Offset (0x9A0), // TURBO_POWER_LIMIT1 (MCHBAR+0x59A0) - PPL1, 15, // PKG_PWR_LIM_1 [14:0] - PL1E,1, // PKG_PWR_LIM1_EN [15] - CLP1,1, // Package Clamping Limitation 1 - } -Name(CLMP, 0) // save the clamp bit -Name(PLEN,0) // save the power limit enable bit -Name(PLSV,0x8000) // save value of PL1 upon entering CS -Name(CSEM, 0) //semaphore to avoid multiple calls to SPL1. SPL1/RPL1 must= always be called in pairs, like push/pop off a stack -// -// SPL1 (Set PL1 to 4.5 watts with clamp bit set) -// Per Legacy Thermal management CS requirements, we would like to set t= he PL1 limit when entering CS to 4.5W with clamp bit set via MMIO. -// This can be done in the ACPI object which gets called by graphics dri= ver during CS Entry. -// Likewise, during CS exit, the BIOS must reset the PL1 value to the pr= evious value prior to CS entry and reset the clamp bit. -// -// Arguments: -// None -// -// Return Value: -// None -Method(SPL1,0,Serialized) -{ - Name(PPUU,0) // units - If (LEqual(CSEM, 1)) - { - Return() // we have already been called, must have CS exit before ca= lling again - } - Store(1, CSEM) // record first call - - Store (PPL1, PLSV) // save PL1 value upon entering CS - Store (PL1E, PLEN) // save PL1 Enable bit upon entering CS - Store (CLP1, CLMP) // save PL1 Clamp bit upon entering CS - - If (LEqual(PWRU,0)) { // use PACKAGE_POWER_SKU_UNIT - Power Units[3:0= ] - Store(1,PPUU) - } Else { - ShiftLeft(Decrement(PWRU),2,PPUU) // get units - } - - Multiply(PLVL,PPUU,Local0) // convert SETUP value to power units in m= illi-watts - Divide(Local0,1000,,Local1) // convert SETUP value to power units in w= atts - Store(Local1, PPL1) // copy value to PL1 - Store(1, PL1E) // set Enable bit - Store(1, CLP1) // set Clamp bit -} -// -// RPL1 (Restore the PL1 register to the values prior to CS entry) -// -// Arguments: -// None -// -// Return Value: -// None -Method(RPL1,0,Serialized) -{ - Store (PLSV, PPL1) // restore value of PL1 upon exiting CS - Store(PLEN, PL1E) // restore the PL1 enable bit - Store(CLMP, CLP1) // restore the PL1 Clamp bit - Store(0, CSEM) // restore semaphore -} - -Name(UAMS, 0) // User Absent Mode state, Zero - User Present; non-Zero - U= ser not present -Name(GLCK, 0) // a spin lock to avoid multi execution of GUAM -// GUAM - Global User Absent Mode -// Run when a change to User Absent mode is made, e.g. screen/display = on/off events. -// Any device that needs notifications of these events includes its own= UAMN Control Method. -// -// Arguments: -// Power State: -// 00h =3D On -// 01h =3D Standby -// other value =3D do nothing & return -// -// Return Value: -// None -// -Method(GUAM,1,Serialized) -{ - Switch(ToInteger(Arg0)) - { - Case(0) // exit CS - { - If(LEqual(GLCK, 1)){ - store(0, GLCK) - - P8XH(0, 0xE1) - P8XH(1, 0xAB) - ADBG("Exit Resiliency") - - // @Todo: Exit EC Low Power Mode here - - - If(PSCP){ - // if P-state Capping s enabled - If (CondRefOf(\_PR.PR00._PPC)) - { - Store(Zero, \_PR.CPPC) - PNOT() - } - } - If(PLCS){ - RPL1() // restore PL1 to pre-CS value upon exiting CS - } - } // end GLCK=3D1 - } // end case(0) - - Case(1) // enter CS - { - If(LEqual(GLCK, 0)){ - store(1, GLCK) - - P8XH(0, 0xE0) - P8XH(1, 00) - ADBG("Enter Resiliency") - - //@Todo: Enter EC Low Power Mode here - - - If(PSCP){ - // if P-state Capping is enabled - If (LAnd(CondRefOf(\_PR.PR00._PSS), CondRefOf(\_PR.PR00._PPC))) - { - If(And(\PC00,0x0400)) - { - Subtract(SizeOf(\_PR.PR00.TPSS), One, \_PR.CPPC) - } Else { - Subtract(SizeOf(\_PR.PR00.LPSS), One, \_PR.CPPC) - } - PNOT() - } - } - If(PLCS){ - SPL1() // set PL1 to low value upon CS entry - } - } // end GLCK=3D0 - } // end case(1) - Default{ - Return() // do nothing - } - } // end switch(arg0) - - Store(LAnd(Arg0, LNot(PWRS)), UAMS) // UAMS: User Absent Mode state, Ze= ro - User Present; non-Zero - User not present - P_CS() // Powergating during CS - -} // end method GUAM() - -// Power CS Powergated Devices: -// Method to enable/disable power during CS -Method(P_CS,0,Serialized) -{ - // NOTE: Do not turn ON Touch devices from here. Touch does not have P= UAM - If(CondRefOf(\_SB.PCI0.PAUD.PUAM)){ // Notify Codec(HD-A/ADS= P) - \_SB.PCI0.PAUD.PUAM() - } - // Adding back USB powergating (ONLY for Win8) until RTD3 walkup port = setup implementation is complete */ - If(LEqual(OSYS,2012)){ // ONLY for Win8 OS - If(CondRefOf(\_SB.PCI0.XHC.DUAM)){ // Notify USB port- RVP - \_SB.PCI0.XHC.DUAM() - } - } - // TODO: Add calls to UAMN methods for - // * USB controller(s) - // * Embedded Controller - // * Sensor devices - // * Audio DSP? - // * Any other devices dependent on User Absent mode for power cont= rols -} - -// SMI I/O Trap: -// Generate a Mutex protected SMI I/O Trap. -// -// Arguments: -// Arg0: I/O Trap type. -// 2 - For DTS -// 3 - For IGD -// 4 - For BIOS Guard Tools -// Arg1: SMI I/O Trap Function to call. -// -// Return Value: -// SMI I/O Trap Return value. -// 0 =3D Success. Non-zero =3D Failure. - -Scope(\) -{ - // - // The IO address in this ACPI Operating Region will be updated during P= OST. - // This address range is used as a HotKey I/O Trap SMI so that ASL and S= MI can - // communicate when needed. - // - OperationRegion(IO_H,SystemIO,0x1000,0x4) - Field(IO_H,ByteAcc,NoLock,Preserve) { - TRPH, 8 - } -} - -Method(TRAP,2,Serialized) -{ - Store(Arg1,SMIF) // Store SMI Function. - - If(LEqual(Arg0,TRAP_TYPE_DTS)) // Is DTS IO Trap? - { - Store(Arg1,\_PR.DTSF) // Store the function number global NVS - Store(0,\_PR.TRPD) // Generate IO Trap. - Return(\_PR.DTSF) // Return status from SMI handler - } - - If(LEqual(Arg0,TRAP_TYPE_IGD)) // Is IGD IO Trap? - { - Store(0,TRPH) // Generate IO Trap. - } - - If(LEqual(Arg0,TRAP_TYPE_BGD)) // Is BIOS Guard TOOLS IO Trap? - { - Store(0,\_PR.TRPF) // Generate IO Trap - } - - Return(SMIF) // Return SMIF. 0 =3D Success. -} - -// Note: Only add the indicator device needed by the platform. - -// -// System Bus -// -Scope(\_SB.PCI0) -{ - - Method(_INI,0, Serialized) - { - - // Determine the OS and store the value, where: - // - // OSYS =3D 1000 =3D Linux. - // OSYS =3D 2000 =3D WIN2000. - // OSYS =3D 2001 =3D WINXP, RTM or SP1. - // OSYS =3D 2002 =3D WINXP SP2. - // OSYS =3D 2006 =3D Vista. - // OSYS =3D 2009 =3D Windows 7 and Windows Server 2008 R2. - // OSYS =3D 2012 =3D Windows 8 and Windows Server 2012. - // OSYS =3D 2013 =3D Windows Blue. - // - // Assume Windows 2000 at a minimum. - - Store(2000,OSYS) - - // Check for a specific OS which supports _OSI. - - If(CondRefOf(\_OSI)) - { - If(\_OSI("Linux")) - { - Store(1000,OSYS) - } - - If(\_OSI("Windows 2001")) // Windows XP - { - Store(2001,OSYS) - } - - If(\_OSI("Windows 2001 SP1")) //Windows XP SP1 - { - Store(2001,OSYS) - } - - If(\_OSI("Windows 2001 SP2")) //Windows XP SP2 - { - Store(2002,OSYS) - } - - If (\_OSI( "Windows 2001.1")) //Windows Server 2003 - { - Store(2003,OSYS) - } - - If(\_OSI("Windows 2006")) //Windows Vista - { - Store(2006,OSYS) - } - - If(\_OSI("Windows 2009")) //Windows 7 and Windows Server 2008 R2 - { - Store(2009,OSYS) - } - - If(\_OSI("Windows 2012")) //Windows 8 and Windows Server 2012 - { - Store(2012,OSYS) - } - - If(\_OSI("Windows 2013")) //Windows 8.1 and Windows Server 2012 R2 - { - Store(2013,OSYS) - } - - If(\_OSI("Windows 2015")) //Windows 10 - { - Store(2015,OSYS) - } - } - - // - // Set DTS NVS data means in OS ACPI mode enabled insteads of GlobalNv= s OperatingSystem (OSYS) - // - If(CondRefOf(\_PR.DTSE)){ - If(LGreaterEqual(\_PR.DTSE, 0x01)){ - Store(0x01, \_PR.DSAE) - } - } - - } - - Method(NHPG,0,Serialized) - { - Store(0,^RP01.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP02.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP03.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP04.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP05.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP06.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP07.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP08.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP09.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP10.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP11.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP12.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP13.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP14.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP15.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP16.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP17.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP18.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP19.HPEX) // clear the hot plug SCI enable bit - Store(0,^RP20.HPEX) // clear the hot plug SCI enable bit - - Store(1,^RP01.HPSX) // clear the hot plug SCI status bit - Store(1,^RP02.HPSX) // clear the hot plug SCI status bit - Store(1,^RP03.HPSX) // clear the hot plug SCI status bit - Store(1,^RP04.HPSX) // clear the hot plug SCI status bit - Store(1,^RP05.HPSX) // clear the hot plug SCI status bit - Store(1,^RP06.HPSX) // clear the hot plug SCI status bit - Store(1,^RP07.HPSX) // clear the hot plug SCI status bit - Store(1,^RP08.HPSX) // clear the hot plug SCI status bit - Store(1,^RP09.HPSX) // clear the hot plug SCI status bit - Store(1,^RP10.HPSX) // clear the hot plug SCI status bit - Store(1,^RP11.HPSX) // clear the hot plug SCI status bit - Store(1,^RP12.HPSX) // clear the hot plug SCI status bit - Store(1,^RP13.HPSX) // clear the hot plug SCI status bit - Store(1,^RP14.HPSX) // clear the hot plug SCI status bit - Store(1,^RP15.HPSX) // clear the hot plug SCI status bit - Store(1,^RP16.HPSX) // clear the hot plug SCI status bit - Store(1,^RP17.HPSX) // clear the hot plug SCI status bit - Store(1,^RP18.HPSX) // clear the hot plug SCI status bit - Store(1,^RP19.HPSX) // clear the hot plug SCI status bit - Store(1,^RP20.HPSX) // clear the hot plug SCI status bit - } - - Method(NPME,0,Serialized) - { - Store(0,^RP01.PMEX) // clear the PME SCI enable bit - Store(0,^RP02.PMEX) // clear the PME SCI enable bit - Store(0,^RP03.PMEX) // clear the PME SCI enable bit - Store(0,^RP04.PMEX) // clear the PME SCI enable bit - Store(0,^RP05.PMEX) // clear the PME SCI enable bit - Store(0,^RP06.PMEX) // clear the PME SCI enable bit - Store(0,^RP07.PMEX) // clear the PME SCI enable bit - Store(0,^RP08.PMEX) // clear the PME SCI enable bit - Store(0,^RP09.PMEX) // clear the PME SCI enable bit - Store(0,^RP10.PMEX) // clear the PME SCI enable bit - Store(0,^RP11.PMEX) // clear the PME SCI enable bit - Store(0,^RP12.PMEX) // clear the PME SCI enable bit - Store(0,^RP13.PMEX) // clear the PME SCI enable bit - Store(0,^RP14.PMEX) // clear the PME SCI enable bit - Store(0,^RP15.PMEX) // clear the PME SCI enable bit - Store(0,^RP16.PMEX) // clear the PME SCI enable bit - Store(0,^RP17.PMEX) // clear the PME SCI enable bit - Store(0,^RP18.PMEX) // clear the PME SCI enable bit - Store(0,^RP19.PMEX) // clear the PME SCI enable bit - Store(0,^RP20.PMEX) // clear the PME SCI enable bit - - Store(1,^RP01.PMSX) // clear the PME SCI status bit - Store(1,^RP02.PMSX) // clear the PME SCI status bit - Store(1,^RP03.PMSX) // clear the PME SCI status bit - Store(1,^RP04.PMSX) // clear the PME SCI status bit - Store(1,^RP05.PMSX) // clear the PME SCI status bit - Store(1,^RP06.PMSX) // clear the PME SCI enable bit - Store(1,^RP07.PMSX) // clear the PME SCI status bit - Store(1,^RP08.PMSX) // clear the PME SCI status bit - Store(1,^RP09.PMSX) // clear the PME SCI status bit - Store(1,^RP10.PMSX) // clear the PME SCI status bit - Store(1,^RP11.PMSX) // clear the PME SCI status bit - Store(1,^RP12.PMSX) // clear the PME SCI status bit - Store(1,^RP13.PMSX) // clear the PME SCI status bit - Store(1,^RP14.PMSX) // clear the PME SCI status bit - Store(1,^RP15.PMSX) // clear the PME SCI status bit - Store(1,^RP16.PMSX) // clear the PME SCI status bit - Store(1,^RP17.PMSX) // clear the PME SCI status bit - Store(1,^RP18.PMSX) // clear the PME SCI status bit - Store(1,^RP19.PMSX) // clear the PME SCI status bit - Store(1,^RP20.PMSX) // clear the PME SCI status bit - } -} - -Scope (\) -{ - // - // Global Name, returns current Interrupt controller mode; - // updated from _PIC control method - // - Name(PICM, 0) - - // - // Procedure: GPRW - // - // Description: Generic Wake up Control Method ("Big brother") - // to detect the Max Sleep State available in ASL Name scop= e - // and Return the Package compatible with _PRW format. - // Input: Arg0 =3D bit offset within GPE register space device event wi= ll be triggered to. - // Arg1 =3D Max Sleep state, device can resume the System from. - // If Arg1 =3D 0, Update Arg1 with Max _Sx state enabled = in the System. - // Output: _PRW package - // - Name(PRWP, Package(){Zero, Zero}) // _PRW Package - - Method(GPRW, 2) - { - Store(Arg0, Index(PRWP, 0)) // copy GPE# - // - // SS1-SS4 - enabled in BIOS Setup Sleep states - // - Store(ShiftLeft(SS1,1),Local0) // S1 ? - Or(Local0,ShiftLeft(SS2,2),Local0) // S2 ? - Or(Local0,ShiftLeft(SS3,3),Local0) // S3 ? - Or(Local0,ShiftLeft(SS4,4),Local0) // S4 ? - // - // Local0 has a bit mask of enabled Sx(1 based) - // bit mask of enabled in BIOS Setup Sleep states(1 based) - // - If(And(ShiftLeft(1, Arg1), Local0)) - { - // - // Requested wake up value (Arg1) is present in Sx list of available= Sleep states - // - Store(Arg1, Index(PRWP, 1)) // copy Sx# - } - Else - { - // - // Not available -> match Wake up value to the higher Sx state - // - ShiftRight(Local0, 1, Local0) - // If(LOr(LEqual(OSFL, 1), LEqual(OSFL, 2))) { // ??? Win9x - // FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 =3D=3D Max Sx - // } Else { // ??? Win2k / XP - FindSetLeftBit(Local0, Index(PRWP,1)) // Arg1 =3D=3D Min Sx - // } - } - - Return(PRWP) - } -} - - -Scope (\_SB) -{ - Name(OSCI, 0) // \_SB._OSC DWORD2 input - Name(OSCO, 0) // \_SB._OSC DWORD2 output - Name(OSCP, 0) // \_SB._OSC CAPABILITIES - // _OSC (Operating System Capabilities) - // _OSC under \_SB scope is used to convey platform wide OSPM capabil= ities. - // For a complete description of _OSC ACPI Control Method, refer to A= CPI 5.0 - // specification, section 6.2.10. - // Arguments: (4) - // Arg0 - A Buffer containing the UUID "0811B06E-4A27-44F9-8D60-3CBBC= 22E7B48" - // Arg1 - An Integer containing the Revision ID of the buffer format - // Arg2 - An Integer containing a count of entries in Arg3 - // Arg3 - A Buffer containing a list of DWORD capabilities - // Return Value: - // A Buffer containing the list of capabilities - // - Method(_OSC,4,Serialized) - { - // - // Point to Status DWORD in the Arg3 buffer (STATUS) - // - CreateDWordField(Arg3, 0, STS0) - // - // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES) - // - CreateDwordField(Arg3, 4, CAP0) - - - // - // Only set 8254 CG if Low Power S0 Idle Capability is enabled - // - If (LEqual(S0ID, One)) { - // - // Set ITSSPRC.8254CGE: Offset 3300h ITSSPRC[2] - // - Store(0x01, \_SB.SCGE) - } - - // - // Check UUID - // - If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) - { - // - // Check Revision - // - If(LEqual(Arg1,One)) - { - Store(CAP0, OSCP) - If(And(CAP0,0x04)) // Check _PR3 Support(BIT2) - { - Store(0x04, OSCO) - If(LNotEqual(And(SGMD,0x0F),2)) // Check Switchable/Hybrid graph= ics is not enabled in bios setup [SgModeMuxless]? - { - If(LEqual(RTD3,0)) // Is RTD3 support disabled in Bios Setup? - { - // RTD3 is disabled via BIOS Setup. - And(CAP0, 0x3B, CAP0) // Clear _PR3 capability - Or(STS0, 0x10, STS0) // Indicate capability bit is cleared - } - } - } - } Else{ - And(STS0,0xFFFFFF00,STS0) - Or(STS0,0xA, STS0) // Unrecognised Revision and report OSC failure - } - } Else { - And(STS0,0xFFFFFF00,STS0) - Or (STS0,0x6, STS0) // Unrecognised UUID and report OSC failure - } - - Return(Arg3) - } // End _OSC - -} // End of Scope(\_SB) - -// -// CS Wake up event support -// -Scope (\_SB) -{ - // Define Sleep button to put the system in sleep - Device (SLPB) - { - Name (_HID, EISAID ("PNP0C0E")) - Name (_STA, 0x0B) - // Bit0 - the device is present: Yes. - // Bit1 - the device is enabled and decoding its resources: Yes. - // Bit2 - the device should be shown in the UI: No. - // Bit3 - the device is functioning properly: Yes. - // Bit4 - the battery is present: N/A - } -} // End of Scope(\_SB) diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platfo= rmGnvs.asl b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platfo= rmGnvs.asl deleted file mode 100644 index 788a8ec491..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.= asl +++ /dev/null @@ -1,8 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.= asl b/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl deleted file mode 100644 index b15b754fb0..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Video.asl +++ /dev/null @@ -1,27 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -External(DIDX) - -// Brightness Notification: -// Generate a brightness related notification -// to the LFP if its populated. -// -// Arguments: -// Arg0: Notification value. -// -// Return Value: -// None - -Method(BRTN,1,Serialized) -{ - If(LEqual(And(DIDX,0x0F00),0x400)) - { - Notify(\_SB.PCI0.GFX0.DD1F,Arg0) - } -} diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3S= ptPcieTbt.asl b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rt= d3SptPcieTbt.asl deleted file mode 100644 index c082988fa9..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3SptPcieT= bt.asl +++ /dev/null @@ -1,403 +0,0 @@ -/** @file - ACPI RTD3 SSDT table for SPT PCIe - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#define PID_ICC 0xDC -#define R_PCH_PCR_ICC_MSKCKRQ 0x100C = ///< Mask Control CLKREQ - -External(PCRA,MethodObj) -External(PCRO,MethodObj) -External(\MMRP, MethodObj) -External(\MMTB, MethodObj) -External(\TRDO, IntObj) -External(\TRD3, IntObj) -External(\TBPE, IntObj) -External(\TOFF, IntObj) -External(\TBSE, IntObj) -External(\TBOD, IntObj) -External(\TBRP, IntObj) -External(\TBHR, IntObj) -External(\RTBC, IntObj) -External(\TBCD, IntObj) - -Name(G2SD, 0) // Go2Sx done, set by GO2S, cleaned by _ON - -Name(WKEN, 0) - - Method(_S0W, 0) - { - /// This method returns the lowest D-state supported by PCIe root port d= uring S0 state - - ///- PMEs can be generated from D3hot for ULT - Return(4) - - /** @defgroup pcie_s0W PCIE _S0W **/ - } // End _S0W - - Method (_DSD, 0) { - Return ( - Package () { - ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), - Package () { - Package (2) {"HotPlugSupportInD3", 1}, - } - } - ) // End of Return () - } - - Method(_DSW, 3) - { - /// This method is used to enable/disable wake from PCIe (WKEN) - If (LGreaterEqual(Arg1, 1)) { /// If entering Sx, need to disable WA= KE# from generating runtime PME - /// Also set 2 to TOFF. - Store(0, WKEN) - Store (2, TOFF) - } Else { /// If Staying in S0 - If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake - { ///- Set PME - Store(1, WKEN) - Store (1, TOFF) - } Else { ///- Disable runtime PME, either because staying in D0 or= disabling wake - Store(0, WKEN) - Store(0, TOFF) - } - } - - /** @defgroup pcie_dsw PCIE _DSW **/ - } // End _DSW - - - PowerResource(PXP, 0, 0) - { - /// Define the PowerResource for PCIe slot - /// Method: _STA(), _ON(), _OFF() - /** @defgroup pcie_pxp PCIE Power Resource **/ - - Method(_STA, 0) - { - Return(PSTA()) - } /** @defgroup pcie_sta PCIE _STA method **/ - - Method(_ON) /// Turn on core power to PCIe Slot - { - Store(1, TRDO) - PON() - Store(0, TRDO) - } /** @defgroup pcie_on PCIE _ON method **/ - - Method(_OFF) /// Turn off core power to PCIe Slot - { - Store(1, TRD3) - POFF() - Store(0, TRD3) - } // End of Method_OFF - } // End PXP - - Method(PSTA, 0) - { - /// Returns the status of PCIe slot core power - // detect power pin status - if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { - if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode - if(LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG,= 3)))){ - Return (1) - } Else { - Return (0) - } - } // GPIO mode - if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode - if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(PWRG, 1)),DeRefOf(In= dex(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){ - Return (1) - } Else { - Return (0) - } - } // IOEX mode - } - // detect reset pin status - if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { - if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode - if(LEqual(\_SB.GGOV(DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG,= 3)))){ - Return (1) - } Else { - Return (0) - } - } // GPIO mode - if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode - if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(RSTG, 1)),DeRefOf(In= dex(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){ - Return (1) - } Else { - Return (0) - } - } // IOEX mode - } - Return (0) - } /** @defgroup pcie_sta PCIE _STA method **/ - - Method (SXEX, 0, Serialized) { - - Store(\MMTB(TBSE), Local7) - OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR PCICFG M= MIO - Field(TBDI,DWordAcc, NoLock, Preserve) { - DIVI, 32, - CMDR, 32, - Offset(0x548), - TB2P, 32, - P2TB, 32 - } - - Store(100, Local1) - Store(0x09, P2TB) // Write SX_EXIT_TBT_CONNECTED to PCIe2TBT - While (LGreater(Local1, 0)) { - - Store(Subtract(Local1, 1), Local1) - Store(TB2P, Local2) - If (LEqual(Local2, 0xFFFFFFFF)) { // Device gone - Return() - } - If (And(Local2, 1)) { // Done - break - } - Sleep(5) - } - Store(0x0, P2TB) // Write 0 to PCIe2TBT - - // Fast Link bring-up flow - Store(500, Local1) - While (LGreater(Local1, 0)) { - Store(Subtract(Local1, 1), Local1) - Store(TB2P, Local2) - If (LEqual(Local2, 0xFFFFFFFF)) {// Device gone - Return() - } - If (LNotEqual(DIVI, 0xFFFFFFFF)) { - break - } - Sleep(10) - } - } // End of Method(SXEX, 0, Serialized) - - Method(PON) /// Turn on core power to PCIe Slot - { - - Store(\MMRP(\TBSE), Local7) - OperationRegion(L23P,SystemMemory,Local7,0xE4) - Field(L23P,WordAcc, NoLock, Preserve) - { - Offset(0xA4),// PMCSR - PSD0, 2, // PowerState - Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable - , 2, - L2TE, 1, // 2, L23_Rdy Entry Request (L23ER) - L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) - } - - Store(\MMTB(\TBSE), Local6) - OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG M= MIO - Field(TBDI,DWordAcc, NoLock, Preserve) { - DIVI, 32, - CMDR, 32, - Offset(0xA4), - TBPS, 2, // PowerState of TBT - Offset(0x548), - TB2P, 32, - P2TB, 32 - } - - Store(0, TOFF) - // Check RTD3 power enable, if already ON, no need to execute sx_exi= t - If (TBPE) { - Return() - } - - Store(0,G2SD) - If (\RTBC) { - /// de-assert CLK_REQ MSK - if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enab= led - PCRA(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,Not(DeRefOf(Index(SCLK, 1))))= // And ~SCLK to clear bit - } - Sleep(\TBCD) - } - - /// Turn ON Power for PCIe Slot - if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enable= d - if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode - \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3))) - Store(1, TBPE) - Sleep(PEP0) /// Sleep for programmable delay - } - if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, = 2)),DeRefOf(Index(PWRG, 3))) - Store(1, TBPE) - Sleep(PEP0) /// Sleep for programmable delay - } - } - - /// De-Assert Reset Pin - if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled - if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode - \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3))) - } - if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, = 2)),DeRefOf(Index(RSTG, 3))) - } - } - - /// Clear DLSULPPGE, then set L23_Rdy to Detect Transition (L23R2DT= ) - Store(0, DPGE) - Store(1, L2TR) - Sleep(16) - Store(0, Local0) - /// Wait up to 12 ms for transition to Detect - While(L2TR) { - If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms - { - Break - } - Sleep(16) - Increment(Local0) - } - /// Once in Detect, wait up to 124 ms for Link Active (typically hap= pens in under 70ms) - /// Worst case per PCIe spec from Detect to Link Active is: - /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config = (24+2+2+2+2) - Store(1, DPGE) - Store(0, Local0) - While(LEqual(LASX,0)) { - If(Lgreater(Local0, 8)) - { - Break - } - Sleep(16) - Increment(Local0) - } - Store(0, LEDM) /// Set PCIEDBG.DMIL1EDM (324[3]) =3D 0 - - // TBT special sleep. - Store(PSD0, Local1) - Store(0, PSD0)// D0 - Store(20, Local2) // Poll for TBT, up to 200 ms - - While (LGreater(Local2, 0)) { - Store(Subtract(Local2, 1), Local2) - Store(TB2P, Local3) - If (LNotEqual(Local3, 0xFFFFFFFF)) { // Done - break - } - Sleep(10) - } - - If (LLessEqual(Local2, 0)) { - } - SXEX() - Store(Local1, PSD0) // Back to Local1 - } /** @defgroup pcie_on PCIE _ON method **/ - - Method(POFF) { /// Turn off core power to PCIe Slot - If (LEqual(TOFF, 0)) { - Return() - } - Store(\MMRP(\TBSE), Local7) - OperationRegion(L23P, SystemMemory, Local7, 0xE4) - Field(L23P,WordAcc, NoLock, Preserve) - { - Offset(0xA4),// PMCSR - PSD0, 2, // PowerState - Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable - , 2, - L2TE, 1, // 2, L23_Rdy Entry Request (L23ER) - L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) - } - - Store(\MMTB(TBSE), Local6) - OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG M= MIO - Field(TBDI,DWordAcc, NoLock, Preserve) { - DIVI, 32, - CMDR, 32, - Offset(0xA4), - TBPS, 2, // PowerState of TBT - Offset(0x548), - TB2P, 32, - P2TB, 32 - } - - Store(PSD0, Local1) - Store(0, PSD0)// D0 - - Store(P2TB, Local3) - - If (Lgreater(TOFF, 1)) { - Sleep(10) - Store(Local1, PSD0) // Back to Local1 - Return() - } - Store(0, TOFF) - - Store(Local1, PSD0) // Back to Local1 - - /// Set L23_Rdy Entry Request (L23ER) - Store(1, L2TE) - Sleep(16) - Store(0, Local0) - While(L2TE) { - If(Lgreater(Local0, 4)) /// Debug - Wait for 5 ms - { - Break - } - Sleep(16) - Increment(Local0) - } - Store(1, LEDM) /// PCIEDBG.DMIL1EDM (324[3]) =3D 1 - - /// Assert Reset Pin - if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled - if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode - \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1)= ) - } - if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, = 2)),Xor(DeRefOf(Index(RSTG, 3)),1)) - } - } - If (\RTBC) { - /// assert CLK_REQ MSK - if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enab= led - PCRO(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,DeRefOf(Index(SCLK, 1))) /= / Or SCLK to set bit - Sleep(16) - } - } - - /// Power OFF for TBT - if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enable= d - if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode - \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1)= ) - } - if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, = 2)),Xor(DeRefOf(Index(PWRG, 3)),1)) - } - } - - Store(0, TBPE) - - Store(1, LDIS) /// Set Link Disable - Store(0, LDIS) /// Toggle link disable - - /// enable WAKE - If (WKEN) { - If (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating ena= bled - If (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode - \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3))) - \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership to= ACPI(0=3DACPI mode, 1=3DGPIO mode) - } - If (LEqual(DeRefOf(Index(WAKG, 0)),2)) { // IOEX mode - \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(WAKG, 1)),DeRefOf(Index(WAKG= , 2)),DeRefOf(Index(WAKG, 3))) - } - } - } - Sleep(\TBOD) - /** @defgroup pcie_off PCIE _OFF method **/ - } // End of Method_OFF - - Name(_PR0, Package(){PXP}) - Name(_PR3, Package(){PXP}) - diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.a= sl b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl deleted file mode 100644 index 2efe1a54f3..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl +++ /dev/null @@ -1,1894 +0,0 @@ -/** @file - Thunderbolt ACPI methods - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ -#define DTBT_CONTROLLER 0x00 -#define DTBT_TYPE_PCH 0x01 -#define DTBT_TYPE_PEG 0x02 -#define DTBT_SMI_HANDLER_NUMBER 0xF7 -#define TBT_SMI_ENUMERATION_FUNCTION 21 -#define TBT_SMI_RESET_SWITCH_FUNCTION 22 -#define TBT_SMI_DISABLE_MSI_FUNCTION 23 -#ifndef BIT29 -#define BIT29 0x20000000 -#endif - -Name(LDLY, 300) //300 ms -Name (TNVB, 0xFFFF0000) // TBT NVS Base address -Name (TNVL, 0xAA55) // TBT NVS Length -Include ("Acpi/TbtNvs.asl") - -External(\_SB.PCI0.RP02.L23D, MethodObj) -External(\_SB.PCI0.RP03.L23D, MethodObj) -External(\_SB.PCI0.RP04.L23D, MethodObj) -External(\_SB.PCI0.RP05.L23D, MethodObj) -External(\_SB.PCI0.RP06.L23D, MethodObj) -External(\_SB.PCI0.RP07.L23D, MethodObj) -External(\_SB.PCI0.RP08.L23D, MethodObj) -External(\_SB.PCI0.RP09.L23D, MethodObj) -External(\_SB.PCI0.RP10.L23D, MethodObj) -External(\_SB.PCI0.RP11.L23D, MethodObj) -External(\_SB.PCI0.RP12.L23D, MethodObj) -External(\_SB.PCI0.RP13.L23D, MethodObj) -External(\_SB.PCI0.RP14.L23D, MethodObj) -External(\_SB.PCI0.RP15.L23D, MethodObj) -External(\_SB.PCI0.RP16.L23D, MethodObj) -External(\_SB.PCI0.RP17.L23D, MethodObj) -External(\_SB.PCI0.RP18.L23D, MethodObj) -External(\_SB.PCI0.RP19.L23D, MethodObj) -External(\_SB.PCI0.RP20.L23D, MethodObj) -External(\_SB.PCI0.RP21.L23D, MethodObj) -External(\_SB.PCI0.RP22.L23D, MethodObj) -External(\_SB.PCI0.RP23.L23D, MethodObj) -External(\_SB.PCI0.RP24.L23D, MethodObj) - -External(\_SB.PCI0.RP01.DL23, MethodObj) -External(\_SB.PCI0.RP02.DL23, MethodObj) -External(\_SB.PCI0.RP03.DL23, MethodObj) -External(\_SB.PCI0.RP04.DL23, MethodObj) -External(\_SB.PCI0.RP05.DL23, MethodObj) -External(\_SB.PCI0.RP06.DL23, MethodObj) -External(\_SB.PCI0.RP07.DL23, MethodObj) -External(\_SB.PCI0.RP08.DL23, MethodObj) -External(\_SB.PCI0.RP09.DL23, MethodObj) -External(\_SB.PCI0.RP10.DL23, MethodObj) -External(\_SB.PCI0.RP11.DL23, MethodObj) -External(\_SB.PCI0.RP12.DL23, MethodObj) -External(\_SB.PCI0.RP13.DL23, MethodObj) -External(\_SB.PCI0.RP14.DL23, MethodObj) -External(\_SB.PCI0.RP15.DL23, MethodObj) -External(\_SB.PCI0.RP16.DL23, MethodObj) -External(\_SB.PCI0.RP17.DL23, MethodObj) -External(\_SB.PCI0.RP18.DL23, MethodObj) -External(\_SB.PCI0.RP19.DL23, MethodObj) -External(\_SB.PCI0.RP20.DL23, MethodObj) -External(\_SB.PCI0.RP21.DL23, MethodObj) -External(\_SB.PCI0.RP22.DL23, MethodObj) -External(\_SB.PCI0.RP23.DL23, MethodObj) -External(\_SB.PCI0.RP24.DL23, MethodObj) - -External(\_SB.PCI0.RTEN, MethodObj) -External(\_SB.PCI0.RTDS, MethodObj) -External(\_SB.PCI0.RP01.PON, MethodObj) -External(\_SB.PCI0.RP02.PON, MethodObj) -External(\_SB.PCI0.RP03.PON, MethodObj) -External(\_SB.PCI0.RP04.PON, MethodObj) -External(\_SB.PCI0.RP05.PON, MethodObj) -External(\_SB.PCI0.RP06.PON, MethodObj) -External(\_SB.PCI0.RP07.PON, MethodObj) -External(\_SB.PCI0.RP08.PON, MethodObj) -External(\_SB.PCI0.RP09.PON, MethodObj) -External(\_SB.PCI0.RP10.PON, MethodObj) -External(\_SB.PCI0.RP11.PON, MethodObj) -External(\_SB.PCI0.RP12.PON, MethodObj) -External(\_SB.PCI0.RP13.PON, MethodObj) -External(\_SB.PCI0.RP14.PON, MethodObj) -External(\_SB.PCI0.RP15.PON, MethodObj) -External(\_SB.PCI0.RP16.PON, MethodObj) -External(\_SB.PCI0.RP17.PON, MethodObj) -External(\_SB.PCI0.RP18.PON, MethodObj) -External(\_SB.PCI0.RP19.PON, MethodObj) -External(\_SB.PCI0.RP20.PON, MethodObj) -External(\_SB.PCI0.RP21.PON, MethodObj) -External(\_SB.PCI0.RP22.PON, MethodObj) -External(\_SB.PCI0.RP23.PON, MethodObj) -External(\_SB.PCI0.RP24.PON, MethodObj) -External(\_SB.PCI0.PEG0.PG00._ON, MethodObj) -External(\_SB.PCI0.PEG1.PG01._ON, MethodObj) -External(\_SB.PCI0.PEG2.PG02._ON, MethodObj) - -Name(TRDO, 0) // 1 during TBT RTD3 _ON -Name(TRD3, 0) // 1 during TBT RTD3 _OFF -Name(TBPE, 0) // Reflects RTD3_PWR_EN value -Name(TOFF, 0) // param to TBT _OFF method - - Method (TBON, 0, Serialized) { - // TBT On process before entering Sx state. - Store(1, TRDO) - Switch (ToInteger(\RPS0)) { // TBT Root port Selector - Case (1) { - If (CondRefOf(\_SB.PCI0.RP01.PON)) { - \_SB.PCI0.RP01.PON() - } - } - Case (2) { - If (CondRefOf(\_SB.PCI0.RP02.PON)) { - \_SB.PCI0.RP02.PON() - } - } - Case (3) { - If (CondRefOf(\_SB.PCI0.RP03.PON)) { - \_SB.PCI0.RP03.PON() - } - } - Case (4) { - If (CondRefOf(\_SB.PCI0.RP04.PON)) { - \_SB.PCI0.RP04.PON() - } - } - Case (5) { - If (CondRefOf(\_SB.PCI0.RP05.PON)) { - \_SB.PCI0.RP05.PON() - } - } - Case (6) { - If (CondRefOf(\_SB.PCI0.RP06.PON)) { - \_SB.PCI0.RP06.PON() - } - } - Case (7) { - If (CondRefOf(\_SB.PCI0.RP07.PON)) { - \_SB.PCI0.RP07.PON() - } - } - Case (8) { - If (CondRefOf(\_SB.PCI0.RP08.PON)) { - \_SB.PCI0.RP08.PON() - } - } - Case (9) { - If (CondRefOf(\_SB.PCI0.RP09.PON)) { - \_SB.PCI0.RP09.PON() - } - } - Case (10) { - If (CondRefOf(\_SB.PCI0.RP10.PON)) { - \_SB.PCI0.RP10.PON() - } - } - Case (11) { - If (CondRefOf(\_SB.PCI0.RP11.PON)) { - \_SB.PCI0.RP11.PON() - } - } - Case (12) { - If (CondRefOf(\_SB.PCI0.RP12.PON)) { - \_SB.PCI0.RP12.PON() - } - } - Case (13) { - If (CondRefOf(\_SB.PCI0.RP13.PON)) { - \_SB.PCI0.RP13.PON() - } - } - Case (14) { - If (CondRefOf(\_SB.PCI0.RP14.PON)) { - \_SB.PCI0.RP14.PON() - } - } - Case (15) { - If (CondRefOf(\_SB.PCI0.RP15.PON)) { - \_SB.PCI0.RP15.PON() - } - } - Case (16) { - If (CondRefOf(\_SB.PCI0.RP16.PON)) { - \_SB.PCI0.RP16.PON() - } - } - Case (17) { - If (CondRefOf(\_SB.PCI0.RP17.PON)) { - \_SB.PCI0.RP17.PON() - } - } - Case (18) { - If (CondRefOf(\_SB.PCI0.RP18.PON)) { - \_SB.PCI0.RP18.PON() - } - } - Case (19) { - If (CondRefOf(\_SB.PCI0.RP19.PON)) { - \_SB.PCI0.RP19.PON() - } - } - Case (20) { - If (CondRefOf(\_SB.PCI0.RP20.PON)) { - \_SB.PCI0.RP20.PON() - } - } - Case (21) { - If (CondRefOf(\_SB.PCI0.RP21.PON)) { - \_SB.PCI0.RP21.PON() - } - } - Case (22) { - If (CondRefOf(\_SB.PCI0.RP22.PON)) { - \_SB.PCI0.RP22.PON() - } - } - Case (23) { - If (CondRefOf(\_SB.PCI0.RP23.PON)) { - \_SB.PCI0.RP23.PON() - } - } - Case (24) { - If (CondRefOf(\_SB.PCI0.RP24.PON)) { - \_SB.PCI0.RP24.PON() - } - } - }//Switch(ToInteger(RPS0)) // TBT Selector - Store(0, TRDO) - } // End of TBON - // - // Name: TBTD - // Description: Function to return the TBT RP# device no - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // Return: TBT RP# device no - // - Method(TBTD,2) - { - ADBG("TBTD") - If (LEqual(Arg1, DTBT_TYPE_PCH)) { - Switch(ToInteger(Arg0)) - { - Case (Package () {1, 2, 3, 4, 5, 6, 7, 8}) - { - Store(0x1C, Local0) //Device28-Function0...Function7 =3D 11100.0= 00...111 - } - Case (Package () {9, 10, 11, 12, 13, 14, 15, 16}) - { - Store(0x1D, Local0) //Device29-Function0...Function7 =3D 11101.0= 00...111 - } - Case (Package () {17, 18, 19, 20, 21, 22, 23, 24}) - { - Store(0x1B, Local0) //Device27-Function0...Function3 =3D 11011.0= 00...011 - } - } - } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { - Switch(ToInteger(Arg0)) - { - Case (Package () {1, 2, 3}) - { - Store(0x1, Local0) //Device1-Function0...Function2 =3D 00001.000= ...010 - } -#ifndef CPU_CFL - Case (Package () {4}) - { - Store(0x6, Local0) //Device6-Function0 =3D 00110.000 - } -#endif - } - } Else { - Store(0xFF, Local0) - } - - ADBG("Device no") - ADBG(Local0) - - Return(Local0) - } // End of Method(TBTD,1) - - // - // Name: TBTF - // Description: Function to return the TBT RP# function no - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // Return: TBT RP# function no - // - Method(TBTF,2) - { - ADBG("TBTF") - If (LEqual(Arg1, DTBT_TYPE_PCH)) { - Switch(ToInteger(Arg0)) - { - Case (1) - { - Store(And(\RPA1,0xF), Local0) //Device28-Function0 =3D 11100.000 - } - Case (2) - { - Store(And(\RPA2,0xF), Local0) //Device28-Function1 =3D 11100.001 - } - Case (3) - { - Store(And(\RPA3,0xF), Local0) //Device28-Function2 =3D 11100.010 - } - Case (4) - { - Store(And(\RPA4,0xF), Local0) //Device28-Function3 =3D 11100.011 - } - Case (5) - { - Store(And(\RPA5,0xF), Local0) //Device28-Function4 =3D 11100.100 - } - Case (6) - { - Store(And(\RPA6,0xF), Local0) //Device28-Function5 =3D 11100.101 - } - Case (7) - { - Store(And(\RPA7,0xF), Local0) //Device28-Function6 =3D 11100.110 - } - Case (8) - { - Store(And(\RPA8,0xF), Local0) //Device28-Function7 =3D 11100.111 - } - Case (9) - { - Store(And(\RPA9,0xF), Local0) //Device29-Function0 =3D 11101.000 - } - Case (10) - { - Store(And(\RPAA,0xF), Local0) //Device29-Function1 =3D 11101.001 - } - Case (11) - { - Store(And(\RPAB,0xF), Local0) //Device29-Function2 =3D 11101.010 - } - Case (12) - { - Store(And(\RPAC,0xF), Local0) //Device29-Function3 =3D 11101.011 - } - Case (13) - { - Store(And(\RPAD,0xF), Local0) //Device29-Function4 =3D 11101.100 - } - Case (14) - { - Store(And(\RPAE,0xF), Local0) //Device29-Function5 =3D 11101.101 - } - Case (15) - { - Store(And(\RPAF,0xF), Local0) //Device29-Function6 =3D 11101.110 - } - Case (16) - { - Store(And(\RPAG,0xF), Local0) //Device29-Function7 =3D 11101.111 - } - Case (17) - { - Store(And(\RPAH,0xF), Local0) //Device27-Function0 =3D 11011.000 - } - Case (18) - { - Store(And(\RPAI,0xF), Local0) //Device27-Function1 =3D 11011.001 - } - Case (19) - { - Store(And(\RPAJ,0xF), Local0) //Device27-Function2 =3D 11011.010 - } - Case (20) - { - Store(And(\RPAK,0xF), Local0) //Device27-Function3 =3D 11011.011 - } - Case (21) - { - Store(And(\RPAL,0xF), Local0) //Device27-Function4 =3D 11011.100 - } - Case (22) - { - Store(And(\RPAM,0xF), Local0) //Device27-Function5 =3D 11011.101 - } - Case (23) - { - Store(And(\RPAN,0xF), Local0) //Device27-Function6 =3D 11011.110 - } - Case (24) - { - Store(And(\RPAO,0xF), Local0) //Device27-Function7 =3D 11011.111 - } - } - } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { - Switch(ToInteger(Arg0)) - { - Case (1) - { - Store(0x0, Local0) //Device1-Function0 =3D 00001.000 - } - Case (2) - { - Store(0x1, Local0) //Device1-Function1 =3D 00001.001 - } - Case (3) - { - Store(0x2, Local0) //Device1-Function2 =3D 00001.010 - } -#ifndef CPU_CFL - Case (4) - { - Store(0x0, Local0) //Device6-Function0 =3D 00110.000 - } -#endif - } - } Else { - Store(0xFF, Local0) - } - - ADBG("Function no") - ADBG(Local0) - - Return(Local0) - } // End of Method(TBTF,1) - - // - // Name: MMRP - // Description: Function to return the Pci base address of TBT rootport - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // - - Method(MMRP, 2, Serialized) - { - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no - - Return(Local0) - } // End of Method(MMRP) - - // - // Name: MMRP - // Description: Function to return the Pci base address of TBT Up stream= port - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // - Method(MMTB, 2, Serialized) - { - ADBG("MMTB") - - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address - - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no - - OperationRegion (MMMM, SystemMemory, Local0, 0x1A) - Field (MMMM, AnyAcc, NoLock, Preserve) - { - Offset(0x19), - SBUS, 8 - } - Store(SBUS, Local2) - Store(\_SB.PCI0.GPCB(), Local0) - Multiply(Local2, 0x100000, Local2) - Add(Local2, Local0, Local0) // TBT HR US port - - ADBG("TBT-US-ADR") - ADBG(Local0) - - Return(Local0) - } // End of Method(MMTB, 1, Serialized) - // - // Name: FFTB - // Description: Function to Check for FFFF in TBT PCIe - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // Return: 1 if TBT PCIe space has value FFFF, 0 if not - // - Method(FFTB, 2, Serialized) - { - ADBG("FFTB") - - Add(MMTB(Arg0, Arg1), 0x548, Local0) - OperationRegion(PXVD,SystemMemory,Local0,0x08) - Field(PXVD,DWordAcc, NoLock, Preserve) - { - TB2P, 32, - P2TB, 32 - } - - Store(TB2P, Local1) - - If(LEqual(Local1, 0xFFFFFFFF)) - { - ADBG("FFTb 1") - Return (1) - } - Else - { - ADBG("FFTb 0") - Return (0) - } - } // End of Method(FFTB) - -Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, = fixed up during POST - -Scope(\_GPE) -{ - // - // - //OS up Mail Box command execution to host router upstream port each tim= e - //exiting from Sx State .Avoids intermediate - //PCIe Scan by OS during resorce allocation - // Arg0 : PCIe Base address - // Arg1 : Controller Type 0x00 : DTBT - //Developer notes: Called twice - // 1. During OS INIT (booting to OS from S3-S5/Reboot) - // 2. Up on Hot plug - // - Method(OSUP, 2, Serialized) - { - ADBG("OSUP") - - Add(Arg0, 0x540, Local0) - OperationRegion(PXVD,SystemMemory,Local0,0x10) - Field(PXVD,DWordAcc, NoLock, Preserve) - { - IT2P, 32, - IP2T, 32, - DT2P, 32, - DP2T, 32 - } - - Store(100, Local1) - Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT - - While(LGreater(Local1, 0)) - { - Store(Subtract(Local1, 1), Local1) - Store(DT2P, Local2) - - If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))//= Device gone - { - ADBG("Dev gone") - Return(2) - } - If(And(Local2, 1)) // Done - { - ADBG("Cmd acknowledged") - break - } - Sleep(50) - } - If(LEqual(TRWA,1)) - { - Store(0xC, DP2T) // Write OSUP to PCIe2TBT - } - Else - { - Store(0x0, DP2T) // Write 0 to PCIe2TBT - } - - //Store(0x00, P2TB) // Write 0 to PCIe2TBT - - ADBG("End-of-OSUP") - - Return(1) - } // End of Method(OSUP, 1, Serialized) - - // - // Check for FFFF in TBT - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // - - Method(TBFF, 2, Serialized) - { - ADBG("TBFF") - - Store(MMTB(Arg0, Arg1), Local0) - OperationRegion (PXVD, SystemMemory, Local0, 0x8) - Field (PXVD, DWordAcc, NoLock, Preserve) { - VEDI, 32, // Vendor/Device ID - CMDR, 32 // CMD register - } - - Store(VEDI, Local1) - - If (LEqual(Local1, 0xFFFFFFFF)) { - If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode? - If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone - Return (2)// Notify only - } - Return (1)// Exit w/o notify - } Else { - Return (OSUP(Local0, DTBT_CONTROLLER)) - } - } Else - { - ADBG("Dev Present") - Return (0) - } - } // End of Method(TBFF, 1, Serialized) - - // - // Secondary bus of TBT RP - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // - - Method(TSUB, 2, Serialized) - { - ADBG("TSUB") - - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address - - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no - - ADBG("ADR") - ADBG(Local0) - - OperationRegion (MMMM, SystemMemory, Local0, 0x1A) - Field (MMMM, AnyAcc, NoLock, Preserve) - { - Offset(0x19), - SBUS, 8 - } - - ADBG("Sec Bus") - ADBG(SBUS) - - Return(SBUS) - } // End of Method(TSUB, 0, Serialized) - - // - // Pmem of TBT RP - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // - - Method(TSUP, 2, Serialized) - { - ADBG("TSUB") - - Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address - - Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no - Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no - - ADBG("ADR:") - ADBG(Local0) - - OperationRegion (MMMM, SystemMemory, Local0, 0x30) - Field (MMMM, AnyAcc, NoLock, Preserve) - { - CMDS, 32, - Offset(0x19), - SBUS, 8, - SBU5, 8, - Offset(0x1C), - SEIO, 32, - MMBL, 32, - PMBL, 32, - - } - - ADBG("Pmem of TBT RP:") - ADBG(PMBL) - - Return(PMBL) - } // End of Method(TSUP, 0, Serialized) - - // - // Wait for secondary bus in TBT RP - // Input: Arg0 -> Tbt Root Port value from Tbt NVS - // Input: Arg1 -> Tbt port type value from Tbt NVS - // - - Method(WSUB, 2, Serialized) - { - ADBG(Concatenate("WSUB=3D", ToHexString(Arg0))) - ADBG(ToHexString(Timer)) - - Store(0, Local0) - Store(0, Local1) - While(1) - { - Store(TSUP(Arg0, Arg1), Local1) - If(LGreater(Local1, 0x1FFF1)) - { - ADBG("WSUB-Finished") - Break - } - Else - { - Add(Local0, 1, Local0) - If(LGreater(Local0, 1000)) - { - Sleep(1000) - ADBG("WSUB-Deadlock") - } - Else - { - Sleep(16) - } - } - } - ADBG(Concatenate("WSUb=3D", ToHexString(Local1))) - } // End of Method(WSUB) - - // Wait for _WAK finished - Method(WWAK) - { - ADBG("WWAK") - - Wait(WFEV, 0xFFFF) - Signal(WFEV) // Set it, to enter on next HP - } // End of Method(WWAK) - - Method(NTFY, 2, Serialized) - { - ADBG("NTFY") - - If(LEqual(NOHP,1)) - { - If (LEqual(Arg1, DTBT_TYPE_PCH)) { - Switch(ToInteger(Arg0)) // TBT Selector - { - Case (1) - { - ADBG("Notify RP01") - Notify(\_SB.PCI0.RP01,0) - } - Case (2) - { - ADBG("Notify RP02") - Notify(\_SB.PCI0.RP02,0) - } - Case (3) - { - ADBG("Notify RP03") - Notify(\_SB.PCI0.RP03,0) - } - Case (4) - { - ADBG("Notify RP04") - Notify(\_SB.PCI0.RP04,0) - } - Case (5) - { - ADBG("Notify RP05") - Notify(\_SB.PCI0.RP05,0) - } - Case (6) - { - ADBG("Notify RP06") - Notify(\_SB.PCI0.RP06,0) - } - Case (7) - { - ADBG("Notify RP07") - Notify(\_SB.PCI0.RP07,0) - } - Case (8) - { - ADBG("Notify RP08") - Notify(\_SB.PCI0.RP08,0) - } - Case (9) - { - ADBG("Notify RP09") - Notify(\_SB.PCI0.RP09,0) - } - Case (10) - { - ADBG("Notify RP10") - Notify(\_SB.PCI0.RP10,0) - } - Case (11) - { - ADBG("Notify RP11") - Notify(\_SB.PCI0.RP11,0) - } - Case (12) - { - ADBG("Notify RP12") - Notify(\_SB.PCI0.RP12,0) - } - Case (13) - { - ADBG("Notify RP13") - Notify(\_SB.PCI0.RP13,0) - } - Case (14) - { - ADBG("Notify RP14") - Notify(\_SB.PCI0.RP14,0) - } - Case (15) - { - ADBG("Notify RP15") - Notify(\_SB.PCI0.RP15,0) - } - Case (16) - { - ADBG("Notify RP16") - Notify(\_SB.PCI0.RP16,0) - } - Case (17) - { - ADBG("Notify RP17") - Notify(\_SB.PCI0.RP17,0) - } - Case (18) - { - ADBG("Notify RP18") - Notify(\_SB.PCI0.RP18,0) - } - Case (19) - { - ADBG("Notify RP19") - Notify(\_SB.PCI0.RP19,0) - } - Case (20) - { - ADBG("Notify RP20") - Notify(\_SB.PCI0.RP20,0) - } - Case (21) - { - ADBG("Notify RP21") - Notify(\_SB.PCI0.RP21,0) - } - Case (22) - { - ADBG("Notify RP22") - Notify(\_SB.PCI0.RP22,0) - } - Case (23) - { - ADBG("Notify RP23") - Notify(\_SB.PCI0.RP23,0) - } - Case (24) - { - ADBG("Notify RP24") - Notify(\_SB.PCI0.RP24,0) - } - }//Switch(ToInteger(TBSS)) // TBT Selector - } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { - Switch(ToInteger(Arg0)) - { - Case (1) - { - ADBG("Notify PEG0") - Notify(\_SB.PCI0.PEG0,0) - } - Case (2) - { - ADBG("Notify PEG1") - Notify(\_SB.PCI0.PEG1,0) - } - Case (3) - { - ADBG("Notify PEG2") - Notify(\_SB.PCI0.PEG2,0) - } -#ifndef CPU_CFL - Case (4) - { - ADBG("Notify PEG3") - Notify(\_SB.PCI0.PEG3,0) - } -#endif - } - }//Switch(ToInteger(TBSS)) // TBT Selector - }//If(NOHP()) - P8XH(0,0xC2) - P8XH(1,0xC2) - }// End of Method(NTFY) - -// -// TBT BIOS, GPIO 5 filtering, -// Hot plug of 12V USB devices, into TBT host router, cause electrical no= ise on PCH GPIOs, -// This noise cause false hot-plug events, and negatively influence BIOS = assisted hot-plug. -// SKL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS= ) on any GPIO pad. Native functions have to implement their own digital gli= tch-filter logic -// if needed. As HW filter was not implemented on SKL PCH, because of tha= t SW workaround should be implemented in BIOS. -// Register 0x544(Bios mailbox) bit 0 definition: -// if BIOS reads bit as 1, BIOS will clear the bit and continue normal fl= ow, if bit is 0 BIOS will exit from method -// - - Method(GNIS,2, Serialized) - { - - ADBG("GNIS") - If(LEqual(GP5F, 0)) - { - ADBG("GNIS_Dis=3D0") - Return(0) - } - // - // BIOS mailbox command for GPIO filter - // - Add(MMTB(Arg0, Arg1), 0x544, Local0) - OperationRegion(PXVD,SystemMemory,Local0,0x08) - - Field(PXVD,DWordAcc, NoLock, Preserve) - { - HPFI, 1, - Offset(0x4), - TB2P, 32 - } - Store(TB2P, Local1) - ADBG(Concatenate("TB2P=3D", ToHexString(Local1))) - If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect? - { - ADBG("GNIS=3D0") - Return(0) - } - Store(HPFI, Local2) - ADBG(Concatenate("HPFI=3D", ToHexString(Local2))) - If(LEqual(Local2, 0x01)) - { - Store(0x00, HPFI) - ADBG("GNIS=3D0") - Return(0) - } - // Any other values treated as a GPIO noise - ADBG("GNIS=3D1") - Return(1) - } - - Method(CHKP,2, Serialized) - { - Add(MMTB(Arg0, Arg1), 0x544, Local0) - OperationRegion(PXVE,SystemMemory,Local0,0x08) - - Field(PXVE,DWordAcc, NoLock, Preserve) - { - HPFI, 1, - Offset(0x4), - TB2P, 32 - } - Store(TB2P, Local1) - And(Local1,BIT29,Local1) - ADBG(Concatenate("Local1=3D", ToHexString(Local1))) - //ADBG(Concatenate("BIT29=3D", ToHexString(LAnd(Local1,BIT29)))) - If(LEqual(Local1, BIT29)) - { - Return(1) - } - Else - { - Return(0) - } - } - - // - // Method to Handle enumerate PCIe structure through - // SMI for Thunderbolt(TM) devices - // - Method(XTBT,2, Serialized) - { - ADBG("XTBT") - ADBG("RP :") - ADBG(Arg0) - Store(Arg0, DTCP) // Root port to enumerate - Store(Arg1, DTPT) // Root port Type - If(LEqual(Arg0, RPS0)) { - Store (1, Local0) - } ElseIf (LEqual(Arg0, RPS1)) { - Store (2, Local0) - } Else { - Store (0, Local0) - Return () - } - - If (TRDO) { - ADBG("Durng TBT_ON") - Return () - } - - If (TRD3) { - ADBG("During TBT_OFF") - Return () - } - WWAK() - WSUB(Arg0, Arg1) - If(GNIS(Arg0, Arg1)) - { - Return() - } - - OperationRegion(SPRT,SystemIO, 0xB2,2) - Field (SPRT, ByteAcc, Lock, Preserve) - { - SSMP, 8 - } - - ADBG("TBT-HP-Handler") - - Acquire(OSUM, 0xFFFF) - Store(TBFF(Arg0, Arg1), Local1) - If(LEqual(Local1, 1))// Only HR - { - Sleep(16) - Release(OSUM) - ADBG("OS_Up_Received") - Return () - } - If(LEqual(Local1, 2)) // Disconnect - { - NTFY(Arg0, Arg1) - Sleep(16) - Release(OSUM) - ADBG("Disconnect") - Return () - } - - // HR and EP - If(LEqual(SOHP, 1)) - { - // Trigger SMI to enumerate PCIe Structure - ADBG("TBT SW SMI") - Store(21, TBSF) - Store(0xF7, SSMP) - } - NTFY(Arg0, Arg1) - Sleep(16) - Release(OSUM) - - ADBG("End-of-XTBT") - } // End of Method(XTBT) - - // - // Calling Method to Handle enumerate PCIe structure through - // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs - // Used in Two ways , - // If CIO GPIO(1 Tier) is Different for the Controllers, this will be us= ed as 1 Tier GPIO Handler for 1st controller - // If CIO GPIO(1 Tier) is Same for all the controllers, this will be use= d as 1 Tier GPIO Handler for All the controllers - // - Method(ATBT) - { - ADBG("ATBT") - // - // Calling Method to Handle enumerate PCIe structure through - // - If(LEqual(CGST,0)) { // If GPIO is Different for each controller - If(LEqual(RPN0,1)) - { - XTBT(RPS0, RPT0) - } - } Else { - If(LEqual(RPN0,1)) - { - XTBT(RPS0, RPT0) - } - ElseIf(LEqual(RPN1,1)) - { - XTBT(RPS1, RPT1) - } - } - ADBG("End-of-ATBT") - } // End of Method(ATBT) - - Method(BTBT) - { - ADBG("BTBT") - // - // Calling Method to Handle enumerate PCIe structure through - // - If(LEqual(CGST,0)) { // If GPIO is Different for each controller - If(LEqual(RPN1,1)) - { - XTBT(RPS1, RPT1) - } - } - ADBG("End-of-BTBT") - } // End of Method(BTBT) - // - // Method to call OSPU Mail box command - // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT - // Arg1 : TBT RP Selector / DMA - // Arg2 : TBT Type (PCH or PEG) - // - Method(TINI, 3, Serialized) - { - ADBG("TINI") - If(Lequal (Arg0, DTBT_CONTROLLER)) - { - //ADBG("DTBT") - Store(MMRP(Arg1, Arg2), Local0) - OperationRegion(RP_X,SystemMemory,Local0,0x20) - Field(RP_X,DWordAcc, NoLock, Preserve) - { - REG0, 32, - REG1, 32, - REG2, 32, - REG3, 32, - REG4, 32, - REG5, 32, - REG6, 32, - REG7, 32 - } - Store(REG6, Local1) - Store(0x00F0F000, REG6) - Store(MMTB(Arg1, Arg2), Local2) - OSUP(Local2, DTBT_CONTROLLER) - Store(Local1, REG6) - } - ADBG("End-of-TINI") - } - -} // End of Scope (\_GPE) - -Scope (\_SB) -{ - // - // The code needs to be executed for TBT Hotplug Handler event (2-tier G= PI GPE event architecture) is presented here - // - Method(THDR, 3, Serialized) - { - ADBG("THDR") - \_SB.CAGS(Arg0) - \_GPE.XTBT(Arg1, Arg2) - } // End of Method(THDR, 3, Serialized) -} // End of Scope(\_SB) - -Scope (\_SB) -{ - // - // Name: CGWR [Combined GPIO Write] - // Description: Function to write into GPIO - // Input: Arg0 -> GpioPad / Expander pin - // Arg1 -> Value - // Return: Nothing - // - Method(CGWR, 2, Serialized) - { - // PCH - If (CondRefOf(\_SB.SGOV)) - { - \_SB.SGOV(Arg0, Arg1) - } - } // End of Method(CGWR, 4, Serialized) - - // - // Name: CGRD [Combined GPIO Read] - // Description: Function to read from GPIO - // Input: Arg0 -> GpioPad / Expander pin - // Arg1 -> 0: GPO [GPIO TX State] - // 1: GPI [GPIO RX State] - // Return: Value - // - Method(CGRD, 2, Serialized) - { - Store(1, Local0) - // PCH - If (LEqual(Arg1, 0)) - { - // GPIO TX State - If (CondRefOf(\_SB.GGOV)) - { - Store(\_SB.GGOV(Arg0), Local0) - } - } - ElseIf (LEqual(Arg1, 1)) - { - // GPIO RX State - If (CondRefOf(\_SB.GGIV)) - { - Store(\_SB.GGIV(Arg0), Local0) - } - } - Return(Local0) - } // End of Method(CGRD, 4, Serialized) - // - // Name: WRGP [GPIO Write] - // Description: Function to write into GPIO - // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo - // Arg1 -> Value - // Return: Nothing - // - Method(WRGP, 2, Serialized) - { - Store(Arg0, Local0) - Store(Arg0, Local1) - And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) - ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) - If (LEqual(And(Local0, 0xFF), 1)) - { - // PCH - \_SB.CGWR(Local1, Arg1) - } - } // End of Method(WRGP, 2, Serialized) - - // - // Name: RDGP [GPIO Read] - // Description: Function to write into GPIO - // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo - // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indic= ator} - // Return: Value - // - Method(RDGP, 2, Serialized) - { - Store(1, Local7) - Store(Arg0, Local0) - Store(Arg0, Local1) - And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) - ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) - If (LEqual(And(Local0, 0xFF), 1)) - { - // PCH - Store(\_SB.CGRD(Local1, Arg1), Local7) - } - Return(Local7) - } // End of Method(RDGP, 2, Serialized) - -} // End of Scope(\_SB) - -Scope(\_SB) -{ - // Asserts/De-asserts TBT force power - Method(TBFP, 2) - { - If(Arg0) - { - // Implementation dependent way to assert TBT force power - If(LEqual(Arg1, 1)) { - CGWR(FPG0, FP0L) - } - Else { - CGWR(FPG1, FP1L) - } - } - Else - { - // Implementation dependent way to de-assert TBT force power - If(LEqual(Arg1, 1)) { - CGWR(FPG0, LNot(FP0L)) - } - Else { - CGWR(FPG1, LNot(FP1L)) - } - } - } - - // WMI ACPI device to control TBT force power - Device(WMTF) - { - // pnp0c14 is pnp id assigned to WMI mapper - Name(_HID, "PNP0C14") - Name(_UID, "TBFP") - - Name(_WDG, Buffer() { - // {86CCFD48-205E-4A77-9C48-2021CBEDE341} - 0x48, 0xFD, 0xCC, 0x86, - 0x5E, 0x20, - 0x77, 0x4A, - 0x9C, 0x48, - 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41, - 84, 70, // Object Id (TF) - 1, // Instance Count - 0x02 // Flags (WMIACPI_REGFLAG_METHOD) - }) - - // Set TBT force power - // Arg2 is force power value - Method(WMTF, 3) - { - CreateByteField(Arg2,0,FP) - - If(FP) - { - TBFP(1, 1) - } - Else - { - TBFP(0, 1) - } - } - } -} // End of Scope(\_SB) - - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1)))) -{ - Scope(\_SB.PCI0.RP01) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP01) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2)))) -{ - Scope(\_SB.PCI0.RP02) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP02) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3)))) -{ - Scope(\_SB.PCI0.RP03) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP03) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4)))) -{ - Scope(\_SB.PCI0.RP04) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP04) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5)))) -{ - Scope(\_SB.PCI0.RP05) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP05) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6)))) -{ - Scope(\_SB.PCI0.RP06) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP06) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7)))) -{ - Scope(\_SB.PCI0.RP07) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP07) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8)))) -{ - Scope(\_SB.PCI0.RP08) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP08) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9)))) -{ - Scope(\_SB.PCI0.RP09) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP09) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10)))) -{ - Scope(\_SB.PCI0.RP10) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP10) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11)))) -{ - Scope(\_SB.PCI0.RP11) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP11) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12)))) -{ - Scope(\_SB.PCI0.RP12) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP12) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13)))) -{ - Scope(\_SB.PCI0.RP13) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP13) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14)))) -{ - Scope(\_SB.PCI0.RP14) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP14) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15)))) -{ - Scope(\_SB.PCI0.RP15) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP15) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16)))) -{ - Scope(\_SB.PCI0.RP16) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP16) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17)))) -{ - Scope(\_SB.PCI0.RP17) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP17) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18)))) -{ - Scope(\_SB.PCI0.RP18) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP18) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19)))) -{ - Scope(\_SB.PCI0.RP19) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP19) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20)))) -{ - Scope(\_SB.PCI0.RP20) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.RP20) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21)))) -{ - Scope(\_SB.PCI0.PEG0) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.PEG0) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22)))) -{ - Scope(\_SB.PCI0.PEG1) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.PEG1) -} - -If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23)))) -{ - Scope(\_SB.PCI0.PEG2) - { - Device(HRUS)// Host router Upstream port - { - Name(_ADR, 0x00000000) - - Method(_RMV) - { - Return(TARS) - } // end _RMV - } - }//End of Scope(\_SB.PCI0.PEG2) -} - -Scope(\_SB) -{ - // - // Name: PERB - // Description: Function to read a Byte from PCIE-MMIO - // Input: Arg0 -> PCIE base address - // Arg1 -> Bus - // Arg2 -> Device - // Arg3 -> Function - // Arg4 -> Register offset - // Return: Byte data read from PCIE-MMIO - // - Method(PERB,5,Serialized) - { - ADBG("PERB") - - Store(Arg0, Local7) - Or(Local7, ShiftLeft(Arg1, 20), Local7) - Or(Local7, ShiftLeft(Arg2, 15), Local7) - Or(Local7, ShiftLeft(Arg3, 12), Local7) - Or(Local7, Arg4, Local7) - - OperationRegion(PCI0, SystemMemory, Local7, 1) - Field(PCI0, ByteAcc,NoLock,Preserve) - { - TEMP, 8 - } - - Return(TEMP) - } // End of Method(PERB,5,Serialized) - - // - // Name: PEWB - // Description: Function to write a Byte into PCIE-MMIO - // Input: Arg0 -> PCIE base address - // Arg1 -> Bus - // Arg2 -> Device - // Arg3 -> Function - // Arg4 -> Register offset - // Arg5 -> Data - // Return: Nothing - // - Method(PEWB,6,Serialized) - { - ADBG("PEWB") - - Store(Arg0, Local7) - Or(Local7, ShiftLeft(Arg1, 20), Local7) - Or(Local7, ShiftLeft(Arg2, 15), Local7) - Or(Local7, ShiftLeft(Arg3, 12), Local7) - Or(Local7, Arg4, Local7) - - OperationRegion(PCI0, SystemMemory, Local7, 1) - Field(PCI0, ByteAcc,NoLock,Preserve) - { - TEMP, 8 - } - - Store(Arg5,TEMP) - } // End of Method(PEWB,6,Serialized) - - // - // Name: PERW - // Description: Function to read a Word from PCIE-MMIO - // Input: Arg0 -> PCIE base address - // Arg1 -> Bus - // Arg2 -> Device - // Arg3 -> Function - // Arg4 -> Register offset - // Return: Word data read from PCIE-MMIO - // - Method(PERW,5,Serialized) - { - ADBG("PERW") - - Store(Arg0, Local7) - Or(Local7, ShiftLeft(Arg1, 20), Local7) - Or(Local7, ShiftLeft(Arg2, 15), Local7) - Or(Local7, ShiftLeft(Arg3, 12), Local7) - Or(Local7, Arg4, Local7) - - OperationRegion(PCI0, SystemMemory, Local7, 2) - Field(PCI0, ByteAcc,NoLock,Preserve) - { - TEMP, 16 - } - - Return(TEMP) - } // End of Method(PERW,5,Serialized) - - // - // Name: PEWW - // Description: Function to write a Word into PCIE-MMIO - // Input: Arg0 -> PCIE base address - // Arg1 -> Bus - // Arg2 -> Device - // Arg3 -> Function - // Arg4 -> Register offset - // Arg5 -> Data - // Return: Nothing - // - Method(PEWW,6,Serialized) - { - ADBG("PEWW") - - Store(Arg0, Local7) - Or(Local7, ShiftLeft(Arg1, 20), Local7) - Or(Local7, ShiftLeft(Arg2, 15), Local7) - Or(Local7, ShiftLeft(Arg3, 12), Local7) - Or(Local7, Arg4, Local7) - - OperationRegion(PCI0, SystemMemory, Local7, 2) - Field(PCI0, ByteAcc,NoLock,Preserve) - { - TEMP, 16 - } - - Store(Arg5,TEMP) - } // End of Method(PEWW,6,Serialized) - - // - // Name: PERD - // Description: Function to read a Dword from PCIE-MMIO - // Input: Arg0 -> PCIE base address - // Arg1 -> Bus - // Arg2 -> Device - // Arg3 -> Function - // Arg4 -> Register offset - // Return: Dword data read from PCIE-MMIO - // - Method(PERD,5,Serialized) - { - ADBG("PERD") - - Store(Arg0, Local7) - Or(Local7, ShiftLeft(Arg1, 20), Local7) - Or(Local7, ShiftLeft(Arg2, 15), Local7) - Or(Local7, ShiftLeft(Arg3, 12), Local7) - Or(Local7, Arg4, Local7) - - OperationRegion(PCI0, SystemMemory, Local7, 4) - Field(PCI0, ByteAcc,NoLock,Preserve) - { - TEMP, 32 - } - - Return(TEMP) - } // End of Method(PERD,5,Serialized) - - // - // Name: PEWD - // Description: Function to write a Dword into PCIE-MMIO - // Input: Arg0 -> PCIE base address - // Arg1 -> Bus - // Arg2 -> Device - // Arg3 -> Function - // Arg4 -> Register offset - // Arg5 -> Data - // Return: Nothing - // - Method(PEWD,6,Serialized) - { - ADBG("PEWD") - - Store(Arg0, Local7) - Or(Local7, ShiftLeft(Arg1, 20), Local7) - Or(Local7, ShiftLeft(Arg2, 15), Local7) - Or(Local7, ShiftLeft(Arg3, 12), Local7) - Or(Local7, Arg4, Local7) - - OperationRegion(PCI0, SystemMemory, Local7, 4) - Field(PCI0, ByteAcc,NoLock,Preserve) - { - TEMP, 32 - } - - Store(Arg5,TEMP) - } // End of Method(PEWD,6,Serialized) - - // - // Name: STDC - // Description: Function to get Standard Capability Register Offset - // Input: Arg0 -> PCIE base address - // Arg1 -> Bus - // Arg2 -> Device - // Arg3 -> Function - // Arg4 -> Capability ID - // Return: Capability Register Offset data - // - Method(STDC,5,Serialized) - { - ADBG("STDC") - - //Check for Referenced device is present or not - Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID regist= er - If(LEqual(Local7, 0xFFFF)) - { - ADBG("Referenced device is not present") - Return(0) - } - - Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status re= gister - If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List - { - //No Capabilities linked list is available - ADBG("No Capabilities linked list is available") - Return(0) - } - - //Local1 is for storing CapabilityID - //Local2 is for storing CapabilityPtr - Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr - - While(1) - { - And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned - - If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate= the last capability in the list - { - ADBG("Capability ID is not found") - Return(0) - } - - Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID - - If(LEqual(Arg4, Local1)) //CapabilityID match - { - ADBG("Capability ID is found") - ADBG("Capability Offset : ") - ADBG(Local2) - Return(Local2) - } - Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //Capa= bilityPtr - Return(0) - } - } // End of Method(STDC,5,Serialized) - -} // End Scope(\_SB) diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/Tbt= Nvs.asl b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs= .asl deleted file mode 100644 index 706796f8c5..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include/Acpi/TbtNvs.asl +++ /dev/null @@ -1,56 +0,0 @@ -/**@file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - // - // Define TBT NVS Area operation region. - // - OperationRegion(BNVS,SystemMemory,TNVB,TNVL) - Field(BNVS,AnyAcc,Lock,Preserve) - { Offset(0), TBSF, 8, // Offset(0), Thunderbolt(TM) SMI Funct= ion Number - Offset(1), SOHP, 8, // Offset(1), SMI on Hot Plug for TBT devi= ces - Offset(2), TWIN, 8, // Offset(2), TbtWin10Support - Offset(3), GP5F, 8, // Offset(3), Gpio filter to detect USB Ho= tplug event - Offset(4), NOHP, 8, // Offset(4), Notify on Hot Plug for TBT d= evices - Offset(5), TBSE, 8, // Offset(5), Thunderbolt(TM) Root port se= lector - Offset(6), WKFN, 8, // Offset(6), WAK Finished - Offset(7), TBTS, 8, // Offset(7), Thunderbolt(TM) support - Offset(8), TARS, 8, // Offset(8), TbtAcpiRemovalSupport - Offset(9), FPEN, 32, // Offset(9), TbtFrcPwrEn - Offset(13), FPG0, 32, // Offset(13), TbtFrcPwrGpioNo - Offset(17), FP0L, 8, // Offset(17), TbtFrcPwrGpioLevel - Offset(18), CPG0, 32, // Offset(18), TbtCioPlugEventGpioNo - Offset(22), RSG0, 32, // Offset(22), TbtPcieRstGpioNo - Offset(26), RS0L, 8, // Offset(26), TbtPcieRstGpioLevel - Offset(27), DTCP, 8, // Offset(27), Current Port that has plug e= vent - Offset(28), RPS0, 8, // Offset(28), Root port Selected by the Us= er - Offset(29), RPT0, 8, // Offset(29), Root port Type - Offset(30), RPS1, 8, // Offset(30), Root port Selected by the Us= er - Offset(31), RPT1, 8, // Offset(31), Root port Type - Offset(32), RPN0, 8, // Offset(32), Root port Enabled by the Use= r - Offset(33), RPN1, 8, // Offset(33), Root port Enabled by the Use= r - Offset(34), FPG1, 32, // Offset(34), TbtFrcPwrGpioNo - Offset(38), FP1L, 8, // Offset(38), TbtFrcPwrGpioLevel - Offset(39), CPG1, 32, // Offset(39), TbtCioPlugEventGpioNo - Offset(43), RSG1, 32, // Offset(43), TbtPcieRstGpioNo - Offset(47), RS1L, 8, // Offset(47), TbtPcieRstGpioLevel - Offset(48), CGST, 8, // Offset(48), Set if Single GPIO is used f= or Multi/Different Controller Hot plug support - Offset(49), DTPT, 8, // Offset(49), Root Port type for which SCI= Triggered - Offset(50), TRWA, 8, // Offset(50), Titan Ridge Osup command - Offset(51), ACDC, 8, // Offset(51), TBT Dynamic AcDc L1 - Offset(52), DT0E, 8, // Offset(52), DTbtController0 is enabled o= r not. - Offset(53), DT1E, 8, // Offset(53), DTbtController1 is enabled o= r not. - Offset(54), TASP, 8, // Offset(54), ASPM setting for all the PCI= e device in TBT daisy chain. - Offset(55), TL1S, 8, // Offset(55), L1 SubState for for all the = PCIe device in TBT daisy chain. - Offset(56), TCLK, 8, // Offset(56), CLK REQ for all the PCIe dev= ice in TBT daisy chain. - Offset(57), TLTR, 8, // Offset(57), LTR for for all the PCIe dev= ice in TBT daisy chain. - Offset(58), TPTM, 8, // Offset(58), PTM for for all the PCIe dev= ice in TBT daisy chain. - Offset(59), TWAK, 8, // Offset(59), Send Go2SxNoWake or GoSxWake= according to TbtWakeupSupport - Offset(60), TBOD, 16, // Offset(60), Rtd3TbtOffDelay TBT RTD3 Off= Delay - Offset(62), TSXW, 8, // Offset(62), TbtSxWakeSwitchLogicEnable S= et True if TBT_WAKE_N will be routed to PCH WakeB at Sx entry point. HW log= ic is required. - Offset(63), RTBT, 8, // Offset(63), Enable Rtd3 support for TBT.= Corresponding to Rtd3Tbt in Setup. - Offset(64), RTBC, 8, // Offset(64), Enable TBT RTD3 CLKREQ mask. - Offset(65), TBCD, 16, // Offset(65), TBT RTD3 CLKREQ mask delay. - } \ No newline at end of file diff --git a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl b/= Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl deleted file mode 100644 index e3b0a1da85..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl +++ /dev/null @@ -1,114 +0,0 @@ -/** @file - ACPI DSDT table - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - - // Define a Global region of ACPI NVS Region that may be used for any - // type of implementation. The starting offset and size will be fixed - // up by the System BIOS during POST. Note that the Size must be a word - // in size to be fixed up correctly. - - - - - OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) - Field(GNVS,AnyAcc,Lock,Preserve) - { - // - // Miscellaneous Dynamic Registers: - // - Offset(0), OSYS, 16, // Offset(0), Operating System - Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SM= I via I/O Trap) - Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value - Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode =3D 1) - // - // Thermal Policy Registers: - // - Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable - Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call - // - // CPU Identification Registers: - // - Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC = Enabled =3D 1) - Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads - // - // PCIe Hot Plug - // - Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control - Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value - // - // Global Variables - // - Offset(14), DSEN, 8, // Offset(14), _DOS Display Support Flag. - Offset(15), GPIC, 8, // Offset(15), Global IOAPIC/8259 Interrupt= Mode Flag. - Offset(16), L01C, 8, // Offset(16), Global L01 Counter. - Offset(17), LTR1, 8, // Offset(17), Latency Tolerance Reporting = Enable - Offset(18), LTR2, 8, // Offset(18), Latency Tolerance Reporting = Enable - Offset(19), LTR3, 8, // Offset(19), Latency Tolerance Reporting = Enable - Offset(20), LTR4, 8, // Offset(20), Latency Tolerance Reporting = Enable - Offset(21), LTR5, 8, // Offset(21), Latency Tolerance Reporting = Enable - Offset(22), LTR6, 8, // Offset(22), Latency Tolerance Reporting = Enable - Offset(23), LTR7, 8, // Offset(23), Latency Tolerance Reporting = Enable - Offset(24), LTR8, 8, // Offset(24), Latency Tolerance Reporting = Enable - Offset(25), LTR9, 8, // Offset(25), Latency Tolerance Reporting = Enable - Offset(26), LTRA, 8, // Offset(26), Latency Tolerance Reporting = Enable - Offset(27), LTRB, 8, // Offset(27), Latency Tolerance Reporting = Enable - Offset(28), LTRC, 8, // Offset(28), Latency Tolerance Reporting = Enable - Offset(29), LTRD, 8, // Offset(29), Latency Tolerance Reporting = Enable - Offset(30), LTRE, 8, // Offset(30), Latency Tolerance Reporting = Enable - Offset(31), LTRF, 8, // Offset(31), Latency Tolerance Reporting = Enable - Offset(32), LTRG, 8, // Offset(32), Latency Tolerance Reporting = Enable - Offset(33), LTRH, 8, // Offset(33), Latency Tolerance Reporting = Enable - Offset(34), LTRI, 8, // Offset(34), Latency Tolerance Reporting = Enable - Offset(35), LTRJ, 8, // Offset(35), Latency Tolerance Reporting = Enable - Offset(36), LTRK, 8, // Offset(36), Latency Tolerance Reporting = Enable - Offset(37), LTRL, 8, // Offset(37), Latency Tolerance Reporting = Enable - Offset(38), LTRM, 8, // Offset(38), Latency Tolerance Reporting = Enable - Offset(39), LTRN, 8, // Offset(39), Latency Tolerance Reporting = Enable - Offset(40), LTRO, 8, // Offset(40), Latency Tolerance Reporting = Enable - Offset(41), OBF1, 8, // Offset(41), Optimized Buffer Flush and F= ill - Offset(42), OBF2, 8, // Offset(42), Optimized Buffer Flush and F= ill - Offset(43), OBF3, 8, // Offset(43), Optimized Buffer Flush and F= ill - Offset(44), OBF4, 8, // Offset(44), Optimized Buffer Flush and F= ill - Offset(45), OBF5, 8, // Offset(45), Optimized Buffer Flush and F= ill - Offset(46), OBF6, 8, // Offset(46), Optimized Buffer Flush and F= ill - Offset(47), OBF7, 8, // Offset(47), Optimized Buffer Flush and F= ill - Offset(48), OBF8, 8, // Offset(48), Optimized Buffer Flush and F= ill - Offset(49), OBF9, 8, // Offset(49), Optimized Buffer Flush and F= ill - Offset(50), OBFA, 8, // Offset(50), Optimized Buffer Flush and F= ill - Offset(51), OBFB, 8, // Offset(51), Optimized Buffer Flush and F= ill - Offset(52), OBFC, 8, // Offset(52), Optimized Buffer Flush and F= ill - Offset(53), OBFD, 8, // Offset(53), Optimized Buffer Flush and F= ill - Offset(54), OBFE, 8, // Offset(54), Optimized Buffer Flush and F= ill - Offset(55), OBFF, 8, // Offset(55), Optimized Buffer Flush and F= ill - Offset(56), OBFG, 8, // Offset(56), Optimized Buffer Flush and F= ill - Offset(57), OBFH, 8, // Offset(57), Optimized Buffer Flush and F= ill - Offset(58), OBFI, 8, // Offset(58), Optimized Buffer Flush and F= ill - Offset(59), OBFJ, 8, // Offset(59), Optimized Buffer Flush and F= ill - Offset(60), OBFK, 8, // Offset(60), Optimized Buffer Flush and F= ill - Offset(61), OBFL, 8, // Offset(61), Optimized Buffer Flush and F= ill - Offset(62), OBFM, 8, // Offset(62), Optimized Buffer Flush and F= ill - Offset(63), OBFN, 8, // Offset(63), Optimized Buffer Flush and F= ill - Offset(64), OBFO, 8, // Offset(64), Optimized Buffer Flush and F= ill - Offset(65), RTD3, 8, // Offset(65), Runtime D3 support. - Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable - Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify S= leep State Change - Offset(68), PSCP, 8, // Offset(68), P-state Capping - Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable - Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse Enabl= e - // - // Driver Mode - // - Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ - Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering = CS - Offset(76), PLVL, 16, // Offset(76), PL1 limit value - Offset(78), PB1E, 8, // Offset(78), 10sec Power button support - Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr - Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support - Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug - Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port se= lector - Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port se= lector - } diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg deleted file mode 100644 index 3edc2b14e8..0000000000 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/build_config.cfg +++ /dev/null @@ -1,33 +0,0 @@ -# @ build_config.cfg -# This is the N1xxWU board specific build settings -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# SPDX-License-Identifier: BSD-2-Clause-Patent -# - - -[CONFIG] -WORKSPACE_PLATFORM_BIN =3D edk2-non-osi/Platform/Intel/ClevoOpenBoardBinPk= g -EDK_SETUP_OPTION =3D -openssl_path =3D -PLATFORM_BOARD_PACKAGE =3D ClevoOpenBoardPkg -PROJECT =3D ClevoOpenBoardPkg/N1xxWU -BOARD =3D N1xxWU -FLASH_MAP_FDF =3D ClevoOpenBoardPkg/N1xxWU/Include/Fdf/FlashMapInclude.fdf -PROJECT_DSC =3D ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc -BOARD_PKG_PCD_DSC =3D ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc -PrepRELEASE =3D DEBUG -SILENT_MODE =3D FALSE -EXT_CONFIG_CLEAR =3D -CapsuleBuild =3D FALSE -EXT_BUILD_FLAGS =3D -CAPSULE_BUILD =3D 0 -TARGET =3D DEBUG -TARGET_SHORT =3D D -PERFORMANCE_BUILD =3D FALSE -FSP_WRAPPER_BUILD =3D TRUE -FSP_BIN_PKG =3D KabylakeFspBinPkg -FSP_PKG_NAME =3D KabylakeFspPkg -FSP_BINARY_BUILD =3D FALSE -FSP_TEST_RELEASE =3D FALSE -SECURE_BOOT_ENABLE =3D FALSE --=20 2.16.2.windows.1