From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: nathaniel.l.desimone@intel.com) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Mon, 23 Sep 2019 01:16:02 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Sep 2019 01:16:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="388405104" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by fmsmga005.fm.intel.com with ESMTP; 23 Sep 2019 01:16:01 -0700 Received: from orsmsx156.amr.corp.intel.com (10.22.240.22) by ORSMSX103.amr.corp.intel.com (10.22.225.130) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 23 Sep 2019 01:16:01 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.55]) by ORSMSX156.amr.corp.intel.com ([169.254.8.15]) with mapi id 14.03.0439.000; Mon, 23 Sep 2019 01:16:00 -0700 From: "Nate DeSimone" To: "Kubacki, Michael A" , "devel@edk2.groups.io" CC: "Chiu, Chasel" , "Sinha, Ankit" , Jeremy Soller Subject: Re: [edk2-platforms][PATCH V1 10/12] KabylakeOpenBoardPkg/GalagoPro3: Add modules Thread-Topic: [edk2-platforms][PATCH V1 10/12] KabylakeOpenBoardPkg/GalagoPro3: Add modules Thread-Index: AQHVb+MGr75vdaW4zE2dxfTEzgp6AKc47igQ Date: Mon, 23 Sep 2019 08:15:59 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEF0A706@ORSMSX114.amr.corp.intel.com> References: <20190920184030.6148-1-michael.a.kubacki@intel.com> <20190920184030.6148-11-michael.a.kubacki@intel.com> In-Reply-To: <20190920184030.6148-11-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTRjN2IxNjctNDQ1Yy00NGQzLTg4Y2MtNDczODI5ZTAzNjBkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZXNTc2VBQXo1eGw5czBuMkY5Q2R3R3dJSk9NMEhScHpBZ2RiRWRSMDlZbDhQdTRQd2hmUHdEWXdHaTJjVFdrdCJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I would like us to re-evaluate whether an override of PlatformInitPreMem is= really needed... but I understand that is not in scope for this patch seri= es. Reviewed-by: Nate DeSimone -----Original Message----- From: Kubacki, Michael A =20 Sent: Friday, September 20, 2019 11:40 AM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L ; Sinha, Ankit ; Jeremy Soller = Subject: [edk2-platforms][PATCH V1 10/12] KabylakeOpenBoardPkg/GalagoPro3: = Add modules REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2207 Adds the modules used for System 76 Galago Pro 3 board support. This override should be removed in a future cleanup change. That is outside= the scope of this change which is to move the contents from ClevoOpenBoard= Pkg/N1xxWU to KabylakeOpenBoardPkg/GalagoPro3. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Ankit Sinha Cc: Jeremy Soller Signed-off-by: Michael Kubacki --- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/Min= PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 ++ Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/Min= PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 +++++= +++++++++++++++ 2 files changed, 707 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platfo= rm/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf= b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/M= inPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf new file mode 100644 index 0000000000..76dd67d1a8 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/I +++ ntel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem. +++ inf @@ -0,0 +1,67 @@ +### @file +# Component information file for the Platform Init Pre-Memory PEI module. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# #=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PlatformInitPreMem + FILE_GUID =3D EEEE611D-F78F-4FB9-B868-55907F169280 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D PlatformInitPreMemEntryPoint + +[LibraryClasses] + BaseMemoryLib + BoardInitLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + MtrrLib + PeimEntryPoint + PeiServicesLib + ReportFvLib + TestPointCheckLib + TimerLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CO= NSUMES + +[Sources] + PlatformInitPreMem.c + +[Ppis] + gEfiPeiMemoryDiscoveredPpiGuid + gEfiPeiMasterBootModePpiGuid ## PRODUCES + gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES + gEfiPeiReadOnlyVariable2PpiGuid + gPeiBaseMemoryTestPpiGuid + gPeiPlatformMemorySizePpiGuid + +[Guids] + gEfiMemoryTypeInformationGuid + +[Depex] + gEfiPeiReadOnlyVariable2PpiGuid diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platfo= rm/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b= /Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/Min= PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c new file mode 100644 index 0000000000..b784026c1b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/I +++ ntel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem. +++ c @@ -0,0 +1,640 @@ +/** @file + Source code file for Platform Init Pre-Memory PEI module + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include=20 + #include + +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +EFI_STATUS +EFIAPI +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize + ); + +/** + + This function checks the memory range in PEI. + + @param PeiServices Pointer to PEI Services. + @param This Pei memory test PPI pointer. + @param BeginAddress Beginning of the memory address to be checked. + @param MemoryLength Bytes of memory range to be checked. + @param Operation Type of memory check operation to be performed. + @param ErrorAddress Return the address of the error memory address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. + +**/ +EFI_STATUS +EFIAPI +BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress + ); + +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |=20 +EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback }; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR=20 +mPpiListRecoveryBootMode =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiBootInRecoveryModePpiGuid, + NULL +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMasterBootModePpiGuid, + NULL +}; + +static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi =3D { BaseMemory= Test }; + +static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi =3D {=20 +GetPlatformMemorySize }; + +static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gPeiBaseMemoryTestPpiGuid, + &mPeiBaseMemoryTestPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiPlatformMemorySizePpiGuid, + &mMemoryMemorySizePpi + }, +}; + +/// +/// Memory Reserved should be between 125% to 150% of the Current=20 +required memory /// otherwise BdsMisc.c would do a reset to make it 125% t= o avoid s4 resume issues. +/// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { + { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL + { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) + { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) + { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)= }, // Runtime Service Data + { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)= }, // Runtime Service Code + { EfiMaxMemoryType, 0 } +}; + +VOID +BuildMemoryTypeInformation ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; + + // + // Locate system configuration variable // Status =3D=20 + PeiServicesLocatePpi( + &gEfiPeiReadOnlyVariable2PpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + (VOID **) &VariableServices // PPI + ); + ASSERT_EFI_ERROR(Status); + + DataSize =3D sizeof (MemoryData); + Status =3D VariableServices->GetVariable ( + VariableServices, + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + if (EFI_ERROR(Status)) { + DataSize =3D sizeof (mDefaultMemoryTypeInformation); + CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize); } + + /// + /// Build the GUID'd HOB for DXE + /// + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + MemoryData, + DataSize + ); +} + +EFI_STATUS +EFIAPI +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; + UINTN Index; + EFI_BOOT_MODE BootMode; + UINTN IndexNumber; + +#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x1= 00000)) + + *MemorySize =3D PEI_MIN_MEMORY_SIZE; + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **)&Variable + ); + + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR=20 + (Status); + + DataSize =3D sizeof (MemoryData); + + Status =3D Variable->GetVariable ( + Variable, + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + IndexNumber =3D sizeof (mDefaultMemoryTypeInformation) / sizeof=20 + (EFI_MEMORY_TYPE_INFORMATION); + + // + // Accumulate maximum amount of memory needed // + + DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n",=20 + DivU64x32(*MemorySize,1024))); DEBUG((DEBUG_ERROR, "IndexNumber:%d=20 + MemoryDataNumber%d \n", IndexNumber,DataSize/ sizeof (EFI_MEMORY_TYPE_INF= ORMATION))); if (EFI_ERROR (Status)) { + // + // Start with minimum memory + // + for (Index =3D 0; Index < IndexNumber; Index++) { + DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformat= ion[Index].NumberOfPages)); + *MemorySize +=3D mDefaultMemoryTypeInformation[Index].NumberOfPages = * EFI_PAGE_SIZE; + } + DEBUG((DEBUG_ERROR, "No memory type, Total platform memory:%dKB=20 + \n", DivU64x32(*MemorySize,1024))); } else { + // + // Start with at least 0x200 pages of memory for the DXE Core and the = DXE Stack + // + for (Index =3D 0; Index < IndexNumber; Index++) { + DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages)); + *MemorySize +=3D MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; + + } + DEBUG((DEBUG_ERROR, "has memory type, Total platform memory:%dKB=20 + \n", DivU64x32(*MemorySize,1024))); } + + return EFI_SUCCESS; +} + +/** + + This function checks the memory range in PEI. + + @param PeiServices Pointer to PEI Services. + @param This Pei memory test PPI pointer. + @param BeginAddress Beginning of the memory address to be checked. + @param MemoryLength Bytes of memory range to be checked. + @param Operation Type of memory check operation to be performed. + @param ErrorAddress Return the address of the error memory address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. + +**/ +EFI_STATUS +EFIAPI +BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress + ) +{ + UINT32 TestPattern; + UINT32 SpanSize; + EFI_PHYSICAL_ADDRESS TempAddress; + +#define MEMORY_TEST_PATTERN 0x5A5A5A5A +#define MEMORY_TEST_COVER_SPAN 0x40000 + + TestPattern =3D MEMORY_TEST_PATTERN; + SpanSize =3D 0; + + // + // Make sure we don't try and test anything above the max physical=20 + address range // ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS); + + switch (Operation) { + case Extensive: + SpanSize =3D 0x4; + break; + + case Sparse: + case Quick: + SpanSize =3D MEMORY_TEST_COVER_SPAN; + break; + + case Ignore: + goto Done; + break; + } + // + // Write the test pattern into memory range // TempAddress =3D=20 + BeginAddress; while (TempAddress < BeginAddress + MemoryLength) { + (*(UINT32 *) (UINTN) TempAddress) =3D TestPattern; + TempAddress +=3D SpanSize; + } + // + // Read pattern from memory and compare it // TempAddress =3D=20 + BeginAddress; while (TempAddress < BeginAddress + MemoryLength) { + if ((*(UINT32 *) (UINTN) TempAddress) !=3D TestPattern) { + *ErrorAddress =3D TempAddress; + return EFI_DEVICE_ERROR; + } + + TempAddress +=3D SpanSize; + } + +Done: + + return EFI_SUCCESS; +} + +/** + Set Cache Mtrr. +**/ +VOID +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + MTRR_SETTINGS MtrrSetting; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + EFI_BOOT_MODE BootMode; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + UINT64 CacheMemoryLength; + + /// + /// Reset all MTRR setting. + /// + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + /// + /// Cache the Flash area as WP to boost performance /// Status =3D=20 + MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to=20 + boost performance /// MtrrSetAllMtrrs (&MtrrSetting); + + /// + /// Set low to 1 MB. Since 1MB cacheability will always be set ///=20 + until override by CSM. + /// Initialize high memory to 0. + /// + LowMemoryLength =3D 0x100000; + HighMemoryLength =3D 0; + ResourceAttribute =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + Status =3D PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR=20 + (Status); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; } + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); while=20 + (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || + ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) + ) { + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n",=20 + LowMemoryLength)); DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D=20 + %lx.\n", HighMemoryLength)); + + /// + /// Assume size of main memory is multiple of 256MB /// =20 + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; MemoryBase= =20 + =3D 0; + + CacheMemoryLength =3D MemoryLength; + /// + /// Programming MTRRs to avoid override SPI region with UC when MAX=20 + TOLUD Length >=3D 3.5GB /// if (MemoryLength > 0xDC000000) { + CacheMemoryLength =3D 0xC0000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xC0000000; + CacheMemoryLength =3D MemoryLength - 0xC0000000; + if (MemoryLength > 0xE0000000) { + CacheMemoryLength =3D 0x20000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xE0000000; + CacheMemoryLength =3D MemoryLength - 0xE0000000; + } + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + if (LowMemoryLength !=3D MemoryLength) { + MemoryBase =3D LowMemoryLength; + MemoryLength -=3D LowMemoryLength; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + MemoryLength, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } + + /// + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC /// Status =3D=20 + MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer /// MtrrSetAllMtrrs=20 + (&MtrrSetting); + + return ; +} + +VOID +ReportCpuHob ( + VOID + ) +{ + UINT8 PhysicalAddressBits; + UINT32 RegEax; + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >=3D=20 + 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits =3D (UINT8) RegEax; } else { + PhysicalAddressBits =3D 36; + } + + /// + /// Create a CPU hand-off information + /// + BuildCpuHob (PhysicalAddressBits, 16); } + +/** + Install Firmware Volume Hob's once there is main memory + + @param[in] PeiServices General purpose services available to ever= y PEIM. + @param[in] NotifyDescriptor Notify that this module published. + @param[in] Ppi PPI that was installed. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + Status =3D BoardInitAfterMemoryInit (); ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR=20 + (Status); + + + ReportCpuHob (); + + TestPointMemoryDiscoveredMtrrFunctional (); + + TestPointMemoryDiscoveredMemoryResourceFunctional (); + + /// + /// If S3 resume, then we are done + /// + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + return EFI_SUCCESS; + } + + TestPointMemoryDiscoveredDmaProtectionEnabled (); + + if (PcdGetBool (PcdStopAfterMemInit)) { + CpuDeadLoop (); + } + + return Status; +} + + +/** + This function handles PlatformInit task after PeiReadOnlyVariable2=20 +PPI produced + + @param[in] PeiServices Pointer to PEI Services Table. + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ +EFI_STATUS +EFIAPI +PlatformInitPreMem ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + // + // Start board detection + // + BoardDetect (); + + BoardDebugInit (); + + TestPointDebugInitDone (); + + if (PcdGetBool (PcdStopAfterDebugInit)) { + CpuDeadLoop (); + } + + BootMode =3D BoardBootModeDetect (); + Status =3D PeiServicesSetBootMode (BootMode); ASSERT_EFI_ERROR=20 + (Status); if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { + Status =3D PeiServicesInstallPpi (&mPpiListRecoveryBootMode); } /// = =20 + /// Signal possible dependent modules that there has been a /// final=20 + boot mode determination, it is used to build BIST /// Hob for Dxe=20 + use. + /// + Status =3D PeiServicesInstallPpi (&mPpiBootMode); ASSERT_EFI_ERROR=20 + (Status); + + BuildMemoryTypeInformation (); + + if (!PcdGetBool(PcdFspWrapperBootMode)) { + Status =3D PeiServicesInstallPpi (mMemPpiList); + ASSERT_EFI_ERROR (Status); + } + + Status =3D BoardInitBeforeMemoryInit (); ASSERT_EFI_ERROR (Status); + + return Status; +} + + +/** + Platform Init before memory PEI module entry point + + @param[in] FileHandle Not used. + @param[in] PeiServices General purpose services available to e= very PEIM. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +PlatformInitPreMemEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + Status =3D PlatformInitPreMem (PeiServices); + + /// + /// After code reorangized, memorycallback will run because the PPI=20 + is already /// installed when code run to here, it is supposed that=20 + the InstallEfiMemory is /// done before. + /// + Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList); + + return Status; +} -- 2.16.2.windows.1