From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.5960.1570768379548673507 for ; Thu, 10 Oct 2019 21:32:59 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Oct 2019 21:32:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,282,1566889200"; d="scan'208";a="188188304" Received: from orsmsx107.amr.corp.intel.com ([10.22.240.5]) by orsmga008.jf.intel.com with ESMTP; 10 Oct 2019 21:32:59 -0700 Received: from orsmsx125.amr.corp.intel.com (10.22.240.125) by ORSMSX107.amr.corp.intel.com (10.22.240.5) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 10 Oct 2019 21:32:58 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.55]) by ORSMSX125.amr.corp.intel.com ([169.254.3.216]) with mapi id 14.03.0439.000; Thu, 10 Oct 2019 21:32:58 -0700 From: "Nate DeSimone" To: "devel@edk2.groups.io" , "Kubacki, Michael A" CC: "Chiu, Chasel" Subject: Re: [edk2-devel] [edk2-platforms][PATCH V1 12/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: DSC cleanup Thread-Topic: [edk2-devel] [edk2-platforms][PATCH V1 12/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: DSC cleanup Thread-Index: AQHVfZerKLQc5/UfP0O+79mNv2gaP6dU3rWg Date: Fri, 11 Oct 2019 04:32:57 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AAEF4CEDF@ORSMSX114.amr.corp.intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> <20191008051645.22052-13-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-13-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjI5NDA1ZjItMjgxYy00Yjg3LWFkMWMtYTU4MDA1ZGFhMmM0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiSlwvaUI5UHBRdlFhREswbWNKU2h2M09EKzl1OHI1eG43M3RYejNuTDJRNFlTMmhyZnFHZ2tCd0cwNkY1ZXdRUkcifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: devel@edk2.groups.io On Behalf Of Kubacki, Mi= chael A Sent: Monday, October 7, 2019 10:17 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L Subject: [edk2-devel] [edk2-platforms][PATCH V1 12/17] WhiskeylakeOpenBoar= dPkg/WhiskeylakeURvp: DSC cleanup REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2243 This change refactors OpenBoardPkg.dsc and OpenBoardPkgPcd.dsc to consolidate redundant sections and better group file content to improve maintainability and readability. The same pattern made in this change for WhiskeylakeURvp is being applied to all existing board packages in Platform/Intel to improve overall consistency. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc = | 502 +++++++++++--------- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.ds= c | 441 +++++++++-------- 2 files changed, 510 insertions(+), 433 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBo= ardPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc index 1d07fdea84..d6eb66a880 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.= dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.= dsc @@ -1,20 +1,13 @@ ## @file -# Platform description. -# +# The main build description file for the WhiskeylakeURvp board. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # -# ## =20 [Defines] - # - # Set platform specific package/folder name, same as passed from PREBUI= LD script. - # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as packag= e build folder - # DEFINE only takes effect at R9 DSC and FDF. - # DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE =3D CoffeelakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE =3D CoffeelakeSiliconBinPkg @@ -24,7 +17,7 @@ DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(B= OARD) =20 # - # Platform On/Off features are defined here + # Include PCD configuration for this board. # !include OpenBoardPkgPcd.dsc =20 @@ -42,8 +35,6 @@ SUPPORTED_ARCHITECTURES =3D IA32|X64 BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D ALL - - FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf =20 FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 @@ -56,163 +47,238 @@ =20 #########################################################################= ####### # -# SKU Identification section - list of all SKU IDs supported by this -# Platform. +# SKU Identification section - list of all SKU IDs supported by this boar= d. # #########################################################################= ####### [SkuIds] - 0|DEFAULT # The entry: 0|DEFAULT is reserved and always re= quired. + 0|DEFAULT # 0|DEFAULT is reserved and always required. 0x60|WhiskeylakeURvp =20 #########################################################################= ####### # -# Library Class section - list of all Library Classes needed by this Plat= form. +# Includes section - other DSC file contents included for this board buil= d. # #########################################################################= ####### =20 - !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc - !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc - !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +####################################### +# Library Includes +####################################### +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +####################################### +# Component Includes +####################################### +[Components.IA32] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +[Components.X64] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + +####################################### +# Build Option Includes +####################################### +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc +!include OpenBoardPkgBuildOption.dsc + +#########################################################################= ####### +# +# Library Class section - list of all Library Classes needed by this boar= d. +# +#########################################################################= ####### =20 [LibraryClasses.common] - - PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/Pei= ReportFvLib.inf - - PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple= /PciHostBridgeLibSimple.inf - PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimp= le/PciSegmentInfoLibSimple.inf - PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootM= anagerLib/DxePlatformBootManagerLib.inf - I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAc= cessLib.inf - GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/B= aseGpioExpanderLib.inf - - PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHook= Lib.inf - - FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWr= apperHobProcessLib/PeiFspWrapperHobProcessLib.inf - PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecFspWrapperPlatformSecLib.inf - + ####################################### + # Edk2 Packages + ####################################### FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseF= spWrapperApiLib.inf FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLi= b/PeiFspWrapperApiTestLib.inf =20 - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrap= perPlatformLib/PeiFspWrapperPlatformLib.inf - SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf - + ####################################### + # Silicon Initialization Package + ####################################### ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCo= nfigBlockLib.inf - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/= BoardInitLibNull.inf - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNul= l/TestPointCheckLibNull.inf - - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmm= TbtCommonLib/TbtCommonLib.inf - !endif - DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPo= licyLib/DxeTbtPolicyLib.inf - # - # Silicon Init Package - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc - PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDx= eSmmPchHsioLib.inf MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPc= iLib.inf + PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDx= eSmmPchHsioLib.inf PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeS= mmPchPmcLib.inf =20 - TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLi= b.inf - -[LibraryClasses.IA32] - # - # PEI phase common - # - SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFs= pPolicyInitLib/PeiFspPolicyInitLib.inf + ##################################### + # Platform Package + ##################################### + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/= BoardInitLibNull.inf + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWr= apperHobProcessLib/PeiFspWrapperHobProcessLib.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrap= perPlatformLib/PeiFspWrapperPlatformLib.inf - !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/= PeiTestPointCheckLib.inf - !endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPoint= Lib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Multi= BoardInitSupportLib/PeiMultiBoardInitSupportLib.inf - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup= portLib/PeiMultiBoardInitSupportLib.inf - TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLi= b.inf + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple= /PciHostBridgeLibSimple.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimp= le/PciSegmentInfoLibSimple.inf + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootM= anagerLib/DxePlatformBootManagerLib.inf + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/Pei= ReportFvLib.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNul= l/TestPointCheckLibNull.inf + + ####################################### + # Board Package + ####################################### + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/B= aseGpioExpanderLib.inf HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/Pe= iHdaVerbTableLib.inf + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAc= cessLib.inf + PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecFspWrapperPlatformSecLib.inf + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLi= b.inf + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTb= tCommonLib/TbtCommonLib.inf +!endif =20 - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbt= PolicyLib/PeiTbtPolicyLib.inf - PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private= /PeiDTbtInitLib/PeiDTbtInitLib.inf - !endif - - # - # Silicon Init Package - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc - PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyIn= itLib/PeiPolicyInitLib.inf - PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/Pe= iPolicyBoardConfigLib.inf - PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicy= UpdateLib/PeiPolicyUpdateLib.inf - PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformH= ooklib.inf - !if $(TARGET) =3D=3D DEBUG - GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/Base= GpioCheckConflictLib.inf - !else - GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/= BaseGpioCheckConflictLibNull.inf - !endif + ####################################### + # Board-specific + ####################################### + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHook= Lib.inf =20 [LibraryClasses.IA32.SEC] + ####################################### + # Platform Package + ####################################### TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Se= cTestPointCheckLib.inf SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLi= bNull/SecBoardInitLibNull.inf + + ####################################### + # Board Package + ####################################### + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFs= pPolicyInitLib/PeiFspPolicyInitLib.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLi= b.inf + +[LibraryClasses.common.PEIM] + ####################################### + # Platform Package + ####################################### + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup= portLib/PeiMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrap= perPlatformLib/PeiFspWrapperPlatformLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Multi= BoardInitSupportLib/PeiMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPoint= Lib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pe= iTestPointCheckLib.inf +!endif + + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/P= eiDTbtInitLib/PeiDTbtInitLib.inf + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPo= licyLib/PeiTbtPolicyLib.inf +!endif + PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInit= Lib/PeiPolicyInitLib.inf + PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyUp= dateLib/PeiPolicyUpdateLib.inf + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFs= pPolicyInitLib/PeiFspPolicyInitLib.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLi= b.inf =20 -[LibraryClasses.X64] - # - # DXE phase common - # - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrap= perPlatformLib/DxeFspWrapperPlatformLib.inf - !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/= DxeTestPointCheckLib.inf - !endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPoint= Lib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Multi= BoardInitSupportLib/DxeMultiBoardInitSupportLib.inf + ####################################### + # Board-specific + ####################################### + PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHoo= klib.inf + PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiP= olicyBoardConfigLib.inf + +!if $(TARGET) =3D=3D DEBUG + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGp= ioCheckConflictLib.inf +!else + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/Ba= seGpioCheckConflictLibNull.inf +!endif + +[LibraryClasses.common.DXE_DRIVER] + ####################################### + # Edk2 Packages + ####################################### + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i= nf + + ####################################### + # Platform Package + ####################################### + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/DxeMultiBoardAcpiSupportLib.inf BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSup= portLib/DxeMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrap= perPlatformLib/DxeFspWrapperPlatformLib.inf MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcp= iSupportLib/DxeMultiBoardAcpiSupportLib.inf - BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/DxeMultiBoardAcpiSupportLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Multi= BoardInitSupportLib/DxeMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPoint= Lib.inf =20 - DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxeP= olicyBoardConfigLib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dx= eTestPointCheckLib.inf +!endif + + ####################################### + # Board Package + ####################################### DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolicyUp= dateLib/DxePolicyUpdateLib.inf - # - # Silicon Init Package - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPo= licyLib/DxeTbtPolicyLib.inf + + ####################################### + # Board-specific + ####################################### + DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxeP= olicyBoardConfigLib.inf + +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ####################################### + # Edk2 Packages + ####################################### DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i= nf =20 + ####################################### + # Silicon Initialization Package + ####################################### + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystem= Lib/DxeRuntimeResetSystemLib.inf + [LibraryClasses.X64.DXE_SMM_DRIVER] + ####################################### + # Edk2 Packages + ####################################### + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i= nf + + ####################################### + # Silicon Initialization Package + ####################################### SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonL= ib/SmmSpiFlashCommonLib.inf - !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/= SmmTestPointCheckLib.inf - !endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPoint= Lib.inf - MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcp= iSupportLib/SmmMultiBoardAcpiSupportLib.inf + + ####################################### + # Platform Package + ####################################### BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppo= rtLib/SmmMultiBoardAcpiSupportLib.inf - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i= nf - -[LibraryClasses.X64.DXE_RUNTIME_DRIVER] - ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystem= Lib/DxeRuntimeResetSystemLib.inf - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.i= nf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcp= iSupportLib/SmmMultiBoardAcpiSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPoint= Lib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sm= mTestPointCheckLib.inf +!endif =20 [Components.IA32] - # - # Common - # - !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc - - # - # FSP wrapper SEC Core - # + ####################################### + # Edk2 Packages + ####################################### UefiCpuPkg/SecCore/SecCore.inf { PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf } =20 # - # Silicon + # In FSP API mode the policy has to be installed before FSP Wrapper upd= ating UPD. + # Add policy as dependency for FSP Wrapper # - !include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf =20 - # - # Platform - # + ####################################### + # Silicon Initialization Package + ####################################### + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam= plePei.inf + + ####################################### + # Platform Package + ####################################### $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf= { @@ -223,12 +289,7 @@ !endif NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf } - IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe= m.inf { - - SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPol= icyInitLibNull/SiliconPolicyInitLibNull.inf - SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconP= olicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf - } + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.in= f { !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE @@ -237,51 +298,43 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.= inf !endif } - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf -#to do $(PLATFORM_PACKAGE)/FspWrapper/FspWrapperPeim/FspWrapperPeim.inf + + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMe= m.inf { + + SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Silic= onPolicyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Sil= iconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostM= em.inf { - SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPol= icyInitLibNull/SiliconPolicyInitLibNull.inf - SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconP= olicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Silic= onPolicyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Sil= iconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf } =20 - # - # Security - # +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif =20 - !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf - !endif - - IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf - IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSam= plePei.inf - - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf - !endif + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf +!endif =20 [Components.X64] - - # - # Common - # - !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc - - $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf - - UefiCpuPkg/CpuDxe/CpuDxe.inf + ####################################### + # Edk2 Packages + ####################################### + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + UefiCpuPkg/CpuDxe/CpuDxe.inf =20 - # - # Shell - # ShellPkg/Application/Shell/Shell.inf { gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE @@ -301,57 +354,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf } =20 - # - # Silicon - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc - - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf - $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf - !endif - - # - # Platform - # - $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{ - - NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf - } - - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf = { - - SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPol= icyInitLibNull/SiliconPolicyInitLibNull.inf - SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyUpdateLibNull/SiliconPolicyUpdateLibNull.inf - } - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf - IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf - - $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - - $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf - $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf - - # - # OS Boot - # - !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf - $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf - $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEn= ableLib.inf - !else - NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.= inf - !endif - } - - $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf - +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 @@ -360,25 +363,66 @@ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerial= Port.inf !endif } +!endif =20 - !endif - - # - # Security - # - $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - - !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf - !endif - + ####################################### + # Silicon Initialization Package + ####################################### IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf - - # - # Other - # + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf =20 - !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc - !include OpenBoardPkgBuildOption.dsc + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf = { + + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPol= icyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconP= olicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + } + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf =20 +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEn= ableLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.= inf + !endif + } + + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf + +!endif + + ####################################### + # Board Package + ####################################### + $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{ + + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf + } + + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf +!endif diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBo= ardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Open= BoardPkgPcd.dsc index 24e3da6686..5cf0aa9d86 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgP= cd.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgP= cd.dsc @@ -1,22 +1,24 @@ ## @file -# Platform description. +# PCD configuration build description file for the WhiskeylakeURvp board= . # +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# +# SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 #########################################################################= ####### # -# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# Pcd Section - list of all PCD Entries used by this board. # #########################################################################= ####### -[PcdsFixedAtBuild] + +[PcdsFixedAtBuild.common] + ###################################### + # Key Boot Stage and FSP configuration + ###################################### # - # Please select BootStage here. + # Please select the Boot Stage here. # Stage 1 - enable debug (system deadloop after debug init) # Stage 2 - mem init (system deadloop after mem init) # Stage 3 - boot to shell only @@ -25,56 +27,74 @@ # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 =20 + # + # 0: FSP Wrapper is running in Dispatch mode. + # 1: FSP Wrapper is running in API mode. + # Note: Dispatch mode is currently NOT supported for this board. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + + # + # FSP API mode does not share stack with the boot loader, + # so FSP needs more temporary memory for FSP heap + stack size. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 + # + # FSP API mode does not need to enlarge the boot loader stack size + # since the stacks are separate. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + [PcdsFeatureFlag.common] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirs= t|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE !endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - -# -# TRUE is ENABLE. FALSE is DISABLE. -# -# -# BIOS build switches configuration -# + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ###################################### + # Silicon Configuration + ###################################### + # Build switches gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE =20 -# CPU + # CPU + gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE =20 -# SA + # SA + gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE @@ -82,166 +102,132 @@ gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE =20 -# ME + # ME gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE =20 + # Others gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE - gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE = - HPET / FALSE - 8254 timer is used. - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 825= 4 timer is used. =20 - gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE =20 -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif =20 - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif =20 - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif =20 - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif =20 - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif =20 - #gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirs= t|FALSE -!if $(TARGET) =3D=3D RELEASE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE !else - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE =20 + ###################################### + # Board Configuration + ###################################### gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE =20 [PcdsFixedAtBuild.common] - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 -!endif - - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 - - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 - - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + ###################################### + # Edk2 Configuration + ###################################### !if $(TARGET) =3D=3D RELEASE gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 !else gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_ME= MORY_ADDRESS) - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_ME= MORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE - -# -# 8MB Default -# -gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 - -# -# 16MB TSEG in Debug build only. -# +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE !endif =20 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 =20 - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B - !endif + # Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 =20 - - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 - !endif - - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEAC000 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFDC0000 + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBu= ild + # (They will be DynamicEx in FSP Dispatch mode) + # =20 ## Specifies the size of the microcode Region. # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 =20 - ## Specifies timeout value in microseconds for the BSP to detect all AP= s for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. @@ -250,6 +236,17 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 =20 + ###################################### + # Silicon Configuration + ###################################### + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpac= eGuid.PcdPciExpressRegionLength + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tab= le - Protection Flags @@ -262,6 +259,19 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 =20 +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 +!endif + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0= 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, = 0x00, 0x00} !endif @@ -287,75 +297,98 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 !endif =20 [PcdsFixedAtBuild.IA32] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + [PcdsFixedAtBuild.X64] + ###################################### + # Edk2 Configuration + ###################################### + # Default platform supported RFC 4646 languages: (American) English gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US= " =20 - [PcdsPatchableInModule.common] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 =20 + ###################################### + # Silicon Configuration + ###################################### !if $(TARGET) =3D=3D DEBUG gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 !endif =20 -[PcdsDynamicHii.X64.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVa= riableGuid|0x0|5 # Variable: L"Timeout" - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"= |gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVa= riableGuid|0x0|1 # Variable: L"Timeout" -!endif - [PcdsDynamicDefault] - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFD50000 - # Platform will pre-allocate UPD buffer and pass it to FspWrapper - # Those dummy address will be patched before FspWrapper executing - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processors - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 - -[PcdsDynamicDefault.common.DEFAULT] - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + # # Set video to native resolution as Windows 8 WHCK requirement. # gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 =20 - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 - gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00 =20 -[PcdsDynamicDefault.common.DEFAULT] + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 =20 - # Tbt - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011 - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 + # Platform will pre-allocate UPD buffer and pass it to FspWrapper + # Those dummy address will be patched before FspWrapper executing + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0 =20 - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 =20 + ###################################### + # Board Configuration + ###################################### + + # Thunderbolt Configuration + gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 + gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + +[PcdsDynamicHii.X64.DEFAULT] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"= |gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVa= riableGuid|0x0|1 # Variable: L"Timeout" +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVa= riableGuid|0x0|5 # Variable: L"Timeout" +!endif --=20 2.16.2.windows.1