From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web12.423.1572485937755785315 for ; Wed, 30 Oct 2019 18:38:57 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 18:38:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,249,1569308400"; d="scan'208";a="212304050" Received: from orsmsx109.amr.corp.intel.com ([10.22.240.7]) by orsmga002.jf.intel.com with ESMTP; 30 Oct 2019 18:38:57 -0700 Received: from orsmsx153.amr.corp.intel.com (10.22.226.247) by ORSMSX109.amr.corp.intel.com (10.22.240.7) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 30 Oct 2019 18:38:56 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.28]) by ORSMSX153.amr.corp.intel.com ([169.254.12.244]) with mapi id 14.03.0439.000; Wed, 30 Oct 2019 18:38:56 -0700 From: "Nate DeSimone" To: "Chiu, Chasel" , "devel@edk2.groups.io" CC: "Kubacki, Michael A" , "Gao, Liming" Subject: Re: [edk2-platforms: PATCH v2 1/6] MinPlatformPkg: Add SetCacheLib library class. Thread-Topic: [edk2-platforms: PATCH v2 1/6] MinPlatformPkg: Add SetCacheLib library class. Thread-Index: AQHVj4Jqy2PKvoPJkEOvk+B+gqxYmKdz+MNQ Date: Thu, 31 Oct 2019 01:38:56 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AB5B8700C@ORSMSX113.amr.corp.intel.com> References: <20191031002952.3860-1-chasel.chiu@intel.com> <20191031002952.3860-2-chasel.chiu@intel.com> In-Reply-To: <20191031002952.3860-2-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjU0YWI1NjItNjk1MS00ZDIxLTk1NmYtOWM2YmQxYWY2MTMxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiaXFLQ09uMktLcms2OFIyUGhoR21aZjlxNXlqa210NkVUVHRyRjViXC94QlBJMHNpTVNySEJ2RHlZU2pTWFc4NHEifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Chiu, Chasel =20 Sent: Wednesday, October 30, 2019 5:30 PM To: devel@edk2.groups.io Cc: Kubacki, Michael A ; Desimone, Nathaniel L= ; Gao, Liming Subject: [edk2-platforms: PATCH v2 1/6] MinPlatformPkg: Add SetCacheLib lib= rary class. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 MinPlatformPkg should contain the library class header (API) and the NULL l= ibrary class instance. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c | 32= 5 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c | 3= 7 +++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h | 3= 4 ++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf | 4= 4 ++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf | 3= 0 ++++++++++++++++++++++++++++++ 5 files changed, 470 insertions(+) diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.= c b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c new file mode 100644 index 0000000000..b5c5041430 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c @@ -0,0 +1,325 @@ +/** @file + +SetCache library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + MTRR_SETTINGS MtrrSetting; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + EFI_BOOT_MODE BootMode; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + UINT64 CacheMemoryLength; + + /// + /// Reset all MTRR setting. + /// + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + /// + /// Cache the Flash area as WP to boost performance /// Status =3D=20 + MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to=20 + boost performance /// MtrrSetAllMtrrs (&MtrrSetting); + + /// + /// Set low to 1 MB. Since 1MB cacheability will always be set ///=20 + until override by CSM. + /// Initialize high memory to 0. + /// + LowMemoryLength =3D 0x100000; + HighMemoryLength =3D 0; + ResourceAttribute =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + Status =3D PeiServicesGetBootMode (&BootMode); ASSERT_EFI_ERROR=20 + (Status); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; } + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); while=20 + (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || + ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) + ) { + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n",=20 + LowMemoryLength)); DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D=20 + %lx.\n", HighMemoryLength)); + + /// + /// Assume size of main memory is multiple of 256MB /// =20 + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; MemoryBase= =20 + =3D 0; + + CacheMemoryLength =3D MemoryLength; + /// + /// Programming MTRRs to avoid override SPI region with UC when MAX=20 + TOLUD Length >=3D 3.5GB /// if (MemoryLength > 0xDC000000) { + CacheMemoryLength =3D 0xC0000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xC0000000; + CacheMemoryLength =3D MemoryLength - 0xC0000000; + if (MemoryLength > 0xE0000000) { + CacheMemoryLength =3D 0x20000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xE0000000; + CacheMemoryLength =3D MemoryLength - 0xE0000000; + } + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + if (LowMemoryLength !=3D MemoryLength) { + MemoryBase =3D LowMemoryLength; + MemoryLength -=3D LowMemoryLength; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + MemoryLength, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } + + /// + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC /// Status =3D=20 + MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer /// MtrrSetAllMtrrs=20 + (&MtrrSetting); + + return ; +} + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + MTRR_SETTINGS MtrrSetting; + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 Power2Length; + EFI_BOOT_MODE BootMode; + UINTN Index; + UINT64 SmramSize; + UINT64 SmramBase; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + return EFI_SUCCESS; + } + // + // Clear the CAR Settings + // + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + // + // Default Cachable attribute will be set to WB to support large=20 + memory size/hot plug memory // MtrrSetting.MtrrDefType &=3D=20 + ~((UINT64)(0xFF)); MtrrSetting.MtrrDefType |=3D (UINT64)=20 + CacheWriteBack; + + // + // Set fixed cache for memory range below 1MB // Status =3D=20 + MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0x0, + 0xA0000, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xC0000, + 0x40000, + CacheWriteProtected + ); + ASSERT_EFI_ERROR ( Status); + + // + // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protoc= ol is not available. + // Set cacheability of SMRAM to WB here to improve SMRAM initialization = performance. + // + SmramSize =3D 0; + SmramBase =3D 0; + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); while=20 + (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { + if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { + SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Ho= b.Guid + 1); + for (Index =3D 0; Index < SmramHobDescriptorBlock->NumberOfSmmRese= rvedRegions; Index++) { + if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0= x100000) { + SmramSize +=3D SmramHobDescriptorBlock->Descriptor[Index].Phys= icalSize; + if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBlock-= >Descriptor[Index].CpuStart) { + SmramBase =3D SmramHobDescriptorBlock->Descriptor[Index].Cpu= Start; + } + } + } + break; + } + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + // + // Set non system memory as UC + // + MemoryBase =3D 0x100000000; + + // + // Add IED size to set whole SMRAM as WB to save MTRR count // =20 + MemoryLength =3D MemoryBase - (SmramBase + SmramSize); while=20 + (MemoryLength !=3D 0) { + Power2Length =3D GetPowerOfTwo64 (MemoryLength); + MemoryBase -=3D Power2Length; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + Power2Length, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + MemoryLength -=3D Power2Length; + } + + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n",=20 + PcdGet64 (PcdPciReservedMemAbove4GBLimit))); + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n",=20 + PcdGet64 (PcdPciReservedMemAbove4GBBase))); + if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReserved= MemAbove4GBBase)) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + PcdGet64 (PcdPciReservedMemAbove4GBBase), + PcdGet64 (PcdPciReservedMemAbove4GBLimit) - Pcd= Get64 (PcdPciReservedMemAbove4GBBase) + 1, + CacheUncacheable + ); + ASSERT_EFI_ERROR ( Status); + } + + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n",=20 + PcdGet64 (PcdPciReservedPMemAbove4GBLimit))); + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n",=20 + PcdGet64 (PcdPciReservedPMemAbove4GBBase))); + if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReserve= dPMemAbove4GBBase)) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + PcdGet64 (PcdPciReservedPMemAbove4GBBase), + PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - Pc= dGet64 (PcdPciReservedPMemAbove4GBBase) + 1, + CacheUncacheable + ); + ASSERT_EFI_ERROR ( Status); + } + + // + // Update MTRR setting from MTRR buffer // MtrrSetAllMtrrs=20 + (&MtrrSetting); + + return Status; +} diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibN= ull.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c new file mode 100644 index 0000000000..581bc7648b --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull. +++ c @@ -0,0 +1,37 @@ +/** @file + +NULL instances of SetCache library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + return; +} + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h b/= Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h new file mode 100644 index 0000000000..d67426cef7 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h @@ -0,0 +1,34 @@ +/** @file + +Header for SetCache library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SET_CACHE_LIB_H_ +#define _SET_CACHE_LIB_H_ + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ); + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ); + +#endif diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.= inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf new file mode 100644 index 0000000000..a53aed858f --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf @@ -0,0 +1,44 @@ +## @file +# Component information file for Platform SetCache Library # #=20 +Copyright (c) 2019, Intel Corporation. All rights reserved.
# #=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SetCacheLib + FILE_GUID =3D 9F2A2899-3AD7-4176-9B89-33B3AC456A99 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + HobLib + MtrrLib + PeiServicesLib + BaseMemoryLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheLib.c + +[Guids] + gEfiSmmSmramMemoryGuid ## CONSUMES + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUME= S + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUME= S + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUME= S + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ##=20 +CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ##=20 +CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ##=20 +CONSUMES diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibN= ull.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull= .inf new file mode 100644 index 0000000000..50419b398b --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull. +++ inf @@ -0,0 +1,30 @@ +## @file +# Component information file for Platform SetCache Library # #=20 +Copyright (c) 2019, Intel Corporation. All rights reserved.
# #=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SetCacheLibNull + FILE_GUID =3D D1ED4CD7-AD20-4943-9192-3ABE766A9411 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + +[Sources] + SetCacheLibNull.c + +[Pcd] -- 2.13.3.windows.1