From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.754.1572632977375916048 for ; Fri, 01 Nov 2019 11:29:37 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 11:29:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194754662" Received: from orsmsx109.amr.corp.intel.com ([10.22.240.7]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 11:29:36 -0700 Received: from orsmsx153.amr.corp.intel.com (10.22.226.247) by ORSMSX109.amr.corp.intel.com (10.22.240.7) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 1 Nov 2019 11:29:36 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.28]) by ORSMSX153.amr.corp.intel.com ([169.254.12.244]) with mapi id 14.03.0439.000; Fri, 1 Nov 2019 11:29:36 -0700 From: "Nate DeSimone" To: "devel@edk2.groups.io" , "Chiu, Chasel" CC: "Kubacki, Michael A" , "Gao, Liming" Subject: Re: [edk2-devel] [edk2-platforms: PATCH v3 2/6] MinPlatformPkg: Add SetCacheMtrrLib library class. Thread-Topic: [edk2-devel] [edk2-platforms: PATCH v3 2/6] MinPlatformPkg: Add SetCacheMtrrLib library class. Thread-Index: AQHVj9X0UmILGkP610SeDKdNw0sIPKd2pChw Date: Fri, 1 Nov 2019 18:29:35 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AB5B96EAD@ORSMSX113.amr.corp.intel.com> References: <20191031102817.17096-1-chasel.chiu@intel.com> <20191031102817.17096-3-chasel.chiu@intel.com> In-Reply-To: <20191031102817.17096-3-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZDA3ZDM0MGUtNzNjNy00YzQyLTk5YTgtMDhmZjY4YTExNjgwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZXRhWm9RU0ZIbW56ZmpOWll0aXRRWDhmSmFnUWpEeEZSRWJlamVUektZZU01aUtPMFwvWURramVnOHByQmxONVwvIn0= x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: devel@edk2.groups.io On Behalf Of Chiu, Chase= l Sent: Thursday, October 31, 2019 3:28 AM To: devel@edk2.groups.io Cc: Kubacki, Michael A ; Desimone, Nathaniel = L ; Gao, Liming Subject: [edk2-devel] [edk2-platforms: PATCH v3 2/6] MinPlatformPkg: Add S= etCacheMtrrLib library class. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 MinPlatformPkg PlatformInit modules to consume SetCacheMtrrLib. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPo= stMem.c | 151 ++---------------------------------------------------------= ---------------------------------------------------------------------------= ----------------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr= eMem.c | 164 ++---------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------ Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPo= stMem.inf | 11 +---------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPr= eMem.inf | 7 ++----- 4 files changed, 7 insertions(+), 326 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pl= atformInitPostMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIn= itPei/PlatformInitPostMem.c index 70e6b9a495..1b00d1dd6a 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformI= nitPostMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor +++ mInitPostMem.c @@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <= Library/PeiServicesLib.h> #include #include -#include -#include =20 #include #include @@ -22,6 +20,7 @@ SPDX-License-= Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 EFI_STATUS EFIAPI @@ -38,152 +37,6 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = = =3D { }; =20 /** - Update MTRR setting and set write back as default memory attribute. - - @retval EFI_SUCCESS The function completes successfully. - @retval Others Some error occurs. -**/ -EFI_STATUS -EFIAPI -SetCacheMtrrAfterEndOfPei ( - VOID - ) -{ - EFI_STATUS Status; - MTRR_SETTINGS MtrrSetting; - EFI_PEI_HOB_POINTERS Hob; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 Power2Length; - EFI_BOOT_MODE BootMode; - UINTN Index; - UINT64 SmramSize; - UINT64 SmramBase; - EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode =3D=3D BOOT_ON_S3_RESUME) { - return EFI_SUCCESS; - } - // - // Clear the CAR Settings - // - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - // - // Default Cachable attribute will be set to WB to support large memory= size/hot plug memory - // - MtrrSetting.MtrrDefType &=3D ~((UINT64)(0xFF)); - MtrrSetting.MtrrDefType |=3D (UINT64) CacheWriteBack; - - // - // Set fixed cache for memory range below 1MB - // - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0x0, - 0xA0000, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xC0000, - 0x40000, - CacheWriteProtected - ); - ASSERT_EFI_ERROR ( Status); - - // - // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH proto= col is not available. - // Set cacheability of SMRAM to WB here to improve SMRAM initialization= performance. - // - SmramSize =3D 0; - SmramBase =3D 0; - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { - if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { - SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (H= ob.Guid + 1); - for (Index =3D 0; Index < SmramHobDescriptorBlock->NumberOfSmmRes= ervedRegions; Index++) { - if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > = 0x100000) { - SmramSize +=3D SmramHobDescriptorBlock->Descriptor[Index].Phy= sicalSize; - if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBlock= ->Descriptor[Index].CpuStart) { - SmramBase =3D SmramHobDescriptorBlock->Descriptor[Index].Cp= uStart; - } - } - } - break; - } - } - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - // - // Set non system memory as UC - // - MemoryBase =3D 0x100000000; - - // - // Add IED size to set whole SMRAM as WB to save MTRR count - // - MemoryLength =3D MemoryBase - (SmramBase + SmramSize); - while (MemoryLength !=3D 0) { - Power2Length =3D GetPowerOfTwo64 (MemoryLength); - MemoryBase -=3D Power2Length; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - Power2Length, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - MemoryLength -=3D Power2Length; - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet6= 4 (PcdPciReservedMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64= (PcdPciReservedMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReserve= dMemAbove4GBBase)) { - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedMemAbove4GBBase), - PcdGet64 (PcdPciReservedMemAbove4GBLimit) - Pc= dGet64 (PcdPciReservedMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet= 64 (PcdPciReservedPMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet6= 4 (PcdPciReservedPMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReserv= edPMemAbove4GBBase)) { - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedPMemAbove4GBBase), - PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - P= cdGet64 (PcdPciReservedPMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - // - // Update MTRR setting from MTRR buffer - // - MtrrSetAllMtrrs (&MtrrSetting); - - return Status; -} - -/** This function handles PlatformInit task at the end of PEI =20 @param[in] PeiServices Pointer to PEI Services Table. @@ -203,7 +56,7 @@ PlatformInitEndOfPei ( ) { EFI_STATUS Status; - + Status =3D BoardInitAfterSiliconInit (); ASSERT_EFI_ERROR (Status); =20 diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pl= atformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIni= tPei/PlatformInitPreMem.c index 2690511abe..c579ff008e 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformI= nitPreMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor +++ mInitPreMem.c @@ -1,7 +1,7 @@ /** @file Source code file for Platform Init Pre-Memory PEI module =20 -Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -15,7 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <= Library/TimerLib.h> #include #include -#include #include #include #include @@ -26,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include= #include #include +#include #include #include #include @@ -319,166 +319,6 @@ Done: return EFI_SUCCESS; } =20 -/** - Set Cache Mtrr. -**/ -VOID -SetCacheMtrr ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_HOB_POINTERS Hob; - MTRR_SETTINGS MtrrSetting; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 LowMemoryLength; - UINT64 HighMemoryLength; - EFI_BOOT_MODE BootMode; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - UINT64 CacheMemoryLength; - - /// - /// Reset all MTRR setting. - /// - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - /// - /// Cache the Flash area as WP to boost performance - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), - (UINTN) PcdGet32 (PcdFlashAreaSize), - CacheWriteProtected - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer for Flash Region to be WP to b= oost performance - /// - MtrrSetAllMtrrs (&MtrrSetting); - - /// - /// Set low to 1 MB. Since 1MB cacheability will always be set - /// until override by CSM. - /// Initialize high memory to 0. - /// - LowMemoryLength =3D 0x100000; - HighMemoryLength =3D 0; - ResourceAttribute =3D ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode !=3D BOOT_ON_S3_RESUME) { - ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; - } - - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTE= M_MEMORY) || - ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMO= RY_RESERVED) && - (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttr= ibute)) - ) { - if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { - HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { - LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } - } - } - - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLe= ngth)); - DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryL= ength)); - - /// - /// Assume size of main memory is multiple of 256MB - /// - MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; - MemoryBase =3D 0; - - CacheMemoryLength =3D MemoryLength; - /// - /// Programming MTRRs to avoid override SPI region with UC when MAX TOL= UD Length >=3D 3.5GB - /// - if (MemoryLength > 0xDC000000) { - CacheMemoryLength =3D 0xC0000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xC0000000; - CacheMemoryLength =3D MemoryLength - 0xC0000000; - if (MemoryLength > 0xE0000000) { - CacheMemoryLength =3D 0x20000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xE0000000; - CacheMemoryLength =3D MemoryLength - 0xE0000000; - } - } - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - if (LowMemoryLength !=3D MemoryLength) { - MemoryBase =3D LowMemoryLength; - MemoryLength -=3D LowMemoryLength; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - MemoryLength, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } - - /// - /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer - /// - MtrrSetAllMtrrs (&MtrrSetting); - - return ; -} - VOID ReportCpuHob ( VOID diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pl= atformInitPostMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/Platform= InitPei/PlatformInitPostMem.inf index 0736c8d494..74a9b91540 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformI= nitPostMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor +++ mInitPostMem.inf @@ -23,15 +23,14 @@ BaseMemoryLib HobLib PeiServicesLib - MtrrLib BoardInitLib TestPointCheckLib + SetCacheMtrrLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec =20 [Sources] PlatformInitPostMem.c @@ -44,14 +43,6 @@ =20 [Protocols] =20 -[Guids] - gEfiSmmSmramMemoryGuid ## CONSUMES - [Depex] gEfiPeiMemoryDiscoveredPpiGuid =20 -[Pcd] - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pl= atformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPreMem.inf index 2c3a13106e..af5dbe8772 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformI= nitPreMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Platfor +++ mInitPreMem.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the Platform Init Pre-Memory PEI module. # -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,23 +22,20 @@ HobLib IoLib MemoryAllocationLib - MtrrLib PeimEntryPoint PeiServicesLib ReportFvLib TestPointCheckLib TimerLib + SetCacheMtrrLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec =20 [Pcd] gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUME= S - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUME= S - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUME= S gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUME= S gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUME= S =20 -- 2.13.3.windows.1