From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web12.1171.1581492045749825019 for ; Tue, 11 Feb 2020 23:20:46 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2020 23:20:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,428,1574150400"; d="scan'208";a="251822764" Received: from orsmsx105.amr.corp.intel.com ([10.22.225.132]) by orsmga002.jf.intel.com with ESMTP; 11 Feb 2020 23:20:46 -0800 Received: from orsmsx115.amr.corp.intel.com (10.22.240.11) by ORSMSX105.amr.corp.intel.com (10.22.225.132) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 11 Feb 2020 23:20:44 -0800 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.140]) by ORSMSX115.amr.corp.intel.com ([169.254.4.100]) with mapi id 14.03.0439.000; Tue, 11 Feb 2020 23:20:44 -0800 From: "Nate DeSimone" To: "Esakkithevar, Kathappan" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Kethi Reddy, Deepika" , "Agyeman, Prince" Subject: Re: [edk2-platforms] [PATCH v2 2/7] CometlakeOpenBoardPkg/CometlakeURvp: Add headers Thread-Topic: [edk2-platforms] [PATCH v2 2/7] CometlakeOpenBoardPkg/CometlakeURvp: Add headers Thread-Index: AQHV4Q9NJJsWkArk102yCXJd9WNNt6gXJ73g Date: Wed, 12 Feb 2020 07:20:44 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AB5D43C43@ORSMSX114.amr.corp.intel.com> References: <20200211191241.53188-1-kathappan.esakkithevar@intel.com> <20200211191241.53188-3-kathappan.esakkithevar@intel.com> In-Reply-To: <20200211191241.53188-3-kathappan.esakkithevar@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYzRmYjRmYTEtMDc4NS00OTdhLTgyODAtNzQ0YWYwYTA3YjFjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiVUlRZWU4T3J0RzVKSWJUanczWU1NVGRYVk03NEwxbExsdFpLdm4raWQ1NXJUXC9jMlhtekxEYmhpT250SVU5RmQifQ== x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Esakkithevar, Kathappan =20 Sent: Tuesday, February 11, 2020 11:13 AM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Kethi Reddy, Deepika ; Agyeman, Prince Subject: [edk2-platforms] [PATCH v2 2/7] CometlakeOpenBoardPkg/CometlakeURv= p: Add headers REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280 Header files for the CometlakeURvp board instance. Signed-off-by: Kathappan Esakkithevar Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Deepika Kethi Reddy Cc: Prince Agyeman --- .../CometlakeURvp/Include/Fdf/FlashMapInclude.fdf | 49 ++++++++ .../CometlakeURvp/Include/PeiPlatformHookLib.h | 131 +++++++++++++++++= ++++ .../CometlakeURvp/Include/PeiPlatformLib.h | 40 +++++++ .../CometlakeURvp/Include/PlatformBoardConfig.h | 105 +++++++++++++++++ .../CometlakeURvp/Include/PlatformInfo.h | 44 +++++++ 5 files changed, 369 insertions(+) create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl= ude/Fdf/FlashMapInclude.fdf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl= ude/PeiPlatformHookLib.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl= ude/PeiPlatformLib.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl= ude/PlatformBoardConfig.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl= ude/PlatformInfo.h diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf= /FlashMapInclude.fdf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/I= nclude/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000..d9959a79d0 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Fdf/Fla +++ shMapInclude.fdf @@ -0,0 +1,49 @@ +## @file +# FDF file for the CometlakeURvp board. +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
# # =20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# +# 8 M BIOS - for FSP wrapper +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# +DEFINE FLASH_BASE =3D 0x= FF800000 # +DEFINE FLASH_SIZE =3D 0x= 00800000 # +DEFINE FLASH_BLOCK_SIZE =3D 0x= 00010000 # +DEFINE FLASH_NUM_BLOCKS =3D 0x= 00000080 # +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D# + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D 0x= 00040000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFF800000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x= 0001E000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D=20 +0x0001E000 # Flash addr (0xFF81E000) SET gEfiMdeModulePkgTokenSpaceGuid.P= cdFlashNvStorageFtwWorkingSize =3D 0x00002000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFF820000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x= 00020000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00040000 # Flash addr (0xFF840000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 00050000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 00090000 # Flash addr (0xFF890000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00070000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00100000 # Flash addr (0xFF900000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 00090000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 00190000 # Flash addr (0xFF990000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00190000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 00320000 # Flash addr (0xFFB20000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00170000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 00490000 # Flash addr (0xFFC90000) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000B0000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00540000 # Flash addr (0xFFD40000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00070000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 005B0000 # Flash addr (0xFFDB0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000EC000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 0069C000 # Flash addr (0xFFE9C000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00014000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D 0x= 006B0000 # Flash addr (0xFFEB0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize =3D 0x= 00010000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006C0000 # Flash addr (0xFFEC0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00140000 # + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pei= PlatformHookLib.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Incl= ude/PeiPlatformHookLib.h new file mode 100644 index 0000000000..690054d2e9 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlat +++ formHookLib.h @@ -0,0 +1,131 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PEI_PLATFORM_HOOK_LIB_H_ +#define _PEI_PLATFORM_HOOK_LIB_H_ + +#include +#include +#include + + +//EC Command to provide one byte of debug indication #define=20 +BSSB_DEBUG_INDICATION 0xAE +/** + Configure EC for specific devices + + @param[in] PchLan - The PchLan of PCH_SETUP variable. + @param[in] BootMode - The current boot mode. +**/ +VOID +EcInit ( + IN UINT8 PchLan, + IN EFI_BOOT_MODE BootMode + ); + +/** + Checks if Premium PMIC present + + @retval TRUE if present + @retval FALSE it discrete/other PMIC **/ BOOLEAN=20 +IsPremiumPmicPresent ( + VOID + ); + +/** + Pmic Programming to supprort LPAL Feature + + @retval NONE +**/ +VOID +PremiumPmicDisableSlpS0Voltage ( + VOID + ); + +/** +Pmic Programming to supprort LPAL Feature + @retval NONE +**/ +VOID +PremiumPmicEnableSlpS0Voltage( + VOID + ); + +/** + Do platform specific programming pre-memory. For example, EC init,=20 +Chipset programming + + @retval Status +**/ +EFI_STATUS +PlatformSpecificInitPreMem ( + VOID + ); + +/** + Do platform specific programming post-memory. + + @retval Status +**/ +EFI_STATUS +PlatformSpecificInit ( + VOID + ); + +/** + Configure GPIO and SIO Before Memory is ready. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitPreMem ( + VOID + ); + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + VOID + ); + +/** +Voltage Margining Routine + +@retval EFI_SUCCESS Operation success +**/ +EFI_STATUS +VoltageMarginingRoutine( + VOID + ); + +/** + Detect recovery mode + + @retval EFI_SUCCESS System in Recovery Mode + @retval EFI_UNSUPPORTED System doesn't support Recovery Mode + @retval EFI_NOT_FOUND System is not in Recovery Mode +**/ +EFI_STATUS +IsRecoveryMode ( + VOID + ); + +/** + Early board Configuration before Memory is ready. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitEarlyPreMem ( + VOID + ); +#endif + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pei= PlatformLib.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/= PeiPlatformLib.h new file mode 100644 index 0000000000..3443479a52 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/PeiPlat +++ formLib.h @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PEI_PLATFORM_LIB_H_ +#define _PEI_PLATFORM_LIB_H_ + + + +#define PEI_DEVICE_DISABLED 0 +#define PEI_DEVICE_ENABLED 1 + +typedef struct { + UINT8 Register; + UINT32 Value; +} PCH_GPIO_DEV; + +// +// GPIO Initialization Data Structure +// +typedef struct{ + PCH_GPIO_DEV Use_Sel; + PCH_GPIO_DEV Use_Sel2; + PCH_GPIO_DEV Use_Sel3; + PCH_GPIO_DEV Io_Sel; + PCH_GPIO_DEV Io_Sel2; + PCH_GPIO_DEV Io_Sel3; + PCH_GPIO_DEV Lvl; + PCH_GPIO_DEV Lvl2; + PCH_GPIO_DEV Lvl3; + PCH_GPIO_DEV Inv; + PCH_GPIO_DEV Blink; + PCH_GPIO_DEV Rst_Sel; + PCH_GPIO_DEV Rst_Sel2; +} GPIO_INIT_STRUCT; + +#endif + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pla= tformBoardConfig.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Inc= lude/PlatformBoardConfig.h new file mode 100644 index 0000000000..4d286b897a --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platfor +++ mBoardConfig.h @@ -0,0 +1,105 @@ +/** @file + Header file for Platform Boards Configurations. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PLATFORM_BOARD_CONFIG_H +#define _PLATFORM_BOARD_CONFIG_H + +#include +#include +#include +#include +#include + +#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1) +#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16)= & 0xFFF0)) + +#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001 #define=20 +BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001 #define=20 +BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001 #define=20 +BOARD_NO_BATTERY_SUPPORT 0 #define BOARD_REAL_BATTERY_SUPPORTED BIT0=20 +#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1 + +#pragma pack(1) + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header +} BOARD_CONFIG_BLOCK; + +typedef struct { + UINT8 GpioSupport; + UINT32 WakeGpioNo; + UINT8 HoldRstExpanderNo; + UINT32 HoldRstGpioNo; + BOOLEAN HoldRstActive; + UINT8 PwrEnableExpanderNo; + UINT32 PwrEnableGpioNo; + BOOLEAN PwrEnableActive; +} SWITCH_GRAPHIC_GPIO; + +typedef struct { + UINT8 ClkReqNumber : 4; + UINT8 ClkReqSupported : 1; + UINT8 DeviceResetPadActiveHigh : 1; + UINT32 DeviceResetPad; +} ROOT_PORT_CLK_INFO; + +typedef struct { + UINT8 Section; + UINT8 Pin; +} EXPANDER_GPIO_CONFIG; + +typedef enum { + BoardGpioTypePch, + BoardGpioTypeExpander, + BoardGpioTypeNotSupported =3D 0xFF +} BOARD_GPIO_TYPE; + +typedef struct { + UINT8 Type; + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG + union { + UINT32 Pin; + EXPANDER_GPIO_CONFIG Expander; + } u; +} BOARD_GPIO_CONFIG; + +// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAG= E from PCH RC. +#define NOT_USED 0xFF +#define FREE_RUNNING 0x80 +#define LAN_CLOCK 0x70 +#define PCIE_PEG 0x40 +#define PCIE_PCH 0x00 + +typedef struct { + UINT32 ClockUsage; + UINT32 ClkReqSupported; +} PCIE_CLOCK_CONFIG; + +typedef union { + UINT64 Blob; + BOARD_GPIO_CONFIG BoardGpioConfig; + ROOT_PORT_CLK_INFO Info; + PCIE_CLOCK_CONFIG PcieClock; +} PCD64_BLOB; + +typedef union { + UINT32 Blob; + USB20_AFE Info; +} PCD32_BLOB; + +#ifndef IO_EXPANDER_DISABLED +#define IO_EXPANDER_DISABLED 0xFF +#endif + +#define SPD_DATA_SIZE 512 + +#pragma pack() + +#endif // _PLATFORM_BOARD_CONFIG_H + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pla= tformInfo.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Pl= atformInfo.h new file mode 100644 index 0000000000..f8854485b4 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Include/Platfor +++ mInfo.h @@ -0,0 +1,44 @@ +/** @file + GUID used for Platform Info Data entries in the HOB list. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PLATFORM_INFO_H_ +#define _PLATFORM_INFO_H_ + +#pragma pack(1) + +/// +/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in=20 +GpioConfig.h /// typedef UINT32 PCH_GPIO_PAD; //Copied from=20 +GpioConfig.h (need to change it based on include) + +typedef struct { +UINT8 Expander; +UINT8 Pin; +UINT16 Reserved; // Reserved for future use +} IO_EXPANDER_PAD; + +typedef union { +PCH_GPIO_PAD PchGpio; +IO_EXPANDER_PAD IoExpGpio; +} GPIO_PAD_CONFIG; + +typedef struct { +UINT8 GpioType; // 0: Disabled (no GPIO support), 1: PCH= , 2: I/O Expander +UINT8 Reserved[3]; // Reserved for future use +GPIO_PAD_CONFIG GpioData; +} PACKED_GPIO_CONFIG; + +typedef union { +PACKED_GPIO_CONFIG PackedGpio; +UINT64 Data64; +} COMMON_GPIO_CONFIG; + +#pragma pack() + +#endif + -- 2.16.2.windows.1