From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web09.1133.1581492063697348932 for ; Tue, 11 Feb 2020 23:21:03 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2020 23:21:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,428,1574150400"; d="scan'208";a="406205727" Received: from orsmsx106.amr.corp.intel.com ([10.22.225.133]) by orsmga005.jf.intel.com with ESMTP; 11 Feb 2020 23:21:01 -0800 Received: from orsmsx159.amr.corp.intel.com (10.22.240.24) by ORSMSX106.amr.corp.intel.com (10.22.225.133) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 11 Feb 2020 23:21:00 -0800 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.140]) by ORSMSX159.amr.corp.intel.com ([169.254.11.53]) with mapi id 14.03.0439.000; Tue, 11 Feb 2020 23:21:00 -0800 From: "Nate DeSimone" To: "Esakkithevar, Kathappan" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Kethi Reddy, Deepika" , "Agyeman, Prince" Subject: Re: [edk2-platforms] [PATCH v2 4/7] CometlakeOpenBoardPkg/CometlakeURvp: Add library instances Thread-Topic: [edk2-platforms] [PATCH v2 4/7] CometlakeOpenBoardPkg/CometlakeURvp: Add library instances Thread-Index: AQHV4Q9axlMzDaWCTkaYeVycz7W6oKgXJ8zw Date: Wed, 12 Feb 2020 07:20:59 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AB5D43C6F@ORSMSX114.amr.corp.intel.com> References: <20200211191241.53188-1-kathappan.esakkithevar@intel.com> <20200211191241.53188-5-kathappan.esakkithevar@intel.com> In-Reply-To: <20200211191241.53188-5-kathappan.esakkithevar@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNmZlNGQ5YTYtMWI3YS00NDBiLTg4MGYtYzQ0Y2ZmODZiMzZkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiOTRZaU0xc3h2WWpXN1JsSXNzNXJpdWlKdnRENEE1NnN3N1hac3IxQmx5bTFzZ2FyVkVadEQ5bVh6ZGZqY0hEUCJ9 x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Esakkithevar, Kathappan =20 Sent: Tuesday, February 11, 2020 11:13 AM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Kethi Reddy, Deepika ; Agyeman, Prince Subject: [edk2-platforms] [PATCH v2 4/7] CometlakeOpenBoardPkg/CometlakeURv= p: Add library instances REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2280 CometlakeURvp library instances. * BaseFuncLib - Board-specific VBT update routines. * BaseGpioCheckConflictLib - Identifies GPIO pad conflicts. * BaseGpioCheckConflictLibNull - NULL library instance. * BasePlatformHookLib - Serial port initialization support. * DxePolicyBoardConfigLib - Board-specific silicon policy configuration in DXE. * PeiBoardInitPostMemLib - PEI post-memory board-specific initialization. This library implements board APIs declared in MinPlatformPkg. * PeiBoardInitPreMemLib - PEI pre-memory board-specific initialization. This library implements board APIs declared in MinPlatformPkg. * PeiMultiBoardInitPostMemLib - PEI post-memory multi-board initialization. This library implements board APIs declared in MinPlatformPkg. * PeiMultiBoardInitPreMemLib - PEI pre-memory multi-board initialization. This library implements board APIs declared in MinPlatformPkg. * PeiPlatformHookLib - PEI board instance-specifc GPIO init. * PeiPolicyBoardConfigLib - Board instance-specific policy init in PEI. * SmmBoardAcpiEnableLib - Board instance-specific SMM ACPI enable support. * SmmMultiBoardAcpiSupportLib - Multi-board ACPI support in SMM. Signed-off-by: Kathappan Esakkithevar Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Deepika Kethi Reddy Cc: Prince Agyeman --- .../Library/BaseFuncLib/BaseFuncLib.inf | 33 + .../CometlakeURvp/Library/BaseFuncLib/Gop.c | 41 + .../BaseGpioCheckConflictLib.c | 137 + .../BaseGpioCheckConflictLib.inf | 35 + .../BaseGpioCheckConflictLibNull.c | 37 + .../BaseGpioCheckConflictLibNull.inf | 32 + .../BasePlatformHookLib/BasePlatformHookLib.c | 156 + .../BasePlatformHookLib/BasePlatformHookLib.inf | 53 + .../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 63 + .../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 50 + .../BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c | 40 + .../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 82 + .../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 50 + .../Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 170 ++ .../CometlakeURvp/Library/BoardInitLib/BoardFunc.c | 19 + .../CometlakeURvp/Library/BoardInitLib/BoardFunc.h | 20 + .../Library/BoardInitLib/BoardFuncInit.c | 26 + .../Library/BoardInitLib/BoardFuncInitPreMem.c | 40 + .../Library/BoardInitLib/BoardInitLib.h | 20 + .../Library/BoardInitLib/BoardPchInitPreMemLib.c | 398 +++ .../Library/BoardInitLib/BoardSaConfigPreMem.h | 83 + .../Library/BoardInitLib/BoardSaInitPreMemLib.c | 383 +++ .../BoardInitLib/CometlakeURvpHsioPtssTables.c | 32 + .../Library/BoardInitLib/CometlakeURvpInit.h | 41 + .../BoardInitLib/GpioTableCmlUlpddr3PreMem.c | 43 + .../BoardInitLib/GpioTableCometlakeULpddr3Rvp.c | 254 ++ .../Library/BoardInitLib/GpioTableDefault.c | 213 ++ .../Library/BoardInitLib/PchHdaVerbTables.h | 3014 ++++++++++++++++= ++++ .../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 40 + .../BoardInitLib/PeiBoardInitPostMemLib.inf | 57 + .../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 106 + .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 118 + .../Library/BoardInitLib/PeiCometlakeURvpDetect.c | 63 + .../BoardInitLib/PeiCometlakeURvpInitPostMemLib.c | 436 +++ .../BoardInitLib/PeiCometlakeURvpInitPreMemLib.c | 562 ++++ .../BoardInitLib/PeiMultiBoardInitPostMemLib.c | 41 + .../BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 207 ++ .../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 83 + .../BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 300 ++ .../DxePolicyBoardConfigLib/DxePolicyBoardConfig.h | 19 + .../DxePolicyBoardConfigLib.inf | 45 + .../DxeSaPolicyBoardConfig.c | 36 + .../PeiPlatformHookLib/PeiPlatformHooklib.c | 299 ++ .../PeiPlatformHookLib/PeiPlatformHooklib.inf | 95 + .../PeiCpuPolicyBoardConfig.c | 49 + .../PeiCpuPolicyBoardConfigPreMem.c | 29 + .../PeiMePolicyBoardConfig.c | 36 + .../PeiMePolicyBoardConfigPreMem.c | 37 + .../PeiPchPolicyBoardConfig.c | 36 + .../PeiPchPolicyBoardConfigPreMem.c | 37 + .../PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h | 22 + .../PeiPolicyBoardConfigLib.inf | 71 + .../PeiSaPolicyBoardConfig.c | 36 + .../PeiSaPolicyBoardConfigPreMem.c | 37 + .../PeiSiPolicyBoardConfig.c | 27 + 55 files changed, 8489 insertions(+) create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BaseFuncLib/BaseFuncLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BaseFuncLib/Gop.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BasePlatformHookLib/BasePlatformHookLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BasePlatformHookLib/BasePlatformHookLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardAcpiLib/SmmBoardAcpiEnableLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardAcpiLib/SmmBoardAcpiEnableLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardAcpiLib/SmmSiliconAcpiEnableLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardFunc.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardFunc.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardFuncInit.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardFuncInitPreMem.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardInitLib.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardPchInitPreMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardSaConfigPreMem.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/BoardSaInitPreMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/CometlakeURvpHsioPtssTables.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/CometlakeURvpInit.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/GpioTableCmlUlpddr3PreMem.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/GpioTableDefault.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PchHdaVerbTables.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiBoardInitPostMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiBoardInitPreMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiBoardInitPreMemLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiCometlakeURvpDetect.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiCometlakeURvpInitPostMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiCometlakeURvpInitPreMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiMultiBoardInitPostMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiMultiBoardInitPostMemLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiMultiBoardInitPreMemLib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/BoardInitLib/PeiMultiBoardInitPreMemLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPlatformHookLib/PeiPlatformHooklib.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPlatformHookLib/PeiPlatformHooklib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c create mode 100644 Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Libr= ary/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= eFuncLib/BaseFuncLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeUR= vp/Library/BaseFuncLib/BaseFuncLib.inf new file mode 100644 index 0000000000..2dad67a1e5 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLi= b/BaseFuncLib.inf @@ -0,0 +1,33 @@ +## @file +# Component information file for Board Functions Library. +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseBoardFuncInitLib + FILE_GUID =3D 7ad17b6c-b9b6-4d88-85c4-7366a2bd12a3 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + +[LibraryClasses] + BaseLib + DebugLib + +[Packages] + CometlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + Gop.c + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= eFuncLib/Gop.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library= /BaseFuncLib/Gop.c new file mode 100644 index 0000000000..8b8089c3c0 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseFuncLi= b/Gop.c @@ -0,0 +1,41 @@ +/** @file + Others Board's PCD function hook. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +// +// Null function for nothing GOP VBT update. +// +VOID +EFIAPI +GopVbtSpecificUpdateNull ( + IN CHILD_STRUCT **ChildStructPtr + ) +{ + return; +} + +// +// for CFL U DDR4 +// +VOID +EFIAPI +CflUDdr4GopVbtSpecificUpdate( + IN CHILD_STRUCT **ChildStructPtr +) +{ + ChildStructPtr[1]->DeviceClass =3D DISPLAY_PORT_ONLY; + ChildStructPtr[1]->DVOPort =3D DISPLAY_PORT_B; + ChildStructPtr[2]->DeviceClass =3D DISPLAY_PORT_HDMI_DVI_COMPATIBLE; + ChildStructPtr[2]->DVOPort =3D DISPLAY_PORT_C; + ChildStructPtr[2]->AUX_Channel =3D AUX_CHANNEL_C; + ChildStructPtr[3]->DeviceClass =3D NO_DEVICE; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= eGpioCheckConflictLib/BaseGpioCheckConflictLib.c b/Platform/Intel/Cometlake= OpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheckCo= nflictLib.c new file mode 100644 index 0000000000..e42bb7cb91 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh= eckConflictLib/BaseGpioCheckConflictLib.c @@ -0,0 +1,137 @@ +/** @file + Implementation of BaseGpioCheckConflictLib. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Check Gpio PadMode conflict and report it. + + @retval none. +**/ +VOID +GpioCheckConflict ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GpioCheckConflictHob; + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData; + UINT32 HobDataSize; + UINT32 GpioCount; + UINT32 GpioIndex; + GPIO_CONFIG GpioActualConfig; + + GpioCheckConflictHob =3D NULL; + GpioCheckConflictHobData =3D NULL; + + DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n")); + + // + //Use Guid to find HOB. + // + GpioCheckConflictHob =3D (EFI_HOB_GUID_TYPE *) GetFirstGuidHob (&gGpioCh= eckConflictHobGuid); + if (GpioCheckConflictHob =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n")); + } else { + while (GpioCheckConflictHob !=3D NULL) { + // + // Find the Data area pointer and Data size from the Hob + // + GpioCheckConflictHobData =3D (GPIO_PAD_MODE_INFO *) GET_GUID_HOB_DAT= A (GpioCheckConflictHob); + HobDataSize =3D GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob); + + GpioCount =3D HobDataSize / sizeof (GPIO_PAD_MODE_INFO); + DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount =3D %d\n", GpioCou= nt)); + + // + // Probe Gpio entries in Hob and compare which are conflicted + // + for (GpioIndex =3D 0; GpioIndex < GpioCount ; GpioIndex++) { + GpioGetPadConfig (GpioCheckConflictHobData[GpioIndex].GpioPad, &Gp= ioActualConfig); + if (GpioCheckConflictHobData[GpioIndex].GpioPadMode !=3D GpioActua= lConfig.PadMode) { + DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on pad %a= \n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad))); + } + } + // + // Find next Hob and return the Hob pointer by the specific Hob Guid + // + GpioCheckConflictHob =3D GET_NEXT_HOB (GpioCheckConflictHob); + GpioCheckConflictHob =3D GetNextGuidHob (&gGpioCheckConflictHobGuid,= GpioCheckConflictHob); + } + + DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n")); + } + + return; +} + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + + @retval none. +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + + UINT32 Index; + UINT32 GpioIndex; + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData; + UINT16 GpioCount; + + GpioCount =3D 0; + GpioIndex =3D 0; + + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n")); + + for (Index =3D 0; Index < GpioTableCount ; Index++) { + if (GpioDefinition[Index].GpioConfig.PadMode =3D=3D GpioHardwareDefaul= t) { + continue; + } else { + // + // Calculate how big size the Hob Data needs + // + GpioCount++; + } + } + + // + // Build a HOB tagged with a GUID for identification and returns + // the start address of GUID HOB data. + // + GpioCheckConflictHobData =3D (GPIO_PAD_MODE_INFO *) BuildGuidHob (&gGpio= CheckConflictHobGuid , GpioCount * sizeof (GPIO_PAD_MODE_INFO)); + + // + // Record Non Default Gpio entries to the Hob + // + for (Index =3D 0; Index < GpioTableCount; Index++) { + if (GpioDefinition[Index].GpioConfig.PadMode =3D=3D GpioHardwareDefaul= t) { + continue; + } else { + GpioCheckConflictHobData[GpioIndex].GpioPad =3D GpioDefinition[Index= ].GpioPad; + GpioCheckConflictHobData[GpioIndex].GpioPadMode =3D GpioDefinition[I= ndex].GpioConfig.PadMode; + GpioIndex++; + } + } + + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n")); + return; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= eGpioCheckConflictLib/BaseGpioCheckConflictLib.inf b/Platform/Intel/Cometla= keOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLib/BaseGpioCheck= ConflictLib.inf new file mode 100644 index 0000000000..a95faa200f --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh= eckConflictLib/BaseGpioCheckConflictLib.inf @@ -0,0 +1,35 @@ +## @file +# Component information file for BaseGpioCheckConflictLib. +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BaseGpioCheckConflictLib + FILE_GUID =3D C19A848A-F013-4DBF-9C23-F0F74DEA6F14 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D GpioCheckConflictLib + +[LibraryClasses] + DebugLib + HobLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioCheckConflictLib.c + +[Guids] + gGpioCheckConflictHobGuid + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= eGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c b/Platform/Intel/C= ometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/Bas= eGpioCheckConflictLibNull.c new file mode 100644 index 0000000000..525a9b3e0f --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh= eckConflictLibNull/BaseGpioCheckConflictLibNull.c @@ -0,0 +1,37 @@ +/** @file + Implementation of BaseGpioCheckConflicLibNull. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + Check Gpio PadMode conflict and report it. +**/ +VOID +GpioCheckConflict ( + VOID + ) +{ + return; +} + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + return; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= eGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf b/Platform/Intel= /CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCheckConflictLibNull/B= aseGpioCheckConflictLibNull.inf new file mode 100644 index 0000000000..0a028ef0ca --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BaseGpioCh= eckConflictLibNull/BaseGpioCheckConflictLibNull.inf @@ -0,0 +1,32 @@ +## @file +# Component information file for BaseGpioCheckConflictLib. +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BaseGpioCheckConflictLibNull + FILE_GUID =3D C19A848A-F013-4DBF-9C23-F0F74DEA6F14 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D GpioCheckConflictLib + +[LibraryClasses] + DebugLib + HobLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioCheckConflictLibNull.c + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= ePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/CometlakeOpenBoardP= kg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..a80e790a86 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatfo= rmHookLib/BasePlatformHookLib.c @@ -0,0 +1,156 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F + +#define IT8628_ENTER_CONFIG_WRITE_SEQ_0 0x87 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_1 0x01 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_2 0x55 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_3 0x55 +#define IT8628_EXIT_CONFIG 0x2 +#define IT8628_CHIPID_BYTE1 0x86 +#define IT8628_CHIPID_BYTE2 0x28 + +typedef struct { + UINT8 Register; + UINT8 Value; +} EFI_SIO_TABLE; + +// +// IT8628 +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = =3D { + {0x023, 0x09}, // Clock Selection register + {0x007, 0x01}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select + {0x030, 0x01}, // Serial Port 1 Activate + {0x007, 0x02}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select + {0x030, 0x01} // Serial Port 2 Activate +}; + +/** + Check whether the IT8628 SIO present on LPC. If yes, enable its serial p= orts +**/ +STATIC +VOID +It8628SioSerialPortInit ( + VOID + ) +{ + UINT8 ChipId0; + UINT8 ChipId1; + UINT16 LpcIoDecondeRangeSet; + UINT16 LpcIoDecoodeSet; + UINT8 Index; + UINT64 LpcBaseAddr; + + ChipId0 =3D 0; + ChipId1 =3D 0; + LpcIoDecondeRangeSet =3D 0; + LpcIoDecoodeSet =3D 0; + + // + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2= Eh/2Fh. + // + LpcBaseAddr =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + LpcIoDecondeRangeSet =3D (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_= CFG_IOD); + LpcIoDecoodeSet =3D (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_I= OE); + PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet = | ((V_LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8))); + PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | (B_= LPC_CFG_IOE_SE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE))); + + // + // Enter MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_0)= ; + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_1)= ; + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_2)= ; + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_3)= ; + + // + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); + ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); + ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + // + // Enable Serial Port 1, Port 2 + // + if ((ChipId0 =3D=3D IT8628_CHIPID_BYTE1) && (ChipId1 =3D=3D IT8628_CHIPI= D_BYTE2)) { + for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof = (EFI_SIO_TABLE); Index++) { + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[In= dex].Register); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Ind= ex].Value); + } + } + + // + // Exit MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); + + return; +} + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function do= es + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succee= ded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + // + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. + // + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); + + // Configure Sio IT8628 + It8628SioSerialPortInit (); + + return RETURN_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Bas= ePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/CometlakeOpenBoar= dPkg/CometlakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..ca723a92cb --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BasePlatfo= rmHookLib/BasePlatformHookLib.inf @@ -0,0 +1,53 @@ +## @file +# Platform Hook Library instance for Cometlake Mobile/Desktop CRB. +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BasePlatformHookLib + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PlatformHookLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciSegmentLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU= MES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUME= S + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUME= S + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSU= MES + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSU= MES + +[FixedPcd] + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding #= # CONSUMES + +[Sources] + BasePlatformHookLib.c + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Co= metlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..a1ed0230ed --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL= ib/SmmBoardAcpiEnableLib.c @@ -0,0 +1,63 @@ +/** @file + Comet Lake U LP3 SMM Board ACPI Enable library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +CometlakeURvpBoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return CometlakeURvpBoardEnableAcpi(EnableSci); +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return CometlakeURvpBoardDisableAcpi(DisableSci); +} + + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/= CometlakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..d67ac1885c --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL= ib/SmmBoardAcpiEnableLib.inf @@ -0,0 +1,50 @@ +## @file +# Comet Lake U LP3 SMM Board ACPI Enable library +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmBoardAcpiEnableLib + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUM= ES + +[Protocols] + +[Sources] + SmmCometlakeURvpAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdAcpiLib/SmmCometlakeURvpAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoa= rdPkg/CometlakeURvp/Library/BoardAcpiLib/SmmCometlakeURvpAcpiEnableLib.c new file mode 100644 index 0000000000..b0d431a08c --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL= ib/SmmCometlakeURvpAcpiEnableLib.c @@ -0,0 +1,40 @@ +/** @file + Comet Lake LP3 SMM Board ACPI Enable library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +CometlakeURvpBoardEnableAcpi( + IN BOOLEAN EnableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDisableAcpi( + IN BOOLEAN DisableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/CometlakeOpenBoard= Pkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c new file mode 100644 index 0000000000..e0d8645f29 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL= ib/SmmMultiBoardAcpiSupportLib.c @@ -0,0 +1,82 @@ +/** @file + Comet Lake U LP3 SMM Multi-Board ACPI Support library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +CometlakeURvpBoardEnableAcpi( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDisableAcpi( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +CometlakeURvpMultiBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return CometlakeURvpBoardEnableAcpi(EnableSci); +} + +EFI_STATUS +EFIAPI +CometlakeURvpMultiBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return CometlakeURvpBoardDisableAcpi(DisableSci); +} + +BOARD_ACPI_ENABLE_FUNC mCometlakeURvpBoardAcpiEnableFunc =3D { + CometlakeURvpMultiBoardEnableAcpi, + CometlakeURvpMultiBoardDisableAcpi, +}; + +EFI_STATUS +EFIAPI +SmmCometlakeURvpMultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () =3D=3D BoardIdCometLakeULpddr3Rvp) { + return RegisterBoardAcpiEnableFunc (&mCometlakeURvpBoardAcpiEnableFunc= ); + } + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/CometlakeOpenBoa= rdPkg/CometlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf new file mode 100644 index 0000000000..b23485be2b --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL= ib/SmmMultiBoardAcpiSupportLib.inf @@ -0,0 +1,50 @@ +## @file +# Comet Lake U LP3 SMM Multi-Board ACPI Support library +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmCometlakeURvpMultiBoardAcpiSupport= Lib + FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D SmmCometlakeURvpMultiBoardAcpiSupport= LibConstructor + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + PmcLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUM= ES + +[Protocols] + +[Sources] + SmmCometlakeURvpAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmMultiBoardAcpiSupportLib.c + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/CometlakeOpenBoardPkg/= CometlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..ffa8738d6b --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardAcpiL= ib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,170 @@ +/** @file + Comet Lake U LP3 SMM Silicon ACPI Enable library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + + UINT32 OutputValue; + UINT32 SmiEn; + UINT32 SmiSts; + UINT32 ULKMC; + UINTN LpcBaseAddress; + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + // + // Get the ACPI Base Address + // + AcpiBaseAddr =3D PmcGetAcpiBase(); + // + // BIOS must also ensure that CF9GR is cleared and locked before handing= control to the + // OS in order to prevent the host from issuing global resets and resett= ing ME + // + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Res= et + // MmioWrite32 ( + // PmcBaseAddress + R_PCH_PMC_ETR3), + // PmInit); + + // + // Clear Port 80h + // + IoWrite8 (0x80, 0); + + // + // Disable SW SMI Timer and clean the status + // + SmiEn =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN); + SmiEn &=3D ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |= B_ACPI_IO_SMI_EN_LEGACY_USB); + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn); + + SmiSts =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS); + SmiSts |=3D B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | = B_ACPI_IO_SMI_EN_LEGACY_USB; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts); + + // + // Disable port 60/64 SMI trap if they are enabled + // + ULKMC =3D MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_UL= KMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC= _64WEN | B_LPC_CFG_ULKMC_A20PASSEN); + MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC); + + // + // Disable PM sources except power button + // + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN); + + // + // Clear PM status except Power Button status for RapidStart Resume + // + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF); + + // + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + // + IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD); + IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0); + + // + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#) + // + OutputValue =3D IoRead32 (AcpiBaseAddr + 0x38); + OutputValue =3D OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPos= ition)); + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue); + + // + // Enable SCI + // + if (EnableSci) { + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); + Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + // + // Get the ACPI Base Address + // + AcpiBaseAddr =3D PmcGetAcpiBase(); + // + // Disable SCI + // + if (DisableSci) { + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardFunc.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/= Library/BoardInitLib/BoardFunc.c new file mode 100644 index 0000000000..fa6a186045 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardFunc.c @@ -0,0 +1,19 @@ +/** @file + Board's PCD function hook. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +EFI_STATUS +PeiBoardSpecificInitPostMemNull ( + VOID + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardFunc.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/= Library/BoardInitLib/BoardFunc.h new file mode 100644 index 0000000000..9e8930755d --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardFunc.h @@ -0,0 +1,20 @@ +/** @file + Header file for Board Hook function intance. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_FUNC_H_ +#define _BOARD_FUNC_H_ + +#include + +EFI_STATUS +PeiBoardSpecificInitPostMemNull ( + VOID + ); + +#endif // _BOARD_FUNC_H_ + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardFuncInit.c b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeU= Rvp/Library/BoardInitLib/BoardFuncInit.c new file mode 100644 index 0000000000..43896af760 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardFuncInit.c @@ -0,0 +1,26 @@ +/** @file + Source code for the board configuration init function in Post Memory ini= t phase. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardFunc.h" + +/** + Board's PCD function hook init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardFunctionInit ( + IN UINT16 BoardId +) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardFuncInitPreMem.c b/Platform/Intel/CometlakeOpenBoardPkg/Come= tlakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c new file mode 100644 index 0000000000..6181cf45ff --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardFuncInitPreMem.c @@ -0,0 +1,40 @@ +/** @file + Source code for the board configuration init function in Post Memory ini= t phase. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +// +// Null function for nothing GOP VBT update. +// +VOID +GopVbtSpecificUpdateNull( + IN CHILD_STRUCT **ChildStructPtr +); +// +// for CFL U DDR4 +// +VOID +CflUDdr4GopVbtSpecificUpdate( + IN CHILD_STRUCT **ChildStructPtr +); +/** + Board's PCD function hook init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardFunctionInitPreMem ( + IN UINT16 BoardId + ) +{ + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardInitLib.h b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeUR= vp/Library/BoardInitLib/BoardInitLib.h new file mode 100644 index 0000000000..758cbaa0b6 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardInitLib.h @@ -0,0 +1,20 @@ +/** @file + Header file for board Init function for Post Memory Init phase. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_LIB_H_ +#define _PEI_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include + +#endif // _PEI_BOARD_INIT_LIB_H_ + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Co= metlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c new file mode 100644 index 0000000000..f9e7aeecb9 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardPchInitPreMemLib.c @@ -0,0 +1,398 @@ +/** @file + Source code for the board PCH configuration Pcd init functions for Pre-Me= mory Init phase. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "CometlakeURvpInit.h" +#include +#include +#include // for USB 20 AFE & Root Port Clk = Info. +#include +#include + +/** + Board Root Port Clock Info configuration init function for PEI pre-memor= y phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +RootPortClkInfoInit ( + IN UINT16 BoardId + ) +{ + PCD64_BLOB *Clock; + UINT32 Index; + + Clock =3D AllocateZeroPool (16 * sizeof (PCD64_BLOB)); + ASSERT (Clock !=3D NULL); + if (Clock =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + // + // The default clock assignment will be FREE_RUNNING, which corresponds = to PchClockUsageUnspecified + // This is safe but power-consuming setting. If Platform code doesn't co= ntain port-clock map for a given board, + // the clocks will keep on running anyway, allowing PCIe devices to oper= ate. Downside is that clocks will + // continue to draw power. To prevent this, remember to provide port-clo= ck map for every board. + // + for (Index =3D 0; Index < 16; Index++) { + Clock[Index].PcieClock.ClkReqSupported =3D TRUE; + Clock[Index].PcieClock.ClockUsage =3D FREE_RUNNING; + } + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. + /// + switch (BoardId) { + // CLKREQ + case BoardIdCometLakeULpddr3Rvp: + Clock[0].PcieClock.ClockUsage =3D PCIE_PCH + 1; + Clock[1].PcieClock.ClockUsage =3D PCIE_PCH + 8; + Clock[2].PcieClock.ClockUsage =3D LAN_CLOCK; + Clock[3].PcieClock.ClockUsage =3D PCIE_PCH + 13; + Clock[4].PcieClock.ClockUsage =3D PCIE_PCH + 4; + Clock[5].PcieClock.ClockUsage =3D PCIE_PCH + 14; + break; + + default: + break; + } + + PcdSet64S (PcdPcieClock0, Clock[ 0].Blob); + PcdSet64S (PcdPcieClock1, Clock[ 1].Blob); + PcdSet64S (PcdPcieClock2, Clock[ 2].Blob); + PcdSet64S (PcdPcieClock3, Clock[ 3].Blob); + PcdSet64S (PcdPcieClock4, Clock[ 4].Blob); + PcdSet64S (PcdPcieClock5, Clock[ 5].Blob); + PcdSet64S (PcdPcieClock6, Clock[ 6].Blob); + PcdSet64S (PcdPcieClock7, Clock[ 7].Blob); + PcdSet64S (PcdPcieClock8, Clock[ 8].Blob); + PcdSet64S (PcdPcieClock9, Clock[ 9].Blob); + PcdSet64S (PcdPcieClock10, Clock[10].Blob); + PcdSet64S (PcdPcieClock11, Clock[11].Blob); + PcdSet64S (PcdPcieClock12, Clock[12].Blob); + PcdSet64S (PcdPcieClock13, Clock[13].Blob); + PcdSet64S (PcdPcieClock14, Clock[14].Blob); + PcdSet64S (PcdPcieClock15, Clock[15].Blob); + + return EFI_SUCCESS; +} + +/** + Board USB related configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +UsbConfigInit ( + IN UINT16 BoardId + ) +{ + PCD32_BLOB *UsbPort20Afe; + + UsbPort20Afe =3D AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof (PCD32_BL= OB)); + ASSERT (UsbPort20Afe !=3D NULL); + if (UsbPort20Afe =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // USB2 AFE settings. + // + UsbPort20Afe[0].Info.Petxiset =3D 7; + UsbPort20Afe[0].Info.Txiset =3D 5; + UsbPort20Afe[0].Info.Predeemp =3D 3; + UsbPort20Afe[0].Info.Pehalfbit =3D 0; + + UsbPort20Afe[1].Info.Petxiset =3D 7; + UsbPort20Afe[1].Info.Txiset =3D 5; + UsbPort20Afe[1].Info.Predeemp =3D 3; + UsbPort20Afe[1].Info.Pehalfbit =3D 0; + + UsbPort20Afe[2].Info.Petxiset =3D 7; + UsbPort20Afe[2].Info.Txiset =3D 5; + UsbPort20Afe[2].Info.Predeemp =3D 3; + UsbPort20Afe[2].Info.Pehalfbit =3D 0; + + UsbPort20Afe[3].Info.Petxiset =3D 7; + UsbPort20Afe[3].Info.Txiset =3D 5; + UsbPort20Afe[3].Info.Predeemp =3D 3; + UsbPort20Afe[3].Info.Pehalfbit =3D 0; + + UsbPort20Afe[4].Info.Petxiset =3D 7; + UsbPort20Afe[4].Info.Txiset =3D 5; + UsbPort20Afe[4].Info.Predeemp =3D 3; + UsbPort20Afe[4].Info.Pehalfbit =3D 0; + + UsbPort20Afe[5].Info.Petxiset =3D 7; + UsbPort20Afe[5].Info.Txiset =3D 5; + UsbPort20Afe[5].Info.Predeemp =3D 3; + UsbPort20Afe[5].Info.Pehalfbit =3D 0; + + UsbPort20Afe[6].Info.Petxiset =3D 7; + UsbPort20Afe[6].Info.Txiset =3D 5; + UsbPort20Afe[6].Info.Predeemp =3D 3; + UsbPort20Afe[6].Info.Pehalfbit =3D 0; + + UsbPort20Afe[7].Info.Petxiset =3D 7; + UsbPort20Afe[7].Info.Txiset =3D 5; + UsbPort20Afe[7].Info.Predeemp =3D 3; + UsbPort20Afe[7].Info.Pehalfbit =3D 0; + + UsbPort20Afe[8].Info.Petxiset =3D 7; + UsbPort20Afe[8].Info.Txiset =3D 5; + UsbPort20Afe[8].Info.Predeemp =3D 3; + UsbPort20Afe[8].Info.Pehalfbit =3D 0; + + UsbPort20Afe[9].Info.Petxiset =3D 7; + UsbPort20Afe[9].Info.Txiset =3D 5; + UsbPort20Afe[9].Info.Predeemp =3D 3; + UsbPort20Afe[9].Info.Pehalfbit =3D 0; + + // + // USB Port Over Current Pin + // + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax); + + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax); + + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip); + + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip); + + // USB2.0 AFE settings + UsbPort20Afe[0].Info.Petxiset =3D 4; + UsbPort20Afe[0].Info.Txiset =3D 0; + UsbPort20Afe[0].Info.Predeemp =3D 3; + UsbPort20Afe[0].Info.Pehalfbit =3D 0; + + UsbPort20Afe[1].Info.Petxiset =3D 4; + UsbPort20Afe[1].Info.Txiset =3D 0; + UsbPort20Afe[1].Info.Predeemp =3D 3; + UsbPort20Afe[1].Info.Pehalfbit =3D 0; + + UsbPort20Afe[2].Info.Petxiset =3D 4; + UsbPort20Afe[2].Info.Txiset =3D 0; + UsbPort20Afe[2].Info.Predeemp =3D 3; + UsbPort20Afe[2].Info.Pehalfbit =3D 0; + + UsbPort20Afe[3].Info.Petxiset =3D 4; + UsbPort20Afe[3].Info.Txiset =3D 0; + UsbPort20Afe[3].Info.Predeemp =3D 3; + UsbPort20Afe[3].Info.Pehalfbit =3D 0; + + UsbPort20Afe[4].Info.Petxiset =3D 4; + UsbPort20Afe[4].Info.Txiset =3D 0; + UsbPort20Afe[4].Info.Predeemp =3D 3; + UsbPort20Afe[4].Info.Pehalfbit =3D 0; + + UsbPort20Afe[5].Info.Petxiset =3D 4; + UsbPort20Afe[5].Info.Txiset =3D 0; + UsbPort20Afe[5].Info.Predeemp =3D 3; + UsbPort20Afe[5].Info.Pehalfbit =3D 0; + + UsbPort20Afe[6].Info.Petxiset =3D 4; + UsbPort20Afe[6].Info.Txiset =3D 0; + UsbPort20Afe[6].Info.Predeemp =3D 3; + UsbPort20Afe[6].Info.Pehalfbit =3D 0; + + UsbPort20Afe[7].Info.Petxiset =3D 4; + UsbPort20Afe[7].Info.Txiset =3D 0; + UsbPort20Afe[7].Info.Predeemp =3D 3; + UsbPort20Afe[7].Info.Pehalfbit =3D 0; + + UsbPort20Afe[8].Info.Petxiset =3D 4; + UsbPort20Afe[8].Info.Txiset =3D 0; + UsbPort20Afe[8].Info.Predeemp =3D 3; + UsbPort20Afe[8].Info.Pehalfbit =3D 0; + + UsbPort20Afe[9].Info.Petxiset =3D 4; + UsbPort20Afe[9].Info.Txiset =3D 0; + UsbPort20Afe[9].Info.Predeemp =3D 3; + UsbPort20Afe[9].Info.Pehalfbit =3D 0; + break; + } + + // + // Save USB2.0 AFE blobs + // + PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob); + PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob); + PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob); + PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob); + PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob); + PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob); + PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob); + PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob); + PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob); + PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob); + PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob); + PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob); + PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob); + PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob); + PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob); + PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob); + + return EFI_SUCCESS; +} + +/** + Board GPIO Group Tier configuration init function for PEI pre-memory pha= se. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +GpioGroupTierInit ( + IN UINT16 BoardId + ) +{ + // + // GPIO Group Tier + // + + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + PcdSet32S (PcdGpioGroupToGpeDw0, GPIO_CNL_LP_GROUP_GPP_G); + PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI); + PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E); + break; + + default: + PcdSet32S (PcdGpioGroupToGpeDw0, 0); + PcdSet32S (PcdGpioGroupToGpeDw1, 0); + PcdSet32S (PcdGpioGroupToGpeDw2, 0); + break; + } + + return EFI_SUCCESS; +} + +/** + GPIO init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +GpioTablePreMemInit ( + IN UINT16 BoardId + ) +{ + // + // GPIO Table Init. + // + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableCmlULpddr3PreM= em); + PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTableCmlULpddr3PreMemSi= ze); + PcdSet32S(PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableCmlU= Lpddr3WwanOnEarlyPreMem); + PcdSet16S(PcdBoardGpioTableWwanOnEarlyPreMemSize, mGpioTableCmlULpdd= r3WwanOnEarlyPreMemSize); + PcdSet32S(PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableCml= ULpddr3WwanOffEarlyPreMem); + PcdSet16S(PcdBoardGpioTableWwanOffEarlyPreMemSize, mGpioTableCmlULpd= dr3WwanOffEarlyPreMemSize); + break; + + default: + break; + } + + return EFI_SUCCESS; +} + +/** + PmConfig init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +PchPmConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when SLP_S0= # is asserted based on board HW design + // 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport) + // 2) Premium PMIC: runtime control for voltage (PcdSlpS0VmRuntimeContro= l) + // Only applys to board with PCH-LP. Board with Discrete PCH doesn't nee= d this setting. + // + switch (BoardId) { + // Discrete VR solution + case BoardIdCometLakeULpddr3Rvp: + PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE); + PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE); + PcdSetBoolS (PcdSlpS0Vm075VSupport, TRUE); + break; + + default: + PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE); + PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE); + PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE); + break; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardSaConfigPreMem.h b/Platform/Intel/CometlakeOpenBoardPkg/Come= tlakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h new file mode 100644 index 0000000000..9ab340c7e1 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardSaConfigPreMem.h @@ -0,0 +1,83 @@ +/** @file + PEI Boards Configurations for PreMem phase. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_ +#define _BOARD_SA_CONFIG_PRE_MEM_H_ + +#include +#include // for MRC Configurati= on +#include // for PCIE RTD3 GPIO +#include // for GPIO definition +#include +#include // for Root Port numbe= r +#include // for Root Port numbe= r + +// +// The following section contains board-specific CMD/CTL/CLK and DQ/DQS ma= pping, needed for LPDDR3/LPDDR4 +// + +// +// DQByteMap[0] - ClkDQByteMap: +// If clock is per rank, program to [0xFF, 0xFF] +// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] +// If clock is shared by 2 ranks but does not go to all bytes, +// Entry[i] defines which DQ bytes Group i services +// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN= /CAB +// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS= /CAB +// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE = /CAB +// For DDR, DQByteMap[3:1] =3D [0xFF, 0] +// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have= 1 CTL / rank +// Variable only exists to make the code eas= ier to use +// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have= 1 CA Vref +// Variable only exists to make the code eas= ier to use +// +// +// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for BoardIdCometLak= eULpddr3Rvp +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapCmlULpddr3Rvp[2][6][2] = =3D { + // Channel 0: + { + { 0xF0, 0x0F }, + { 0x00, 0x0F }, + { 0xF0, 0x0F }, + { 0xF0, 0x00 }, + { 0xFF, 0x00 }, + { 0xFF, 0x00 } + }, + // Channel 1: + { + { 0x0F, 0xF0 }, + { 0x00, 0xF0 }, + { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, + { 0xFF, 0x00 }, + { 0xFF, 0x00 } + } +}; + +// +// DQS byte swizzling between CPU and DRAM - for CML-U LPDDR3 RVP +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqsMapCpu2DramCmlULpddr3Rvp[2][8= ] =3D { + { 5, 6, 7, 4, 1, 0, 2, 3 }, // Channel 0 + { 2, 3, 1, 0, 6, 4, 5, 7 } // Channel 1 +}; + + +// +// Reference RCOMP resistors on motherboard - for CML-U LPDDR3 RVP +// +const UINT16 RcompResistorCmlULpKc[SA_MRC_MAX_RCOMP] =3D { 200, 81, 162 }; + +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for CM= L-U LPDDR3 RVP +// +const UINT16 RcompTargetCmlULpKc[SA_MRC_MAX_RCOMP_TARGETS] =3D { 100, 40, = 40, 23, 40 }; + +#endif // _BOARD_SA_CONFIG_PRE_MEM_H_ + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Com= etlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c new file mode 100644 index 0000000000..3d5fce20d9 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/BoardSaInitPreMemLib.c @@ -0,0 +1,383 @@ +/** @file + Source code for the board SA configuration Pcd init functions in Pre-Memo= ry init phase. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardSaConfigPreMem.h" +#include "SaPolicyCommon.h" +#include "CometlakeURvpInit.h" +#include +#include +// +// LPDDR3 178b 8Gb die, DDP, x32 +// Micron MT52L512M32D2PF-093 +// 2133, 16-20-20-45 +// 2 ranks per channel, 2 SDRAMs per rank, 4x8Gb =3D 4GB total per channel +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr3Ddp8Gb178b2133Spd[] =3D { + 0x24, // 512 SPD bytes used, 512 total + 0x01, // SPD Revision 0.1 + 0x0F, // DRAM Type: LPDDR3 SDRAM + 0x0E, // Module Type: Non-DIMM Solution + 0x15, // 8 Banks, 8 Gb SDRAM density + 0x19, // 15 Rows, 10 Columns + 0x90, // SDRAM Package Type: DDP, 1 Channel per package + 0x00, // SDRAM Optional Features: none, tMAW =3D 8192 * tREFI + 0x00, // SDRAM Thermal / Refresh options: none + 0x00, // Other SDRAM Optional Features: none + 0x00, // Reserved + 0x0B, // Module Nominal Voltage, VDD =3D 1.2v + 0x0B, // SDRAM width: 32 bits, 2 Ranks + 0x03, // SDRAM bus width: 1 Channel, 64 bits channel width + 0x00, // Module Thermal Sensor: none + 0x00, // Extended Module Type: Reserved + 0x00, // Signal Loading: Unspecified + 0x00, // MTB =3D 0.125ns, FTB =3D 1 ps + 0x08, // tCKmin =3D 0.938 ns (LPDDR3-2133) + 0xFF, // tCKmax =3D 32.002 ns + 0xD4, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (First Byte) + 0x01, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Second Byte) + 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Third Byte) + 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Fourth Byte) + 0x78, // Minimum CAS Latency (tAAmin) =3D 15.008 ns + 0x00, // Read and Write Latency Set options: none + 0x90, // Minimum RAS-to-CAS delay (tRCDmin) =3D 18 ns + 0xA8, // Row precharge time for all banks (tRPab) =3D 21 ns + 0x90, // Minimum row precharge time (tRPmin) =3D 18 ns + 0x90, // tRFCab =3D 210 ns (8 Gb) + 0x06, // tRFCab MSB + 0xD0, // tRFCpb =3D 90 ns (8 Gb) + 0x02, // tRFCpb MSB + 0, 0, 0, 0, 0, 0, 0, // 33-39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 40-49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 50-59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 60-69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 70-79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 80-89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 90-99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 100-109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 110-119 + 0x00, // FTB for Row precharge time per bank (tR= Ppb) =3D 18 ns + 0x00, // FTB for Row precharge time for all bank= s (tRPab) =3D 21 ns + 0x00, // FTB for Minimum RAS-to-CAS delay (tRCDm= in) =3D 18 ns + 0x08, // FTB for tAAmin =3D 15.008 ns (LPDDR3-21= 33) + 0x7F, // FTB for tCKmax =3D 32.002 ns + 0xC2, // FTB for tCKmin =3D 0.938 ns (LPDDR3-213= 3) + 0, 0, 0, 0, // 126-129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 130-139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 140-149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 150-159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 160-169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 170-179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 180-189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 190-199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 200-209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 210-219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 220-229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 230-239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 240-249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 250-259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 260-269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 270-279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 280-289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 290-299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 300-309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 310-319 + 0, 0, 0, 0, 0, // 320-324 + 0x55, 0, 0, 0, // 325-328: Module ID: Module Serial Numbe= r + 0x20, 0x20, 0x20, 0x20, 0x20, // 329-333: Module Part Number: Unused byt= es coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, // 334-338: Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, // 339-343: Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, // 344-348: Module Part Number + 0x00, // 349 Module Revision Code + 0x00, // 350 DRAM Manufacturer ID Code, Least Si= gnificant Byte + 0x00, // 351 DRAM Manufacturer ID Code, Most Sig= nificant Byte + 0x00, // 352 DRAM Stepping + 0, 0, 0, 0, 0, 0, 0, // 353 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 430 - 439 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 440 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 500 - 509 + 0, 0 // 510 - 511 +}; + +// +// Display DDI settings for WHL ERB +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] = =3D { + DdiPortAEdp, // DDI Port A Config : DdiPortADisabled =3D Disabled, D= diPortAEdp =3D eDP, DdiPortAMipiDsi =3D MIPI DSI + DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiDdcEnable, // DDI Port B DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC + DdiDdcEnable, // DDI Port C DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC + DdiDdcEnable, // DDI Port D DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC + DdiDisable // DDI Port F DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC +}; + +/** + MRC configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id= . + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaMiscConfigInit ( + IN UINT16 BoardId + ) +{ + // + // UserBd + // + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + // + // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUs= er4 for ULT platforms. + // This is required to skip Memory voltage programming based on GPIO= 's in MRC + // + PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platf= orm + break; + + default: + // MiscPeiPreMemConfig.UserBd =3D 0 by default. + break; + } + + PcdSet16S (PcdSaDdrFreqLimit, 0); + + return EFI_SUCCESS; +} + +/** + Board Memory Init related configuration init function for PEI pre-memory= phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +MrcConfigInit ( + IN UINT16 BoardId + ) +{ + CPU_FAMILY CpuFamilyId; + + CpuFamilyId =3D GetCpuFamily(); + + if (CpuFamilyId =3D=3D EnumCpuCflDtHalo) { + PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE); + } else { + PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE); + } + + // + // Example policy for DIMM slots implementation boards: + // 1. Assign Smbus address of DIMMs and SpdData will be updated later + // by reading from DIMM SPD. + // 2. No need to apply hardcoded SpdData buffers here for such board. + // + // Comet Lake U LP3 has removable DIMM slots. + // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to = 0. + // Example: + // PcdMrcSpdData =3D 0 + // PcdMrcSpdDataSize =3D 0 + // PcdMrcSpdAddressTable0 =3D 0xA0 + // PcdMrcSpdAddressTable1 =3D 0xA2 + // PcdMrcSpdAddressTable2 =3D 0xA4 + // PcdMrcSpdAddressTable3 =3D 0xA6 + // + // If a board has soldered down memory. It should use the following set= tings. + // Example: + // PcdMrcSpdAddressTable0 =3D 0 + // PcdMrcSpdAddressTable1 =3D 0 + // PcdMrcSpdAddressTable2 =3D 0 + // PcdMrcSpdAddressTable3 =3D 0 + // PcdMrcSpdData =3D static data buffer + // PcdMrcSpdDataSize =3D sizeof (static data buffer) + // + + // + // SPD Address Table + // + PcdSet32S (PcdMrcSpdData, (UINTN)mLpddr3Ddp8Gb178b2133Spd); + PcdSet16S (PcdMrcSpdDataSize, sizeof(mLpddr3Ddp8Gb178b2133Spd)); + PcdSet8S (PcdMrcSpdAddressTable0, 0); + PcdSet8S (PcdMrcSpdAddressTable1, 0); + PcdSet8S (PcdMrcSpdAddressTable2, 0); + PcdSet8S (PcdMrcSpdAddressTable3, 0); + + // + // DRAM SPD Data & related configuration + // + // Setting the PCD's to default value (CML LP3). It will be overriden to= board specific settings below. + PcdSet32S(PcdMrcDqByteMap, (UINTN) DqByteMapCmlULpddr3Rvp); + PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapCmlULpddr3Rvp)); + PcdSet32S(PcdMrcDqsMapCpu2Dram, (UINTN) DqsMapCpu2DramCmlULpddr3Rvp); + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (DqsMapCpu2DramCmlULpddr3Rvp= )); + + switch (BoardId) { + + case BoardIdCometLakeULpddr3Rvp: + PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorCmlULpKc); + PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetCmlULpKc); + PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE); + PcdSetBoolS(PcdMrcDqPinsInterleaved, FALSE); + break; + + default: + break; + } + + // + // CA Vref routing: board-dependent + // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L) + // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used) + // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4) + // + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards + break; + + default: + PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards + break; + } + + return EFI_SUCCESS; +} + +/** + Board SA related GPIO configuration init function for PEI pre-memory pha= se. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaGpioConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update board's GPIO for PEG slot reset + // + PcdSetBoolS (PcdPegGpioResetControl, TRUE); + PcdSetBoolS (PcdPegGpioResetSupoort, FALSE); + PcdSet32S (PcdPeg0ResetGpioPad, 0); + PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE); + PcdSet32S (PcdPeg3ResetGpioPad, 0); + PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE); + + // + // PCIE RTD3 GPIO + // + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + PcdSet8S(PcdRootPortIndex, 4); + PcdSet8S (PcdPcie0GpioSupport, PchGpio); + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15); + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie1GpioSupport, NotSupported); + PcdSet32S (PcdPcie1WakeGpioNo, 0); + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie1HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE); + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie2GpioSupport, NotSupported); + PcdSet32S (PcdPcie2WakeGpioNo, 0); + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie2HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE); + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE); + break; + + default: + PcdSet8S(PcdRootPortIndex, 0xFF); + PcdSet8S (PcdPcie0GpioSupport, NotSupported); + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie1GpioSupport, NotSupported); + PcdSet32S (PcdPcie1WakeGpioNo, 0); + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie1HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE); + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie2GpioSupport, NotSupported); + PcdSet32S (PcdPcie2WakeGpioNo, 0); + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie2HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE); + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE); + break; + } + + return EFI_SUCCESS; +} + +/** + SA Display DDI configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaDisplayConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update Display DDI Config + // + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConf= ig); + PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdi= Config)); + break; + + default: + break; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/CometlakeURvpHsioPtssTables.c b/Platform/Intel/CometlakeOpenBoard= Pkg/CometlakeURvp/Library/BoardInitLib/CometlakeURvpHsioPtssTables.c new file mode 100644 index 0000000000..15fc18c7ae --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/CometlakeURvpHsioPtssTables.c @@ -0,0 +1,32 @@ +/** @file + CometlakeURvp HSIO PTSS H File + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef COMETLAKE_RVP3_HSIO_PTSS_H_ +#define COMETLAKE_RVP3_HSIO_PTSS_H_ + +#include + +#ifndef HSIO_PTSS_TABLE_SIZE +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size =3D sizeof (A) / sizeof (HSIO_PTS= S_TABLES) +#endif + +//BoardId CometlakeURvp +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_CometlakeURvp[] =3D { + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0} +}; + +UINT16 PchLpHsioPtss_Cx_CometlakeURvp_Size =3D sizeof(PchLpHsioPtss_Cx_Com= etlakeURvp) / sizeof(HSIO_PTSS_TABLES); + +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_CometlakeURvp[] =3D { + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0}, +}; + +UINT16 PchLpHsioPtss_Bx_CometlakeURvp_Size =3D sizeof(PchLpHsioPtss_Bx_Com= etlakeURvp) / sizeof(HSIO_PTSS_TABLES); + +#endif // COMETLAKE_RVP_HSIO_PTSS_H_ + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/CometlakeURvpInit.h b/Platform/Intel/CometlakeOpenBoardPkg/Cometl= akeURvp/Library/BoardInitLib/CometlakeURvpInit.h new file mode 100644 index 0000000000..cbfa60907c --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/CometlakeURvpInit.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _COMET_LAKE_U_RVP_INIT_H_ +#define _COMET_LAKE_U_RVP_INIT_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_CometlakeURvp[]; +extern UINT16 PchLpHsioPtss_Bx_CometlakeURvp_Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_CometlakeURvp[]; +extern UINT16 PchLpHsioPtss_Cx_CometlakeURvp_Size; + + +extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3PreMem[]; +extern UINT16 mGpioTableCmlULpddr3PreMemSize; +extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOnEarlyPreMem[]; +extern UINT16 mGpioTableCmlULpddr3WwanOnEarlyPreMemSize; +extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOffEarlyPreMem[]; +extern UINT16 mGpioTableCmlULpddr3WwanOffEarlyPreMemSize; + +extern GPIO_INIT_CONFIG mGpioTableDefault[]; +extern UINT16 mGpioTableDefaultSize; +extern GPIO_INIT_CONFIG mGpioTableCmlULpddr3[]; +extern UINT16 mGpioTableCmlULpddr3Size; + +#endif // _COMET_LAKE_U_LP3_INIT_H_ + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/GpioTableCmlUlpddr3PreMem.c b/Platform/Intel/CometlakeOpenBoardPk= g/CometlakeURvp/Library/BoardInitLib/GpioTableCmlUlpddr3PreMem.c new file mode 100644 index 0000000000..9becd139e6 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/GpioTableCmlUlpddr3PreMem.c @@ -0,0 +1,43 @@ +/** @file + GPIO definition table for Comet Lake U LP3 RVP Pre-Memory + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +GPIO_INIT_CONFIG mGpioTableCmlULpddr3PreMem[] =3D +{ + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R= ST_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_P= WREN_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_PWREN_N +}; +UINT16 mGpioTableCmlULpddr3PreMemSize =3D sizeof (mGpioTableCmlULpddr3PreM= em) / sizeof (GPIO_INIT_CONFIG); + +GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOnEarlyPreMem[] =3D +{ + // Turn on WWAN power and de-assert reset pins by default + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock}}, //WWAN_WAKE_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_FCP_OFF + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_PERST + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_DISABLE_N +}; +UINT16 mGpioTableCmlULpddr3WwanOnEarlyPreMemSize =3D sizeof(mGpioTableCmlU= Lpddr3WwanOnEarlyPreMem) / sizeof(GPIO_INIT_CONFIG); + + +GPIO_INIT_CONFIG mGpioTableCmlULpddr3WwanOffEarlyPreMem[] =3D +{ + // Assert reset pins and then turn off WWAN power + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_PERST + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS +}; +UINT16 mGpioTableCmlULpddr3WwanOffEarlyPreMemSize =3D sizeof(mGpioTableCml= ULpddr3WwanOffEarlyPreMem) / sizeof(GPIO_INIT_CONFIG); diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/GpioTableCometlakeULpddr3Rvp.c b/Platform/Intel/CometlakeOpenBoar= dPkg/CometlakeURvp/Library/BoardInitLib/GpioTableCometlakeULpddr3Rvp.c new file mode 100644 index 0000000000..a0b466ba01 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/GpioTableCometlakeULpddr3Rvp.c @@ -0,0 +1,254 @@ +/** @file + GPIO definition table for Comet Lake U LP3 RVP + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include +#include + +GPIO_INIT_CONFIG mGpioTableCmlULpddr3[] =3D +{ +// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, = GPIRoutConfig, PadRstCfg, Term, + //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_0 + //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_1 + //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_CSB + //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPPC_A6_SERIRQ + // TPM interrupt + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K,= GpioPadConfigUnlock }}, //SPI_TPM_INT_N + //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwn= Gpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //eSPI_CLK + //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTer= mNone }}, + //{GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= Inv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTe= rmWpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N + // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, Gp= ioTermNone }}, //SLATEMODE_HALLOUT + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL= _SLOT1 + //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOw= nGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRese= t, GpioTermNone }}, //eSPI_Reset + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SP= KR_PD_N + //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SD_PWREN + //A18-A23 -> Under GPIO table for GPIO Termination -20K WPU + {GPIO_CNL_LP_GPP_A18, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //ACCEL_INT + {GPIO_CNL_LP_GPP_A19, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //ALS_INT + {GPIO_CNL_LP_GPP_A20, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //HUMAN_PRESENCE_INT + {GPIO_CNL_LP_GPP_A21, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //HALL_SENSOR_INT + {GPIO_CNL_LP_GPP_A22, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //IVCAM_WAKE + {GPIO_CNL_LP_GPP_A23, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //SHARED_INT + //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, Gp= ioPadUnlock }}, //FORCE_PAD_INT + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi= oOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioOutputStateUnlo= ck} }, //BT_DISABLE_N + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WWAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_NAND_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //LAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WLAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_SLOT1_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PM_SLP_S0_N + //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PLT_RST_N + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_= PWR_EN + //B15 -Unused pin -> Under GPIO table for GPIO Termination - Input sensi= ng disable + {GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, G= pioPadConfigUnlock } }, //FPS_INT_N + {GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock= } }, //FPS_RESET_N + // B15 -Unused pin -> No Reboot Straps + //{GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, // NO_REBOOT + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CS_FPS + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CLK_FPS + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MISO_FPS + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MOSI_FPS + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone, GpioPa= dUnlock }}, //EC_SLP_S0_CS_N + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_CLK + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_DATA + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioOutputStat= eUnlock }}, //WIFI_RF_KILL_N + //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_CLK + //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_DATA + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTerm= None, GpioPadConfigUnlock }}, //WIFI_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + {GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnGpio , GpioDirIn , Gp= ioOutDefault , GpioIntLevel | GpioIntApic , GpioPlatformReset, GpioTermWpu2= 0K }}, //CODEC_INT_N + {GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, G= pioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K, GpioPadConfig= Unlock }}, //TBT_CIO_PLUG_EVENT_N + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUn= lock }}, //TBT_FORCE_PWR + //move to premem phase for early power turn on + // {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE= _NAND_RST_N + // {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCI= E_NAND_PWREN_N + // {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT= 1_PWREN_N + // {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT= 1_RST_N + + //Only clear Reset pins in Post-Mem + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_RST_N + + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SCL + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RXD + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_TXD + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RTS + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_CTS + //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CS0_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CLK_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MISO + //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MOSI + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRes= et, GpioTermNone }}, //IMGCLKOUT + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SCL + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL= 2_RST_N + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermN= one, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioHostDeepReset, GpioTe= rmWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermN= one }}, //Former NFC_RST_N + //{GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PW= REN + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PN= L_RST_N + //(Not used) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //Former NFC_INT_N + //{GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermN= one, GpioPadConfigUnlock }}, //WIGIG_WAKE_N + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_1 + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_1 + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_0 + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_0 + //(CSME control) {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostO= wnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //SPI1_TCH_PNL_IO2 + //(CSME control) {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostO= wnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //SPI1_TCH_PNL_IO3 + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset,= GpioTermNone }}, //SSP_MCLK + //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, = GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, = GpioTermWpu20K }}, //Reserved for SATA/PCIE detect + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformRe= set, GpioTermNone }}, //M.2_SSD_DET + {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Rese= rved for SATA HP val + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone,= GpioPadUnlock}}, //EC_SMI_N + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone= , GpioPadConfigUnlock }}, //DGPU_PWROK + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //SSD_DEVSLP + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //HDD_DEVSLP + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn= , GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTe= rmNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,= GpioTermNone }}, //SATA_LED_N + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gpi= oTermNone }}, //BSSB_CLK + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDef= ault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, //BSSB_DI + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_2 + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_3 + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_HPD + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_HPD_EC + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_HPD + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //EDP_HPD + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_DATA + //F0- unused pin-Input Sensing disable F4-F7 -> Under GPIO table for GP= IO Termination -20K WPU + {GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNo= ne, GpioOutHigh, GpioIntLevel, GpioResumeReset, GpioTermNone }}, //GPP= _F0_COEX3 + //{GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K }}, //S= ATA_HDD_PWREN + {GPIO_CNL_LP_GPP_F4, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_BRI_DT_UART0_RTSB + {GPIO_CNL_LP_GPP_F5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_BRI_RSP_UART0_RXD + {GPIO_CNL_LP_GPP_F6, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_RGI_DT_UART0_TXD + {GPIO_CNL_LP_GPP_F7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_RGI_RSP_UART0_CTSB + //{GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //CNV_MFUART2_RXD + //{GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //CNV_MFUART2_TXD + + //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be= used at IsRecoveryMode() + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K}}, /= /BIOS_REC + + //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F11_EMMC_CMD + //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F12_EMMC_DATA0 + //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F13_EMMC_DATA1 + //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F14_EMMC_DATA2 + //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F15_EMMC_DATA3 + //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F16_EMMC_DATA4 + //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F17_EMMC_DATA5 + //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F18_EMMC_DATA6 + //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F19_EMMC_DATA7 + //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F20_EMMC_RCLK + //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F21_EMMC_CLK + //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F22_EMMC_RESETB + //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTerm= None }}, //GPP_F_23 + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_0_SD3_CMD + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_3_SD3_D2 + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_4_SD3_D3 + {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_G_5_SD3_CDB + //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNone }}, //GPP_G_6_SD3_CLK + {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= d20K }}, //GPP_G_7_SD3_WP + //@todo - GPP-H0-3 are connected to M2 slot for discrete/integrated CNV = solution, dynamic detection should be done before programming. For CNVi, RC= will configure pins //Platform: RestrictedContent + //H0-H3 -> Under GPIO table for GPIO Termination -20K WPU + {GPIO_CNL_LP_GPP_H0, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_0_SSP2_SCLK + {GPIO_CNL_LP_GPP_H1, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_1_SSP2_SFRM + {GPIO_CNL_LP_GPP_H2, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_2_SSP2_TXD + {GPIO_CNL_LP_GPP_H3, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_3_SSP2_RXD + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_4_I2C2_SDA + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_5_I2C2_SCL + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_6_I2C3_SDA + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_7_I2C3_SCL + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_8_I2C4_SDA + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_9_I2C4_SCL + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_PWREN + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_RECOVERY + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_MUX_SEL0 + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_KEY + //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_CLK + //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_DATA + //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOw= nGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //VCCIO_LPM + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_MUX_SEL1 + //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H21 + //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H23 + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_BATLOW_N + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //BC_ACOK + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LAN_WAKE + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_PWRBTN_N + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S3_N + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S4_N + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SLP_A_N + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //GPD_7 + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SUS_CLK + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_WLAN_N + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S5_N + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LANPHY_EN + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir= Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd= 20K }}, // 20K PD for PECI + // + // CML Delta GPIO Start + // + + // Bluetooth start + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, G= pioPadUnlock } }, //BT_UART_WAKE + // Bluetooth end + + // VRALERT start + //(RC control) {GPIO_CNL_LP_GPP_B2,{ GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //VRALERT + // VRALERT end + + // Camera start + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,= GpioTermNone }}, //Camera / IRIS_STROBE on CNL U + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,= GpioTermNone }}, //Camera / UF_CAM_PRIVACY_LED on CNL U + {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,= GpioTermNone }}, //Camera / RC Control on CNL U + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //WRF_IMG= _RST2 + {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, Gp= ioTermWpu20K }}, //WRF_IMG_PWR0_ENABLE + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,= GpioTermWpu20K }}, //WRF_IMG_PWR1_ENABLE + {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, // WRF_IM= G_PWR_CTRL + {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, // WRF_IM= G_PWR2_ENABLE + // Below is commented since D16 is used for EN_V3.3A_WWAN_LS, so cannot = be used for Camera HDR now. + // This need to be corrected in SR'19 SKU schematic to us eit for Camera= HDR. + //{GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, Gpi= oDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformRese= t, GpioTermWpu20K }}, //WRF_IMG_CLK_ENABLE + // Camera end + + // x4 slot start + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R= ST_N + // x4 slot end + + // TBT Start + { GPIO_CNL_LP_GPP_D15,{ GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //TBT_CIO_PWR_= EN + // TBT End + + // EC + { GPIO_CNL_LP_GPP_E16,{ GpioPadModeGpio, GpioHostOwnAcpi, GpioDi= rInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, Gpi= oTermWpu20K, GpioPadConfigUnlock } }, //SMC_RUNTIME_SCI_N + // Unused start + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset,= GpioTermWpu20K }}, //Unused so disabled / WF_CLK_EN on CNL U + // Unused end + + // + // CML Delta GPIO End + // +}; + +UINT16 mGpioTableCmlULpddr3Size =3D sizeof (mGpioTableCmlULpddr3) / sizeof= (GPIO_INIT_CONFIG); diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/GpioTableDefault.c b/Platform/Intel/CometlakeOpenBoardPkg/Cometla= keURvp/Library/BoardInitLib/GpioTableDefault.c new file mode 100644 index 0000000000..9cc8b50023 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/GpioTableDefault.c @@ -0,0 +1,213 @@ +/** @file + GPIO definition table + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +// +// CNL U DRR4 Board GPIO table configuration is used as default +// +GPIO_INIT_CONFIG mGpioTableDefault[] =3D +{ +// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, = GPIRoutConfig, PadRstCfg, Term, + //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_0 + //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_1 + //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_CSB + //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPPC_A6_SERIRQ + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpu= 20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N + //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwn= Gpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //eSPI_CLK + //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTer= mNone }}, + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTerm= Wpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N + // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, Gp= ioTermNone }}, //SLATEMODE_HALLOUT + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL= _SLOT1 + //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOw= nGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRese= t, GpioTermNone }}, //eSPI_Reset + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SP= KR_PD_N + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WFC= AM_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SD_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //ACCEL_INT + //(RC control) {GPIO_CNL_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //ALS_INT + //(RC control) {GPIO_CNL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //HUMAN_PRESENCE_INT + //(RC control) {GPIO_CNL_LP_GPP_A21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //HALL_SENSOR_INT + //(RC control) {GPIO_CNL_LP_GPP_A22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //IVCAM_WAKE + //(RC control) {GPIO_CNL_LP_GPP_A23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //SHARED_INT + //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, Gp= ioPadConfigUnlock | GpioOutputStateUnlock } }, //BT_UART_WAKE + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, Gp= ioPadConfigUnlock | GpioOutputStateUnlock }}, //FORCE_PAD_INT + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi= oOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioPadConfigUnlock= } }, //BT_DISABLE_N + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WWAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_NAND_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //LAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WLAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_SLOT1_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PM_SLP_S0_N + //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PLT_RST_N + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_= PWR_EN + //(CSME Pad) {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefau= lt, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNon= e }}, //NFC_DFU + { GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, = GpioPadConfigUnlock } }, //FPS_INT_N + { GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnloc= k} }, //FPS_RESET_N + {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_E= N + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CS_FPS + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CLK_FPS + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MISO_FPS + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MOSI_FPS + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone}}, //E= C_SLP_S0_CS_N + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_CLK + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_DATA + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone }}, //WIFI_RF_= KILL_N + //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_CLK + //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_DATA + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTerm= None, GpioPadConfigUnlock }}, //WIFI_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu2= 0K } }, //CODEC_INT_N + { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K= , GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //TBT_= FORCE_PWR + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAN= D_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_PWREN_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PW= REN_N + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R= ST_N + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SCL + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RXD + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_TXD + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RTS + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_CTS + //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CS0_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CLK_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MISO + //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MOSI + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRes= et, GpioTermNone }}, //IMGCLKOUT + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SCL + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL= 2_RST_N + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermN= one, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioPlatformReset, GpioTe= rmWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermN= one }}, //NFC_RST_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PWRE= N + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PN= L_RST_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //NFC_INT_N + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNon= e, GpioPadConfigUnlock }}, //WIGIG_WAKE_N + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_1 + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_1 + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_0 + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_0 + {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnDefault, GpioD= irInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNon= e }}, //SPI1_TCH_PNL_IO2 + {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnDefault, GpioD= irInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNon= e }}, //SPI1_TCH_PNL_IO3 + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset,= GpioTermNone }}, //SSP_MCLK + //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, = GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, = GpioTermWpu20K }}, //Reserved for SATA/PCIE detect + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformRe= set, GpioTermNone }}, //M.2_SSD_DET + {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Rese= rved for SATA HP val + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone}= }, //EC_SMI_N + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone= , GpioPadConfigUnlock }}, //DGPU_PWROK + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //SSD_DEVSLP + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //HDD_DEVSLP + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn= , GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTe= rmNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,= GpioTermNone }}, //SATA_LED_N + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gpi= oTermNone }}, //BSSB_CLK + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDef= ault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, //BSSB_DI + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_2 + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_3 + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_HPD + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_HPD_EC + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_HPD + //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI4_HPD + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //EDP_HPD + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_CTRL_DATA + //(Not used){GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault= , GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTe= rmNone }}, //GPP_F0_COEX3 + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SAT= A_HDD_PWREN + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF_C= LK_EN + //(RC control) {GPIO_CNL_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_BRI_DT_UART0_RTSB + //(RC control) {GPIO_CNL_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_BRI_RSP_UART0_RXD + //(RC control) {GPIO_CNL_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_RGI_DT_UART0_TXD + //(RC control) {GPIO_CNL_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_RGI_RSP_UART0_CTSB + {GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //CNV_MFUART2_RXD + {GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //CNV_MFUART2_TXD + + //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be= used at IsRecoveryMode() + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //B= IOS_REC + + //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F11_EMMC_CMD + //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F12_EMMC_DATA0 + //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F13_EMMC_DATA1 + //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F14_EMMC_DATA2 + //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F15_EMMC_DATA3 + //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F16_EMMC_DATA4 + //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F17_EMMC_DATA5 + //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F18_EMMC_DATA6 + //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F19_EMMC_DATA7 + //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F20_EMMC_RCLK + //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F21_EMMC_CLK + //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F22_EMMC_RESETB + //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTerm= None }}, //GPP_F_23 + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_0_SD3_CMD + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_3_SD3_D2 + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_4_SD3_D3 + {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_G_5_SD3_CDB + //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNone }}, //GPP_G_6_SD3_CLK + {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= d20K }}, //GPP_G_7_SD3_WP + //{GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_0_SSP2_SCLK + //{GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_1_SSP2_SFRM + //{GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_2_SSP2_TXD + //{GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_3_SSP2_RXD + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_4_I2C2_SDA + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_5_I2C2_SCL + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_6_I2C3_SDA + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_7_I2C3_SCL + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_8_I2C4_SDA + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_9_I2C4_SCL + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_PWREN + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_RECOVERY + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IR= IS_STROBE + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_MUX_SEL0 + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadU= nlock }}, //UF_CAM_PRIVACY_LED + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_KEY + //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_CLK + //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_DATA + //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOw= nGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //VCCIO_LPM + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_MUX_SEL1 + //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //IMGCLKOUT_WF_CAM + //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H21 + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF= _CAM_RST + //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H23 + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_BATLOW_N + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //BC_ACOK + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LAN_WAKE + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_PWRBTN_N + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S3_N + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S4_N + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SLP_A_N + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //GPD_7 + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SUS_CLK + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_WLAN_N + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S5_N + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LANPHY_EN + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir= Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd= 20K }}, // 20K PD for PECI +}; +UINT16 mGpioTableDefaultSize =3D sizeof (mGpioTableDefault) / sizeof (GPIO= _INIT_CONFIG); diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PchHdaVerbTables.h b/Platform/Intel/CometlakeOpenBoardPkg/Cometla= keURvp/Library/BoardInitLib/PchHdaVerbTables.h new file mode 100644 index 0000000000..2e4bef3246 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PchHdaVerbTables.h @@ -0,0 +1,3014 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_VERB_TABLES_H_ +#define _PCH_HDA_VERB_TABLES_H_ + +#include + +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: CFL Display Audio Codec + // Revision ID =3D 0xFF + // Codec Vendor: 0x8086280B + // + 0x8086, 0x280B, + 0xFF, 0xFF, + // + // Display Audio Verb Table + // + // For GEN9, the Vendor Node ID is 08h + // Port to be exposed to the inbox driver in the vanilla mode: PORT C - = BIT[7:6] =3D 01b + 0x00878140, + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010 + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020 + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030 + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + // Disable the third converter and third Pin (NID 08h) + 0x00878140 +); + +// +//codecs verb tables +// +HDAUDIO_VERB_TABLE HdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40622005 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D20, + 0x01D71E62, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + // + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +); // HdaVerbTableAlc700 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc701 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC701) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0701 + // + 0x10EC, 0x0701, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC701 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40610041 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC1124 + 0x00172024, + 0x00172111, + 0x001722EC, + 0x00172310, + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C41, + 0x01D71D00, + 0x01D71E61, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B +); // HdaVerbTableAlc701 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC274) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0274 + // + 0x10EC, 0x0274, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC274 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6 + //The number of verb command block : 16 + + // NID 0x12 : 0x40000000 + // NID 0x13 : 0x411111F0 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x411111F0 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11020 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40451B05 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211010 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //,DA Codec Subsystem ID : 0x10EC10F6 + 0x001720F6, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + //Pin widget 0x14 - NPC + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S_OUT2 + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S_OUT1 + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + //Pin widget 0x18 - I2S_IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D1B, + 0x01D71E45, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C10, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205006F, + 0x02042C0B, + //Widget node 0x20 - 1 : + 0x02050035, + 0x02048968, + 0x05B50001, + 0x05B48540, + //Widget node 0x20 - 2 : + 0x05850000, + 0x05843888, + 0x05850000, + 0x05843888, + //Widget node 0x20 - 3 : + 0x0205004A, + 0x0204201B, + 0x0205004A, + 0x0204201B +); //HdaVerbTableAlc274 + +// +// CFL S Audio Codec +// +STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_IN= IT ( + // + // VerbTable: (Realtek ALC700) CFL S RVP + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C + //The number of verb command block : 17 + + // NID 0x12 : 0x90A60130 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x03011010 + // NID 0x17 : 0x90170120 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A1103E + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x03A11040 + // NID 0x1D : 0x40600001 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x0421102F + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC112C + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C30, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671C10, + 0x01671D10, + 0x01671E01, + 0x01671F03, + //Pin widget 0x17 - I2S-OUT + 0x01771C20, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C3E, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71C40, + 0x01B71D10, + 0x01B71EA1, + 0x01B71F03, + //Pin widget 0x1D - PC-BEEP + 0x01D71C01, + 0x01D71D00, + 0x01D71E60, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of= NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14) + 0x0205006B, + 0x02044260, + 0x0205006B, + 0x02044260, + //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700 + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent co= ntrol + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 4 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + + //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC= 1305 EQ setting + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x02042213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); + + +// +// WHL codecs verb tables +// +HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) WHL RVP + // Revision ID =3D 0xff + // Codec Verb Table for WHL PCH boards + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x02A19040 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40638029 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x02211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C40, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C29, + 0x01D71D80, + 0x01D71E63, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F02, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + + //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 byp= ass DAC02 DRE(NID5B bit14) + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + + //Widget node 0x20 -2: + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + + //Widget node 0x20 - 3 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + + //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC= 1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x0204E213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204422E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); // WhlHdaVerbTableAlc700 + +#endif // _PCH_HDA_VERB_TABLES_H_ + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/C= ometlakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 0000000000..74581ac6bd --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiBoardInitPostMemLib.c @@ -0,0 +1,40 @@ +/** @file + Comet Lake U LP3 Board Initialization Post-Memory library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +CometlakeURvpBoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + CometlakeURvpBoardInitBeforeSiliconInit(); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/CometlakeOpenBoardPkg= /CometlakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..458242a5f7 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiBoardInitPostMemLib.inf @@ -0,0 +1,57 @@ +## @file +# Component information file for CometlakeURvpInitLib in PEI post memory p= hase. +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardPostMemInitLib + FILE_GUID =3D 7fcc3900-d38d-419f-826b-72481e8b5509 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + GpioExpanderLib + GpioLib + HdaVerbTableLib + MemoryAllocationLib + PcdLib + SiliconInitLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiCometlakeURvpInitPostMemLib.c + PeiBoardInitPostMemLib.c + GpioTableDefault.c + GpioTableCometlakeULpddr3Rvp.c + +[Pcd] + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize + + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardPkg/Co= metlakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..137b7353e4 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiBoardInitPreMemLib.c @@ -0,0 +1,106 @@ +/** @file + Comet Lake U LP3 Board Initialization Pre-Memory library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +CometlakeURvpBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +CometlakeURvpBoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + CometlakeURvpBoardDetect(); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + CometlakeURvpBoardDebugInit(); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return CometlakeURvpBoardBootModeDetect(); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + CometlakeURvpBoardInitBeforeMemoryInit(); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/CometlakeOpenBoardPkg/= CometlakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..b7f96f1b99 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiBoardInitPreMemLib.inf @@ -0,0 +1,118 @@ +## @file +# Component information file for PEI CometlakeURvp Board Init Pre-Mem Libr= ary +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardInitPreMemLib + FILE_GUID =3D ec3675bc-1470-417d-826e-37378140213d + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + SiliconInitLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiCometlakeURvpDetect.c + PeiCometlakeURvpInitPreMemLib.c + CometlakeURvpHsioPtssTables.c + PeiBoardInitPreMemLib.c + +[Pcd] + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # SA Misc Config + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # USB 2.0 Port AFE + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent + + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiCometlakeURvpDetect.c b/Platform/Intel/CometlakeOpenBoardPkg/C= ometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpDetect.c new file mode 100644 index 0000000000..e113ac3ae0 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiCometlakeURvpDetect.c @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "CometlakeURvpInit.h" + +#include +#include + +BOOLEAN +CometlakeURvp( + VOID + ) +{ + return TRUE; +} + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDetect( + VOID + ) +{ + if (LibPcdGetSku () !=3D 0) { + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "CometlakeURvpDetectionCallback\n")); + + if (CometlakeURvp()) { + LibPcdSetSku (BoardIdCometLakeULpddr3Rvp); + + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + ASSERT (LibPcdGetSku() =3D=3D BoardIdCometLakeULpddr3Rvp); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiCometlakeURvpInitPostMemLib.c b/Platform/Intel/CometlakeOpenBo= ardPkg/CometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpInitPostMemLib.c new file mode 100644 index 0000000000..306ffbf21b --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiCometlakeURvpInitPostMemLib.c @@ -0,0 +1,436 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "CometlakeURvpInit.h" +#include + +EFI_STATUS +BoardFunctionInit ( + IN UINT16 BoardId + ); + +/** + GPIO init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardGpioInit( + IN UINT16 BoardId + ) +{ + // + // GPIO Table Init. + // + switch (BoardId) { + + case BoardIdCometLakeULpddr3Rvp: + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableCmlULpddr3); + PcdSet16S (PcdBoardGpioTableSize, mGpioTableCmlULpddr3Size); + PcdSet32S (PcdBoardGpioTable2, 0); + PcdSet16S (PcdBoardGpioTable2Size, 0); + break; + + default: + DEBUG ((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...= \n")); + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableDefault); + PcdSet16S (PcdBoardGpioTableSize, mGpioTableDefaultSize); + break; + } + + return EFI_SUCCESS; +} + +/** + Touch panel GPIO init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +TouchPanelGpioInit ( + IN UINT16 BoardId + ) +{ + switch (BoardId) { + default: + PcdSet32S (PcdBoardGpioTableTouchPanel, 0); + break; + } + return EFI_SUCCESS; +} + +/** + Misc. init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardMiscInit ( + IN UINT16 BoardId + ) +{ + PcdSetBoolS (PcdDebugUsbUartEnable, FALSE); + + switch (BoardId) { + + case BoardIdCometLakeULpddr3Rvp: + + PcdSetBoolS(PcdMipiCamGpioEnable, FALSE); + break; + + default: + PcdSetBoolS(PcdMipiCamGpioEnable, FALSE); + break; + } + + return EFI_SUCCESS; +} + +/** + Security GPIO init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardSecurityInit ( + IN UINT16 BoardId + ) +{ + switch (BoardId) { + + case BoardIdCometLakeULpddr3Rvp: + + // TPM interrupt connects to GPIO_CNL_H_GPP_A_7 + PcdSet32S (PcdTpm2CurrentIrqNum, 0x1F); + break; + } + + return EFI_SUCCESS; +} + +/** + Board configuration initialization in the post-memory boot phase. +**/ +VOID +BoardConfigInit ( + VOID + ) +{ + EFI_STATUS Status; + UINT16 BoardId; + + BoardId =3D BoardIdCometLakeULpddr3Rvp; + + Status =3D BoardGpioInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D TouchPanelGpioInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D HdaVerbTableInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D BoardMiscInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D BoardFunctionInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D BoardSecurityInit (BoardId); + ASSERT_EFI_ERROR (Status); +} + +/** + Create the HOB for hotkey status for 'Attempt USB First' feature + + @retval EFI_SUCCESS HOB Creating successful. + @retval Others HOB Creating failed. +**/ +EFI_STATUS +CreateAttemptUsbFirstHotkeyInfoHob ( + VOID + ) +{ + EFI_STATUS Status; + ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo; + + Status =3D EFI_SUCCESS; + + ZeroMem ( + &AttemptUsbFirstHotkeyInfo, + sizeof (AttemptUsbFirstHotkeyInfo) + ); + + AttemptUsbFirstHotkeyInfo.RevisonId =3D 0; + AttemptUsbFirstHotkeyInfo.HotkeyTriggered =3D FALSE; + + /// + /// Build HOB for Attempt USB First feature + /// + BuildGuidDataHob ( + &gAttemptUsbFirstHotkeyInfoHobGuid, + &(AttemptUsbFirstHotkeyInfo), + sizeof (ATTEMPT_USB_FIRST_HOTKEY_INFO) + ); + + return Status; +} + +/** + Search and identify the physical address of a + file module inside the FW_BINARIES_FV_SIGNED FV + + @retval EFI_SUCCESS If address has been found + @retval Others If address has not been found +**/ +EFI_STATUS +FindModuleInFlash2 ( + IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader, + IN EFI_GUID *GuidPtr, + IN OUT UINT32 *ModulePtr, + IN OUT UINT32 *ModuleSize + ) +{ + EFI_FFS_FILE_HEADER *FfsHeader; + EFI_FV_FILE_INFO FileInfo; + EFI_PEI_FILE_HANDLE FileHandle; + EFI_COMMON_SECTION_HEADER *SectionHeader; + VOID *FileBuffer; + EFI_STATUS Status; + + FfsHeader =3D NULL; + FileHandle =3D NULL; + SectionHeader =3D NULL; + FileBuffer =3D NULL; + + while (TRUE) { + // + // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware vol= ume + // + Status =3D PeiServicesFfsFindNextFile (EFI_FV_FILETYPE_FIRMWARE_VOLUME= _IMAGE, FvHeader, &FileHandle); + if (EFI_ERROR (Status)) { + // unable to find FV_IMAGE file in this FV + break; + } + + FfsHeader =3D (EFI_FFS_FILE_HEADER*)FileHandle; + DEBUG ((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader)); + DEBUG ((DEBUG_INFO, " Name =3D 0x%g\n", &FfsHeader->Name)); + DEBUG ((DEBUG_INFO, " Type =3D 0x%X\n", FfsHeader->Type)); + if (IS_FFS_FILE2 (FfsHeader)) { + DEBUG ((DEBUG_INFO, " Size =3D 0x%X\n", FFS_FILE2_SIZE(FfsHeader))); + } + else { + DEBUG ((DEBUG_INFO, " Size =3D 0x%X\n", FFS_FILE_SIZE(FfsHeader))); + } + + // + // Locate FW_BINARIES_FV FV_IMAGE Section + // + Status =3D PeiServicesFfsFindSectionData (EFI_SECTION_FIRMWARE_VOLUME_= IMAGE, FileHandle, &FileBuffer); + if (EFI_ERROR (Status)) { + // continue to search for the next FV_IMAGE file + DEBUG ((DEBUG_INFO, "FW_BINARIES_FV section not found. Status =3D %r= \n", Status)); + continue; + } + + SectionHeader =3D (EFI_COMMON_SECTION_HEADER *)FileBuffer; + DEBUG ((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n", + (UINT32)(UINT8 *)SectionHeader)); + if (IS_SECTION2(SectionHeader)) { + DEBUG ((DEBUG_INFO, " Guid =3D 0x%g\n", + &((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->SectionDefinitionGu= id)); + DEBUG ((DEBUG_INFO, " DataOfset =3D 0x%X\n", + ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset)); + } + else { + DEBUG ((DEBUG_INFO, " Guid =3D 0x%g\n", + &((EFI_GUID_DEFINED_SECTION *)SectionHeader)->SectionDefinitionGui= d)); + DEBUG ((DEBUG_INFO, " DataOfset =3D 0x%X\n", + ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset)); + } + DEBUG ((DEBUG_INFO, " Type =3D 0x%X\n", SectionHeader->Type)); + + // + // Locate Firmware File System file within Firmware Volume + // + Status =3D PeiServicesFfsFindFileByName (GuidPtr, FileBuffer, (VOID **= )&FfsHeader); + if (EFI_ERROR (Status)) { + // continue to search for the next FV_IMAGE file + DEBUG ((DEBUG_INFO, "Module not found. Status =3D %r\n", Status)); + continue; + } + + *ModulePtr =3D (UINT32)((UINT8 *)FfsHeader + sizeof(EFI_FFS_FILE_HEADE= R)); + + // + // Get File Information + // + Status =3D PeiServicesFfsGetFileInfo (FfsHeader, &FileInfo); + if (!EFI_ERROR (Status)) { + *ModuleSize =3D (UINT32)FileInfo.BufferSize; + DEBUG ((DEBUG_INFO, "Module {0x%g} found at =3D 0x%X, Size =3D 0x%X\= n", + &FfsHeader->Name, *ModulePtr, *ModuleSize)); + return Status; + } + } + + return EFI_NOT_FOUND; +} + +/** + Get the ChipsetInit Binary pointer. + + @retval EFI_SUCCESS - ChipsetInit Binary found. + @retval EFI_NOT_FOUND - ChipsetInit Binary not found. +**/ +EFI_STATUS +UpdateChipsetInitPtr ( + VOID + ) +{ + EFI_STATUS Status; + PCH_STEPPING PchStep; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + EFI_GUID *ChipsetInitBinaryGuidPtr; + SI_POLICY_PPI *SiPolicyPpi; + PCH_HSIO_CONFIG *HsioConfig; + UINT32 ModuleAddr; + UINT32 ModuleSize; + + ModuleAddr =3D 0; + ModuleSize =3D 0; + PchStep =3D PchStepping (); + + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID = *)&HsioConfig); + ASSERT_EFI_ERROR (Status); + + ChipsetInitBinaryGuidPtr =3D NULL; + if (IsPchLp()) { + switch (PchStep) { + case PCH_A0: + case PCH_D0: + case PCH_D1: + ChipsetInitBinaryGuidPtr =3D &gCnlPchLpChipsetInitTableDxGuid; + DEBUG ((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n"))= ; + break; + default: + return EFI_NOT_FOUND; + } + } else { + return EFI_NOT_FOUND; + } + + // + // Locate Firmware Volume header + // + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32 (PcdFlashFvPos= tMemoryBase); + Status =3D FindModuleInFlash2 (FvHeader, ChipsetInitBinaryGuidPtr, &Modu= leAddr, &ModuleSize); + // + // Get ChipsetInit Binary Pointer + // + HsioConfig->ChipsetInitBinPtr =3D ModuleAddr; + + // + // Get File Size + // + HsioConfig->ChipsetInitBinLen =3D ModuleSize; + + DEBUG ((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig->Chi= psetInitBinPtr)); + DEBUG ((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig->Chipset= InitBinLen)); + + return Status; +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +CometlakeURvpBoardInitBeforeSiliconInit( + VOID + ) +{ + EFI_STATUS Status; + UINT8 FwConfig; + + BoardConfigInit (); + // + // Configure GPIO and SIO + // + Status =3D BoardInit (); + ASSERT_EFI_ERROR (Status); + + FwConfig =3D FwConfigProduction; + PeiPolicyInit (FwConfig); + + // + // Create USB Boot First hotkey information HOB + // + CreateAttemptUsbFirstHotkeyInfoHob (); + + // + // Initializing Platform Specific Programming + // + Status =3D PlatformSpecificInit (); + ASSERT_EFI_ERROR(Status); + + // + // Update ChipsetInitPtr + // + Status =3D UpdateChipsetInitPtr (); + + /// + /// Do Late PCH init + /// + LateSiliconInit (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiCometlakeURvpInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoa= rdPkg/CometlakeURvp/Library/BoardInitLib/PeiCometlakeURvpInitPreMemLib.c new file mode 100644 index 0000000000..af80a69ee4 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiCometlakeURvpInitPreMemLib.c @@ -0,0 +1,562 @@ +/** @file + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "CometlakeURvpInit.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/// +/// Reset Generator I/O Port +/// +#define RESET_GENERATOR_PORT 0xCF9 + +typedef struct { + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 Length; +} MEMORY_MAP; + +// +// Reference RCOMP resistors on motherboard - for WHL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX= _RCOMP] =3D { 200, 81, 162 }; + +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for WH= L RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 40, 23, 40 }; + +GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] =3D { + { FixedPcdGet64 (PcdApicLocalAddress), FixedPcdGet32 (PcdApicLocalMmioS= ize) }, + { FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32 (PcdMchMmioSize) }= , + { FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32 (PcdDmiMmioSize) }= , + { FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32 (PcdEpMmioSize) }, + { FixedPcdGet64 (PcdGdxcBaseAddress), FixedPcdGet32 (PcdGdxcMmioSize) = } +}; + +EFI_STATUS +MrcConfigInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +SaGpioConfigInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +SaMiscConfigInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +RootPortClkInfoInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +UsbConfigInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +GpioGroupTierInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +GpioTablePreMemInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +PchPmConfigInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +SaDisplayConfigInit ( + IN UINT16 BoardId + ); + +EFI_STATUS +BoardFunctionInitPreMem ( + IN UINT16 BoardId + ); + +EFI_STATUS +EFIAPI +PlatformInitPreMemCallBack ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotify ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +EFI_STATUS +EFIAPI +PchReset ( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +static EFI_PEI_RESET_PPI mResetPpi =3D { + PchReset +}; + +static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] =3D { + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiResetPpiGuid, + &mResetPpi + } +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEfiPeiReadOnlyVariable2PpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify +}; + +/** + Board misc init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardMiscInitPreMem ( + IN UINT16 BoardId + ) +{ + PCD64_BLOB PcdData; + + // + // RecoveryMode GPIO + // + PcdData.Blob =3D 0; + PcdData.BoardGpioConfig.Type =3D BoardGpioTypeNotSupported; + + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + PcdData.BoardGpioConfig.Type =3D BoardGpioTypePch; + PcdData.BoardGpioConfig.u.Pin =3D GPIO_CNL_LP_GPP_F10; + break; + + default: + break; + } + + // + // Configure WWAN Full Card Power Off and reset pins + // + switch (BoardId) { + case BoardIdCometLakeULpddr3Rvp: + // + // According to board default settings, GPP_D16 is used to enable/di= sable modem + // power. An alternative way to contol modem power is to toggle FCP_= OFF via GPP_D13 + // but board rework is required. + // + PcdSet32S (PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16); + PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1); + PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15); + PcdSet8S (PcdWwanPerstGpioPolarity, 1); + break; + + default: + break; + } + + PcdSet64S (PcdRecoveryModeGpio, PcdData.Blob); + + // + // Pc8374SioKbc Present + // + PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE); + + return EFI_SUCCESS; +} + +/** + Board configuration initialization in the pre-memory boot phase. +**/ +VOID +BoardConfigInitPreMem ( + VOID + ) +{ + EFI_STATUS Status; + UINT16 BoardId; + + BoardId =3D BoardIdCometLakeULpddr3Rvp; + + Status =3D MrcConfigInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D SaGpioConfigInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D SaMiscConfigInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D RootPortClkInfoInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D UsbConfigInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D GpioGroupTierInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D GpioTablePreMemInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D PchPmConfigInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D BoardMiscInitPreMem (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D SaDisplayConfigInit (BoardId); + ASSERT_EFI_ERROR (Status); + + Status =3D BoardFunctionInitPreMem (BoardId); + ASSERT_EFI_ERROR (Status); +} + +/** + This function handles PlatformInit task after PeiReadOnlyVariable2 PPI p= roduced + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_SUCCESS The function completes successfully + @retval others Failure +**/ +EFI_STATUS +EFIAPI +PlatformInitPreMemCallBack ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + UINT8 FwConfig; + + // + // Init Board Config Pcd. + // + BoardConfigInitPreMem (); + + DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the confi= guration to production mode!\n")); + FwConfig =3D FwConfigProduction; + PcdSetBoolS (PcdPcieWwanEnable, FALSE); + PcdSetBoolS (PcdWwanResetWorkaround, FALSE); + + // + // Early Board Configuration before memory is ready. + // + Status =3D BoardInitEarlyPreMem (); + ASSERT_EFI_ERROR (Status); + + /// + /// If there was unexpected reset but no WDT expiration and no resume fr= om S3/S4, + /// clear unexpected reset status and enforce expiration. This is to inf= orm Firmware + /// which has no access to unexpected reset status bit, that something w= ent wrong. + /// + OcWdtResetCheck (); + + Status =3D OcWdtInit (); + ASSERT_EFI_ERROR (Status); + + // + // Initialize Intel PEI Platform Policy + // + PeiPolicyInitPreMem (FwConfig); + + /// + /// Configure GPIO and SIO + /// + Status =3D BoardInitPreMem (); + ASSERT_EFI_ERROR (Status); + + /// + /// Install Pre Memory PPIs + /// + Status =3D PeiServicesInstallPpi (&mPreMemPpiList[0]); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Provide hard reset PPI service. + To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xC= F9). + + @param[in] PeiServices General purpose services available to ever= y PEIM. + + @retval Not return System reset occured. + @retval EFI_DEVICE_ERROR Device error, could not reset the system. +**/ +EFI_STATUS +EFIAPI +PchReset ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + DEBUG ((DEBUG_INFO, "Perform Cold Reset\n")); + IoWrite8 (RESET_GENERATOR_PORT, 0x0E); + + CpuDeadLoop (); + + /// + /// System reset occured, should never reach at this line. + /// + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR); + return EFI_DEVICE_ERROR; +} + +/** + Install Firmware Volume Hob's once there is main memory + + @param[in] PeiServices General purpose services available to ever= y PEIM. + @param[in] NotifyDescriptor Notify that this module published. + @param[in] Ppi PPI that was installed. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotify ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINTN Index; + UINT8 PhysicalAddressBits; + UINT32 RegEax; + MEMORY_MAP PcieMmioMap; + + Index =3D 0; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits =3D (UINT8)RegEax; + } + else { + PhysicalAddressBits =3D 36; + } + + /// + /// Create a CPU hand-off information + /// + BuildCpuHob (PhysicalAddressBits, 16); + + /// + /// Build Memory Mapped IO Resource which is used to build E820 Table in= LegacyBios. + /// + PcieMmioMap.BaseAddress =3D FixedPcdGet64 (PcdPciExpressBaseAddress); + PcieMmioMap.Length =3D PcdGet32 (PcdPciExpressRegionLength); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + PcieMmioMap.BaseAddress, + PcieMmioMap.Length + ); + BuildMemoryAllocationHob ( + PcieMmioMap.BaseAddress, + PcieMmioMap.Length, + EfiMemoryMappedIO + ); + for (Index =3D 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Index+= +) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + MmioMap[Index].BaseAddress, + MmioMap[Index].Length + ); + BuildMemoryAllocationHob ( + MmioMap[Index].BaseAddress, + MmioMap[Index].Length, + EfiMemoryMappedIO + ); + } + + // + // Report resource HOB for flash FV + // + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) FixedPcdGet32 (PcdFlashAreaSize) + ); + + BuildMemoryAllocationHob ( + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) FixedPcdGet32 (PcdFlashAreaSize), + EfiMemoryMappedIO + ); + + BuildFvHob ( + (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress), + (UINTN)FixedPcdGet32 (PcdFlashAreaSize) + ); + + return Status; +} + +/** + Board configuration init function for PEI pre-memory phase. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +CometlakeURvpInitPreMem ( + VOID + ) +{ + EFI_STATUS Status; + + /// + /// Install Stall PPI + /// + Status =3D InstallStallPpi (); + ASSERT_EFI_ERROR (Status); + + // + // Install PCH RESET PPI and EFI RESET2 PeiService + // + Status =3D PchInitializeReset (); + ASSERT_EFI_ERROR (Status); + + /// + /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI= produced + /// + Status =3D PeiServicesNotifyPpi (&mPreMemNotifyList); + + /// + /// After code reorangized, memorycallback will run because the PPI is a= lready + /// installed when code run to here, it is supposed that the InstallEfiM= emory is + /// done before. + /// + Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList); + + return EFI_SUCCESS; +} + +/** + Configure GPIO and SIO before memory ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +CometlakeURvpBoardInitBeforeMemoryInit( + VOID + ) +{ + /// + /// Do basic PCH init + /// + SiliconInit (); + + CometlakeURvpInitPreMem(); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDebugInit( + VOID + ) +{ + /// + /// Do Early PCH init + /// + EarlySiliconInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +CometlakeURvpBoardBootModeDetect( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/CometlakeOpenBoard= Pkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 0000000000..560f05380c --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,41 @@ +/** @file + Comet Lake U LP3 Multi-Board Initialization Post-Memory library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +CometlakeURvpBoardInitBeforeSiliconInit( + VOID + ); + +BOARD_POST_MEM_INIT_FUNC mCometlakeURvpBoardInitFunc =3D { + CometlakeURvpBoardInitBeforeSiliconInit, + NULL, // BoardInitAfterSiliconInit +}; + +EFI_STATUS +EFIAPI +PeiCometlakeURvpMultiBoardInitLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () =3D=3D BoardIdCometLakeULpddr3Rvp) { + return RegisterBoardPostMemInit (&mCometlakeURvpBoardInitFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/CometlakeOpenBoa= rdPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..b3b121e9e8 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,207 @@ +## @file +# Component information file for CometlakeURvpInitLib in PEI post memory p= hase. +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiCometlakeURvpMultiBoardInitLib + FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D PeiCometlakeURvpMultiBoardInitLibCons= tructor + + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + MultiBoardInitSupportLib + HdaVerbTableLib + PeiPlatformHookLib + PeiPolicyInitLib + PchInfoLib + SiliconInitLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + SecurityPkg/SecurityPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiCometlakeURvpInitPostMemLib.c + PeiMultiBoardInitPostMemLib.c + BoardFunc.c + BoardFuncInit.c + GpioTableDefault.c + GpioTableCometlakeULpddr3Rvp.c + +[FixedPcd] + +[Pcd] + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize + + #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + # Board Init Table List + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemS= ize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem= Size + + # WWAN Full Card Power Off and reset pins + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity + + # SA Misc Config + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit + + # Display DDI + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable #= # PRODUCES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize #= # PRODUCES + + # PEG Reset By GPIO + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive + + # PCIE RTD3 GPIO + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive + + # CA Vref Configuration + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig + + # PCIe Clock Info + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15 + + # USB 2.0 Port AFE + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe + + # USB 2.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + + # USB 3.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + + # GPIO Group Tier + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + # Pch PmConfig Policy + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport + + # Misc + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable + + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 = ## CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size = ## CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable + # TPM interrupt + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum + +[Guids] + gAttemptUsbFirstHotkeyInfoHobGuid ## CONSUMES + gCnlPchLpChipsetInitTableDxGuid ## CONSUMES diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/CometlakeOpenBoardP= kg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 0000000000..37df5c0e35 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,83 @@ +/** @file + Comet Lake U LP3 Multi-Board Initialization Pre-Memory library + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDetect( + VOID + ); + +EFI_STATUS +EFIAPI +CometlakeURvpMultiBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +CometlakeURvpBoardBootModeDetect( + VOID + ); + +EFI_STATUS +EFIAPI +CometlakeURvpBoardDebugInit( + VOID + ); + +EFI_STATUS +EFIAPI +CometlakeURvpBoardInitBeforeMemoryInit( + VOID + ); + +BOARD_DETECT_FUNC mCometlakeURvpBoardDetectFunc =3D { + CometlakeURvpMultiBoardDetect +}; + +BOARD_PRE_MEM_INIT_FUNC mCometlakeURvpBoardPreMemInitFunc =3D { + CometlakeURvpBoardDebugInit, + CometlakeURvpBoardBootModeDetect, + CometlakeURvpBoardInitBeforeMemoryInit, + NULL, // BoardInitAfterMemoryInit + NULL, // BoardInitBeforeTempRamExit + NULL, // BoardInitAfterTempRamExit +}; + +EFI_STATUS +EFIAPI +CometlakeURvpMultiBoardDetect( + VOID + ) +{ + CometlakeURvpBoardDetect(); + if (LibPcdGetSku () =3D=3D BoardIdCometLakeULpddr3Rvp) { + RegisterBoardPreMemInit (&mCometlakeURvpBoardPreMemInitFunc); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PeiCometlakeURvpMultiBoardInitPreMemLibConstructor ( + VOID + ) +{ + return RegisterBoardDetect (&mCometlakeURvpBoardDetectFunc); +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/CometlakeOpenBoar= dPkg/CometlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..636816ad81 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,300 @@ +## @file +# Component information file for PEI CometlakeURvp Board Init Pre-Mem Libr= ary +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiCometlakeURvpMultiBoardInitPreMemL= ib + FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D PeiCometlakeURvpMultiBoardInitPreMemL= ibConstructor + + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + GpioLib + MemoryAllocationLib + MultiBoardInitSupportLib + OcWdtLib + PcdLib + PchResetLib + PeiPlatformHookLib + PeiPolicyInitLib + PlatformHookLib + SiliconInitLib + StallPpiLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiCometlakeURvpInitPreMemLib.c + CometlakeURvpHsioPtssTables.c + PeiMultiBoardInitPreMemLib.c + PeiCometlakeURvpDetect.c + BoardSaInitPreMemLib.c + BoardPchInitPreMemLib.c + BoardFuncInitPreMem.c + GpioTableCmlUlpddr3PreMem.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES + gEfiPeiResetPpiGuid ## PRODUCES + +[Guids] + gPchGeneralPreMemConfigGuid ## CONSUMES + +[Pcd] + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # PCH-H HSIO PTSS Table + #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + + # SA Misc Config + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # USB 2.0 Port AFE + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent + + #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + # Board Init Table List + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemS= ize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem= Size + + # WWAN Full Card Power Off and reset pins + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity + + # SA Misc Config + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit + + # Display DDI + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable #= # PRODUCES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize #= # PRODUCES + + # PEG Reset By GPIO + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive + + # PCIE RTD3 GPIO + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive + + # CA Vref Configuration + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig + + # PCIe Clock Info + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15 + + # USB 2.0 Port AFE + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe + + # USB 2.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + + # USB 3.0 Port Over Current Pin + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + + # GPIO Group Tier + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + # Pch PmConfig Policy + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport + + # Misc + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable + + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType + + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUC= ES + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress + + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdMchMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize ## CONSUMES + + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Dxe= PolicyBoardConfigLib/DxePolicyBoardConfig.h b/Platform/Intel/CometlakeOpenB= oardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.= h new file mode 100644 index 0000000000..c420873002 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyB= oardConfigLib/DxePolicyBoardConfig.h @@ -0,0 +1,19 @@ +/** @file + Header file for DxePolicyBoardConfig library instance. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_POLICY_BOARD_CONFIG_H_ +#define _DXE_POLICY_BOARD_CONFIG_H_ + +#include +#include +#include +#include + + +#endif + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Dxe= PolicyBoardConfigLib/DxePolicyBoardConfigLib.inf b/Platform/Intel/Cometlake= OpenBoardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoardCo= nfigLib.inf new file mode 100644 index 0000000000..b4da7162c1 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyB= oardConfigLib/DxePolicyBoardConfigLib.inf @@ -0,0 +1,45 @@ +## @file +# Module Information file for DxePolicyBoardConfigLib Library +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DxePolicyBoardConfigLib + FILE_GUID =3D 17836E9F-7188-4640-80A3-B4441585FFE9 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + LIBRARY_CLASS =3D DxePolicyUpdateLib|DXE_DRIVER + +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + DxeSaPolicyBoardConfig.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + BaseMemoryLib + PcdLib + DebugLib + HobLib + ConfigBlockLib + +[Guids] + gMemoryDxeConfigGuid ## CONSUMES + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Dxe= PolicyBoardConfigLib/DxeSaPolicyBoardConfig.c b/Platform/Intel/CometlakeOpe= nBoardPkg/CometlakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardCon= fig.c new file mode 100644 index 0000000000..78edbab5ad --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/DxePolicyB= oardConfigLib/DxeSaPolicyBoardConfig.c @@ -0,0 +1,36 @@ +/** @file + Intel DXE SA Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "DxePolicyBoardConfig.h" +#include + +/** + This function performs DXE SA Policy update by board configuration. + + @param[in, out] DxeSaPolicy DXE SA Policy + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicyBoardConfig ( + IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy + ) +{ + EFI_STATUS Status; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in DXE\n")); + + Status =3D GetConfigBlock ((VOID *)DxeSaPolicy, &gMemoryDxeConfigGuid, (= VOID *)&MemoryDxeConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/CometlakeOpenBoardPkg= /CometlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..6a47a9bd09 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPlatfor= mHookLib/PeiPlatformHooklib.c @@ -0,0 +1,299 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 + +#define RECOVERY_MODE_GPIO_PIN 0 // = Platform specific @todo use PCD + +#define MANUFACTURE_MODE_GPIO_PIN 0 // = Platform specific @todo use PCD + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + + CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount); + + + GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +/** + Configure GPIO group GPE tier. + + @retval none. +**/ +VOID +GpioGroupTierInitHook( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n")); + + if (PcdGet32 (PcdGpioGroupToGpeDw0)) { + GpioSetGroupToGpeDwX (PcdGet32 (PcdGpioGroupToGpeDw0), + PcdGet32 (PcdGpioGroupToGpeDw1), + PcdGet32 (PcdGpioGroupToGpeDw2)); + } + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n")); +} + +/** + Configure single GPIO pad for touchpanel interrupt +**/ +VOID +TouchpanelGpioInit ( + VOID + ) +{ + GPIO_INIT_CONFIG* TouchpanelPad; + GPIO_PAD_OWN PadOwnVal; + + PadOwnVal =3D 0; + TouchpanelPad =3D (VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableTouchPanel= ); + if (TouchpanelPad !=3D NULL) { + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal); + if (PadOwnVal =3D=3D GpioPadOwnHost) { + GpioConfigurePads (1, TouchpanelPad); + } + } +} + +/** + Configure GPIO Before Memory is not ready. + +**/ +VOID +GpioInitPreMem ( + VOID + ) +{ + if (PcdGet32 (PcdBoardGpioTablePreMem) !=3D 0 && PcdGet16 (PcdBoardGpioT= ablePreMemSize) !=3D 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), (U= INTN) PcdGet16 (PcdBoardGpioTablePreMemSize)); + } +} + +/** + Basic GPIO configuration before memory is ready + +**/ +VOID +GpioInitEarlyPreMem ( + VOID + ) +{ + GPIO_CONFIG BbrstConfig; + UINT32 WwanBbrstGpio; + + WwanBbrstGpio =3D PcdGet32 (PcdWwanBbrstGpio); + + if (WwanBbrstGpio) { + // + // BIOS needs to put modem in OFF state for the two scenarios below. + // 1. Modem RESET# is not asserted via PLTRST# in the previous sleep s= tate + // 2. Modem is disabled via setup option + // + GpioGetPadConfig (WwanBbrstGpio, &BbrstConfig); + if ((PcdGetBool (PcdPcieWwanEnable) =3D=3D FALSE) || + (PcdGetBool (PcdWwanResetWorkaround) =3D=3D TRUE && + BbrstConfig.Direction =3D=3D GpioDirOut && + BbrstConfig.OutputState =3D=3D GpioOutHigh)) { + // + // Assert FULL_CARD_POWER_OFF#, RESET# and PERST# GPIOs + // + if (PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem) !=3D 0 && PcdGet1= 6 (PcdBoardGpioTableWwanOffEarlyPreMemSize) !=3D 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOff= EarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize)); + } + if (PcdGetBool (PcdPcieWwanEnable) =3D=3D TRUE && PcdGetBool (PcdWwa= nResetWorkaround) =3D=3D TRUE) { + MicroSecondDelay (1 * 1000); // Delay by 1ms + } + } + + // + // Turn ON modem power and de-assert RESET# and PERST# GPIOs + // + if (PcdGetBool (PcdPcieWwanEnable) =3D=3D TRUE) { + if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) !=3D 0 && PcdGet16= (PcdBoardGpioTableWwanOnEarlyPreMemSize) !=3D 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOnE= arlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize)); + } + } + } +} + +/** + Configure GPIO + +**/ +VOID +GpioInit ( + VOID + ) +{ + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) Pc= dGet16 (PcdBoardGpioTableSize)); + + if (PcdGet32 (PcdBoardGpioTable2)) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable2), (UINTN)= PcdGet16 (PcdBoardGpioTable2Size)); + } + + TouchpanelGpioInit(); + + // + // Lock pads after initializing platform GPIO. + // Pads which were requested to be unlocked during configuration + // will not be locked. + // + GpioLockPads (); + + return; +} + +/** + Configure Super IO + +**/ +VOID +SioInit ( + VOID + ) +{ + // + // Program and Enable Default Super IO Configuration Port Addresses and = range + // + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x1= 0); + + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10); + return; +} + +/** + Configure GPIO and SIO before memory ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitPreMem ( + VOID + ) +{ + // + // Obtain Platform Info from HOB. + // + GpioInitPreMem (); + GpioGroupTierInitHook (); + SioInit (); + + return EFI_SUCCESS; +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + VOID + ) +{ + + GpioInit (); + + return EFI_SUCCESS; +} + +/** + Do platform specific programming post-memory. + + @retval EFI_SUCCESS The function completed successfully. +**/ + +EFI_STATUS +PlatformSpecificInit ( + VOID + ) +{ + GPIO_CONFIG GpioConfig; + + if (IsCnlPch ()) { + + // + // Tristate unused pins by audio link mode. + // + ZeroMem(&GpioConfig, sizeof(GPIO_CONFIG)); + GpioConfig.PadMode =3D GpioPadModeGpio; + GpioConfig.HostSoftPadOwn =3D GpioHostOwnGpio; + GpioConfig.Direction =3D GpioDirNone; + GpioConfig.OutputState =3D GpioOutDefault; + GpioConfig.InterruptConfig =3D GpioIntDis; + GpioConfig.PowerConfig =3D GpioPlatformReset; + GpioConfig.ElectricalConfig =3D GpioTermNone; + + GpioSetPadConfig (GPIO_CNL_LP_SSP1_SFRM, &GpioConfig); + GpioSetPadConfig (GPIO_CNL_LP_SSP1_TXD, &GpioConfig); + + } + + return EFI_SUCCESS; +} + +/** + Early Board Configuration before memory is ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitEarlyPreMem ( + VOID + ) +{ + GpioInitEarlyPreMem (); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/CometlakeOpenBoardP= kg/CometlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..193ccc841f --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPlatfor= mHookLib/PeiPlatformHooklib.inf @@ -0,0 +1,95 @@ +## @file +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPlatformHookLib + FILE_GUID =3D AD901798-B0DA-4B20-B90C-283F886E76D0 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC + +[LibraryClasses] + DebugLib + BaseMemoryLib + IoLib + HobLib + PcdLib + TimerLib + PchCycleDecodingLib + GpioLib + CpuPlatformLib + PeiServicesLib + ConfigBlockLib + PeiSaPolicyLib + GpioExpanderLib + PmcLib + PchPcrLib + PciSegmentLib + GpioCheckConflictLib + +[Packages] + MdePkg/MdePkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2 #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel #= # CONSUMES + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemS= ize + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem= Size + + # GPIO Group Tier + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 #= # CONSUMES + + # Misc + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio #= # CONSUMES + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable #= # CONSUMES + + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable + gCometlakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround + +[Sources] + PeiPlatformHooklib.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + +[Guids] + gSaDataHobGuid ## CONSUMES + gEfiGlobalVariableGuid ## CONSUMES + gGpioCheckConflictHobGuid ## CONSUMES + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c b/Platform/Intel/CometlakeOp= enBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardC= onfig.c new file mode 100644 index 0000000000..d1d1920823 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiCpuPolicyBoardConfig.c @@ -0,0 +1,49 @@ +/** @file + Intel PEI CPU Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI CPU Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "Updating CPU Policy by board config in Post Mem\n"))= ; + + Status =3D PeiServicesLocatePpi( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c b/Platform/Intel/Comet= lakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPolicy= BoardConfigPreMem.c new file mode 100644 index 0000000000..2b80a268e6 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiCpuPolicyBoardConfigPreMem.c @@ -0,0 +1,29 @@ +/** @file + Intel PEI CPU Pre-Memory Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI CPU Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiMePolicyBoardConfig.c b/Platform/Intel/CometlakeOpe= nBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardCon= fig.c new file mode 100644 index 0000000000..cff2b03ca9 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiMePolicyBoardConfig.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI ME Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI ME Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Post Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI= D *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c b/Platform/Intel/Cometl= akeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicyBo= ardConfigPreMem.c new file mode 100644 index 0000000000..610b6b8cb5 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiMePolicyBoardConfigPreMem.c @@ -0,0 +1,37 @@ +/** @file + Intel PEI ME Pre-Memory Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI ME Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Pre Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMePeiPreMemConf= igGuid, (VOID *) &MePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiPchPolicyBoardConfig.c b/Platform/Intel/CometlakeOp= enBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardC= onfig.c new file mode 100644 index 0000000000..a3b3a63eec --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiPchPolicyBoardConfig.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI PCH Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI PCH Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + PCH_GENERAL_CONFIG *PchGeneralConfig; + + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Post Mem\n"))= ; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid,= (VOID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c b/Platform/Intel/Comet= lakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPolicy= BoardConfigPreMem.c new file mode 100644 index 0000000000..01bb75525b --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiPchPolicyBoardConfigPreMem.c @@ -0,0 +1,37 @@ +/** @file + Intel PEI PCH Pre-Memory Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI PCH Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Pre Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMe= mConfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiPolicyBoardConfig.h b/Platform/Intel/CometlakeOpenB= oardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.= h new file mode 100644 index 0000000000..64f6c67639 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiPolicyBoardConfig.h @@ -0,0 +1,22 @@ +/** @file + Header file for PeiPolicyBoardConfig library instance. + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_POLICY_BOARD_CONFIG_H_ +#define _PEI_POLICY_BOARD_CONFIG_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf b/Platform/Intel/Cometlake= OpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardCo= nfigLib.inf new file mode 100644 index 0000000000..9eb7c5eef0 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiPolicyBoardConfigLib.inf @@ -0,0 +1,71 @@ +## @file +# Module Information file for PeiPolicyBoardConfigLib Library +# +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPolicyBoardConfigLib + FILE_GUID =3D B1E959E3-9DCA-4D6F-938C-420C3BF5D820 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPolicyBoardConfigLib|PEIM PEI_CORE= SEC + +[Sources] + PeiCpuPolicyBoardConfigPreMem.c + PeiCpuPolicyBoardConfig.c + PeiMePolicyBoardConfigPreMem.c + PeiMePolicyBoardConfig.c + PeiPchPolicyBoardConfigPreMem.c + PeiPchPolicyBoardConfig.c + PeiSaPolicyBoardConfigPreMem.c + PeiSaPolicyBoardConfig.c + PeiSiPolicyBoardConfig.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + CometlakeOpenBoardPkg/OpenBoardPkg.dec + SecurityPkg/SecurityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[LibraryClasses] + PcdLib + DebugLib + HobLib + ConfigBlockLib + IoLib + BaseCryptLib + BaseMemoryLib + +[Guids] + gCpuSecurityPreMemConfigGuid ## CONSUMES + gMePeiPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gPchGeneralConfigGuid ## CONSUMES + gEfiTpmDeviceInstanceTpm20DtpmGuid + gEfiTpmDeviceInstanceTpm12Guid + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = ## CONSUMES + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiSaPolicyBoardConfig.c b/Platform/Intel/CometlakeOpe= nBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardCon= fig.c new file mode 100644 index 0000000000..a8f6860bd0 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiSaPolicyBoardConfig.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI SA Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI SA Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + GRAPHICS_PEI_CONFIG *GtConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Post Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid= , (VOID *)&GtConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c b/Platform/Intel/Cometl= akeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBo= ardConfigPreMem.c new file mode 100644 index 0000000000..aef2c8958f --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiSaPolicyBoardConfigPreMem.c @@ -0,0 +1,37 @@ +/** @file + Intel PEI SA Pre-Memory Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI SA Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Pre Mem\n")); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + return Status; +} + + diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/Pei= PolicyBoardConfigLib/PeiSiPolicyBoardConfig.c b/Platform/Intel/CometlakeOpe= nBoardPkg/CometlakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardCon= fig.c new file mode 100644 index 0000000000..e8dd2b9609 --- /dev/null +++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/Library/PeiPolicyB= oardConfigLib/PeiSiPolicyBoardConfig.c @@ -0,0 +1,27 @@ +/** @file + Intel PEI SA Policy update by board configuration + + + Copyright (c) 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI SI Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + return EFI_SUCCESS; +} + --=20 2.16.2.windows.1