From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web12.302.1582755456267293948 for ; Wed, 26 Feb 2020 14:17:36 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: nathaniel.l.desimone@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Feb 2020 14:17:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,489,1574150400"; d="scan'208";a="238182852" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by orsmga003.jf.intel.com with ESMTP; 26 Feb 2020 14:17:35 -0800 Received: from orsmsx121.amr.corp.intel.com (10.22.225.226) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 26 Feb 2020 14:17:35 -0800 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.140]) by ORSMSX121.amr.corp.intel.com ([169.254.10.140]) with mapi id 14.03.0439.000; Wed, 26 Feb 2020 14:17:35 -0800 From: "Nate DeSimone" To: "Agyeman, Prince" , "devel@edk2.groups.io" CC: "Chiu, Chasel" Subject: Re: [edk2-platforms] [PATCH 2/2] CoffeelakeSiliconPkg: Add Missing Library Thread-Topic: [edk2-platforms] [PATCH 2/2] CoffeelakeSiliconPkg: Add Missing Library Thread-Index: AQHV7D/jiGEEXtbKsUmclmmGxID5KaguDHzg Date: Wed, 26 Feb 2020 22:17:34 +0000 Message-ID: <02A34F284D1DA44BB705E61F7180EF0AB5D8CCE1@ORSMSX114.amr.corp.intel.com> References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjNmMzZmY2ItMzg4MC00ZTQyLWE5Y2QtN2Y1ZjA5YTU0ODdlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiXC9wWWtvZWIrQThIZEhNM1BHUlwvemI2NmVSbHRJd2dpUWRuTElXdENwbEF5U3pWNjBCb0dqcjJQdjVPVFBKbnBIIn0= x-ctpclassification: CTP_NT x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Return-Path: nathaniel.l.desimone@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone -----Original Message----- From: Agyeman, Prince =20 Sent: Tuesday, February 25, 2020 4:59 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Desimone, Nathaniel L Subject: [edk2-platforms] [PATCH 2/2] CoffeelakeSiliconPkg: Add Missing Lib= rary REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2408 Added GbeMdiLib implementation and added additional registers definitions n= eeded by GbeMdilib. This fixes the linker errors seen during VS2017 builds Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Prince Agyeman --- .../Pch/Include/Library/GbeMdiLib.h | 53 ++- .../Pch/Include/Register/PchRegsLan.h | 14 +- .../Library/PeiDxeSmmGbeMdiLib/GbeMdiLib.c | 391 ++++++++++++++++++ .../PeiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf | 32 ++ .../Pch/PchInit/Smm/PchInitSmm.inf | 1 + .../CoffeelakeSiliconPkg/SiPkgCommonLib.dsc | 4 +- 6 files changed, 492 insertions(+), 3 deletions(-) create mode 100644 Sil= icon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGbeMdiLib/GbeMdiLib.c create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSm= mGbeMdiLib/PeiDxeSmmGbeMdiLib.inf diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiL= ib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h index a6ce032eba..280dee411f 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h @@ -21,7 +21,7 @@ - Registers / bits of new devices introduced in a PCH generation will be= just named as "_PCH_" without [generation_name] inserted. =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.=20 +
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -29,7 +29,35 @@ #i= fndef _GBE_MDI_LIB_H_ #define _GBE_MDI_LIB_H_ =20 + +#define GBE_MAX_LOOP_TIME 4000 +#define GBE_ACQUIRE_MDIO_DELAY 50 +#define GBE_MDI_SET_PAGE_DELAY 4000 // 4 mSec delay after setting page + + +// +// Custom Mode Control PHY Address 01, Page 769, Register 16 // +#define R_PHY_MDI_PAGE_769_REGISETER_16_CMC 0x0010 +// +// Custom Mode Control +// Page 769, Register 16, BIT 10 +// 0 - normal MDIO frequency access +// 1 - reduced MDIO frequency access (slow mdio) +// required for read during cable disconnect +// +#define B_PHY_MDI_PAGE_769_REGISETER_16_CMC_MDIO_FREQ_ACCESS BIT10 + // +// LAN PHY MDI settings +// +#define B_PHY_MDI_READY BIT28 +#define B_PHY_MDI_READ BIT27 +#define B_PHY_MDI_WRITE BIT26 +// +// PHY SPECIFIC registers +// +#define B_PHY_MDI_PHY_ADDRESS_02 BIT22 // // PHY GENERAL registers // Registers 0 to 15 are defined by the specification @@ -37,8 +65,22 @@ // #define B_PHY_MDI_PHY_ADDRESS_01 BIT21 #define B_PHY_MDI_PHY_ADDRESS_MASK (BIT25 | BIT24 | BIT23 | BIT22 | BIT= 21) +// +// PHY Identifier Register 2 +// Bits [15:10] - PHY ID Number - The PHY identifier composed of bits 3= through 18 +// of the Organizationally Unique Identi= fier (OUI) +// Bits [9:4] - Device Model Number +// Bits [3:0] - Device Revision Number +// +#define R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2 0x00030000 + #define MDI_REG_SHIFT(x) (x << 16) +#define B_PHY_MDI_PHY_REGISTER_MASK (BIT20 | BIT19 | BIT= 18 | BIT17 | BIT16) +#define R_PHY_MDI_PHY_REG_SET_ADDRESS 0x00110000 // Used a= fter new page setting #define R_PHY_MDI_PHY_REG_DATA_READ_WRITE 0x00120000 +#define R_PHY_MDI_PHY_REG_SET_PAGE 0x001F0000 + +// // LAN PHY MDI registers and bits // =20 @@ -131,6 +173,7 @@ =20 **/ VOID +EFIAPI GbeMdiForceMACtoSMB ( IN UINT32 GbeBar ); @@ -144,6 +187,7 @@ GbeMdiForceMACtoSMB ( @retval EFI_TIMEOUT **/ EFI_STATUS +EFIAPI GbeMdiWaitReady ( IN UINT32 GbeBar ); @@ -160,6 +204,7 @@ GbeMdiWaitReady ( @retval EFI_TIMEOUT **/ EFI_STATUS +EFIAPI GbeMdiAcquireMdio ( IN UINT32 GbeBar ); @@ -170,6 +215,7 @@ GbeMdiAcquireMdio ( @param [in] GbeBar GbE MMIO space **/ VOID +EFIAPI GbeMdiReleaseMdio ( IN UINT32 GbeBar ); @@ -186,6 +232,7 @@ GbeMdiReleaseMdio ( @retval EFI_DEVICE_ERROR Returned if both attermps of setting page fail= ed **/ EFI_STATUS +EFIAPI GbeMdiSetPage ( IN UINT32 GbeBar, IN UINT32 Page @@ -200,6 +247,7 @@ GbeMdiSetPage ( @return EFI_STATUS **/ EFI_STATUS +EFIAPI GbeMdiSetRegister ( IN UINT32 GbeBar, IN UINT32 Register @@ -219,6 +267,7 @@ GbeMdiSetRegister ( @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed **/ EFI_STATUS +EFIAPI GbeMdiRead ( IN UINT32 GbeBar, IN UINT32 PhyAddress, @@ -239,6 +288,7 @@ GbeMdiRead ( @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed **/ EFI_STATUS +EFIAPI GbeMdiWrite ( IN UINT32 GbeBar, IN UINT32 PhyAddress, @@ -257,6 +307,7 @@ GbeMdiWrite ( @return EFI_INVALID_PARAMETER When GbeBar is incorrect **/ EFI_STATUS +EFIAPI GbeMdiGetLanPhyRevision ( IN UINT32 GbeBar, OUT UINT16 *LanPhyRevision diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sLan.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan= .h index f649873f67..8efc9fad09 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan.h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan +++ .h @@ -30,7 +30,7 @@ - RegisterName: Full register name. =20 - Copyright (c) 2019 Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.=20 +
=20 SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -49,6 +49,17 @@ #define R_LAN_CFG_PMCS 0xCC #define B_LAN_CFG_PMCS_PS (BIT1 | BIT0) #define V_LAN_CFG_PMCS_PS0 0x00 +#define R_LAN_MEM_CSR_CTRL 0 +#define B_LAN_MEM_CSR_CTRL_LANPHYPC_OVERRIDE BIT16 +#define B_LAN_MEM_CSR_CTRL_LANPHYPC_VAL BIT17 +#define R_LAN_MEM_CSR_CTRL_EXT 0x0018 +#define B_LAN_MEM_CSR_CTRL_EXT_LPCD BIT2 +#define B_LAN_MEM_CSR_CTRL_EXT_FORCE_SMB BIT11 +#define R_LAN_MEM_CSR_MDIC 0x0020 +#define B_LAN_MEM_CSR_MDIC_RB BIT28 +#define B_LAN_MEM_CSR_MDIC_DATA 0xFFFF +#define R_LAN_MEM_CSR_EXTCNF_CTRL 0x0F00 +#define B_LAN_MEM_CSR_EXTCNF_CTRL_SWFLAG BIT5 #define R_LAN_MEM_CSR_RAL 0x5400 #define R_LAN_MEM_CSR_RAH 0x5404 #define B_LAN_MEM_CSR_RAH_RAH 0x0000FFFF @@ -56,3 +67,4 @@ #define B_LAN_MEM_CSR_WUC_APME BIT0 =20 #endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGbeMdi= Lib/GbeMdiLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmG= beMdiLib/GbeMdiLib.c new file mode 100644 index 0000000000..e5aa10de3b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGbeMdiLib/ +++ GbeMdiLib.c @@ -0,0 +1,391 @@ +/** @file + Gbe MDI Library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2020 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Validates both Phy Address and Regster. + + @param [in] PhyAddress + @param [in] PhyRegister + + @retval BOOLEAN TRUE Validation passed + FALSE If the data is not within its range + +**/ +BOOLEAN +EFIAPI +IsPhyAddressRegisterValid ( + IN UINT32 PhyAddress, + IN UINT32 PhyRegister + ) +{ + if (((PhyAddress & (~B_PHY_MDI_PHY_ADDRESS_MASK)) !=3D 0) || ((PhyRegist= er & (~B_PHY_MDI_PHY_REGISTER_MASK)) !=3D 0)) { + DEBUG ((DEBUG_ERROR, "IsPhyAddressRegisterValid validation failed! Phy= Address: 0x%08X PhyRegister: 0x%08X \n", PhyAddress, PhyRegister)); + return FALSE; + } + return TRUE; +} + +/** + Change Extended Device Control Register BIT 11 to 1 which + forces the interface between the MAC and the Phy to be on SMBus. + Cleared on the assertion of PCI reset. + + @param [in] GbeBar GbE MMIO space + +**/ +VOID +EFIAPI +GbeMdiForceMacToSmb ( + IN UINT32 GbeBar + ) +{ + MmioOr32 (GbeBar + R_LAN_MEM_CSR_CTRL_EXT,=20 +B_LAN_MEM_CSR_CTRL_EXT_FORCE_SMB); +} + +/** + Test for MDIO operation complete. + + @param [in] GbeBar GbE MMIO space + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT +**/ +EFI_STATUS +EFIAPI +GbeMdiWaitReady ( + IN UINT32 GbeBar + ) +{ + UINT32 Count; + + for (Count =3D 0; Count < GBE_MAX_LOOP_TIME; ++Count) { + if (MmioRead32 (GbeBar + R_LAN_MEM_CSR_MDIC) & B_LAN_MEM_CSR_MDIC_RB) = { + return EFI_SUCCESS; + } + MicroSecondDelay (GBE_ACQUIRE_MDIO_DELAY); + } + DEBUG ((DEBUG_ERROR, "GbeMdiWaitReady Timeout reached. MDIO operation=20 +failed to complete in %d micro seconds\n", GBE_MAX_LOOP_TIME *=20 +GBE_ACQUIRE_MDIO_DELAY)); + return EFI_TIMEOUT; +} + +/** + Acquire MDIO software semaphore. + + 1. Ensure that MBARA offset F00h [5] =3D 1b 2. Poll MBARA offset F00h=20 + [5] up to 200ms + + @param [in] GbeBar GbE MMIO space + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT +**/ +EFI_STATUS +EFIAPI +GbeMdiAcquireMdio ( + IN UINT32 GbeBar + ) +{ + UINT32 ExtCnfCtrl; + UINT32 Count; + + MmioOr32 (GbeBar + R_LAN_MEM_CSR_EXTCNF_CTRL,=20 +B_LAN_MEM_CSR_EXTCNF_CTRL_SWFLAG); + for (Count =3D 0; Count < GBE_MAX_LOOP_TIME; ++Count) { + ExtCnfCtrl =3D MmioRead32 (GbeBar + R_LAN_MEM_CSR_EXTCNF_CTRL); + if (ExtCnfCtrl & B_LAN_MEM_CSR_EXTCNF_CTRL_SWFLAG) { + return EFI_SUCCESS; + } + MicroSecondDelay (GBE_ACQUIRE_MDIO_DELAY); + } + DEBUG ((DEBUG_ERROR, "GbeMdiAcquireMdio Timeout. Unable to acquire=20 +MDIO Semaphore in %d micro seconds\n", GBE_MAX_LOOP_TIME *=20 +GBE_ACQUIRE_MDIO_DELAY)); + return EFI_TIMEOUT; +} + +/** + Release MDIO software semaphore by clearing MBARA offset F00h [5] + + @param [in] GbeBar GbE MMIO space +**/ +VOID +EFIAPI +GbeMdiReleaseMdio ( + IN UINT32 GbeBar + ) +{ + ASSERT (MmioRead32 (GbeBar + R_LAN_MEM_CSR_EXTCNF_CTRL) &=20 +B_LAN_MEM_CSR_EXTCNF_CTRL_SWFLAG); + MmioAnd32 (GbeBar + R_LAN_MEM_CSR_EXTCNF_CTRL, (UINT32)=20 +~B_LAN_MEM_CSR_EXTCNF_CTRL_SWFLAG); + ASSERT ((MmioRead32 (GbeBar + R_LAN_MEM_CSR_EXTCNF_CTRL) &=20 +B_LAN_MEM_CSR_EXTCNF_CTRL_SWFLAG) =3D=3D 0); } + +/** + Sets page on MDI + Page setting is attempted twice. + If first attempt failes MAC and the Phy are force to be on SMBus. + + Waits 4 mSec after page setting + + @param [in] GbeBar GbE MMIO space + @param [in] Data Value to write in lower 16bits. + + @retval EFI_SUCCESS Page setting was successfull + @retval EFI_DEVICE_ERROR Returned if both attermps of setting page=20 +failed **/ EFI_STATUS EFIAPI GbeMdiSetPage ( + IN UINT32 GbeBar, + IN UINT32 Page + ) +{ + EFI_STATUS Status; + + MmioWrite32 (GbeBar + R_LAN_MEM_CSR_MDIC, (~B_PHY_MDI_READY) &=20 + (B_PHY_MDI_WRITE | B_PHY_MDI_PHY_ADDRESS_01 |=20 + R_PHY_MDI_PHY_REG_SET_PAGE | ((Page * 32) & 0xFFFF))); + + Status =3D GbeMdiWaitReady (GbeBar); + + if (Status =3D=3D EFI_TIMEOUT) { + DEBUG ((DEBUG_INFO, "GbeMdiSetPage Timeout reached. Forcing the interf= ace between the MAC and the Phy to be on SMBus\n")); + GbeMdiForceMacToSmb (GbeBar); + // + // Retry page setting + // + MmioWrite32 (GbeBar + R_LAN_MEM_CSR_MDIC, (~B_PHY_MDI_READY) & (B_PHY_= MDI_WRITE | B_PHY_MDI_PHY_ADDRESS_01 | R_PHY_MDI_PHY_REG_SET_PAGE | ((Page = * 32) & 0xFFFF))); + Status =3D GbeMdiWaitReady (GbeBar); + if (Status =3D=3D EFI_TIMEOUT) { + DEBUG ((DEBUG_ERROR, "GbeMdiSetPage retry page setting failed!\n")); + return EFI_DEVICE_ERROR; + } + } + + // + // Delay required for page to set properly // MicroSecondDelay=20 + (GBE_MDI_SET_PAGE_DELAY); + + return Status; +} + +/** + Sets Register in current page. + + @param [in] GbeBar GbE MMIO space + @param [in] register Register number valid only in lower 16 Bits + + @return EFI_STATUS +**/ +EFI_STATUS +EFIAPI +GbeMdiSetRegister ( + IN UINT32 GbeBar, + IN UINT32 Register + ) +{ + MmioWrite32 (GbeBar + R_LAN_MEM_CSR_MDIC, (~B_PHY_MDI_READY) &=20 +(B_PHY_MDI_WRITE | B_PHY_MDI_PHY_ADDRESS_01 |=20 +R_PHY_MDI_PHY_REG_SET_ADDRESS | (Register & 0xFFFF))); + return GbeMdiWaitReady (GbeBar); +} + +/** + Perform MDI write. + + @param [in] GbeBar GbE MMIO space + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 + @param [in] PhyRegister Phy Register + @param [in] WriteData Value to write in lower 16bits. + + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton=20 +failed **/ EFI_STATUS EFIAPI GbeMdiWrite ( + IN UINT32 GbeBar, + IN UINT32 PhyAddress, + IN UINT32 PhyRegister, + IN UINT32 WriteData + ) +{ + if(!IsPhyAddressRegisterValid (PhyAddress, PhyRegister)) { + DEBUG ((DEBUG_ERROR, "GbeMdiWrite PhyAddressRegister validaton failed!= \n")); + return EFI_INVALID_PARAMETER; + } + + MmioWrite32 (GbeBar + R_LAN_MEM_CSR_MDIC, (~B_PHY_MDI_READY) &=20 +(B_PHY_MDI_WRITE | PhyAddress | PhyRegister | (WriteData & 0xFFFF))); + return GbeMdiWaitReady (GbeBar); +} + +/** + Perform MDI read. + + @param [in] GbeBar GbE MMIO space + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 + @param [in] PhyRegister Phy Register + @param [out] ReadData Return Value + + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton=20 +failed **/ EFI_STATUS EFIAPI GbeMdiRead ( + IN UINT32 GbeBar, + IN UINT32 PhyAddress, + IN UINT32 PhyRegister, + OUT UINT16 *ReadData + ) +{ + EFI_STATUS Status; + + if(!IsPhyAddressRegisterValid (PhyAddress, PhyRegister)) { + DEBUG ((DEBUG_ERROR, "GbeMdiRead PhyAddressRegister validaton failed!\= n")); + return EFI_INVALID_PARAMETER; + } + + MmioWrite32 (GbeBar + R_LAN_MEM_CSR_MDIC, (~B_PHY_MDI_READY) &=20 +(B_PHY_MDI_READ | PhyAddress | PhyRegister)); + Status =3D GbeMdiWaitReady (GbeBar); + if (EFI_SUCCESS =3D=3D Status) { + *ReadData =3D (UINT16) MmioRead32 (GbeBar + R_LAN_MEM_CSR_MDIC); + } + return Status; +} + +/** + Gets Phy Revision and Model Number + from PHY IDENTIFIER register 2 (offset 3) + + @param [in] GbeBar GbE MMIO space + @param [out] LanPhyRevision Return Value + + @return EFI_STATUS + @return EFI_INVALID_PARAMETER When GbeBar is incorrect + When Phy register or address is out of=20 +bounds **/ EFI_STATUS EFIAPI GbeMdiGetLanPhyRevision ( + IN UINT32 GbeBar, + OUT UINT16 *LanPhyRevision + ) +{ + EFI_STATUS Status; + UINT8 LpcdLoop; + + if (!((GbeBar & 0xFFFFF000) > 0)) { + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision GbeBar validation failed= ! Bar: 0x%08X \n", GbeBar)); + return EFI_INVALID_PARAMETER; + } + + Status =3D GbeMdiAcquireMdio (GbeBar); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to aquire MDIO se= maphore. Status: %r\n", Status)); + return Status; + } + + Status =3D GbeMdiSetPage (GbeBar,=20 + PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to Set Page 769. = Status: %r\n", Status)); + GbeMdiReleaseMdio (GbeBar); + return Status; + } + + // + // Set register to: Custom Mode Control + // Reduced MDIO frequency access (slow mdio) + // BIT 10 set to 1 + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT= =20 + (R_PHY_MDI_PAGE_769_REGISETER_16_CMC), BIT13 | B_PHY_MDI_PAGE_769_REGISET= ER_16_CMC_MDIO_FREQ_ACCESS | BIT8 | BIT7); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to enable slow MD= IO mode. Status: %r\n", Status)); + GbeMdiReleaseMdio (GbeBar); + return Status; + } + + // + // Read register PHY Version from PHY IDENTIFIER 2 (offset 0x3) + // Bits [9:4] - Device Model Number + // Bits [3:0] - Device Revision Number + // + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02,=20 + R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision); + + // + // Failed to obtain PHY REV + // + if (*LanPhyRevision =3D=3D 0x0) { + if ((MmioRead32 (GbeBar + R_LAN_MEM_CSR_CTRL) & (B_LAN_MEM_CSR_CTRL_LA= NPHYPC_OVERRIDE | B_LAN_MEM_CSR_CTRL_LANPHYPC_VAL))) { + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to read Phy Rev= ision. Other component tried to initialize GbE and failed.\n")); + Status =3D EFI_DEVICE_ERROR; + goto PHY_EXIT; + } + DEBUG ((DEBUG_INFO, "GbeMdiGetLanPhyRevision failed to read Revision. = Overriding LANPHYPC\n", Status)); + // + // Taking over LANPHYPC + // 1. SW signal override - 1st cycle. + // 2. Turn LCD on - 2nd cycle. + // + MmioOr32 (GbeBar + R_LAN_MEM_CSR_CTRL, B_LAN_MEM_CSR_CTRL_LANPHYPC_OVE= RRIDE); + MmioOr32 (GbeBar + R_LAN_MEM_CSR_CTRL,=20 + B_LAN_MEM_CSR_CTRL_LANPHYPC_VAL); + + // + // Poll on LPCD for 100mSec + // + LpcdLoop =3D 101; + while (LpcdLoop > 0) { + if (MmioRead32 (GbeBar + R_LAN_MEM_CSR_CTRL_EXT) & B_LAN_MEM_CSR_CTR= L_EXT_LPCD) { + break; + } else { + LpcdLoop--; + MicroSecondDelay (1000); + } + } + + if (LpcdLoop > 0) { + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02, R_PHY_MDI_G= ENEREAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision); + } + // + // Restore LANPHYPC + // 1. Turn LCD off - 1st cycle. + // 2. Remove SW signal override - 2nd cycle. + // + MmioAnd32 (GbeBar + R_LAN_MEM_CSR_CTRL, (UINT32) ~B_LAN_MEM_CSR_CTRL_L= ANPHYPC_VAL); + MmioAnd32 (GbeBar + R_LAN_MEM_CSR_CTRL, (UINT32)=20 + ~B_LAN_MEM_CSR_CTRL_LANPHYPC_OVERRIDE); + } + +PHY_EXIT: + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to read Revision = and Model Number from PHY Identifier 2. Status: %r\n", Status)); + GbeMdiReleaseMdio (GbeBar); + return Status; + } + + // + // Switch back to normal MDIO frequency access // Status =3D=20 + GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT=20 + (R_PHY_MDI_PAGE_769_REGISETER_16_CMC), (~B_PHY_MDI_PAGE_769_REGISETER_16_= CMC_MDIO_FREQ_ACCESS) & (BIT13 | BIT8 | BIT7)); if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to disable=20 + slow MDIO mode. Status: %r\n", Status)); } + + GbeMdiReleaseMdio (GbeBar); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGbeMdi= Lib/PeiDxeSmmGbeMdiLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library= /PeiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf new file mode 100644 index 0000000000..be54788149 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGbeMdiLib/ +++ PeiDxeSmmGbeMdiLib.inf @@ -0,0 +1,32 @@ +## @file +# Gbe MDI Library. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2020 Intel Corporation. All rights reserved.
# #=20 +SPDX-License-Identifier: BSD-2-Clause-Patent ## + + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDxeSmmGbeMdiLib + FILE_GUID =3D 0360E6F6-892A-4852-BF98-15C0D30D8A48 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D GbeMdiLib + +[LibraryClasses] + BaseLib + IoLib + DebugLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + GbeMdiLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.= inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.inf index 267c45872d..9418d7a4c8 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.inf +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.inf @@ -46,6 +46,7 @@ TimerLib ConfigBlockLib PmcPrivateLib SataLib +GbeMdiLib =20 [Packages] MdePkg/MdePkg.dec diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc b/Silico= n/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc index 7a9911e825..c631421408 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc @@ -1,7 +1,7 @@ ## @file # Component description file for the Coffee Lake silicon package both PEI= and DXE libraries DSC file. # -# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# Copyright (c) 2019 - 2020 Intel Corporation. All rights reserved.=20 +
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -34,6 +34,8 @@ DEFINE= PCH =3D Cnl PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcieRpLib/Pei= DxeSmmPchPcieRpLib.inf PchPcrLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcrLib/PeiDxeSmm= PchPcrLib.inf PmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib= .inf + GbeMdiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmGbeMdiLib/PeiDxe + GbeMdiLib|SmmGbeMdiLib.inf + =20 PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSbiAccessL= ib/PeiDxeSmmPchSbiAccessLib.inf GpioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpio= Lib.inf -- 2.19.1.windows.1