From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.136; helo=mga12.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 48D302117CE94 for ; Tue, 6 Nov 2018 03:37:36 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Nov 2018 03:37:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,471,1534834800"; d="scan'208";a="103826156" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga004.fm.intel.com with ESMTP; 06 Nov 2018 03:37:35 -0800 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 6 Nov 2018 03:37:35 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 6 Nov 2018 03:37:34 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.84]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.161]) with mapi id 14.03.0415.000; Tue, 6 Nov 2018 19:37:33 +0800 From: "Yao, Jiewen" To: "Chiu, Chasel" CC: "edk2-devel@lists.01.org" , "Desimone, Nathaniel L" Thread-Topic: [PATCH] IntelFsp2WrapperPkg: Support FSP Dispatch mode Thread-Index: AQHUdbI+wJBrTYniKE6T15dRKFY5C6VCntFM Date: Tue, 6 Nov 2018 11:37:32 +0000 Message-ID: <02AD6047-4226-42C5-9185-0EC788903D48@intel.com> References: <20181106092042.9520-1-chasel.chiu@intel.com> In-Reply-To: <20181106092042.9520-1-chasel.chiu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: MIME-Version: 1.0 Subject: Re: [PATCH] IntelFsp2WrapperPkg: Support FSP Dispatch mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Nov 2018 11:37:36 -0000 Content-Language: zh-CN Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable hi chasel I think our guide is not to use #if, but use if() Is there any special reason in this patch? thank you! Yao, Jiewen > =1B$B:_=1B(B 2018=1B$BG/=1B(B11=1B$B7n=1B(B6=1B$BF|!$2<8a=1B(B5:22=1B$B!$= =1B(BChiu, Chasel =1B$B=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1300 >=20 > Provides PCD selection for FSP Wrapper to support Dispatch > mode. Also PcdFspmBaseAddress should support Dynamic for > recovery scenario (multiple FSP-M binary in flash) >=20 > Test: Verified on internal platform and both API and > DISPATCH modes booted successfully. >=20 > Cc: Jiewen Yao > Cc: Desimone Nathaniel L > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu > --- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 16 ++++++++++++= ++-- > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 14 ++++++++++++= -- > IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 3 ++- > IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++- > IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec | 13 +++++++++++-= - > 5 files changed, 41 insertions(+), 8 deletions(-) >=20 > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/Inte= lFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > index 7b7c5f5d86..8128a26873 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c > @@ -3,7 +3,7 @@ > register TemporaryRamDonePpi to call TempRamExit API, and register Memo= ryDiscoveredPpi > notify to call FspSiliconInit API. >=20 > - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the B= SD License > which accompanies this distribution. The full text of the license may = be found at > @@ -65,7 +65,7 @@ PeiFspMemoryInit ( > FspHobListPtr =3D NULL; > FspmUpdDataPtr =3D NULL; >=20 > - FspmHeaderPtr =3D (FSP_INFO_HEADER *)FspFindFspHeader (PcdGet32 (PcdFs= pmBaseAddress)); > + FspmHeaderPtr =3D (FSP_INFO_HEADER *) FspFindFspHeader (PcdGet32 (PcdF= spmBaseAddress)); > DEBUG ((DEBUG_INFO, "FspmHeaderPtr - 0x%x\n", FspmHeaderPtr)); > if (FspmHeaderPtr =3D=3D NULL) { > return EFI_DEVICE_ERROR; > @@ -155,8 +155,20 @@ FspmWrapperInit ( > { > EFI_STATUS Status; >=20 > + Status =3D EFI_SUCCESS; > + > +#if FixedPcdGet8 (PcdFspModeSelection) =3D=3D 1 > Status =3D PeiFspMemoryInit (); > ASSERT_EFI_ERROR (Status); > +#else > + PeiServicesInstallFvInfoPpi ( > + NULL, > + (VOID *)(UINTN) PcdGet32 (PcdFspmBaseAddress), > + (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFspmBas= eAddress))->FvLength, > + NULL, > + NULL > + ); > +#endif >=20 > return Status; > } > diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/Inte= lFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > index 70dac7a414..d11655df89 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c > @@ -3,7 +3,7 @@ > register TemporaryRamDonePpi to call TempRamExit API, and register Memo= ryDiscoveredPpi > notify to call FspSiliconInit API. >=20 > - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
> + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the B= SD License > which accompanies this distribution. The full text of the license may = be found at > @@ -349,7 +349,17 @@ FspsWrapperPeimEntryPoint ( > { > DEBUG ((DEBUG_INFO, "FspsWrapperPeimEntryPoint\n")); >=20 > - FspsWrapperInit (); > +#if FixedPcdGet8 (PcdFspModeSelection) =3D=3D 1 > + FspsWrapperInit (); > +#else > + PeiServicesInstallFvInfoPpi ( > + NULL, > + (VOID *)(UINTN) PcdGet32 (PcdFspsBaseAddress), > + (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFspsB= aseAddress))->FvLength, > + NULL, > + NULL > + ); > +#endif >=20 > return EFI_SUCCESS; > } > diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf b/In= telFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > index 542356b582..b3776a80f3 100644 > --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf > @@ -6,7 +6,7 @@ > # register TemporaryRamDonePpi to call TempRamExit API, and register Memo= ryDiscoveredPpi > # notify to call FspSiliconInit API. > # > -# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. > # > # This program and the accompanying materials > # are licensed and made available under the terms and conditions of the = BSD License > @@ -61,6 +61,7 @@ > [Pcd] > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES >=20 > [Sources] > FspmWrapperPeim.c > diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/In= telFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > index cd87a99c40..910286982b 100644 > --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf > @@ -6,7 +6,7 @@ > # register TemporaryRamDonePpi to call TempRamExit API, and register Memo= ryDiscoveredPpi > # notify to call FspSiliconInit API. > # > -# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved. > +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. > # > # This program and the accompanying materials > # are licensed and made available under the terms and conditions of the = BSD License > @@ -68,6 +68,7 @@ > [Pcd] > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES >=20 > [Guids] > gFspHobGuid ## CONSUMES ## HOB > diff --git a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec b/IntelFsp2Wrapp= erPkg/IntelFsp2WrapperPkg.dec > index 69df16452d..96f2858fb4 100644 > --- a/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > +++ b/IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > @@ -71,9 +71,8 @@ > ## Indicate the PEI memory size platform want to report > gIntelFsp2WrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize|0x3000000|UINT= 32|0x40000005 >=20 > - ## This is the base address of FSP-T/M/S > + ## This is the base address of FSP-T > gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0x00000000|UINT32|0x= 00000300 > - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0= x00000301 >=20 > ## This PCD indicates if FSP APIs are skipped from FSP wrapper.

> # If a bit is set, that means this FSP API is skipped.
> @@ -93,7 +92,17 @@ > # @Prompt Skip FSP API from FSP wrapper. > gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi|0x00000000|UINT32|0x40000= 009 >=20 > + ## This PCD decides how Wrapper code utilizes FSP > + # 0: DISPATCH mode (FSP Wrapper will load PeiCore from FSP without cal= ling FSP API) > + # 1: API mode (FSP Wrapper will call FSP API) > + # > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0x00000001|UINT8|0= x4000000A > + > [PcdsFixedAtBuild, PcdsPatchableInModule,PcdsDynamic,PcdsDynamicEx] > + # > + ## These are the base address of FSP-M/S > + # > + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0x00000000|UINT32|0= x00001000 > gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0x00000000|UINT32|0x= 00001001 > # > # To provide flexibility for platform to pre-allocate FSP UPD buffer > --=20 > 2.13.3.windows.1 >=20