[edk2-devel] 回复: [PATCH v4 1/3] MdeModulePkg/DxeIplPeim: fix PcdUse5LevelPageTable assert

["gaoliming via groups.io" <gaoliming=byosoft.com.cn@groups.io>]

Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

> -----邮件原件-----
> 发件人: Gerd Hoffmann <kraxel@redhat.com>
> 发送时间: 2024年2月22日 18:54
> 收件人: devel@edk2.groups.io
> 抄送: Michael Roth <michael.roth@amd.com>; Jiewen Yao
> <jiewen.yao@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Laszlo
> Ersek <lersek@redhat.com>; Tom Lendacky <thomas.lendacky@amd.com>;
> Paolo Bonzini <pbonzini@redhat.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>; Gerd Hoffmann <kraxel@redhat.com>; Min Xu
> <min.m.xu@intel.com>; Erdem Aktas <erdemaktas@google.com>; Oliver
> Steffen <osteffen@redhat.com>; Ard Biesheuvel <ardb@kernel.org>
> 主题: [PATCH v4 1/3] MdeModulePkg/DxeIplPeim: fix
> PcdUse5LevelPageTable assert
> 
> PcdUse5LevelPageTable documentation says:
> 
>   Indicates if 5-Level Paging will be enabled in long mode. 5-Level
>   Paging will not be enabled when the PCD is TRUE but CPU doesn't support
>   5-Level Paging.
> 
> So running in 4-level paging mode with PcdUse5LevelPageTable=TRUE is
> possible.  The only invalid combination is 5-level paging being active
> with PcdUse5LevelPageTable=FALSE.
> 
> Fix the ASSERT accordingly.
> 
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> Acked-by: Ard Biesheuvel <ardb@kernel.org>
> ---
>  MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> index 980c2002d4f5..1d240e95966e 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> @@ -745,7 +745,9 @@ CreateIdentityMappingPageTables (
>      //
>      Cr4.UintN         = AsmReadCr4 ();
>      Page5LevelSupport = (Cr4.Bits.LA57 != 0);
> -    ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport);
> +    if (Page5LevelSupport) {
> +      ASSERT (PcdGetBool (PcdUse5LevelPageTable));
> +    }
>    } else {
>      //
>      // If cpu runs in 32bit protected mode PEI, Page table Level in DXE
is
> decided by PCD and feature capability.
> --
> 2.43.2





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