From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 1055574003E for ; Fri, 1 Mar 2024 12:44:34 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=n7T/Bjy1zvT+bJLsWGMDH0xPZBkHa/zrrw8Dzq4vMBo=; c=relaxed/simple; d=groups.io; h=From:To:Cc:References:In-Reply-To:Subject:Date:Message-ID:MIME-Version:Thread-Index:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding:Content-Language; s=20140610; t=1709297073; v=1; b=p9ns4iflODlKTlRJgLB4wtBGiPsqf0FMHfBWFss0hgbNpUB/XY/WZWve2BQ95bHp9I2UljKq 8vtJOvIgW9jGwRtllQu3+Wv2QUk4ra26jh7besjFR1ZXy1OaB8im1dmkXXYCl2Pszqgffx4ti87 eSr8JXmcawBUegsfMzg9YD+Q= X-Received: by 127.0.0.2 with SMTP id lF6YYY7687511x0U2Vs2Jdre; Fri, 01 Mar 2024 04:44:33 -0800 X-Received: from zrleap.intel-email.com (zrleap.intel-email.com [114.80.218.36]) by mx.groups.io with SMTP id smtpd.web10.21634.1709297072995674993 for ; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gaoliming@byosoft.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: PyqRVQ07n8PguA6bx6QbJk8nx7686176AA= Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable Content-Language: zh-cn X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=p9ns4ifl; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Liming Gao > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: Gerd Hoffmann > =B7=A2=CB=CD=CA=B1=BC=E4: 2024=C4=EA2=D4=C222=C8=D5 18:54 > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io > =B3=AD=CB=CD: Michael Roth ; Jiewen Yao > ; Liming Gao ; Laszlo > Ersek ; Tom Lendacky ; > Paolo Bonzini ; Ard Biesheuvel > ; Gerd Hoffmann ; Min Xu > ; Erdem Aktas ; Oliver > Steffen ; Ard Biesheuvel > =D6=F7=CC=E2: [PATCH v4 2/3] MdeModulePkg/DxeIplPeim: rename variable >=20 > Rename Page5LevelSupported to Page5LevelEnabled. >=20 > The variable is set to true in case 5-paging level is enabled (64-bit > PEI) or will be enabled (32-bit PEI), it does *not* tell whenever the > 5-level paging is supported by the CPU. >=20 > Signed-off-by: Gerd Hoffmann > Reviewed-by: Laszlo Ersek > Acked-by: Ard Biesheuvel > --- > .../Core/DxeIplPeim/X64/VirtualMemory.c | 22 +++++++++---------- > 1 file changed, 11 insertions(+), 11 deletions(-) >=20 > diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > index 1d240e95966e..df6196a41cd5 100644 > --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > @@ -696,7 +696,7 @@ CreateIdentityMappingPageTables ( > UINTN TotalPagesNum; > UINTN BigPageAddress; > VOID *Hob; > - BOOLEAN > Page5LevelSupport; > + BOOLEAN > Page5LevelEnabled; > BOOLEAN Page1GSupport; > PAGE_TABLE_1G_ENTRY > *PageDirectory1GEntry; > UINT64 AddressEncMask; > @@ -744,15 +744,15 @@ CreateIdentityMappingPageTables ( > // If cpu has already run in 64bit long mode PEI, Page table Level i= n DXE > must align with previous level. > // > Cr4.UintN =3D AsmReadCr4 (); > - Page5LevelSupport =3D (Cr4.Bits.LA57 !=3D 0); > - if (Page5LevelSupport) { > + Page5LevelEnabled =3D (Cr4.Bits.LA57 !=3D 0); > + if (Page5LevelEnabled) { > ASSERT (PcdGetBool (PcdUse5LevelPageTable)); > } > } else { > // > // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is > decided by PCD and feature capability. > // > - Page5LevelSupport =3D FALSE; > + Page5LevelEnabled =3D FALSE; > if (PcdGetBool (PcdUse5LevelPageTable)) { > AsmCpuidEx ( > CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, > @@ -763,12 +763,12 @@ CreateIdentityMappingPageTables ( > NULL > ); > if (EcxFlags.Bits.FiveLevelPage !=3D 0) { > - Page5LevelSupport =3D TRUE; > + Page5LevelEnabled =3D TRUE; > } > } > } >=20 > - DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n"= , > PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); > + DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u > 1GPage=3D%u\n", PhysicalAddressBits, Page5LevelEnabled, Page1GSupport)); >=20 > // > // IA-32e paging translates 48-bit linear addresses to 52-bit physical > addresses > @@ -776,7 +776,7 @@ CreateIdentityMappingPageTables ( > // due to either unsupported by HW, or disabled by PCD. > // > ASSERT (PhysicalAddressBits <=3D 52); > - if (!Page5LevelSupport && (PhysicalAddressBits > 48)) { > + if (!Page5LevelEnabled && (PhysicalAddressBits > 48)) { > PhysicalAddressBits =3D 48; > } >=20 > @@ -811,7 +811,7 @@ CreateIdentityMappingPageTables ( > // > // Substract the one page occupied by PML5 entries if 5-Level Paging i= s > disabled. > // > - if (!Page5LevelSupport) { > + if (!Page5LevelEnabled) { > TotalPagesNum--; > } >=20 > @@ -831,7 +831,7 @@ CreateIdentityMappingPageTables ( > // By architecture only one PageMapLevel4 exists - so lets allocate > storage for it. > // > PageMap =3D (VOID *)BigPageAddress; > - if (Page5LevelSupport) { > + if (Page5LevelEnabled) { > // > // By architecture only one PageMapLevel5 exists - so lets allocate > storage for it. > // > @@ -853,7 +853,7 @@ CreateIdentityMappingPageTables ( > PageMapLevel4Entry =3D (VOID *)BigPageAddress; > BigPageAddress +=3D SIZE_4KB; >=20 > - if (Page5LevelSupport) { > + if (Page5LevelEnabled) { > // > // Make a PML5 Entry > // > @@ -947,7 +947,7 @@ CreateIdentityMappingPageTables ( > ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof > (PAGE_MAP_AND_DIRECTORY_POINTER)); > } >=20 > - if (Page5LevelSupport) { > + if (Page5LevelEnabled) { > Cr4.UintN =3D AsmReadCr4 (); > Cr4.Bits.LA57 =3D 1; > AsmWriteCr4 (Cr4.UintN); > -- > 2.43.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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