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Tue, 16 Jan 2024 01:01:33 -0600 From: "Abdul Lateef Attar via groups.io" To: CC: Abdul Lateef Attar , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v1 2/2] UefiCpuPkg/BaseXApicX2ApicLib: Implements AMD extended cpu topology Date: Tue, 16 Jan 2024 12:31:21 +0530 Message-ID: <030184fe0cac804e7f3c98569ebedaf67c71fc50.1705387772.git.AbdulLateef.Attar@amd.com> In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343F:EE_|SA1PR12MB8987:EE_ X-MS-Office365-Filtering-Correlation-Id: 321dc651-1f2e-4624-24c3-08dc1660fa88 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: NrXMn2OVOe5/Yc2q1K24JiU6s159KXSLDRwbvFmA+DKwAA6gwjyBvxMjRsBbDGvwgEVUXxG3Q/pAhYKNrJrvWooRtu+1D6sooDymP7lSZEWB11W0Yyc+lyk51juBkRwGeSSHbr2sL0pda/5ektaqlw+sI1i1DItugZWB7Ibx3RbDZgTOZmBzTwioapVNgDhWl8wKza6V0h7Dl88I/jk5SIomrH+MLgHtbK9Igx1NhNhI5ULi3LBqA7g6KK4HxBsDhn82uscLyB09UN1Pj6jzMJTtR5puHWnAcJrLUYCXGr9L+hiqKaZaHBXbwkv3dTAsZ4N8xEXObbl20WNqf4djZ/zD1wCqWn3z6q4cyVOPkLn5qDrPlUaPeNNoIVmO/jQFqpj2TYjcoY3tKtqh2fCuMURWwOQ8+ilfOYdf8GyoROPb96lEgZXI7A2cWoIg5Caj09SGEzap83Ff7wWWg3W+rd1qUhM96Ws+N2f2O8j3SaSKF+mccokqQaEZL+CH9uWwKjYX2v87XTLMBbCWDMOcuGZCqIhLxTeVkTwPinbtiU2qoA0NIp4bMd/M5YwKfMSKIgseN28ragSjHJK3M5Q9MG5Z+7U8cvZ5IYPPgWAcZKk2kO47PnYKHwiBxncOFzR6Bnd5ZyK8kIcPNxJxwhnnNgg3YUrWwQyCiDjQdxJsgBWrRjJrFcnVGq356FAxfPE6XxNAf1KdbCwTxyluDkHpQIZRNoRIxhFVNj9E9q/7M5klHn0jTS/uhsqeOze1+AVRxAGnekrV0HPORDVUSI2oYQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2024 07:01:35.4728 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 321dc651-1f2e-4624-24c3-08dc1660fa88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8987 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,AbdulLateef.Attar@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: LaVD8BCvSrGBaKU2sWlTXGh1x7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=mHIl5+Ra; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") From: Abdul Lateef Attar This patch adds support for AMD's new extended topology. If processor supports CPUID 80000026 leaf then obtain the topology information using new method. Algorithm: if CPUID is AMD: then check for AMD's extended cpu tology leaf. if yes then extract cpu tology based on AMD programmer manual's instruction. else then fallback to existing topology function. endif endif Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Abdul Lateef Attar --- .../Library/BaseXApicLib/BaseXApicLib.c | 122 +++++++++++++++++- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 122 +++++++++++++++++- 2 files changed, 242 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index efb9d71ca1..5e941d0dc8 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,7 +4,7 @@ This local APIC library instance supports xAPIC mode only. =20 Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
- Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1157,6 +1157,121 @@ GetProcessorLocationByApicId ( } } =20 +/** + Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor fam= ily. + + The algorithm assumes the target system has symmetry across physical + package boundaries with respect to the number of threads per core, numbe= r of + cores per module, number of modules per die, number + of dies per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Die Returns the processor die ID. + @param[out] Tile Returns zero. + @param[out] Module Returns the processor module ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +EFIAPI +AmdGetProcessorLocation2ByApicId ( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Die OPTIONAL, + OUT UINT32 *Tile OPTIONAL, + OUT UINT32 *Module OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINT32 PreviousLevel; + UINT32 Data; + + if (Die !=3D NULL) { + *Die =3D 0; + } + + if (Tile !=3D NULL) { + *Tile =3D 0; + } + + if (Module !=3D NULL) { + *Module =3D 0; + } + + /// Check if extended toplogy supported + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); + if (MaxExtendedCpuIdIndex < AMD_CPUID_EXTENDED_TOPOLOGY) { + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); + return; + } + + PreviousLevel =3D 0; + SubIndex =3D 0; + do { + AsmCpuidEx ( + AMD_CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + + if (ExtendedTopologyEbx.Bits.LogicalProcessors =3D=3D CPUID_EXTENDED_T= OPOLOGY_LEVEL_TYPE_INVALID) { + break; + } + + Data =3D InitialApicId >> PreviousLevel; + Data &=3D (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLevel)= ) - 1; + + switch (ExtendedTopologyEcx.Bits.LevelType) { + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT: + if (Thread !=3D NULL) { + *Thread =3D Data; + } + + break; + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE: + if (Core !=3D NULL) { + *Core =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE: + if (Module !=3D NULL) { + *Module =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE: + if (Die !=3D NULL) { + *Die =3D Data; + } + + break; + default: + break; + } + + SubIndex++; + PreviousLevel =3D ExtendedTopologyEax.Bits.ApicIdShift; + } while (ExtendedTopologyEbx.Bits.LogicalProcessors !=3D CPUID_EXTENDED_= TOPOLOGY_LEVEL_TYPE_INVALID); + + /// Package value + if ((PreviousLevel !=3D 0) && (Package !=3D NULL)) { + *Package =3D InitialApicId >> PreviousLevel; + } + + return; +} + /** Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor= . =20 @@ -1194,6 +1309,11 @@ GetProcessorLocation2ByApicId ( UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_= DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_= TYPE_DIE + 2]; =20 + if (StandardSignatureIsAuthenticAMD ()) { + AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, M= odule, Core, Thread); + return; + } + for (LevelType =3D 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] =3D 0; } diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index c0a8475833..a7563f6596 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,7 +5,7 @@ which have xAPIC and x2APIC modes. =20 Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
- Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1396,6 +1396,121 @@ GetProcessorLocationByApicId ( } } =20 +/** + Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor fam= ily. + + The algorithm assumes the target system has symmetry across physical + package boundaries with respect to the number of threads per core, numbe= r of + cores per module, number of modules per die, number + of dies per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Die Returns the processor die ID. + @param[out] Tile Returns zero. + @param[out] Module Returns the processor module ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +EFIAPI +AmdGetProcessorLocation2ByApicId ( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Die OPTIONAL, + OUT UINT32 *Tile OPTIONAL, + OUT UINT32 *Module OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINT32 PreviousLevel; + UINT32 Data; + + if (Die !=3D NULL) { + *Die =3D 0; + } + + if (Tile !=3D NULL) { + *Tile =3D 0; + } + + if (Module !=3D NULL) { + *Module =3D 0; + } + + /// Check if extended toplogy supported + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); + if (MaxExtendedCpuIdIndex < AMD_CPUID_EXTENDED_TOPOLOGY) { + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); + return; + } + + PreviousLevel =3D 0; + SubIndex =3D 0; + do { + AsmCpuidEx ( + AMD_CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + + if (ExtendedTopologyEbx.Bits.LogicalProcessors =3D=3D CPUID_EXTENDED_T= OPOLOGY_LEVEL_TYPE_INVALID) { + break; + } + + Data =3D InitialApicId >> PreviousLevel; + Data &=3D (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLevel)= ) - 1; + + switch (ExtendedTopologyEcx.Bits.LevelType) { + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT: + if (Thread !=3D NULL) { + *Thread =3D Data; + } + + break; + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE: + if (Core !=3D NULL) { + *Core =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE: + if (Module !=3D NULL) { + *Module =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE: + if (Die !=3D NULL) { + *Die =3D Data; + } + + break; + default: + break; + } + + SubIndex++; + PreviousLevel =3D ExtendedTopologyEax.Bits.ApicIdShift; + } while (ExtendedTopologyEbx.Bits.LogicalProcessors !=3D CPUID_EXTENDED_= TOPOLOGY_LEVEL_TYPE_INVALID); + + /// Package value + if ((PreviousLevel !=3D 0) && (Package !=3D NULL)) { + *Package =3D InitialApicId >> PreviousLevel; + } + + return; +} + /** Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor= . =20 @@ -1433,6 +1548,11 @@ GetProcessorLocation2ByApicId ( UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_= DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_= TYPE_DIE + 2]; =20 + if (StandardSignatureIsAuthenticAMD ()) { + AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, M= odule, Core, Thread); + return; + } + for (LevelType =3D 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] =3D 0; } --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113869): https://edk2.groups.io/g/devel/message/113869 Mute This Topic: https://groups.io/mt/103757657/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-