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Thu, 22 Sep 2022 13:36:52 -0700 From: "Jeff Brasen" To: CC: , , , , , Jeff Brasen Subject: [PATCH v5 1/3] DynamicTablesPkg: Add CM_ARM_CPC_INFO object Date: Thu, 22 Sep 2022 14:36:44 -0600 Message-ID: <03d241a3a0143019586a5b2c68f3f49189f70dbd.1663878888.git.jbrasen@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-NVConfidentiality: public Return-Path: jbrasen@nvidia.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT084:EE_|IA1PR12MB7614:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c332564-d692-41e3-92d4-08da9cda36e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dydjeTsVOSQ4eeZ9tLiwwWgVpQSuV0i77cErTddmHMj1zTpngk56S7q6SA5s2qJmKl1XYwBRyjSI7Q1QwQ/fAnIMusInlNVNIhfp+FtUdQo288Z8oV4o5BZ09XyUyo3I8pM5Hq0gs3m2FSi5XB/9OjAcLf3hgfDFau65/0fMsAsooDDhTC1a4+E/u4F1KWalp6KuoJmb36HPwTelEUU2uRP8VEbE43Xtfk5SuQkx/W+v5GHRK2UNEI3wlPQKk/xCpEIdIuPkwRLoZlJqhc1yIDaLsfWARXoSuIIW1X9+BmWtwOTVmGqIFSEyx+B/OwxNp18AGXPCi9rVYj0Ot+ufXUVhp48QScdrAiXgTLNyjcHA0OMCFvArwlIotu/AdyqWkKSJbzPD2VqfkN+TL33BpBgxreVv58whJxwaZGxXhqICGLSV8bgzO0rCz+CkAje/YN9EAWS7L9AZoJj6OiUrO+6gaQowumAEEzXZLmje6iwuWIMVtxfxCXUYcnzH/goe0OKxAM+akLboiDCO8kPvOPG4Qd1SV3uXn4S8tswaqRek/ziYqLPftIy3yp8QrJPPkddGU+5YDxfPvnvTk+ZwRs72gbZWflY2UeM/99nUCIK+MoztadHGEtODdDPcq5IkzG90KkleK7PeOEKuPvWk+OVdRIY/3nzlQdHELXa2dXWjbLh/qVv5jomIP68mLUeMfYvIM4o4nBqUiQiGsshHcJMw4iykUKpaQCmIF7FJ/FiZl3rBHHrriCWkA3/4q/djFsk1kNUvOHQNqH+7BFiCag== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(396003)(376002)(346002)(451199015)(40470700004)(36840700001)(46966006)(2906002)(36756003)(7696005)(426003)(336012)(2616005)(47076005)(186003)(8676002)(30864003)(107886003)(6666004)(41300700001)(5660300002)(26005)(4326008)(8936002)(82310400005)(40460700003)(356005)(40480700001)(7636003)(86362001)(83380400001)(36860700001)(316002)(6916009)(54906003)(82740400003)(478600001)(70586007)(70206006);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 20:37:06.2537 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c332564-d692-41e3-92d4-08da9cda36e4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7614 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Introduce the CM_ARM_CPC_INFO CmObj in the ArmNameSpaceObjects.=0D This allows to describe CPC information, as described in ACPI 6.4,=0D s8.4.7.1 "_CPC (Continuous Performance Control)".=0D =0D Signed-off-by: Jeff Brasen =0D ---=0D .../Include/ArmNameSpaceObjects.h | 60 ++++++---=0D DynamicTablesPkg/Include/Library/AmlCpcInfo.h | 124 ++++++++++++++++++=0D .../ConfigurationManagerObjectParser.c | 115 +++++++++++++---=0D 3 files changed, 265 insertions(+), 34 deletions(-)=0D create mode 100644 DynamicTablesPkg/Include/Library/AmlCpcInfo.h=0D =0D diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h b/DynamicTables= Pkg/Include/ArmNameSpaceObjects.h=0D index 102e0f96be..ea5bf81070 100644=0D --- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h=0D +++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h=0D @@ -14,6 +14,7 @@=0D #define ARM_NAMESPACE_OBJECTS_H_=0D =0D #include =0D +#include =0D =0D #pragma pack(1)=0D =0D @@ -63,6 +64,7 @@ typedef enum ArmObjectID {=0D EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info=0D EArmObjRmr, ///< 40 - Reserved Memory Range Nod= e=0D EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor=0D + EArmObjCpcInfo, ///< 42 - Continuous Performance Co= ntrol Info=0D EArmObjMax=0D } EARM_OBJECT_ID;=0D =0D @@ -97,99 +99,105 @@ typedef struct CmArmPowerManagementProfileInfo {=0D */=0D typedef struct CmArmGicCInfo {=0D /// The GIC CPU Interface number.=0D - UINT32 CPUInterfaceNumber;=0D + UINT32 CPUInterfaceNumber;=0D =0D /** The ACPI Processor UID. This must match the=0D _UID of the CPU Device object information described=0D in the DSDT/SSDT for the CPU.=0D */=0D - UINT32 AcpiProcessorUid;=0D + UINT32 AcpiProcessorUid;=0D =0D /** The flags field as described by the GICC structure=0D in the ACPI Specification.=0D */=0D - UINT32 Flags;=0D + UINT32 Flags;=0D =0D /** The parking protocol version field as described by=0D the GICC structure in the ACPI Specification.=0D */=0D - UINT32 ParkingProtocolVersion;=0D + UINT32 ParkingProtocolVersion;=0D =0D /** The Performance Interrupt field as described by=0D the GICC structure in the ACPI Specification.=0D */=0D - UINT32 PerformanceInterruptGsiv;=0D + UINT32 PerformanceInterruptGsiv;=0D =0D /** The CPU Parked address field as described by=0D the GICC structure in the ACPI Specification.=0D */=0D - UINT64 ParkedAddress;=0D + UINT64 ParkedAddress;=0D =0D /** The base address for the GIC CPU Interface=0D as described by the GICC structure in the=0D ACPI Specification.=0D */=0D - UINT64 PhysicalBaseAddress;=0D + UINT64 PhysicalBaseAddress;=0D =0D /** The base address for GICV interface=0D as described by the GICC structure in the=0D ACPI Specification.=0D */=0D - UINT64 GICV;=0D + UINT64 GICV;=0D =0D /** The base address for GICH interface=0D as described by the GICC structure in the=0D ACPI Specification.=0D */=0D - UINT64 GICH;=0D + UINT64 GICH;=0D =0D /** The GICV maintenance interrupt=0D as described by the GICC structure in the=0D ACPI Specification.=0D */=0D - UINT32 VGICMaintenanceInterrupt;=0D + UINT32 VGICMaintenanceInterrupt;=0D =0D /** The base address for GICR interface=0D as described by the GICC structure in the=0D ACPI Specification.=0D */=0D - UINT64 GICRBaseAddress;=0D + UINT64 GICRBaseAddress;=0D =0D /** The MPIDR for the CPU=0D as described by the GICC structure in the=0D ACPI Specification.=0D */=0D - UINT64 MPIDR;=0D + UINT64 MPIDR;=0D =0D /** The Processor Power Efficiency class=0D as described by the GICC structure in the=0D ACPI Specification.=0D */=0D - UINT8 ProcessorPowerEfficiencyClass;=0D + UINT8 ProcessorPowerEfficiencyClass;=0D =0D /** Statistical Profiling Extension buffer overflow GSIV. Zero if=0D unsupported by this processor. This field was introduced in=0D ACPI 6.3 (MADT revision 5) and is therefore ignored when=0D generating MADT revision 4 or lower.=0D */=0D - UINT16 SpeOverflowInterrupt;=0D + UINT16 SpeOverflowInterrupt;=0D =0D /** The proximity domain to which the logical processor belongs.=0D This field is used to populate the GICC affinity structure=0D in the SRAT table.=0D */=0D - UINT32 ProximityDomain;=0D + UINT32 ProximityDomain;=0D =0D /** The clock domain to which the logical processor belongs.=0D This field is used to populate the GICC affinity structure=0D in the SRAT table.=0D */=0D - UINT32 ClockDomain;=0D + UINT32 ClockDomain;=0D =0D /** The GICC Affinity flags field as described by the GICC Affinity stru= cture=0D in the SRAT table.=0D */=0D - UINT32 AffinityFlags;=0D + UINT32 AffinityFlags;=0D +=0D + /** Optional field: Reference Token for the Cpc info of this processor.= =0D + Token identifying a CM_ARM_OBJ_REF structure, itself referencing=0D + CM_ARM_CPC_INFO objects.=0D + */=0D + CM_OBJECT_TOKEN CpcToken;=0D } CM_ARM_GICC_INFO;=0D =0D /** A structure that describes the=0D @@ -1070,6 +1078,24 @@ typedef struct CmArmRmrDescriptor {=0D UINT64 Length;=0D } CM_ARM_MEMORY_RANGE_DESCRIPTOR;=0D =0D +/** A structure that describes the Cpc information.=0D +=0D + Continuous Performance Control is described in DSDT/SSDT and associated= =0D + to cpus/clusters in the cpu topology.=0D +=0D + Unsupported Optional registers should be encoded with NULL resource=0D + Register {(SystemMemory, 0, 0, 0, 0)}=0D +=0D + For values that support Integer or Buffer, integer will be used=0D + if buffer is NULL resource.=0D + If resource is not NULL then Integer must be 0=0D +=0D + Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control)=0D +=0D + ID: EArmObjCpcInfo=0D +*/=0D +typedef AML_CPC_INFO CM_ARM_CPC_INFO;=0D +=0D #pragma pack()=0D =0D #endif // ARM_NAMESPACE_OBJECTS_H_=0D diff --git a/DynamicTablesPkg/Include/Library/AmlCpcInfo.h b/DynamicTablesP= kg/Include/Library/AmlCpcInfo.h=0D new file mode 100644=0D index 0000000000..8981c22954=0D --- /dev/null=0D +++ b/DynamicTablesPkg/Include/Library/AmlCpcInfo.h=0D @@ -0,0 +1,124 @@=0D +/** @file=0D +=0D + Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved= .
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef AML_CPC_INFO_H_=0D +#define AML_CPC_INFO_H_=0D +=0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +/** A structure that describes the Cpc information.=0D +=0D + Continuous Performance Control is described in DSDT/SSDT and associated= =0D + to cpus/clusters in the cpu topology.=0D +=0D + Unsupported Optional registers should be encoded with NULL resource=0D + Register {(SystemMemory, 0, 0, 0, 0)}=0D +=0D + For values that support Integer or Buffer, integer will be used=0D + if buffer is NULL resource.=0D + If resource is not NULL then Integer must be 0=0D +=0D + Cf. ACPI 6.4, s8.4.7.1 _CPC (Continuous Performance Control)=0D +=0D +**/=0D +=0D +typedef struct AmlCpcInfo {=0D + /// The revision number of the _CPC package format.=0D + UINT32 Revision;=0D +=0D + /// Indicates the highest level of performance the processor=0D + /// is theoretically capable of achieving.=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE HighestPerformanceBuffer;=0D + UINT32 HighestPerformanceInteger;=0D +=0D + /// Indicates the highest sustained performance level of the processor.= =0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE NominalPerformanceBuffer;=0D + UINT32 NominalPerformanceInteger;=0D +=0D + /// Indicates the lowest performance level of the processor with non-lin= ear power savings.=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE LowestNonlinearPerformanceBuff= er;=0D + UINT32 LowestNonlinearPerformanceInte= ger;=0D +=0D + /// Indicates the lowest performance level of the processor..=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE LowestPerformanceBuffer;=0D + UINT32 LowestPerformanceInteger;=0D +=0D + /// Guaranteed Performance Register Buffer.=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE GuaranteedPerformanceRegister;= =0D +=0D + /// Desired Performance Register Buffer.=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DesiredPerformanceRegister;=0D +=0D + /// Minimum Performance Register Buffer.=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE MinimumPerformanceRegister;=0D +=0D + /// Maximum Performance Register Buffer.=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE MaximumPerformanceRegister;=0D +=0D + /// Performance Reduction Tolerance Register.=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PerformanceReductionToleranceR= egister;=0D +=0D + /// Time Window Register.=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE TimeWindowRegister;=0D +=0D + /// Counter Wraparound Time=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CounterWraparoundTimeBuffer;=0D + UINT32 CounterWraparoundTimeInteger;= =0D +=0D + /// Reference Performance Counter Register=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReferencePerformanceCounterReg= ister;=0D +=0D + /// Delivered Performance Counter Register=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE DeliveredPerformanceCounterReg= ister;=0D +=0D + /// Performance Limited Register=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE PerformanceLimitedRegister;=0D +=0D + /// CPPC EnableRegister=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE CPPCEnableRegister;=0D +=0D + /// Autonomous Selection Enable=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE AutonomousSelectionEnableBuffe= r;=0D + UINT32 AutonomousSelectionEnableInteg= er;=0D +=0D + /// AutonomousActivity-WindowRegister=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE AutonomousActivityWindowRegist= er;=0D +=0D + /// EnergyPerformance-PreferenceRegister=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE EnergyPerformancePreferenceReg= ister;=0D +=0D + /// Reference Performance=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE ReferencePerformanceBuffer;=0D + UINT32 ReferencePerformanceInteger;=0D +=0D + /// Lowest Frequency=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE LowestFrequencyBuffer;=0D + UINT32 LowestFrequencyInteger;=0D +=0D + /// Nominal Frequency=0D + /// Optional=0D + EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE NominalFrequencyBuffer;=0D + UINT32 NominalFrequencyInteger;=0D +} AML_CPC_INFO;=0D +=0D +#pragma pack()=0D +=0D +#endif //AML_CPC_INFO_H_=0D diff --git a/DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationMa= nagerObjectParser.c b/DynamicTablesPkg/Library/Common/TableHelperLib/Config= urationManagerObjectParser.c=0D index c1b21d24a4..08b4f60dfb 100644=0D --- a/DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerOb= jectParser.c=0D +++ b/DynamicTablesPkg/Library/Common/TableHelperLib/ConfigurationManagerOb= jectParser.c=0D @@ -34,23 +34,24 @@ STATIC CONST CM_OBJ_PARSER CmArmPowerManagementProfile= InfoParser[] =3D {=0D /** A parser for EArmObjGicCInfo.=0D */=0D STATIC CONST CM_OBJ_PARSER CmArmGicCInfoParser[] =3D {=0D - { "CPUInterfaceNumber", 4, "0x%x", NULL },=0D - { "AcpiProcessorUid", 4, "0x%x", NULL },=0D - { "Flags", 4, "0x%x", NULL },=0D - { "ParkingProtocolVersion", 4, "0x%x", NULL },=0D - { "PerformanceInterruptGsiv", 4, "0x%x", NULL },=0D - { "ParkedAddress", 8, "0x%llx", NULL },=0D - { "PhysicalBaseAddress", 8, "0x%llx", NULL },=0D - { "GICV", 8, "0x%llx", NULL },=0D - { "GICH", 8, "0x%llx", NULL },=0D - { "VGICMaintenanceInterrupt", 4, "0x%x", NULL },=0D - { "GICRBaseAddress", 8, "0x%llx", NULL },=0D - { "MPIDR", 8, "0x%llx", NULL },=0D - { "ProcessorPowerEfficiencyClass", 1, "0x%x", NULL },=0D - { "SpeOverflowInterrupt", 2, "0x%x", NULL },=0D - { "ProximityDomain", 4, "0x%x", NULL },=0D - { "ClockDomain", 4, "0x%x", NULL },=0D - { "AffinityFlags", 4, "0x%x", NULL }=0D + { "CPUInterfaceNumber", 4, "0x%x", N= ULL },=0D + { "AcpiProcessorUid", 4, "0x%x", N= ULL },=0D + { "Flags", 4, "0x%x", N= ULL },=0D + { "ParkingProtocolVersion", 4, "0x%x", N= ULL },=0D + { "PerformanceInterruptGsiv", 4, "0x%x", N= ULL },=0D + { "ParkedAddress", 8, "0x%llx", N= ULL },=0D + { "PhysicalBaseAddress", 8, "0x%llx", N= ULL },=0D + { "GICV", 8, "0x%llx", N= ULL },=0D + { "GICH", 8, "0x%llx", N= ULL },=0D + { "VGICMaintenanceInterrupt", 4, "0x%x", N= ULL },=0D + { "GICRBaseAddress", 8, "0x%llx", N= ULL },=0D + { "MPIDR", 8, "0x%llx", N= ULL },=0D + { "ProcessorPowerEfficiencyClass", 1, "0x%x", N= ULL },=0D + { "SpeOverflowInterrupt", 2, "0x%x", N= ULL },=0D + { "ProximityDomain", 4, "0x%x", N= ULL },=0D + { "ClockDomain", 4, "0x%x", N= ULL },=0D + { "AffinityFlags", 4, "0x%x", N= ULL },=0D + { "CpcToken", sizeof (CM_OBJECT_TOKEN), "0x%p", N= ULL }=0D };=0D =0D /** A parser for EArmObjGicDInfo.=0D @@ -423,6 +424,84 @@ STATIC CONST CM_OBJ_PARSER CmPciInterruptMapInfoParse= r[] =3D {=0D ARRAY_SIZE (CmArmGenericInterruptParser) },=0D };=0D =0D +/** A parser for EArmObjCpcInfo.=0D +*/=0D +STATIC CONST CM_OBJ_PARSER CmArmCpcInfoParser[] =3D {=0D + { "Revision", 4, = "0x%lx", NULL },=0D + { "HighestPerformanceBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "HighestPerformanceInteger", 4, = "0x%lx", NULL },=0D + { "NominalPerformanceBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "NominalPerformanceInteger", 4, = "0x%lx", NULL },=0D + { "LowestNonlinearPerformanceBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "LowestNonlinearPerformanceInteger", 4, = "0x%lx", NULL },=0D + { "LowestPerformanceBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "LowestPerformanceInteger", 4, = "0x%lx", NULL },=0D + { "GuaranteedPerformanceRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "DesiredPerformanceRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "MinimumPerformanceRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "MaximumPerformanceRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "PerformanceReductionToleranceRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "TimeWindowRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "CounterWraparoundTimeBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "CounterWraparoundTimeInteger", 4, = "0x%lx", NULL },=0D + { "ReferencePerformanceCounterRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "DeliveredPerformanceCounterRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "PerformanceLimitedRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "CPPCEnableRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "AutonomousSelectionEnableBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "AutonomousSelectionEnableInteger", 4, = "0x%lx", NULL },=0D + { "AutonomousActivityWindowRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "EnergyPerformancePreferenceRegister", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "ReferencePerformanceBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "ReferencePerformanceInteger", 4, = "0x%lx", NULL },=0D + { "LowestFrequencyBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "LowestFrequencyInteger", 4, = "0x%lx", NULL },=0D + { "NominalFrequencyBuffer", sizeof (EFI_ACPI_6_4_GENERIC_= ADDRESS_STRUCTURE),=0D + NULL, NULL, AcpiGenericAddressParser,=0D + ARRAY_SIZE (AcpiGenericAddressParser) },=0D + { "NominalFrequencyInteger", 4, = "0x%lx", NULL },=0D +};=0D +=0D /** A parser for Arm namespace objects.=0D */=0D STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] =3D {=0D @@ -501,6 +580,8 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectPar= ser[] =3D {=0D ARRAY_SIZE (CmArmPciAddressMapInfoParser) },=0D { "EArmObjPciInterruptMapInfo", CmPciInterruptMapInfoParser,=0D ARRAY_SIZE (CmPciInterruptMapInfoParser) },=0D + { "EArmObjCpcInfo", CmArmCpcInfoParser,=0D + ARRAY_SIZE (CmArmCpcInfoParser) },=0D { "EArmObjMax", NULL, = 0 },=0D };=0D =0D -- =0D 2.25.1=0D =0D