From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::c43; helo=mail-yw1-xc43.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-yw1-xc43.google.com (mail-yw1-xc43.google.com [IPv6:2607:f8b0:4864:20::c43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9CFD9211E7437 for ; Thu, 21 Mar 2019 21:29:05 -0700 (PDT) Received: by mail-yw1-xc43.google.com with SMTP id z191so867167ywa.6 for ; Thu, 21 Mar 2019 21:29:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=sXrYFJnRwMizFDAAVDE3HMZR+rDcc4/cfMMp0xXUMAg=; b=q7cQSMOn21gQ0BA4mvdnQD49adRQP5z41ns7P0yVMSpPpciWE199KSL9I2KQhMI1DN /tO8fZKkZlOlDSFFkScBtagaRnBu3IA4ujrFS/dQC91uxy9do03pcr9UyuJanl1ODLLK shT6dEGWWftGuhYJBLipt1yvOR75ZlVXJ4dLKyTbYVr6Skku37bDkO8Ad9c0BgNjuj5g XZ9iFANOm4h6NVOdF6CUCKf2ajVK2zt76nu7CWCYHzrhXJ6e+SDPiDCRURuLzxRlXy98 fgDsEwz2s7IJAPDpT+Oq1WGyXJ9kC6v4e0IlgntZcnbKP9gqVuXBTaJFbsy5AJyvjnNq Stag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=sXrYFJnRwMizFDAAVDE3HMZR+rDcc4/cfMMp0xXUMAg=; b=iR5Dhs0+SbTs9wfK7cr76FIPfWvMd8niEuBAwk14StjYtC4MmGwubeElrvsZJVDlin jEjBOcSRTGg49HjxhZeWxThjNi/g5Y67sna+quPAJqrwjpiE80gmNQpEYXk1YlFLoYAO ERgbi1/bbSg+lborA4NDSaFlVFAwOh6xHWS347fOJ8vXJicj1fyhLilfGPOZgPtilptL bDWl1WY1W75m4kXE+PR7qPAYjUtepvvJWr3gigiEPCiCw5ARNixXehlbmvUnuyM4kJgx TAGdHmCumuy/QjKErxwwfkTbG3R9eplVpLoAaZdIp9Fc/JGsIBZLiRYKdfSJU1+YcDm4 ScDQ== X-Gm-Message-State: APjAAAX4U7ruzsZG82TD0Asz8Qpe4cOPRHRzjLbTicmPjLk5s03O4oKI zltkZTVR/kDkUjc5t6IQVA4NxQ== X-Google-Smtp-Source: APXvYqyr9vN00KUEpNE6xi3V0AWouun6v79TnG0p2ckUqn4xfJap+/ulaxdSiPVyk5TQwsxgQmPJIw== X-Received: by 2002:a25:34d3:: with SMTP id b202mr6467939yba.188.1553228944034; Thu, 21 Mar 2019 21:29:04 -0700 (PDT) Received: from [10.95.0.10] ([64.64.108.214]) by smtp.gmail.com with ESMTPSA id j185sm1135710ywd.36.2019.03.21.21.28.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Mar 2019 21:29:03 -0700 (PDT) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, zhangfeng56@huawei.com, xiaojun2@hisilicon.com References: <20190320080829.52003-1-ming.huang@linaro.org> <20190320080829.52003-14-ming.huang@linaro.org> <20190321123200.fl5xlmkmprwur4dl@bivouac.eciton.net> From: Ming Huang Message-ID: <03dba555-d56b-2fdf-ee75-a9787f648f15@linaro.org> Date: Fri, 22 Mar 2019 12:28:54 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20190321123200.fl5xlmkmprwur4dl@bivouac.eciton.net> Subject: Re: [PATCH edk2-platforms v3 13/18] Hisilicon/D06: Add Setup Item "Support DPC" and delete some PCIe menus X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Mar 2019 04:29:05 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 3/21/2019 8:32 PM, Leif Lindholm wrote: > Hi Ming, > > On Wed, Mar 20, 2019 at 04:08:24PM +0800, Ming Huang wrote: >> Add setup item "Support DPC" to enable or disable PCIe DPC >> (Downstream Port Containment). >> >> The pcie menu is suppressed for original code as these menus >> are not ready. This patch remove the suppression for pcie menu, >> so delete these menus for now. > > As the commit message shows, this patch does two unrelated things. > Could you break this patch up into two separate ones and resubmit just > those? I will break this patch up into two seperate ones soon. Thanks > > I will cherry-pick this patch manually in order to have it included in > RPF 2019.03 -rc1, but I would prefer what goes in upstream to be > cleaner. > > Best Regards, > > Leif > >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> --- >> Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- >> 5 files changed, 10 insertions(+), 197 deletions(-) >> >> diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h >> index f120e3123c83..c0097d0829f0 100644 >> --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h >> +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h >> @@ -49,6 +49,7 @@ typedef struct { >> UINT8 OSWdtAction; >> /*PCIe Config*/ >> UINT8 PcieSRIOVSupport; >> + UINT8 PcieDPCSupport; >> UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; >> UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; >> UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr >> index 08236704fbfe..93ccb99bdc67 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr >> @@ -62,11 +62,9 @@ formset >> prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), >> help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP); >> >> - suppressif TRUE; >> goto PCIE_CONFIG_FORM_ID, >> prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), >> help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); >> - endif; >> >> goto MISC_CONFIG_FORM_ID, >> prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c >> index 6668103af027..be4ce8820f73 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c >> @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( >> Configuration.OSWdtTimeout = 5; >> Configuration.OSWdtAction = 1; >> // >> + //Set the default value of the PCIe option >> + // >> + Configuration.PcieDPCSupport = 0; >> + // >> //Set the default value of the Misc option >> // >> Configuration.EnableSmmu = 1; >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr >> index 7cf7cdd29ba2..c65907fe846e 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr >> @@ -17,203 +17,12 @@ >> form formid = PCIE_CONFIG_FORM_ID, >> title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE); >> >> - goto VFR_FORMID_PCIE_SOCKET0, >> - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), >> - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_SOCKET1, >> - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), >> - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); >> - >> - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, >> - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), >> - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), >> + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, >> + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), >> + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), >> option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; >> option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; >> endoneof; >> >> endform; >> >> -form formid = VFR_FORMID_PCIE_SOCKET0, >> - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); >> - >> - goto VFR_FORMID_PCIE_PORT2, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT4, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT5, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT6, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT7, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_SOCKET1, >> - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); >> - goto VFR_FORMID_PCIE_PORT10, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT12, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT13, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT0, >> - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); >> - #undef INDEX >> - #define INDEX 0 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT1, >> - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 1 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT2, >> - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 2 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT3, >> - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 3 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT4, >> - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 4 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT5, >> - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 5 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT6, >> - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 6 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT7, >> - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 7 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT8, >> - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 8 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT9, >> - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 9 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT10, >> - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 10 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT11, >> - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 11 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT12, >> - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 12 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT13, >> - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 13 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT14, >> - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 14 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT15, >> - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 15 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni >> index d87d30f975b8..0127ea952dee 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni >> @@ -26,7 +26,8 @@ >> #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" >> #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" >> #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" >> - >> +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" >> +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" >> #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press to config this port." >> #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" >> #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0" >> -- >> 2.9.5 >>